RISC-V: Add rounding mode enum for fixed-point intrinsics

Hi, since fixed-point with modeling rounding mode intrinsics are coming:
https://github.com/riscv-non-isa/rvv-intrinsic-doc/pull/222

I am adding vxrm rounding mode enum to user first before the API intrinsic.

This patch is simple && obvious.

Ok for trunk ?

gcc/ChangeLog:

	* config/riscv/riscv-vector-builtins.cc (register_vxrm): New function.
	(DEF_RVV_VXRM_ENUM): New macro.
	(handle_pragma_vector): Add vxrm enum register.
	* config/riscv/riscv-vector-builtins.def (DEF_RVV_VXRM_ENUM): New macro.
	(RNU): Ditto.
	(RNE): Ditto.
	(RDN): Ditto.
	(ROD): Ditto.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/base/vxrm-1.c: New test.

1 files changed, 29 insertions, 0 deletions

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vxrm-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vxrm-1.c
new file mode 100644
index 00000000000..0d364787ad0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vxrm-1.c
@@ -0,0 +1,29 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3" } */
+
+#include "riscv_vector.h"
+
+size_t f0 ()
+{
+  return VXRM_RNU;
+}
+
+size_t f1 ()
+{
+  return VXRM_RNE;
+}
+
+size_t f2 ()
+{
+  return VXRM_RDN;
+}
+
+size_t f3 ()
+{
+  return VXRM_ROD;
+}
+
+/* { dg-final { scan-assembler-times {li\s+[a-x0-9]+,\s*0} 1} } */
+/* { dg-final { scan-assembler-times {li\s+[a-x0-9]+,\s*1} 1} } */
+/* { dg-final { scan-assembler-times {li\s+[a-x0-9]+,\s*2} 1} } */
+/* { dg-final { scan-assembler-times {li\s+[a-x0-9]+,\s*3} 1} } */