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author | Jivan Hakobyan <jivanhakobyan9@gmail.com> | 2023-05-17 13:00:28 -0600 |
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committer | Jeff Law <jlaw@ventanamicro.com> | 2023-05-17 13:04:35 -0600 |
commit | 6da6ed95c9ca247d405da3dfb737b743686fe5e6 (patch) | |
tree | bbe8b754bd425be1b1f8e0451187f1b6d758fe61 /gcc/testsuite/gcc.target/riscv/zbb-rol-ror-04.c | |
parent | 98827c53ed38886795b1f479c1d997fd89011c38 (diff) | |
download | gcc-6da6ed95c9ca247d405da3dfb737b743686fe5e6.tar.gz |
RISC-V: Remove masking third operand of rotate instructions
Rotate instructions do not need to mask the third operand.
For example, RV64 the following code:
unsigned long foo1(unsigned long rs1, unsigned long rs2)
{
long shamt = rs2 & (64 - 1);
return (rs1 << shamt) | (rs1 >> ((64 - shamt) & (64 - 1)));
}
Compiles to:
foo1:
andi a1,a1,63
rol a0,a0,a1
ret
This patch removes unnecessary masking.
Besides, I have merged masking insns for shifts that were written before.
gcc/ChangeLog:
* config/riscv/riscv.md (*<optab><GPR:mode>3_mask): New pattern,
combined from ...
(*<optab>si3_mask, *<optab>di3_mask): Here.
(*<optab>si3_mask_1, *<optab>di3_mask_1): And here.
* config/riscv/bitmanip.md (*<bitmanip_optab><GPR:mode>3_mask): New
pattern.
(*<bitmanip_optab>si3_sext_mask): Likewise.
* config/riscv/iterators.md (shiftm1): Use const_si_mask_operand
and const_di_mask_operand.
(bitmanip_rotate): New iterator.
(bitmanip_optab): Add rotates.
* config/riscv/predicates.md (const_si_mask_operand): Renamed
from const31_operand. Generalize to handle more mask constants.
(const_di_mask_operand): Similarly.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/shift-and-2.c: Fixed test
* gcc.target/riscv/zbb-rol-ror-01.c: New test
* gcc.target/riscv/zbb-rol-ror-02.c: New test
* gcc.target/riscv/zbb-rol-ror-03.c: New test
* gcc.target/riscv/zbb-rol-ror-04.c: New test
* gcc.target/riscv/zbb-rol-ror-05.c: New test
* gcc.target/riscv/zbb-rol-ror-06.c: New test
* gcc.target/riscv/zbb-rol-ror-07.c: New test
Diffstat (limited to 'gcc/testsuite/gcc.target/riscv/zbb-rol-ror-04.c')
-rw-r--r-- | gcc/testsuite/gcc.target/riscv/zbb-rol-ror-04.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/gcc/testsuite/gcc.target/riscv/zbb-rol-ror-04.c b/gcc/testsuite/gcc.target/riscv/zbb-rol-ror-04.c index 08053484cb2..7ef4c29dd5b 100644 --- a/gcc/testsuite/gcc.target/riscv/zbb-rol-ror-04.c +++ b/gcc/testsuite/gcc.target/riscv/zbb-rol-ror-04.c @@ -2,6 +2,7 @@ /* { dg-options "-march=rv64gc_zbb -mabi=lp64d -fno-lto -O2" } */ /* { dg-skip-if "" { *-*-* } { "-g" } } */ /* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-final { scan-assembler-not "and" } } */ /* **foo1: |