2012-06-01 Basile Starynkevitch <basile@starynkevitch.net>

	MELT branch merged with trunk rev 188095 using svnmerge



git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/branches/melt-branch@188099 138bc75d-0d04-0410-961f-82ee72b054a4

27 files changed, 518 insertions, 5 deletions

diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 1c1b28eeab9..29ed833df4c 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,76 @@
+2012-05-31  Richard Guenther  <rguenther@suse.de>
+
+	* gcc.dg/tree-ssa/ldist-pr45948-2.c: New testcase copy of
+	ldist-pr45948.c with disabled SCCP.
+
+2012-05-31  Richard Guenther  <rguenther@suse.de>
+
+	PR middle-end/48493
+	* gcc.dg/torture/pr48493.c: New testcase.
+
+2012-05-31  Greta Yorsh  <Greta.Yorsh@arm.com>
+
+	* lib/target-supports.exp (check_effective_target_vect_char_mult): Add
+	arm32 to targets.
+	* gcc.dg/vect/slp-perm-8.c (main): Prevent vectorization
+	of the initialization loop.
+        (dg-final): Adjust the expected number of vectorized loops depending
+	on vect_char_mult target selector.
+
+2012-05-31  Hans-Peter Nilsson  <hp@axis.com>
+
+	* gcc.target/cris/asm-v8.S, gcc.target/cris/asm-v10.S,
+	gcc.target/cris/asm-other.S, gcc.target/cris/inasm-v8.c,
+	gcc.target/cris/inasm-v10.c, gcc.target/cris/inasm-other.c:
+	New tests.
+
+2012-05-30  Jason Merrill  <jason@redhat.com>
+
+	PR c++/53356
+	* g++.dg/init/new34.C: New.
+	* g++.dg/tree-ssa/stabilize1.C: New.
+
+2012-05-30  Jakub Jelinek  <jakub@redhat.com>
+
+	PR c++/53356
+	* g++.dg/init/new33.C: New test.
+
+2012-05-30  Richard Guenther  <rguenther@suse.de>
+
+	PR middle-end/53501
+	* gcc.dg/torture/pr53501.c: New testcase.
+	* c-c++-common/restrict-2.c: Adjust.
+
+2012-05-30  Alan Modra  <amodra@gmail.com>
+
+	* gcc.target/powerpc/powerpc.exp: Load torture-options.exp, call
+	torture-finish.
+
+2012-05-30  Marc Glisse  <marc.glisse@inria.fr>
+
+	* gcc.target/i386/shuf-concat.c: New test.
+
+2012-05-30  Jakub Jelinek  <jakub@redhat.com>
+
+	PR rtl-optimization/53519
+	* gcc.c-torture/compile/pr53519.c: New test.
+
+2012-05-30  Ramana Radhakrishnan  <ramana.radhakrishnan@linaro.org>
+
+	* gcc.target/arm/neon-vrev.c: New.
+
+2012-05-29  Oleg Endo  <olegendo@gcc.gnu.org>
+
+	PR target/51340
+	* gcc.target/sh/pr51340-1.c: New.
+	* gcc.target/sh/pr51340-2.c: New.
+	* gcc.target/sh/pr51340-3.c: New.
+
+2012-05-29  Richard Guenther  <rguenther@suse.de>
+
+	PR tree-optimization/53516
+	* gcc.dg/torture/pr53516.c: New testcase.
+
 2012-05-29  Dodji Seketeli  <dodji@redhat.com>
 
 	PR preprocessor/53229
diff --git a/gcc/testsuite/c-c++-common/restrict-2.c b/gcc/testsuite/c-c++-common/restrict-2.c
index 3f71b77b9ce..42ed398f670 100644
--- a/gcc/testsuite/c-c++-common/restrict-2.c
+++ b/gcc/testsuite/c-c++-common/restrict-2.c
@@ -10,5 +10,5 @@ void foo (float * __restrict__ a, float * __restrict__ b, int n, int j)
 
 /* We should move the RHS of the store out of the loop.  */
 
-/* { dg-final { scan-tree-dump-times "Moving statement" 11 "lim1" } } */
+/* { dg-final { scan-tree-dump-times "Moving statement" 10 "lim1" } } */
 /* { dg-final { cleanup-tree-dump "lim1" } } */
diff --git a/gcc/testsuite/g++.dg/init/new33.C b/gcc/testsuite/g++.dg/init/new33.C
new file mode 100644
index 00000000000..18da79e7e9a
--- /dev/null
+++ b/gcc/testsuite/g++.dg/init/new33.C
@@ -0,0 +1,11 @@
+// PR c++/53356
+// { dg-do compile }
+
+struct A {};
+struct B { operator const A & () const; };
+struct C { operator const A & () const; C (); };
+struct D { operator const A & () const; D (); ~D (); };
+
+A *foo () { return new A (B ()); }
+A *bar () { return new A (C ()); }
+A *baz () { return new A (D ()); }
diff --git a/gcc/testsuite/g++.dg/init/new34.C b/gcc/testsuite/g++.dg/init/new34.C
new file mode 100644
index 00000000000..9e67eb34174
--- /dev/null
+++ b/gcc/testsuite/g++.dg/init/new34.C
@@ -0,0 +1,11 @@
+// PR c++/53356
+
+struct A { A(); ~A(); };
+
+struct B {
+    operator const A () const;
+};
+
+A* cause_ICE() {
+  return new A((A(),A()));
+}
diff --git a/gcc/testsuite/g++.dg/tree-ssa/stabilize1.C b/gcc/testsuite/g++.dg/tree-ssa/stabilize1.C
new file mode 100644
index 00000000000..2fe723c3aae
--- /dev/null
+++ b/gcc/testsuite/g++.dg/tree-ssa/stabilize1.C
@@ -0,0 +1,14 @@
+// PR c++/53356
+// { dg-options "-fdump-tree-gimple" }
+// { dg-final { scan-tree-dump-not "= 0" "gimple" } }
+// { dg-final { cleanup-tree-dump "gimple" } }
+
+class A {};
+
+struct B {
+    operator const A &() const;
+};
+
+A* cause_ICE() {
+    return new A(B());
+}
diff --git a/gcc/testsuite/gcc.c-torture/compile/pr53519.c b/gcc/testsuite/gcc.c-torture/compile/pr53519.c
new file mode 100644
index 00000000000..3adadcb2c0e
--- /dev/null
+++ b/gcc/testsuite/gcc.c-torture/compile/pr53519.c
@@ -0,0 +1,26 @@
+/* PR rtl-optimization/53519 */
+
+int a, b, c, d, e;
+
+short int
+foo (short int x)
+{
+  return a == 0 ? x : 0;
+}
+
+short int
+bar (int x, int y)
+{
+  return x + y;
+}
+
+void
+baz (void)
+{
+  if (!e)
+    {
+      int f = foo (65535 ^ b);
+      if (bar (!6L <= ~f, ~e) == c)
+	d = 0;
+    }
+}
diff --git a/gcc/testsuite/gcc.dg/pr52558-1.c b/gcc/testsuite/gcc.dg/pr52558-1.c
new file mode 100644
index 00000000000..c34ad0655d3
--- /dev/null
+++ b/gcc/testsuite/gcc.dg/pr52558-1.c
@@ -0,0 +1,22 @@
+/* { dg-do compile } */
+/* { dg-options "--param allow-store-data-races=0 -O2 -fdump-tree-lim1" } */
+
+/* Test that `count' is not written to unless p->data > 0.  */
+
+int count;
+
+struct obj {
+    int data;
+    struct obj *next;
+} *q;
+
+void func()
+{
+  struct obj *p;
+  for (p = q; p; p = p->next)
+    if (p->data > 0)
+      count++;
+}
+
+/* { dg-final { scan-tree-dump-times "MEM count_lsm.. count_lsm_flag" 1 "lim1" } } */
+/* { dg-final { cleanup-tree-dump "lim1" } } */
diff --git a/gcc/testsuite/gcc.dg/pr52558-2.c b/gcc/testsuite/gcc.dg/pr52558-2.c
new file mode 100644
index 00000000000..6d5f51c4f0c
--- /dev/null
+++ b/gcc/testsuite/gcc.dg/pr52558-2.c
@@ -0,0 +1,23 @@
+/* { dg-do compile } */
+/* { dg-options "--param allow-store-data-races=0 -O2 -fdump-tree-lim1" } */
+
+/* Test that g_2 is not written to unless !g_1.  */
+
+int g_1 = 1;
+int g_2 = 0;
+
+int func_1(void)
+{
+ int l;
+ for (l = 0; l < 1234; l++)
+ {
+   if (g_1)
+     return l;
+   else
+     g_2 = 0;
+ }
+ return 999;
+}
+
+/* { dg-final { scan-tree-dump-times "MEM.*g_2_lsm_flag" 1 "lim1" } } */
+/* { dg-final { cleanup-tree-dump "lim1" } } */
diff --git a/gcc/testsuite/gcc.dg/tm/reg-promotion.c b/gcc/testsuite/gcc.dg/tm/reg-promotion.c
new file mode 100644
index 00000000000..337c29f6c6e
--- /dev/null
+++ b/gcc/testsuite/gcc.dg/tm/reg-promotion.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-options "-fgnu-tm -O2 -fdump-tree-lim1" } */
+
+/* Test that `count' is not written to unless p->data>0.  */
+
+int count;
+
+struct obj {
+    int data;
+    struct obj *next;
+} *q;
+
+void func()
+{
+  struct obj *p;
+  __transaction_atomic {
+    for (p = q; p; p = p->next)
+      if (p->data > 0)
+	count++;
+  }
+}
+
+/* { dg-final { scan-tree-dump-times "MEM count_lsm.. count_lsm_flag" 1 "lim1" } } */
+/* { dg-final { cleanup-tree-dump "lim1" } } */
diff --git a/gcc/testsuite/gcc.dg/torture/pr48493.c b/gcc/testsuite/gcc.dg/torture/pr48493.c
new file mode 100644
index 00000000000..ddb61f2e067
--- /dev/null
+++ b/gcc/testsuite/gcc.dg/torture/pr48493.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+
+typedef long long T __attribute__((may_alias, aligned (1)));
+
+struct S
+{
+  _Complex float d __attribute__((aligned (8)));
+};
+
+void bar (struct S);
+
+void
+f1 (T x)
+{
+  struct S s;
+  *(T *) ((char *) &s.d + 1) = x;
+  bar (s);
+}
diff --git a/gcc/testsuite/gcc.dg/torture/pr53501.c b/gcc/testsuite/gcc.dg/torture/pr53501.c
new file mode 100644
index 00000000000..36e3ae61e8f
--- /dev/null
+++ b/gcc/testsuite/gcc.dg/torture/pr53501.c
@@ -0,0 +1,22 @@
+/* { dg-do run } */
+
+extern void abort (void);
+
+int e[100], n, here;
+
+void __attribute__((noinline))
+foo(void)
+{
+  int i, k = 0;
+  for (i = 0; i < n; ++i) { e[k] = 10; ++k; e[k] = 10; ++k; }
+  for (i = 0; i < k; ++i) here = 1;
+  if (here != 1)
+    abort ();
+}
+
+int main(void)
+{
+  n = 10;
+  foo();
+  return 0;
+}
diff --git a/gcc/testsuite/gcc.dg/torture/pr53516.c b/gcc/testsuite/gcc.dg/torture/pr53516.c
new file mode 100644
index 00000000000..7f8094d19cd
--- /dev/null
+++ b/gcc/testsuite/gcc.dg/torture/pr53516.c
@@ -0,0 +1,32 @@
+/* { dg-do run } */
+/* { dg-options "-ftree-vectorize -ftree-loop-distribute-patterns" } */
+
+extern void abort (void);
+
+struct Foo
+{
+  char a : 1;
+  char b : 7;
+};
+
+struct Foo x[256];
+int y[256];
+
+void __attribute__((noinline,noclone)) bar (int n)
+{
+  int i;
+  for (i = 0; i < n; ++i)
+    {
+      x[i].a = 0;
+      y[i] = 3;
+    }
+}
+
+int main()
+{
+  x[5].b = 7;
+  bar (256);
+  if (x[5].b != 7)
+    abort ();
+  return 0;
+}
diff --git a/gcc/testsuite/gcc.dg/tree-ssa/ldist-pr45948-2.c b/gcc/testsuite/gcc.dg/tree-ssa/ldist-pr45948-2.c
new file mode 100644
index 00000000000..aecb49f1c6b
--- /dev/null
+++ b/gcc/testsuite/gcc.dg/tree-ssa/ldist-pr45948-2.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -ftree-loop-distribution -fno-tree-scev-cprop" } */
+
+extern void bar(int);
+
+void
+foo (int i, int n)
+{
+  int a[30];
+  int b[30];
+  for (; i < n; i++)
+    a[i] = b[i] = 0;
+
+  while (1)
+    if (b[0])
+      bar (a[i - 1]);
+}
diff --git a/gcc/testsuite/gcc.dg/vect/slp-perm-8.c b/gcc/testsuite/gcc.dg/vect/slp-perm-8.c
index d211ef943b3..c4854d544b0 100644
--- a/gcc/testsuite/gcc.dg/vect/slp-perm-8.c
+++ b/gcc/testsuite/gcc.dg/vect/slp-perm-8.c
@@ -32,8 +32,7 @@ int main (int argc, const char* argv[])
     {
       input[i] = i;
       output[i] = 0;
-      if (input[i] > 256)
-        abort ();
+      __asm__ volatile ("");
     }
 
   for (i = 0; i < N / 3; i++)
@@ -52,7 +51,8 @@ int main (int argc, const char* argv[])
   return 0;
 }
 
-/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 2 "vect" { target vect_perm_byte } } } */
+/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 2 "vect" { target { vect_perm_byte && vect_char_mult } } } } */
+/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target { vect_perm_byte && {! vect_char_mult } } } } } */
 /* { dg-final { scan-tree-dump-times "vectorizing stmts using SLP" 1 "vect" { target vect_perm_byte } } } */
 /* { dg-final { cleanup-tree-dump "vect" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon-vrev.c b/gcc/testsuite/gcc.target/arm/neon-vrev.c
new file mode 100644
index 00000000000..10f41bc32bb
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon-vrev.c
@@ -0,0 +1,105 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-O2" } */
+/* { dg-add-options arm_neon } */
+
+#include <arm_neon.h>
+
+uint16x4_t
+tst_vrev642_u16 (uint16x4_t __a)
+{
+  uint16x4_t __rv;
+  uint16x4_t __mask1 = { 3, 2, 1, 0};
+  return __builtin_shuffle ( __a, __mask1) ;
+}
+
+uint16x8_t
+tst_vrev64q2_u16 (uint16x8_t __a)
+{
+  uint16x8_t __rv;
+  uint16x8_t __mask1 = {3, 2, 1, 0, 7, 6, 5, 4 };
+  return __builtin_shuffle ( __a, __mask1) ;
+}
+
+uint8x8_t
+tst_vrev642_u8 (uint8x8_t __a)
+{
+  uint8x8_t __rv;
+  uint8x8_t __mask1 = { 7, 6, 5, 4, 3, 2, 1, 0};
+  return __builtin_shuffle ( __a, __mask1) ;
+}
+
+uint8x16_t
+tst_vrev64q2_u8 (uint8x16_t __a)
+{
+  uint8x16_t __rv;
+  uint8x16_t __mask1 = {7, 6, 5, 4, 3, 2, 1, 0, 15, 14, 13, 12, 11, 10, 9, 8};
+  return __builtin_shuffle ( __a, __mask1) ;
+
+}
+
+uint32x2_t
+tst_vrev642_u32 (uint32x2_t __a)
+{
+  uint32x2_t __rv;
+  uint32x2_t __mask1 = {1, 0};
+  return __builtin_shuffle ( __a, __mask1) ;
+
+}
+
+uint32x4_t
+tst_vrev64q2_u32 (uint32x4_t __a)
+{
+  uint32x4_t __rv;
+  uint32x4_t __mask1 = {1, 0, 3, 2};
+  return __builtin_shuffle ( __a, __mask1) ;
+}
+
+uint16x4_t
+tst_vrev322_u16 (uint16x4_t __a)
+{
+  uint16x4_t __mask1 = { 1, 0, 3, 2 };
+  return __builtin_shuffle (__a, __mask1);
+}
+
+uint16x8_t
+tst_vrev32q2_u16 (uint16x8_t __a)
+{
+  uint16x8_t __mask1 = { 1, 0, 3, 2, 5, 4, 7, 6 }; 
+  return __builtin_shuffle (__a, __mask1);
+}
+
+uint8x8_t
+tst_vrev322_u8 (uint8x8_t __a)
+{
+  uint8x8_t __mask1 = { 3, 2, 1, 0, 7, 6, 5, 4};
+  return __builtin_shuffle (__a, __mask1);
+}
+
+uint8x16_t
+tst_vrev32q2_u8 (uint8x16_t __a)
+{
+  uint8x16_t __mask1 = { 3, 2, 1, 0, 7, 6, 5, 4, 11, 10, 9, 8, 15, 14, 13, 12};
+  return __builtin_shuffle (__a, __mask1);
+}
+
+uint8x8_t
+tst_vrev162_u8 (uint8x8_t __a)
+{
+  uint8x8_t __mask = { 1, 0, 3, 2, 5, 4, 7, 6};
+  return __builtin_shuffle (__a, __mask);
+}
+
+uint8x16_t
+tst_vrev16q2_u8 (uint8x16_t __a)
+{
+  uint8x16_t __mask = { 1, 0, 3, 2, 5, 4, 7, 6, 9, 8, 11, 10, 13, 12, 15, 14};
+  return __builtin_shuffle (__a, __mask);
+}
+
+/* { dg-final {scan-assembler-times "vrev32\.16\\t" 2} }  */
+/* { dg-final {scan-assembler-times "vrev32\.8\\t" 2} }  */ 
+/* { dg-final {scan-assembler-times "vrev16\.8\\t" 2} }  */
+/* { dg-final {scan-assembler-times "vrev64\.8\\t" 2} }  */
+/* { dg-final {scan-assembler-times "vrev64\.32\\t" 2} }  */
+/* { dg-final {scan-assembler-times "vrev64\.16\\t" 2} }  */
diff --git a/gcc/testsuite/gcc.target/cris/asm-other.S b/gcc/testsuite/gcc.target/cris/asm-other.S
new file mode 100644
index 00000000000..4fe7ebfc41c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/cris/asm-other.S
@@ -0,0 +1,15 @@
+/* { dg-do assemble } */
+/* { dg-options "-DOTHER_ISA=0 -march=v0" { target crisv32-*-* } } */
+/* { dg-options "-DOTHER_ISA=32 -march=v32" { target cris-*-* } } */
+
+/* Make sure we can assemble for the "other" variant, with the twist
+   that the gcc option -march=v0 isn't valid for the assembler.  */
+        .text
+#if OTHER_ISA == 32
+	addoq 42,$r1,$acr
+#else
+0:
+	move.d [$r2=$r0+42],$r1
+	bwf 0b
+	nop
+#endif
diff --git a/gcc/testsuite/gcc.target/cris/asm-v10.S b/gcc/testsuite/gcc.target/cris/asm-v10.S
new file mode 100644
index 00000000000..c85ebe293bc
--- /dev/null
+++ b/gcc/testsuite/gcc.target/cris/asm-v10.S
@@ -0,0 +1,6 @@
+/* { dg-do assemble } */
+/* { dg-options "-DOTHER_ISA=10 -march=v10" } */
+
+/* Check that -march=v10 is also recognized.  */
+
+#include "asm-other.S"
diff --git a/gcc/testsuite/gcc.target/cris/asm-v8.S b/gcc/testsuite/gcc.target/cris/asm-v8.S
new file mode 100644
index 00000000000..3fba3188454
--- /dev/null
+++ b/gcc/testsuite/gcc.target/cris/asm-v8.S
@@ -0,0 +1,6 @@
+/* { dg-do assemble } */
+/* { dg-options "-DOTHER_ISA=8 -march=v8" } */
+
+/* Check that -march=v8 is also recognized.  */
+
+#include "asm-other.S"
diff --git a/gcc/testsuite/gcc.target/cris/inasm-other.c b/gcc/testsuite/gcc.target/cris/inasm-other.c
new file mode 100644
index 00000000000..c1c043f56d3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/cris/inasm-other.c
@@ -0,0 +1,23 @@
+/* { dg-do assemble } */
+/* { dg-options "-DOTHER_ISA=0 -march=v0" { target crisv32-*-* } } */
+/* { dg-options "-DOTHER_ISA=32 -march=v32" { target cris-*-* } } */
+
+/* Make sure we can (generate code and) assemble for the "other"
+   variant, with the twist that the gcc option -march=v0 isn't
+   valid for the assembler.  We don't check that the generated code
+   is for the other variant; other tests cover that already, but they
+   don't *assemble* the result.  We can't trust the prologue and
+   epilogue to contain incompatible insns (they actually deliberately
+   don't, usually and it'd be brittle to tweak the function signature
+   to make it so), so we force some with inline asm.  */
+
+void f(void)
+{
+#if OTHER_ISA == 32
+  asm volatile ("addoq 42,$r11,$acr");
+#else
+  asm volatile ("0: move.d [$r12=$sp+42],$r10\n\t"
+		"bwf 0b\n\t"
+		"nop");
+#endif
+}
diff --git a/gcc/testsuite/gcc.target/cris/inasm-v10.c b/gcc/testsuite/gcc.target/cris/inasm-v10.c
new file mode 100644
index 00000000000..75379b3c8c2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/cris/inasm-v10.c
@@ -0,0 +1,6 @@
+/* { dg-do assemble } */
+/* { dg-options "-DOTHER_ISA=10 -march=v10" } */
+
+/* Check that -march=v10 is also recognized.  */
+
+#include "inasm-other.c"
diff --git a/gcc/testsuite/gcc.target/cris/inasm-v8.c b/gcc/testsuite/gcc.target/cris/inasm-v8.c
new file mode 100644
index 00000000000..b2fb3053c40
--- /dev/null
+++ b/gcc/testsuite/gcc.target/cris/inasm-v8.c
@@ -0,0 +1,6 @@
+/* { dg-do assemble } */
+/* { dg-options "-DOTHER_ISA=8 -march=v8" } */
+
+/* Check that -march=v8 is also recognized.  */
+
+#include "inasm-other.c"
diff --git a/gcc/testsuite/gcc.target/i386/shuf-concat.c b/gcc/testsuite/gcc.target/i386/shuf-concat.c
new file mode 100644
index 00000000000..04ed4a9dbb8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/shuf-concat.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-O -msse2 -mfpmath=sse" } */
+
+typedef double v2df __attribute__ ((__vector_size__ (16)));
+
+v2df f(double d,double e){
+  v2df x={-d,d};
+  v2df y={-e,e};
+  return __builtin_ia32_shufpd(x,y,1);
+}
+
+/* { dg-final { scan-assembler-not "\tv?shufpd\[ \t\]" } } */
+/* { dg-final { scan-assembler-times "\tv?unpcklpd\[ \t\]" 1 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/powerpc.exp b/gcc/testsuite/gcc.target/powerpc/powerpc.exp
index adc59f5804d..c59e4c3ef4d 100644
--- a/gcc/testsuite/gcc.target/powerpc/powerpc.exp
+++ b/gcc/testsuite/gcc.target/powerpc/powerpc.exp
@@ -23,6 +23,7 @@ if { ![istarget powerpc*-*-*] && ![istarget rs6000-*-*] } then {
 
 # Load support procs.
 load_lib gcc-dg.exp
+load_lib torture-options.exp
 
 # If a testcase doesn't have special options, use these.
 global DEFAULT_CFLAGS
@@ -47,4 +48,5 @@ set-torture-options $SAVRES_TEST_OPTS
 gcc-dg-runtest [list $srcdir/$subdir/savres.c] $alti
 
 # All done.
+torture-finish
 dg-finish
diff --git a/gcc/testsuite/gcc.target/sh/pr51340-1.c b/gcc/testsuite/gcc.target/sh/pr51340-1.c
new file mode 100644
index 00000000000..337d502b9f8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/sh/pr51340-1.c
@@ -0,0 +1,13 @@
+/* Check that the fmac insn is generated when -funsafe-math-optimizations
+   is specified.  */
+/* { dg-do compile { target "sh*-*-*" } } */
+/* { dg-options "-O1 -funsafe-math-optimizations" } */
+/* { dg-skip-if "" { "sh*-*-*" } { "-m1" "-m2" "-m4al" "*nofpu" "-m4-340*" "-m4-400*" "-m4-500*" "-m5*" } { "" } }  */
+/* { dg-final { scan-assembler "fmac" } } */
+
+float
+test_func (float a, float b, float c, float d, float e, float f)
+{
+  return a * b + c * d + e * f;
+}
+
diff --git a/gcc/testsuite/gcc.target/sh/pr51340-2.c b/gcc/testsuite/gcc.target/sh/pr51340-2.c
new file mode 100644
index 00000000000..ef9622ec47f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/sh/pr51340-2.c
@@ -0,0 +1,12 @@
+/* Check that the fmac insn is not generated when -mno-fused-madd is specified.  */
+/* { dg-do compile { target "sh*-*-*" } } */
+/* { dg-options "-O1 -funsafe-math-optimizations -mno-fused-madd" } */
+/* { dg-skip-if "" { "sh*-*-*" } { "-m1" "-m2" "-m4al" "*nofpu" "-m4-340*" "-m4-400*" "-m4-500*" "-m5*" } { "" } }  */
+/* { dg-final { scan-assembler-not "fmac" } } */
+
+float
+test_func (float a, float b, float c, float d, float e, float f)
+{
+  return a * b + c * d + e * f;
+}
+
diff --git a/gcc/testsuite/gcc.target/sh/pr51340-3.c b/gcc/testsuite/gcc.target/sh/pr51340-3.c
new file mode 100644
index 00000000000..d641ae3534e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/sh/pr51340-3.c
@@ -0,0 +1,12 @@
+/* Check that the fmac insn is generated when -mfused-madd is specified.  */
+/* { dg-do compile { target "sh*-*-*" } } */
+/* { dg-options "-O1 -mfused-madd" } */
+/* { dg-skip-if "" { "sh*-*-*" } { "-m1" "-m2" "-m4al" "*nofpu" "-m4-340*" "-m4-400*" "-m4-500*" "-m5*" } { "" } }  */
+/* { dg-final { scan-assembler "fmac" } } */
+
+float
+test_func (float a, float b, float c, float d, float e, float f)
+{
+  return a * b + c * d + e * f;
+}
+
diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp
index b93dc5cda59..568f6b1cc5d 100644
--- a/gcc/testsuite/lib/target-supports.exp
+++ b/gcc/testsuite/lib/target-supports.exp
@@ -3462,7 +3462,8 @@ proc check_effective_target_vect_char_mult { } {
 	set et_vect_char_mult_saved 0
 	if { [istarget ia64-*-*]
 	     || [istarget i?86-*-*]
-	     || [istarget x86_64-*-*] } {
+	     || [istarget x86_64-*-*]
+            || [check_effective_target_arm32] } {
 	   set et_vect_char_mult_saved 1
 	}
     }