2005-04-29 Geoffrey Keating <geoffk@apple.com>

	* config/rs6000/rs6000.md (floatsidf2_internal): Merge to create
	define_insn_and_split.  Split only when memory operand is
	offsettable.  Use adjust_address rather than plus_constant.
	(floatunssidf2_internal): Likewise.
	(fix_truncdfsi2_internal): Split only when memory operand is
	offsettable.  Use adjust_address rather than plus_constant.
	(fix_trunctfsi2_internal): Likewise.
	(floatsidf2_internal): Likewise.

Index: testsuite/ChangeLog
2005-05-02  Geoffrey Keating  <geoffk@apple.com>

	* gcc.dg/rs6000-fpint-2.c: New.


git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@99126 138bc75d-0d04-0410-961f-82ee72b054a4

4 files changed, 56 insertions, 60 deletions

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index d39c6d26d00..b781ed82af5 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,15 @@
+2005-04-29  Geoffrey Keating  <geoffk@apple.com>
+
+	PR target/20813
+	* config/rs6000/rs6000.md (floatsidf2_internal): Merge to create
+	define_insn_and_split.  Split only when memory operand is
+	offsettable.  Use adjust_address rather than plus_constant.
+	(floatunssidf2_internal): Likewise.
+	(fix_truncdfsi2_internal): Split only when memory operand is
+	offsettable.  Use adjust_address rather than plus_constant.
+	(fix_trunctfsi2_internal): Likewise.
+	(floatsidf2_internal): Likewise.
+
 2005-05-02  Diego Novillo  <dnovillo@redhat.com>
 
 	* tree-vrp.c (set_value_range_to_nonnull): Declare inline.
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index c40731ca7ba..790a7098fcf 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -5163,7 +5163,7 @@
   operands[6] = gen_reg_rtx (SImode);
 }")
 
-(define_insn "*floatsidf2_internal"
+(define_insn_and_split "*floatsidf2_internal"
   [(set (match_operand:DF 0 "gpc_reg_operand" "=&f")
 	(float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
    (use (match_operand:SI 2 "gpc_reg_operand" "r"))
@@ -5173,30 +5173,14 @@
    (clobber (match_operand:SI 6 "gpc_reg_operand" "=&r"))]
   "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
   "#"
-  [(set_attr "length" "24")])
-
-(define_split
-  [(set (match_operand:DF 0 "gpc_reg_operand" "")
-	(float:DF (match_operand:SI 1 "gpc_reg_operand" "")))
-   (use (match_operand:SI 2 "gpc_reg_operand" ""))
-   (use (match_operand:DF 3 "gpc_reg_operand" ""))
-   (clobber (match_operand:DF 4 "offsettable_mem_operand" ""))
-   (clobber (match_operand:DF 5 "gpc_reg_operand" ""))
-   (clobber (match_operand:SI 6 "gpc_reg_operand" ""))]
-  "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
-  [(set (match_operand:DF 0 "gpc_reg_operand" "")
-	(float:DF (match_operand:SI 1 "gpc_reg_operand" "")))
-   (use (match_operand:SI 2 "gpc_reg_operand" ""))
-   (use (match_operand:DF 3 "gpc_reg_operand" ""))
-   (clobber (match_operand:DF 4 "offsettable_mem_operand" ""))
-   (clobber (match_operand:DF 5 "gpc_reg_operand" ""))
-   (clobber (match_operand:SI 6 "gpc_reg_operand" ""))]
+  "&& (!no_new_pseudos || offsettable_nonstrict_memref_p (operands[4]))"
+  [(pc)]
   "
 {
   rtx lowword, highword;
-  gcc_assert (GET_CODE (operands[4]) == MEM);
-  highword = XEXP (operands[4], 0);
-  lowword = plus_constant (highword, 4);
+  gcc_assert (MEM_P (operands[4]));
+  highword = adjust_address (operands[4], SImode, 0);
+  lowword = adjust_address (operands[4], SImode, 4);
   if (! WORDS_BIG_ENDIAN)
     {
       rtx tmp;
@@ -5205,12 +5189,13 @@
 
   emit_insn (gen_xorsi3 (operands[6], operands[1],
 			 GEN_INT (~ (HOST_WIDE_INT) 0x7fffffff)));
-  emit_move_insn (gen_rtx_MEM (SImode, lowword), operands[6]);
-  emit_move_insn (gen_rtx_MEM (SImode, highword), operands[2]);
+  emit_move_insn (lowword, operands[6]);
+  emit_move_insn (highword, operands[2]);
   emit_move_insn (operands[5], operands[4]);
   emit_insn (gen_subdf3 (operands[0], operands[5], operands[3]));
   DONE;
-}")
+}"
+  [(set_attr "length" "24")])
 
 (define_expand "floatunssisf2"
   [(set (match_operand:SF 0 "gpc_reg_operand" "")
@@ -5249,7 +5234,7 @@
   operands[5] = gen_reg_rtx (DFmode);
 }")
 
-(define_insn "*floatunssidf2_internal"
+(define_insn_and_split "*floatunssidf2_internal"
   [(set (match_operand:DF 0 "gpc_reg_operand" "=&f")
 	(unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
    (use (match_operand:SI 2 "gpc_reg_operand" "r"))
@@ -5258,40 +5243,27 @@
    (clobber (match_operand:DF 5 "gpc_reg_operand" "=&f"))]
   "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
   "#"
-  [(set_attr "length" "20")])
-
-(define_split
-  [(set (match_operand:DF 0 "gpc_reg_operand" "")
-	(unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "")))
-   (use (match_operand:SI 2 "gpc_reg_operand" ""))
-   (use (match_operand:DF 3 "gpc_reg_operand" ""))
-   (clobber (match_operand:DF 4 "offsettable_mem_operand" ""))
-   (clobber (match_operand:DF 5 "gpc_reg_operand" ""))]
-  "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
-  [(set (match_operand:DF 0 "gpc_reg_operand" "")
-	(unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "")))
-   (use (match_operand:SI 2 "gpc_reg_operand" ""))
-   (use (match_operand:DF 3 "gpc_reg_operand" ""))
-   (clobber (match_operand:DF 4 "offsettable_mem_operand" ""))
-   (clobber (match_operand:DF 5 "gpc_reg_operand" ""))]
+  "&& (!no_new_pseudos || offsettable_nonstrict_memref_p (operands[4]))"
+  [(pc)]
   "
 {
   rtx lowword, highword;
-  gcc_assert (GET_CODE (operands[4]) == MEM);
-  highword = XEXP (operands[4], 0);
-  lowword = plus_constant (highword, 4);
+  gcc_assert (MEM_P (operands[4]));
+  highword = adjust_address (operands[4], SImode, 0);
+  lowword = adjust_address (operands[4], SImode, 4);
   if (! WORDS_BIG_ENDIAN)
     {
       rtx tmp;
       tmp = highword; highword = lowword; lowword = tmp;
     }
 
-  emit_move_insn (gen_rtx_MEM (SImode, lowword), operands[1]);
-  emit_move_insn (gen_rtx_MEM (SImode, highword), operands[2]);
+  emit_move_insn (lowword, operands[1]);
+  emit_move_insn (highword, operands[2]);
   emit_move_insn (operands[5], operands[4]);
   emit_insn (gen_subdf3 (operands[0], operands[5], operands[3]));
   DONE;
-}")
+}"
+  [(set_attr "length" "20")])
 
 ; In the TARGET_PPC_GFXOPT case, this could and probably should
 ; take a memory destination; but actually making this work is hard.
@@ -5331,19 +5303,17 @@
    (clobber (match_operand:DI 3 "memory_operand" "=o"))]
   "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS"
   "#"
-  "&& 1"
+  "&& (!no_new_pseudos || offsettable_nonstrict_memref_p (operands[3]))"
   [(pc)]
   "
 {
   rtx lowword;
-  gcc_assert (GET_CODE (operands[3]) == MEM);
-  lowword = XEXP (operands[3], 0);
-  if (WORDS_BIG_ENDIAN)
-    lowword = plus_constant (lowword, 4);
+  gcc_assert (MEM_P (operands[3]));
+  lowword = adjust_address (operands[3], SImode, WORDS_BIG_ENDIAN ? 4 : 0);
 
   emit_insn (gen_fctiwz (operands[2], operands[1]));
   emit_move_insn (operands[3], operands[2]);
-  emit_move_insn (operands[0], gen_rtx_MEM (SImode, lowword));
+  emit_move_insn (operands[0], lowword);
   DONE;
 }"
   [(set_attr "length" "16")])
@@ -8476,20 +8446,18 @@
   "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
    && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
   "#"
-  "&& reload_completed"
+  "&& (!no_new_pseudos || offsettable_nonstrict_memref_p (operands[5]))"
   [(pc)]
 {
   rtx lowword;
   emit_insn (gen_fix_trunc_helper (operands[2], operands[1], operands[3]));
 
-  gcc_assert (GET_CODE (operands[5]) == MEM);
-  lowword = XEXP (operands[5], 0);
-  if (WORDS_BIG_ENDIAN)
-    lowword = plus_constant (lowword, 4);
+  gcc_assert (MEM_P (operands[5]));
+  lowword = adjust_address (operands[5], SImode, WORDS_BIG_ENDIAN ? 4 : 0);
 
   emit_insn (gen_fctiwz (operands[4], operands[2]));
   emit_move_insn (operands[5], operands[4]);
-  emit_move_insn (operands[0], gen_rtx_MEM (SImode, lowword));
+  emit_move_insn (operands[0], lowword);
   DONE;
 })
 
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index d39b39b755b..573f19109ff 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,8 @@
+2005-05-02  Geoffrey Keating  <geoffk@apple.com>
+
+	PR target/20813
+	* gcc.dg/rs6000-fpint-2.c: New.
+
 2005-05-02  Joseph S. Myers  <joseph@codesourcery.com>
 
 	PR c/15698
diff --git a/gcc/testsuite/gcc.dg/rs6000-fpint-2.c b/gcc/testsuite/gcc.dg/rs6000-fpint-2.c
new file mode 100644
index 00000000000..a2ada5b7dae
--- /dev/null
+++ b/gcc/testsuite/gcc.dg/rs6000-fpint-2.c
@@ -0,0 +1,11 @@
+/* { dg-do compile { target powerpc*-*-* rs6000-*-* } } */
+/* { dg-options "-mno-powerpc-gfxopt -mpowerpc64" } */
+extern void bar (void *);
+extern double x;
+void
+foo (void)
+{
+  char buf2 [32][1024];
+  bar (buf2 [(int) x]);
+}
+