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| author | uros <uros@138bc75d-0d04-0410-961f-82ee72b054a4> | 2005-10-03 05:24:08 +0000 |
|---|---|---|
| committer | uros <uros@138bc75d-0d04-0410-961f-82ee72b054a4> | 2005-10-03 05:24:08 +0000 |
| commit | e1e3944758567303042726f87a25bf01e369dea1 (patch) | |
| tree | 10114132af635929addd6f80325683b4a5947f9a /gcc | |
| parent | 42cb9f7ba99a1104e90b180456133739a85914e1 (diff) | |
| download | gcc-e1e3944758567303042726f87a25bf01e369dea1.tar.gz | |
* lib/target-supports.exp (check_effective_target_vect_shift):
Implement with result caching. Add i?86, x86_64 and ia64 targets.
(check_effective_target_vect_condition): Fix copy-n-pasto.
* gcc.dg/vect/pr22480.c : Enable for effective-target vect_shift.
* gcc.dg/vect/vect-shift-1.c: Remove XFAIL for i?86 and x86_64
targets.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@104888 138bc75d-0d04-0410-961f-82ee72b054a4
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/testsuite/ChangeLog | 10 | ||||
| -rwxr-xr-x | gcc/testsuite/gcc.dg/vect/pr22480.c | 2 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.dg/vect/vect-shift-1.c | 7 | ||||
| -rw-r--r-- | gcc/testsuite/lib/target-supports.exp | 20 |
4 files changed, 26 insertions, 13 deletions
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index d34c5322960..a297cb321bc 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,13 @@ +2005-10-03 Uros Bizjak <uros@kss-loka.si> + + * lib/target-supports.exp (check_effective_target_vect_shift): + Implement with result caching. Add i?86, x86_64 and ia64 targets. + (check_effective_target_vect_condition): Fix copy-n-pasto. + + * gcc.dg/vect/pr22480.c : Enable for effective-target vect_shift. + * gcc.dg/vect/vect-shift-1.c: Remove XFAIL for i?86 and x86_64 + targets. + 2005-10-02 Mark Mitchell <mark@codesourcery.com> PR c++/22621 diff --git a/gcc/testsuite/gcc.dg/vect/pr22480.c b/gcc/testsuite/gcc.dg/vect/pr22480.c index 83f311aa266..a7e238f2271 100755 --- a/gcc/testsuite/gcc.dg/vect/pr22480.c +++ b/gcc/testsuite/gcc.dg/vect/pr22480.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-require-effective-target vect_int } */ +/* { dg-require-effective-target vect_shift } */ void test_1 (void) diff --git a/gcc/testsuite/gcc.dg/vect/vect-shift-1.c b/gcc/testsuite/gcc.dg/vect/vect-shift-1.c index e8b8bc6befc..75070166aae 100644 --- a/gcc/testsuite/gcc.dg/vect/vect-shift-1.c +++ b/gcc/testsuite/gcc.dg/vect/vect-shift-1.c @@ -3,9 +3,6 @@ #include <stdarg.h> #include <signal.h> -#define N 16 -#define MAX 42 - extern void abort(void); int main () @@ -23,7 +20,5 @@ int main () return 0; } - - -/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { xfail i?86-*-* x86_64-*-* } } } */ +/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" } } */ /* { dg-final { cleanup-tree-dump "vect" } } */ diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp index 14426ec82c3..6cbbf146ef3 100644 --- a/gcc/testsuite/lib/target-supports.exp +++ b/gcc/testsuite/lib/target-supports.exp @@ -888,14 +888,22 @@ proc check_effective_target_arm32 { } { # Return 1 if the target supports hardware vector shift operation. proc check_effective_target_vect_shift { } { - if { [istarget powerpc*-*-*] } { - set answer 1 + global et_vect_shift_saved + + if [info exists et_vect_shift_saved] { + verbose "check_effective_target_vect_shift: using cached result" 2 } else { - set answer 0 + set et_vect_shift_saved 0 + if { [istarget powerpc*-*-*] + || [istarget ia64-*-*] + || [istarget i?86-*-*] + || [istarget x86_64-*-*] } { + set et_vect_shift_saved 1 + } } - verbose "check_effective_target_vect_shift: returning $answer" 2 - return $answer + verbose "check_effective_target_vect_shift: returning $et_vect_shift_saved" 2 + return $et_vect_shift_saved } # Return 1 if the target supports hardware vectors of long, 0 otherwise. @@ -1047,7 +1055,7 @@ proc check_effective_target_vect_no_align { } { proc check_effective_target_vect_condition { } { global et_vect_cond_saved - if [info exists et_vect_int_cond] { + if [info exists et_vect_cond_saved] { verbose "check_effective_target_vect_cond: using cached result" 2 } else { set et_vect_cond_saved 0 |