diff options
14 files changed, 32 insertions, 252 deletions
diff --git a/gcc/config/arm/arm-builtins.c b/gcc/config/arm/arm-builtins.c index 33e8015b140..db505a4cbf9 100644 --- a/gcc/config/arm/arm-builtins.c +++ b/gcc/config/arm/arm-builtins.c @@ -811,23 +811,23 @@ arm_ldrgbwbu_z_qualifiers[SIMD_MAX_BUILTIN_ARGS] static enum arm_type_qualifiers arm_strsbwbs_qualifiers[SIMD_MAX_BUILTIN_ARGS] - = { qualifier_void, qualifier_unsigned, qualifier_const, qualifier_none}; + = { qualifier_unsigned, qualifier_unsigned, qualifier_const, qualifier_none}; #define STRSBWBS_QUALIFIERS (arm_strsbwbs_qualifiers) static enum arm_type_qualifiers arm_strsbwbu_qualifiers[SIMD_MAX_BUILTIN_ARGS] - = { qualifier_void, qualifier_unsigned, qualifier_const, qualifier_unsigned}; + = { qualifier_unsigned, qualifier_unsigned, qualifier_const, qualifier_unsigned}; #define STRSBWBU_QUALIFIERS (arm_strsbwbu_qualifiers) static enum arm_type_qualifiers arm_strsbwbs_p_qualifiers[SIMD_MAX_BUILTIN_ARGS] - = { qualifier_void, qualifier_unsigned, qualifier_const, + = { qualifier_unsigned, qualifier_unsigned, qualifier_const, qualifier_none, qualifier_unsigned}; #define STRSBWBS_P_QUALIFIERS (arm_strsbwbs_p_qualifiers) static enum arm_type_qualifiers arm_strsbwbu_p_qualifiers[SIMD_MAX_BUILTIN_ARGS] - = { qualifier_void, qualifier_unsigned, qualifier_const, + = { qualifier_unsigned, qualifier_unsigned, qualifier_const, qualifier_unsigned, qualifier_unsigned}; #define STRSBWBU_P_QUALIFIERS (arm_strsbwbu_p_qualifiers) diff --git a/gcc/config/arm/arm_mve.h b/gcc/config/arm/arm_mve.h index ccdac673d12..6c0d1e2e634 100644 --- a/gcc/config/arm/arm_mve.h +++ b/gcc/config/arm/arm_mve.h @@ -13956,64 +13956,56 @@ __extension__ extern __inline void __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) __arm_vstrdq_scatter_base_wb_s64 (uint64x2_t * __addr, const int __offset, int64x2_t __value) { - __builtin_mve_vstrdq_scatter_base_wb_sv2di (*__addr, __offset, __value); - __builtin_mve_vstrdq_scatter_base_wb_add_sv2di (*__addr, __offset, *__addr); + *__addr = __builtin_mve_vstrdq_scatter_base_wb_sv2di (*__addr, __offset, __value); } __extension__ extern __inline void __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) __arm_vstrdq_scatter_base_wb_u64 (uint64x2_t * __addr, const int __offset, uint64x2_t __value) { - __builtin_mve_vstrdq_scatter_base_wb_uv2di (*__addr, __offset, __value); - __builtin_mve_vstrdq_scatter_base_wb_add_uv2di (*__addr, __offset, *__addr); + *__addr = __builtin_mve_vstrdq_scatter_base_wb_uv2di (*__addr, __offset, __value); } __extension__ extern __inline void __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) __arm_vstrdq_scatter_base_wb_p_s64 (uint64x2_t * __addr, const int __offset, int64x2_t __value, mve_pred16_t __p) { - __builtin_mve_vstrdq_scatter_base_wb_p_sv2di (*__addr, __offset, __value, __p); - __builtin_mve_vstrdq_scatter_base_wb_p_add_sv2di (*__addr, __offset, *__addr, __p); + *__addr = __builtin_mve_vstrdq_scatter_base_wb_p_sv2di (*__addr, __offset, __value, __p); } __extension__ extern __inline void __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) __arm_vstrdq_scatter_base_wb_p_u64 (uint64x2_t * __addr, const int __offset, uint64x2_t __value, mve_pred16_t __p) { - __builtin_mve_vstrdq_scatter_base_wb_p_uv2di (*__addr, __offset, __value, __p); - __builtin_mve_vstrdq_scatter_base_wb_p_add_uv2di (*__addr, __offset, *__addr, __p); + *__addr = __builtin_mve_vstrdq_scatter_base_wb_p_uv2di (*__addr, __offset, __value, __p); } __extension__ extern __inline void __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) __arm_vstrwq_scatter_base_wb_p_s32 (uint32x4_t * __addr, const int __offset, int32x4_t __value, mve_pred16_t __p) { - __builtin_mve_vstrwq_scatter_base_wb_p_sv4si (*__addr, __offset, __value, __p); - __builtin_mve_vstrwq_scatter_base_wb_p_add_sv4si (*__addr, __offset, *__addr, __p); + *__addr = __builtin_mve_vstrwq_scatter_base_wb_p_sv4si (*__addr, __offset, __value, __p); } __extension__ extern __inline void __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) __arm_vstrwq_scatter_base_wb_p_u32 (uint32x4_t * __addr, const int __offset, uint32x4_t __value, mve_pred16_t __p) { - __builtin_mve_vstrwq_scatter_base_wb_p_uv4si (*__addr, __offset, __value, __p); - __builtin_mve_vstrwq_scatter_base_wb_p_add_uv4si (*__addr, __offset, *__addr, __p); + *__addr = __builtin_mve_vstrwq_scatter_base_wb_p_uv4si (*__addr, __offset, __value, __p); } __extension__ extern __inline void __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) __arm_vstrwq_scatter_base_wb_s32 (uint32x4_t * __addr, const int __offset, int32x4_t __value) { - __builtin_mve_vstrwq_scatter_base_wb_sv4si (*__addr, __offset, __value); - __builtin_mve_vstrwq_scatter_base_wb_add_sv4si (*__addr, __offset, *__addr); + *__addr = __builtin_mve_vstrwq_scatter_base_wb_sv4si (*__addr, __offset, __value); } __extension__ extern __inline void __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) __arm_vstrwq_scatter_base_wb_u32 (uint32x4_t * __addr, const int __offset, uint32x4_t __value) { - __builtin_mve_vstrwq_scatter_base_wb_uv4si (*__addr, __offset, __value); - __builtin_mve_vstrwq_scatter_base_wb_add_uv4si (*__addr, __offset, *__addr); + *__addr = __builtin_mve_vstrwq_scatter_base_wb_uv4si (*__addr, __offset, __value); } __extension__ extern __inline uint8x16_t @@ -19128,16 +19120,14 @@ __extension__ extern __inline void __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) __arm_vstrwq_scatter_base_wb_f32 (uint32x4_t * __addr, const int __offset, float32x4_t __value) { - __builtin_mve_vstrwq_scatter_base_wb_fv4sf (*__addr, __offset, __value); - __builtin_mve_vstrwq_scatter_base_wb_add_fv4sf (*__addr, __offset, *__addr); + *__addr = __builtin_mve_vstrwq_scatter_base_wb_fv4sf (*__addr, __offset, __value); } __extension__ extern __inline void __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) __arm_vstrwq_scatter_base_wb_p_f32 (uint32x4_t * __addr, const int __offset, float32x4_t __value, mve_pred16_t __p) { - __builtin_mve_vstrwq_scatter_base_wb_p_fv4sf (*__addr, __offset, __value, __p); - __builtin_mve_vstrwq_scatter_base_wb_p_add_fv4sf (*__addr, __offset, *__addr, __p); + *__addr = __builtin_mve_vstrwq_scatter_base_wb_p_fv4sf (*__addr, __offset, __value, __p); } __extension__ extern __inline float16x8_t diff --git a/gcc/config/arm/arm_mve_builtins.def b/gcc/config/arm/arm_mve_builtins.def index ac928183512..f38926ffd8e 100644 --- a/gcc/config/arm/arm_mve_builtins.def +++ b/gcc/config/arm/arm_mve_builtins.def @@ -826,19 +826,9 @@ VAR3 (QUADOP_UNONE_UNONE_UNONE_IMM_UNONE, vidupq_m_n_u, v16qi, v8hi, v4si) VAR3 (TERNOP_UNONE_UNONE_UNONE_IMM, vdwdupq_n_u, v16qi, v4si, v8hi) VAR3 (TERNOP_UNONE_UNONE_UNONE_IMM, viwdupq_n_u, v16qi, v4si, v8hi) VAR1 (STRSBWBU, vstrwq_scatter_base_wb_u, v4si) -VAR1 (STRSBWBU, vstrwq_scatter_base_wb_add_u, v4si) -VAR1 (STRSBWBU, vstrwq_scatter_base_wb_add_s, v4si) -VAR1 (STRSBWBU, vstrwq_scatter_base_wb_add_f, v4sf) VAR1 (STRSBWBU, vstrdq_scatter_base_wb_u, v2di) -VAR1 (STRSBWBU, vstrdq_scatter_base_wb_add_u, v2di) -VAR1 (STRSBWBU, vstrdq_scatter_base_wb_add_s, v2di) VAR1 (STRSBWBU_P, vstrwq_scatter_base_wb_p_u, v4si) -VAR1 (STRSBWBU_P, vstrwq_scatter_base_wb_p_add_u, v4si) -VAR1 (STRSBWBU_P, vstrwq_scatter_base_wb_p_add_s, v4si) -VAR1 (STRSBWBU_P, vstrwq_scatter_base_wb_p_add_f, v4sf) VAR1 (STRSBWBU_P, vstrdq_scatter_base_wb_p_u, v2di) -VAR1 (STRSBWBU_P, vstrdq_scatter_base_wb_p_add_u, v2di) -VAR1 (STRSBWBU_P, vstrdq_scatter_base_wb_p_add_s, v2di) VAR1 (STRSBWBS, vstrwq_scatter_base_wb_s, v4si) VAR1 (STRSBWBS, vstrwq_scatter_base_wb_f, v4sf) VAR1 (STRSBWBS, vstrdq_scatter_base_wb_s, v2di) diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md index 0d77601fed3..5dad38899be 100644 --- a/gcc/config/arm/mve.md +++ b/gcc/config/arm/mve.md @@ -9700,38 +9700,10 @@ [(set_attr "type" "mve_move") (set_attr "length""8")]) -(define_expand "mve_vstrwq_scatter_base_wb_<supf>v4si" - [(match_operand:V4SI 0 "s_register_operand" "=w") - (match_operand:SI 1 "mve_vldrd_immediate" "Ri") - (match_operand:V4SI 2 "s_register_operand" "w") - (unspec:V4SI [(const_int 0)] VSTRWSBWBQ)] - "TARGET_HAVE_MVE" -{ - rtx ignore_wb = gen_reg_rtx (V4SImode); - emit_insn ( - gen_mve_vstrwq_scatter_base_wb_<supf>v4si_insn (ignore_wb, operands[0], - operands[1], operands[2])); - DONE; -}) - -(define_expand "mve_vstrwq_scatter_base_wb_add_<supf>v4si" - [(match_operand:V4SI 0 "s_register_operand" "=w") - (match_operand:SI 1 "mve_vldrd_immediate" "Ri") - (match_operand:V4SI 2 "s_register_operand" "0") - (unspec:V4SI [(const_int 0)] VSTRWSBWBQ)] - "TARGET_HAVE_MVE" -{ - rtx ignore_vec = gen_reg_rtx (V4SImode); - emit_insn ( - gen_mve_vstrwq_scatter_base_wb_<supf>v4si_insn (operands[0], operands[2], - operands[1], ignore_vec)); - DONE; -}) - ;; -;; [vstrwq_scatter_base_wb_s vstrdq_scatter_base_wb_u] +;; [vstrwq_scatter_base_wb_s vstrwq_scatter_base_wb_u] ;; -(define_insn "mve_vstrwq_scatter_base_wb_<supf>v4si_insn" +(define_insn "mve_vstrwq_scatter_base_wb_<supf>v4si" [(set (mem:BLK (scratch)) (unspec:BLK [(match_operand:V4SI 1 "s_register_operand" "0") @@ -9753,42 +9725,10 @@ } [(set_attr "length" "4")]) -(define_expand "mve_vstrwq_scatter_base_wb_p_<supf>v4si" - [(match_operand:V4SI 0 "s_register_operand" "=w") - (match_operand:SI 1 "mve_vldrd_immediate" "Ri") - (match_operand:V4SI 2 "s_register_operand" "w") - (match_operand:HI 3 "vpr_register_operand") - (unspec:V4SI [(const_int 0)] VSTRWSBWBQ)] - "TARGET_HAVE_MVE" -{ - rtx ignore_wb = gen_reg_rtx (V4SImode); - emit_insn ( - gen_mve_vstrwq_scatter_base_wb_p_<supf>v4si_insn (ignore_wb, operands[0], - operands[1], operands[2], - operands[3])); - DONE; -}) - -(define_expand "mve_vstrwq_scatter_base_wb_p_add_<supf>v4si" - [(match_operand:V4SI 0 "s_register_operand" "=w") - (match_operand:SI 1 "mve_vldrd_immediate" "Ri") - (match_operand:V4SI 2 "s_register_operand" "0") - (match_operand:HI 3 "vpr_register_operand") - (unspec:V4SI [(const_int 0)] VSTRWSBWBQ)] - "TARGET_HAVE_MVE" -{ - rtx ignore_vec = gen_reg_rtx (V4SImode); - emit_insn ( - gen_mve_vstrwq_scatter_base_wb_p_<supf>v4si_insn (operands[0], operands[2], - operands[1], ignore_vec, - operands[3])); - DONE; -}) - ;; ;; [vstrwq_scatter_base_wb_p_s vstrwq_scatter_base_wb_p_u] ;; -(define_insn "mve_vstrwq_scatter_base_wb_p_<supf>v4si_insn" +(define_insn "mve_vstrwq_scatter_base_wb_p_<supf>v4si" [(set (mem:BLK (scratch)) (unspec:BLK [(match_operand:V4SI 1 "s_register_operand" "0") @@ -9811,38 +9751,10 @@ } [(set_attr "length" "8")]) -(define_expand "mve_vstrwq_scatter_base_wb_fv4sf" - [(match_operand:V4SI 0 "s_register_operand" "=w") - (match_operand:SI 1 "mve_vldrd_immediate" "Ri") - (match_operand:V4SF 2 "s_register_operand" "w") - (unspec:V4SI [(const_int 0)] VSTRWQSBWB_F)] - "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" -{ - rtx ignore_wb = gen_reg_rtx (V4SImode); - emit_insn ( - gen_mve_vstrwq_scatter_base_wb_fv4sf_insn (ignore_wb,operands[0], - operands[1], operands[2])); - DONE; -}) - -(define_expand "mve_vstrwq_scatter_base_wb_add_fv4sf" - [(match_operand:V4SI 0 "s_register_operand" "=w") - (match_operand:SI 1 "mve_vldrd_immediate" "Ri") - (match_operand:V4SI 2 "s_register_operand" "0") - (unspec:V4SI [(const_int 0)] VSTRWQSBWB_F)] - "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" -{ - rtx ignore_vec = gen_reg_rtx (V4SFmode); - emit_insn ( - gen_mve_vstrwq_scatter_base_wb_fv4sf_insn (operands[0], operands[2], - operands[1], ignore_vec)); - DONE; -}) - ;; ;; [vstrwq_scatter_base_wb_f] ;; -(define_insn "mve_vstrwq_scatter_base_wb_fv4sf_insn" +(define_insn "mve_vstrwq_scatter_base_wb_fv4sf" [(set (mem:BLK (scratch)) (unspec:BLK [(match_operand:V4SI 1 "s_register_operand" "0") @@ -9864,42 +9776,10 @@ } [(set_attr "length" "4")]) -(define_expand "mve_vstrwq_scatter_base_wb_p_fv4sf" - [(match_operand:V4SI 0 "s_register_operand" "=w") - (match_operand:SI 1 "mve_vldrd_immediate" "Ri") - (match_operand:V4SF 2 "s_register_operand" "w") - (match_operand:HI 3 "vpr_register_operand") - (unspec:V4SI [(const_int 0)] VSTRWQSBWB_F)] - "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" -{ - rtx ignore_wb = gen_reg_rtx (V4SImode); - emit_insn ( - gen_mve_vstrwq_scatter_base_wb_p_fv4sf_insn (ignore_wb, operands[0], - operands[1], operands[2], - operands[3])); - DONE; -}) - -(define_expand "mve_vstrwq_scatter_base_wb_p_add_fv4sf" - [(match_operand:V4SI 0 "s_register_operand" "=w") - (match_operand:SI 1 "mve_vldrd_immediate" "Ri") - (match_operand:V4SI 2 "s_register_operand" "0") - (match_operand:HI 3 "vpr_register_operand") - (unspec:V4SI [(const_int 0)] VSTRWQSBWB_F)] - "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" -{ - rtx ignore_vec = gen_reg_rtx (V4SFmode); - emit_insn ( - gen_mve_vstrwq_scatter_base_wb_p_fv4sf_insn (operands[0], operands[2], - operands[1], ignore_vec, - operands[3])); - DONE; -}) - ;; ;; [vstrwq_scatter_base_wb_p_f] ;; -(define_insn "mve_vstrwq_scatter_base_wb_p_fv4sf_insn" +(define_insn "mve_vstrwq_scatter_base_wb_p_fv4sf" [(set (mem:BLK (scratch)) (unspec:BLK [(match_operand:V4SI 1 "s_register_operand" "0") @@ -9922,38 +9802,10 @@ } [(set_attr "length" "8")]) -(define_expand "mve_vstrdq_scatter_base_wb_<supf>v2di" - [(match_operand:V2DI 0 "s_register_operand" "=w") - (match_operand:SI 1 "mve_vldrd_immediate" "Ri") - (match_operand:V2DI 2 "s_register_operand" "w") - (unspec:V2DI [(const_int 0)] VSTRDSBWBQ)] - "TARGET_HAVE_MVE" -{ - rtx ignore_wb = gen_reg_rtx (V2DImode); - emit_insn ( - gen_mve_vstrdq_scatter_base_wb_<supf>v2di_insn (ignore_wb, operands[0], - operands[1], operands[2])); - DONE; -}) - -(define_expand "mve_vstrdq_scatter_base_wb_add_<supf>v2di" - [(match_operand:V2DI 0 "s_register_operand" "=w") - (match_operand:SI 1 "mve_vldrd_immediate" "Ri") - (match_operand:V2DI 2 "s_register_operand" "0") - (unspec:V2DI [(const_int 0)] VSTRDSBWBQ)] - "TARGET_HAVE_MVE" -{ - rtx ignore_vec = gen_reg_rtx (V2DImode); - emit_insn ( - gen_mve_vstrdq_scatter_base_wb_<supf>v2di_insn (operands[0], operands[2], - operands[1], ignore_vec)); - DONE; -}) - ;; ;; [vstrdq_scatter_base_wb_s vstrdq_scatter_base_wb_u] ;; -(define_insn "mve_vstrdq_scatter_base_wb_<supf>v2di_insn" +(define_insn "mve_vstrdq_scatter_base_wb_<supf>v2di" [(set (mem:BLK (scratch)) (unspec:BLK [(match_operand:V2DI 1 "s_register_operand" "0") @@ -9975,42 +9827,10 @@ } [(set_attr "length" "4")]) -(define_expand "mve_vstrdq_scatter_base_wb_p_<supf>v2di" - [(match_operand:V2DI 0 "s_register_operand" "=w") - (match_operand:SI 1 "mve_vldrd_immediate" "Ri") - (match_operand:V2DI 2 "s_register_operand" "w") - (match_operand:HI 3 "vpr_register_operand") - (unspec:V2DI [(const_int 0)] VSTRDSBWBQ)] - "TARGET_HAVE_MVE" -{ - rtx ignore_wb = gen_reg_rtx (V2DImode); - emit_insn ( - gen_mve_vstrdq_scatter_base_wb_p_<supf>v2di_insn (ignore_wb, operands[0], - operands[1], operands[2], - operands[3])); - DONE; -}) - -(define_expand "mve_vstrdq_scatter_base_wb_p_add_<supf>v2di" - [(match_operand:V2DI 0 "s_register_operand" "=w") - (match_operand:SI 1 "mve_vldrd_immediate" "Ri") - (match_operand:V2DI 2 "s_register_operand" "0") - (match_operand:HI 3 "vpr_register_operand") - (unspec:V2DI [(const_int 0)] VSTRDSBWBQ)] - "TARGET_HAVE_MVE" -{ - rtx ignore_vec = gen_reg_rtx (V2DImode); - emit_insn ( - gen_mve_vstrdq_scatter_base_wb_p_<supf>v2di_insn (operands[0], operands[2], - operands[1], ignore_vec, - operands[3])); - DONE; -}) - ;; ;; [vstrdq_scatter_base_wb_p_s vstrdq_scatter_base_wb_p_u] ;; -(define_insn "mve_vstrdq_scatter_base_wb_p_<supf>v2di_insn" +(define_insn "mve_vstrdq_scatter_base_wb_p_<supf>v2di" [(set (mem:BLK (scratch)) (unspec:BLK [(match_operand:V2DI 1 "s_register_operand" "0") @@ -10028,7 +9848,7 @@ ops[0] = operands[1]; ops[1] = operands[2]; ops[2] = operands[3]; - output_asm_insn ("vpst\;\tvstrdt.u64\t%q2, [%q0, %1]!",ops); + output_asm_insn ("vpst;vstrdt.u64\t%q2, [%q0, %1]!",ops); return ""; } [(set_attr "length" "8")]) diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_wb_p_s64.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_wb_p_s64.c index 6570d4abd23..319188b706f 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_wb_p_s64.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_wb_p_s64.c @@ -10,12 +10,10 @@ foo (uint64x2_t * addr, const int offset, int64x2_t value, mve_pred16_t p) vstrdq_scatter_base_wb_p_s64 (addr, 8, value, p); } -/* { dg-final { scan-assembler "vstrdt.u64" } } */ - void foo1 (uint64x2_t * addr, const int offset, int64x2_t value, mve_pred16_t p) { vstrdq_scatter_base_wb_p (addr, 8, value, p); } -/* { dg-final { scan-assembler "vstrdt.u64" } } */ +/* { dg-final { scan-assembler-times "vstrdt.u64\tq\[0-9\]+, \\\[q\[0-9\]+, #\[0-9\]+\\\]!" 2 } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_wb_p_u64.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_wb_p_u64.c index 8444a3acd4c..940b5421c84 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_wb_p_u64.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_wb_p_u64.c @@ -10,12 +10,10 @@ foo (uint64x2_t * addr, const int offset, uint64x2_t value, mve_pred16_t p) vstrdq_scatter_base_wb_p_u64 (addr, 8, value, p); } -/* { dg-final { scan-assembler "vstrdt.u64" } } */ - void foo1 (uint64x2_t * addr, const int offset, uint64x2_t value, mve_pred16_t p) { vstrdq_scatter_base_wb_p (addr, 8, value, p); } -/* { dg-final { scan-assembler "vstrdt.u64" } } */ +/* { dg-final { scan-assembler-times "vstrdt.u64\tq\[0-9\]+, \\\[q\[0-9\]+, #\[0-9\]+\\\]!" 2 } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_wb_s64.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_wb_s64.c index e0ec283d100..33926d5c9e2 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_wb_s64.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_wb_s64.c @@ -10,12 +10,10 @@ foo (uint64x2_t * addr, const int offset, int64x2_t value) vstrdq_scatter_base_wb_s64 (addr, 8, value); } -/* { dg-final { scan-assembler "vstrd.u64" } } */ - void foo1 (uint64x2_t * addr, const int offset, int64x2_t value) { vstrdq_scatter_base_wb (addr, 8, value); } -/* { dg-final { scan-assembler "vstrd.u64" } } */ +/* { dg-final { scan-assembler-times "vstrd.u64\tq\[0-9\]+, \\\[q\[0-9\]+, #\[0-9\]+\\\]!" 2 } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_wb_u64.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_wb_u64.c index fe41d6b5c74..b7ffcf9b5dd 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_wb_u64.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_base_wb_u64.c @@ -10,12 +10,10 @@ foo (uint64x2_t * addr, const int offset, uint64x2_t value) vstrdq_scatter_base_wb_u64 (addr, 8, value); } -/* { dg-final { scan-assembler "vstrd.u64" } } */ - void foo1 (uint64x2_t * addr, const int offset, uint64x2_t value) { vstrdq_scatter_base_wb (addr, 8, value); } -/* { dg-final { scan-assembler "vstrd.u64" } } */ +/* { dg-final { scan-assembler-times "vstrd.u64\tq\[0-9\]+, \\\[q\[0-9\]+, #\[0-9\]+\\\]!" 2 } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_f32.c index f4ceabb8680..b2cc6e555ae 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_f32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_f32.c @@ -10,12 +10,10 @@ foo (uint32x4_t * addr, const int offset, float32x4_t value) vstrwq_scatter_base_wb_f32 (addr, 8, value); } -/* { dg-final { scan-assembler "vstrw.u32" } } */ - void foo1 (uint32x4_t * addr, const int offset, float32x4_t value) { vstrwq_scatter_base_wb (addr, 8, value); } -/* { dg-final { scan-assembler "vstrw.u32" } } */ +/* { dg-final { scan-assembler-times "vstrw.u32\tq\[0-9\]+, \\\[q\[0-9\]+, #\[0-9\]+\\\]!" 2 } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_p_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_p_f32.c index cb2eb685139..4befd49d7b9 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_p_f32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_p_f32.c @@ -10,12 +10,10 @@ foo (uint32x4_t * addr, const int offset, float32x4_t value, mve_pred16_t p) vstrwq_scatter_base_wb_p_f32 (addr, 8, value, p); } -/* { dg-final { scan-assembler "vstrwt.u32" } } */ - void foo1 (uint32x4_t * addr, const int offset, float32x4_t value, mve_pred16_t p) { vstrwq_scatter_base_wb_p (addr, 8, value, p); } -/* { dg-final { scan-assembler "vstrwt.u32" } } */ +/* { dg-final { scan-assembler-times "vstrwt.u32\tq\[0-9\]+, \\\[q\[0-9\]+, #\[0-9\]+\\\]!" 2 } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_p_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_p_s32.c index d973c021ba3..dfb1827c4f0 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_p_s32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_p_s32.c @@ -10,12 +10,10 @@ foo (uint32x4_t * addr, const int offset, int32x4_t value, mve_pred16_t p) vstrwq_scatter_base_wb_p_s32 (addr, 8, value, p); } -/* { dg-final { scan-assembler "vstrwt.u32" } } */ - void foo1 (uint32x4_t * addr, const int offset, int32x4_t value, mve_pred16_t p) { vstrwq_scatter_base_wb_p (addr, 8, value, p); } -/* { dg-final { scan-assembler "vstrwt.u32" } } */ +/* { dg-final { scan-assembler-times "vstrwt.u32\tq\[0-9\]+, \\\[q\[0-9\]+, #\[0-9\]+\\\]!" 2 } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_p_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_p_u32.c index c0f0964c657..4eb78c600be 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_p_u32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_p_u32.c @@ -10,12 +10,10 @@ foo (uint32x4_t * addr, const int offset, uint32x4_t value, mve_pred16_t p) vstrwq_scatter_base_wb_p_u32 (addr, 8, value, p); } -/* { dg-final { scan-assembler "vstrwt.u32" } } */ - void foo1 (uint32x4_t * addr, const int offset, uint32x4_t value, mve_pred16_t p) { vstrwq_scatter_base_wb_p (addr, 8, value, p); } -/* { dg-final { scan-assembler "vstrwt.u32" } } */ +/* { dg-final { scan-assembler-times "vstrwt.u32\tq\[0-9\]+, \\\[q\[0-9\]+, #\[0-9\]+\\\]!" 2 } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_s32.c index 6ef095526e5..618dbaf5aa6 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_s32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_s32.c @@ -10,12 +10,10 @@ foo (uint32x4_t * addr, const int offset, int32x4_t value) vstrwq_scatter_base_wb_s32 (addr, 8, value); } -/* { dg-final { scan-assembler "vstrw.u32" } } */ - void foo1 (uint32x4_t * addr, const int offset, int32x4_t value) { vstrwq_scatter_base_wb (addr, 8, value); } -/* { dg-final { scan-assembler "vstrw.u32" } } */ +/* { dg-final { scan-assembler-times "vstrw.u32\tq\[0-9\]+, \\\[q\[0-9\]+, #\[0-9\]+\\\]!" 2 } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_u32.c index 620dffa8391..912a4590cf5 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_u32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_u32.c @@ -10,12 +10,10 @@ foo (uint32x4_t * addr, uint32x4_t value) vstrwq_scatter_base_wb_u32 (addr, 8, value); } -/* { dg-final { scan-assembler "vstrw.u32" } } */ - void foo1 (uint32x4_t * addr, uint32x4_t value) { vstrwq_scatter_base_wb (addr, 8, value); } -/* { dg-final { scan-assembler "vstrw.u32" } } */ +/* { dg-final { scan-assembler-times "vstrw.u32\tq\[0-9\]+, \\\[q\[0-9\]+, #\[0-9\]+\\\]!" 2 } } */ |