diff options
| -rw-r--r-- | gcc/ChangeLog | 15 | ||||
| -rw-r--r-- | gcc/config/mips/mips.md | 6 | ||||
| -rw-r--r-- | gcc/testsuite/ChangeLog | 9 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/mips/pr37362.c | 19 |
4 files changed, 40 insertions, 9 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index fc9a9fe2d2c..a32aa1297a8 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,12 @@ +2008-11-18 Uros Bizjak <ubizjak@gmail.com> + + PR target/37362 + * config/mips/mips.md (move_doubleword_fpr<mode>): Check that "high" + is a register or zero operand in the correct mode before generating + mtch1 insn or a register operand in the correct mode before generating + mfch1 insn. + (mtch1<mode>): Correct operand 1 predicate to reg_or_0_operand. + 2008-11-18 Adam Nemet <anemet@caviumnetworks.com> * config.gcc (mips*-sde-elf*): Handle mipsisa64r2*. @@ -209,11 +218,9 @@ * ira-color.c (push_allocnos_to_stack): Check ALLOCNO_BAD_SPILL_P. - * ira-build.c (ira_create_allocno): Initialize - ALLOCNO_BAD_SPILL_P. + * ira-build.c (ira_create_allocno): Initialize ALLOCNO_BAD_SPILL_P. (create_cap_allocno, propagate_allocno_info, - remove_unnecessary_allocnos): Set up or update - ALLOCNO_BAD_SPILL_P. + remove_unnecessary_allocnos): Set up or update ALLOCNO_BAD_SPILL_P. (update_bad_spill_attribute): New function. (ira_build): Call it. diff --git a/gcc/config/mips/mips.md b/gcc/config/mips/mips.md index 92e637c5a58..22fcc8875cb 100644 --- a/gcc/config/mips/mips.md +++ b/gcc/config/mips/mips.md @@ -4508,7 +4508,7 @@ rtx low = mips_subword (operands[1], 0); rtx high = mips_subword (operands[1], 1); emit_insn (gen_load_low<mode> (operands[0], low)); - if (ISA_HAS_MXHC1) + if (ISA_HAS_MXHC1 && reg_or_0_operand (high, <HALFMODE>mode)) emit_insn (gen_mthc1<mode> (operands[0], high, operands[0])); else emit_insn (gen_load_high<mode> (operands[0], high, operands[0])); @@ -4518,7 +4518,7 @@ rtx low = mips_subword (operands[0], 0); rtx high = mips_subword (operands[0], 1); emit_insn (gen_store_word<mode> (low, operands[1], const0_rtx)); - if (ISA_HAS_MXHC1) + if (ISA_HAS_MXHC1 && register_operand (high, <HALFMODE>mode)) emit_insn (gen_mfhc1<mode> (high, operands[1])); else emit_insn (gen_store_word<mode> (high, operands[1], const1_rtx)); @@ -4573,7 +4573,7 @@ ;; value in the low word. (define_insn "mthc1<mode>" [(set (match_operand:SPLITF 0 "register_operand" "=f") - (unspec:SPLITF [(match_operand:<HALFMODE> 1 "general_operand" "dJ") + (unspec:SPLITF [(match_operand:<HALFMODE> 1 "reg_or_0_operand" "dJ") (match_operand:SPLITF 2 "register_operand" "0")] UNSPEC_MTHC1))] "TARGET_HARD_FLOAT && ISA_HAS_MXHC1" diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 8ed4c3b9b75..27c26a315b5 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,8 @@ +2008-11-18 Uros Bizjak <ubizjak@gmail.com> + + PR target/37362 + * gcc.target/mips/pr37362.c: New test. + 2008-11-18 Jason Merrill <jason@redhat.com> Jakub Jelinek <jakub@redhat.com> @@ -42,8 +47,8 @@ * gcc.dg/pr38140.c: New test. 2008-11-17 Jack Howarth <howarth@bromo.med.uc.edu> - - PR testsuite/38099 + + PR testsuite/38099 * gcc.dg/compat/struct-layout-1_generate.c: Also use -no-mmx on i?86/x86_64 darwin. * g++.dg/compat/struct-layout-1_generate.c: Same. diff --git a/gcc/testsuite/gcc.target/mips/pr37362.c b/gcc/testsuite/gcc.target/mips/pr37362.c new file mode 100644 index 00000000000..a356b787035 --- /dev/null +++ b/gcc/testsuite/gcc.target/mips/pr37362.c @@ -0,0 +1,19 @@ +/* { dg-do compile } */ +/* { dg-mips-options "-march=mips64r2 -mabi=n32" } */ + +typedef float TFtype __attribute__((mode(TF))); + +TFtype +__powitf (TFtype x, int m) +{ + unsigned int n = m < 0 ? -m : m; + TFtype y = n % 2 ? x : 1; + while (n >>= 1) + { + x = x * x; + if (n % 2) + y = y * x; + } + return m < 0 ? 1/y : y; +} + |