diff options
Diffstat (limited to 'gcc/config/i386/i386.md')
| -rw-r--r-- | gcc/config/i386/i386.md | 41 |
1 files changed, 39 insertions, 2 deletions
diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md index 5fcebb5cc6a..d0c0d23df28 100644 --- a/gcc/config/i386/i386.md +++ b/gcc/config/i386/i386.md @@ -408,7 +408,7 @@ ;; Processor type. (define_attr "cpu" "none,pentium,pentiumpro,geode,k6,athlon,k8,core2,nehalem, atom,slm,haswell,generic,amdfam10,bdver1,bdver2,bdver3, - bdver4,btver2" + bdver4,btver2,znver1" (const (symbol_ref "ix86_schedule"))) ;; A basic instruction type. Refinements due to arguments to be @@ -1170,6 +1170,7 @@ (include "bdver1.md") (include "bdver3.md") (include "btver2.md") +(include "znver1.md") (include "geode.md") (include "atom.md") (include "slm.md") @@ -1673,6 +1674,7 @@ (set_attr "athlon_decode" "vector") (set_attr "amdfam10_decode" "direct") (set_attr "bdver1_decode" "double") + (set_attr "znver1_decode" "double") (set (attr "enabled") (cond [(eq_attr "alternative" "0") (symbol_ref "TARGET_MIX_SSE_I387") @@ -1692,7 +1694,8 @@ (set_attr "mode" "<X87MODEF:MODE>") (set_attr "athlon_decode" "vector") (set_attr "amdfam10_decode" "direct") - (set_attr "bdver1_decode" "double")]) + (set_attr "bdver1_decode" "double") + (set_attr "znver1_decode" "double")]) ;; Push/pop instructions. @@ -4013,6 +4016,10 @@ (eq_attr "alternative" "0")) (const_string "0") (const_string "1"))) + (set (attr "znver1_decode") + (if_then_else (eq_attr "prefix_0f" "0") + (const_string "double") + (const_string "direct"))) (set (attr "modrm") (if_then_else (eq_attr "prefix_0f" "0") (const_string "0") @@ -4964,6 +4971,7 @@ "fild%Z1\t%1" [(set_attr "type" "fmov") (set_attr "mode" "<MODE>") + (set_attr "znver1_decode" "double") (set_attr "fp_int_src" "true")]) (define_insn "float<SWI48x:mode>xf2" @@ -4973,6 +4981,7 @@ "fild%Z1\t%1" [(set_attr "type" "fmov") (set_attr "mode" "XF") + (set_attr "znver1_decode" "double") (set_attr "fp_int_src" "true")]) (define_expand "float<SWI48:mode><MODEF:mode>2" @@ -5022,6 +5031,7 @@ (set_attr "athlon_decode" "*,double,direct") (set_attr "amdfam10_decode" "*,vector,double") (set_attr "bdver1_decode" "*,double,direct") + (set_attr "znver1_decode" "double,*,*") (set_attr "fp_int_src" "true") (set (attr "enabled") (cond [(eq_attr "alternative" "0") @@ -5042,6 +5052,7 @@ "fild%Z1\t%1" [(set_attr "type" "fmov") (set_attr "mode" "<MODEF:MODE>") + (set_attr "znver1_decode" "double") (set_attr "fp_int_src" "true")]) ;; Try TARGET_USE_VECTOR_CONVERTS, but not so hard as to require extra memory @@ -10810,6 +10821,7 @@ "bts{q}\t{%1, %0|%0, %1}" [(set_attr "type" "alu1") (set_attr "prefix_0f" "1") + (set_attr "znver1_decode" "double") (set_attr "mode" "DI")]) (define_insn "*btrq" @@ -10822,6 +10834,7 @@ "btr{q}\t{%1, %0|%0, %1}" [(set_attr "type" "alu1") (set_attr "prefix_0f" "1") + (set_attr "znver1_decode" "double") (set_attr "mode" "DI")]) (define_insn "*btcq" @@ -10834,6 +10847,7 @@ "btc{q}\t{%1, %0|%0, %1}" [(set_attr "type" "alu1") (set_attr "prefix_0f" "1") + (set_attr "znver1_decode" "double") (set_attr "mode" "DI")]) ;; Allow Nocona to avoid these instructions if a register is available. @@ -12513,6 +12527,7 @@ [(set_attr "type" "alu1") (set_attr "prefix_0f" "1") (set_attr "btver2_decode" "double") + (set_attr "znver1_decode" "vector") (set_attr "mode" "<MODE>")]) (define_expand "ctz<mode>2" @@ -12991,6 +13006,7 @@ "bsr{q}\t{%1, %0|%0, %1}" [(set_attr "type" "alu1") (set_attr "prefix_0f" "1") + (set_attr "znver1_decode" "vector") (set_attr "mode" "DI")]) (define_insn "bsr" @@ -13002,6 +13018,7 @@ "bsr{l}\t{%1, %0|%0, %1}" [(set_attr "type" "alu1") (set_attr "prefix_0f" "1") + (set_attr "znver1_decode" "vector") (set_attr "mode" "SI")]) (define_insn "*bsrhi" @@ -13013,6 +13030,7 @@ "bsr{w}\t{%1, %0|%0, %1}" [(set_attr "type" "alu1") (set_attr "prefix_0f" "1") + (set_attr "znver1_decode" "vector") (set_attr "mode" "HI")]) (define_expand "popcount<mode>2" @@ -14164,6 +14182,7 @@ && flag_finite_math_only" "fprem" [(set_attr "type" "fpspc") + (set_attr "znver1_decode" "vector") (set_attr "mode" "XF")]) (define_expand "fmodxf3" @@ -14238,6 +14257,7 @@ && flag_finite_math_only" "fprem1" [(set_attr "type" "fpspc") + (set_attr "znver1_decode" "vector") (set_attr "mode" "XF")]) (define_expand "remainderxf3" @@ -14314,6 +14334,7 @@ && flag_unsafe_math_optimizations" "f<sincos>" [(set_attr "type" "fpspc") + (set_attr "znver1_decode" "vector") (set_attr "mode" "XF")]) (define_insn "*<sincos>_extend<mode>xf2_i387" @@ -14327,6 +14348,7 @@ && flag_unsafe_math_optimizations" "f<sincos>" [(set_attr "type" "fpspc") + (set_attr "znver1_decode" "vector") (set_attr "mode" "XF")]) ;; When sincos pattern is defined, sin and cos builtin functions will be @@ -14345,6 +14367,7 @@ && flag_unsafe_math_optimizations" "fsincos" [(set_attr "type" "fpspc") + (set_attr "znver1_decode" "vector") (set_attr "mode" "XF")]) (define_split @@ -14380,6 +14403,7 @@ && flag_unsafe_math_optimizations" "fsincos" [(set_attr "type" "fpspc") + (set_attr "znver1_decode" "vector") (set_attr "mode" "XF")]) (define_split @@ -14435,6 +14459,7 @@ && standard_80387_constant_p (operands[3]) == 2" "fptan" [(set_attr "type" "fpspc") + (set_attr "znver1_decode" "vector") (set_attr "mode" "XF")]) (define_insn "fptan_extend<mode>xf4_i387" @@ -14451,6 +14476,7 @@ && standard_80387_constant_p (operands[3]) == 2" "fptan" [(set_attr "type" "fpspc") + (set_attr "znver1_decode" "vector") (set_attr "mode" "XF")]) (define_expand "tanxf2" @@ -14495,6 +14521,7 @@ && flag_unsafe_math_optimizations" "fpatan" [(set_attr "type" "fpspc") + (set_attr "znver1_decode" "vector") (set_attr "mode" "XF")]) (define_insn "fpatan_extend<mode>xf3_i387" @@ -14511,6 +14538,7 @@ && flag_unsafe_math_optimizations" "fpatan" [(set_attr "type" "fpspc") + (set_attr "znver1_decode" "vector") (set_attr "mode" "XF")]) (define_expand "atan2xf3" @@ -14667,6 +14695,7 @@ && flag_unsafe_math_optimizations" "fyl2x" [(set_attr "type" "fpspc") + (set_attr "znver1_decode" "vector") (set_attr "mode" "XF")]) (define_insn "fyl2x_extend<mode>xf3_i387" @@ -14682,6 +14711,7 @@ && flag_unsafe_math_optimizations" "fyl2x" [(set_attr "type" "fpspc") + (set_attr "znver1_decode" "vector") (set_attr "mode" "XF")]) (define_expand "logxf2" @@ -14784,6 +14814,7 @@ && flag_unsafe_math_optimizations" "fyl2xp1" [(set_attr "type" "fpspc") + (set_attr "znver1_decode" "vector") (set_attr "mode" "XF")]) (define_insn "fyl2xp1_extend<mode>xf3_i387" @@ -14799,6 +14830,7 @@ && flag_unsafe_math_optimizations" "fyl2xp1" [(set_attr "type" "fpspc") + (set_attr "znver1_decode" "vector") (set_attr "mode" "XF")]) (define_expand "log1pxf2" @@ -14846,6 +14878,7 @@ && flag_unsafe_math_optimizations" "fxtract" [(set_attr "type" "fpspc") + (set_attr "znver1_decode" "vector") (set_attr "mode" "XF")]) (define_insn "fxtract_extend<mode>xf3_i387" @@ -14861,6 +14894,7 @@ && flag_unsafe_math_optimizations" "fxtract" [(set_attr "type" "fpspc") + (set_attr "znver1_decode" "vector") (set_attr "mode" "XF")]) (define_expand "logbxf2" @@ -14937,6 +14971,7 @@ && flag_unsafe_math_optimizations" "f2xm1" [(set_attr "type" "fpspc") + (set_attr "znver1_decode" "vector") (set_attr "mode" "XF")]) (define_insn "fscalexf4_i387" @@ -14951,6 +14986,7 @@ && flag_unsafe_math_optimizations" "fscale" [(set_attr "type" "fpspc") + (set_attr "znver1_decode" "vector") (set_attr "mode" "XF")]) (define_expand "expNcorexf3" @@ -15294,6 +15330,7 @@ && flag_unsafe_math_optimizations" "frndint" [(set_attr "type" "fpspc") + (set_attr "znver1_decode" "vector") (set_attr "mode" "XF")]) (define_expand "rint<mode>2" |