summaryrefslogtreecommitdiff
path: root/gcc/config/rs6000/altivec.md
diff options
context:
space:
mode:
Diffstat (limited to 'gcc/config/rs6000/altivec.md')
-rw-r--r--gcc/config/rs6000/altivec.md381
1 files changed, 175 insertions, 206 deletions
diff --git a/gcc/config/rs6000/altivec.md b/gcc/config/rs6000/altivec.md
index a01a3c69239..2759f2d31a5 100644
--- a/gcc/config/rs6000/altivec.md
+++ b/gcc/config/rs6000/altivec.md
@@ -291,8 +291,8 @@
;; Load up a vector with the most significant bit set by loading up -1 and
;; doing a shift left
(define_split
- [(set (match_operand:VM 0 "altivec_register_operand" "")
- (match_operand:VM 1 "easy_vector_constant_msb" ""))]
+ [(set (match_operand:VM 0 "altivec_register_operand")
+ (match_operand:VM 1 "easy_vector_constant_msb"))]
"VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode) && reload_completed"
[(const_int 0)]
{
@@ -318,8 +318,8 @@
})
(define_split
- [(set (match_operand:VM 0 "altivec_register_operand" "")
- (match_operand:VM 1 "easy_vector_constant_add_self" ""))]
+ [(set (match_operand:VM 0 "altivec_register_operand")
+ (match_operand:VM 1 "easy_vector_constant_add_self"))]
"VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode) && reload_completed"
[(set (match_dup 0) (match_dup 3))
(set (match_dup 0) (match_dup 4))]
@@ -347,8 +347,8 @@
})
(define_split
- [(set (match_operand:VM 0 "altivec_register_operand" "")
- (match_operand:VM 1 "easy_vector_constant_vsldoi" ""))]
+ [(set (match_operand:VM 0 "altivec_register_operand")
+ (match_operand:VM 1 "easy_vector_constant_vsldoi"))]
"VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode) && can_create_pseudo_p ()"
[(set (match_dup 2) (match_dup 3))
(set (match_dup 4) (match_dup 5))
@@ -692,9 +692,9 @@
;; We do multiply as a fused multiply-add with an add of a -0.0 vector.
(define_expand "altivec_mulv4sf3"
- [(set (match_operand:V4SF 0 "register_operand" "")
- (fma:V4SF (match_operand:V4SF 1 "register_operand" "")
- (match_operand:V4SF 2 "register_operand" "")
+ [(set (match_operand:V4SF 0 "register_operand")
+ (fma:V4SF (match_operand:V4SF 1 "register_operand")
+ (match_operand:V4SF 2 "register_operand")
(match_dup 3)))]
"VECTOR_UNIT_ALTIVEC_P (V4SFmode)"
{
@@ -728,9 +728,9 @@
[(set_attr "type" "veccomplex")])
(define_expand "mulv4si3"
- [(use (match_operand:V4SI 0 "register_operand" ""))
- (use (match_operand:V4SI 1 "register_operand" ""))
- (use (match_operand:V4SI 2 "register_operand" ""))]
+ [(use (match_operand:V4SI 0 "register_operand"))
+ (use (match_operand:V4SI 1 "register_operand"))
+ (use (match_operand:V4SI 2 "register_operand"))]
"TARGET_ALTIVEC"
{
rtx zero;
@@ -780,9 +780,9 @@
})
(define_expand "mulv8hi3"
- [(use (match_operand:V8HI 0 "register_operand" ""))
- (use (match_operand:V8HI 1 "register_operand" ""))
- (use (match_operand:V8HI 2 "register_operand" ""))]
+ [(use (match_operand:V8HI 0 "register_operand"))
+ (use (match_operand:V8HI 1 "register_operand"))
+ (use (match_operand:V8HI 2 "register_operand"))]
"TARGET_ALTIVEC"
{
rtx zero = gen_reg_rtx (V8HImode);
@@ -940,9 +940,9 @@
[(set_attr "type" "veccomplex")])
(define_expand "altivec_vmrghb"
- [(use (match_operand:V16QI 0 "register_operand" ""))
- (use (match_operand:V16QI 1 "register_operand" ""))
- (use (match_operand:V16QI 2 "register_operand" ""))]
+ [(use (match_operand:V16QI 0 "register_operand"))
+ (use (match_operand:V16QI 1 "register_operand"))
+ (use (match_operand:V16QI 2 "register_operand"))]
"TARGET_ALTIVEC"
{
rtvec v;
@@ -1004,9 +1004,9 @@
[(set_attr "type" "vecperm")])
(define_expand "altivec_vmrghh"
- [(use (match_operand:V8HI 0 "register_operand" ""))
- (use (match_operand:V8HI 1 "register_operand" ""))
- (use (match_operand:V8HI 2 "register_operand" ""))]
+ [(use (match_operand:V8HI 0 "register_operand"))
+ (use (match_operand:V8HI 1 "register_operand"))
+ (use (match_operand:V8HI 2 "register_operand"))]
"TARGET_ALTIVEC"
{
rtvec v;
@@ -1060,9 +1060,9 @@
[(set_attr "type" "vecperm")])
(define_expand "altivec_vmrghw"
- [(use (match_operand:V4SI 0 "register_operand" ""))
- (use (match_operand:V4SI 1 "register_operand" ""))
- (use (match_operand:V4SI 2 "register_operand" ""))]
+ [(use (match_operand:V4SI 0 "register_operand"))
+ (use (match_operand:V4SI 1 "register_operand"))
+ (use (match_operand:V4SI 2 "register_operand"))]
"VECTOR_MEM_ALTIVEC_P (V4SImode)"
{
rtvec v;
@@ -1131,9 +1131,9 @@
[(set_attr "type" "vecperm")])
(define_expand "altivec_vmrglb"
- [(use (match_operand:V16QI 0 "register_operand" ""))
- (use (match_operand:V16QI 1 "register_operand" ""))
- (use (match_operand:V16QI 2 "register_operand" ""))]
+ [(use (match_operand:V16QI 0 "register_operand"))
+ (use (match_operand:V16QI 1 "register_operand"))
+ (use (match_operand:V16QI 2 "register_operand"))]
"TARGET_ALTIVEC"
{
rtvec v;
@@ -1195,9 +1195,9 @@
[(set_attr "type" "vecperm")])
(define_expand "altivec_vmrglh"
- [(use (match_operand:V8HI 0 "register_operand" ""))
- (use (match_operand:V8HI 1 "register_operand" ""))
- (use (match_operand:V8HI 2 "register_operand" ""))]
+ [(use (match_operand:V8HI 0 "register_operand"))
+ (use (match_operand:V8HI 1 "register_operand"))
+ (use (match_operand:V8HI 2 "register_operand"))]
"TARGET_ALTIVEC"
{
rtvec v;
@@ -1251,9 +1251,9 @@
[(set_attr "type" "vecperm")])
(define_expand "altivec_vmrglw"
- [(use (match_operand:V4SI 0 "register_operand" ""))
- (use (match_operand:V4SI 1 "register_operand" ""))
- (use (match_operand:V4SI 2 "register_operand" ""))]
+ [(use (match_operand:V4SI 0 "register_operand"))
+ (use (match_operand:V4SI 1 "register_operand"))
+ (use (match_operand:V4SI 2 "register_operand"))]
"VECTOR_MEM_ALTIVEC_P (V4SImode)"
{
rtvec v;
@@ -1410,9 +1410,9 @@
[(set_attr "type" "vecperm")])
(define_expand "vec_widen_umult_even_v16qi"
- [(use (match_operand:V8HI 0 "register_operand" ""))
- (use (match_operand:V16QI 1 "register_operand" ""))
- (use (match_operand:V16QI 2 "register_operand" ""))]
+ [(use (match_operand:V8HI 0 "register_operand"))
+ (use (match_operand:V16QI 1 "register_operand"))
+ (use (match_operand:V16QI 2 "register_operand"))]
"TARGET_ALTIVEC"
{
if (VECTOR_ELT_ORDER_BIG)
@@ -1423,9 +1423,9 @@
})
(define_expand "vec_widen_smult_even_v16qi"
- [(use (match_operand:V8HI 0 "register_operand" ""))
- (use (match_operand:V16QI 1 "register_operand" ""))
- (use (match_operand:V16QI 2 "register_operand" ""))]
+ [(use (match_operand:V8HI 0 "register_operand"))
+ (use (match_operand:V16QI 1 "register_operand"))
+ (use (match_operand:V16QI 2 "register_operand"))]
"TARGET_ALTIVEC"
{
if (VECTOR_ELT_ORDER_BIG)
@@ -1436,9 +1436,9 @@
})
(define_expand "vec_widen_umult_even_v8hi"
- [(use (match_operand:V4SI 0 "register_operand" ""))
- (use (match_operand:V8HI 1 "register_operand" ""))
- (use (match_operand:V8HI 2 "register_operand" ""))]
+ [(use (match_operand:V4SI 0 "register_operand"))
+ (use (match_operand:V8HI 1 "register_operand"))
+ (use (match_operand:V8HI 2 "register_operand"))]
"TARGET_ALTIVEC"
{
if (VECTOR_ELT_ORDER_BIG)
@@ -1449,9 +1449,9 @@
})
(define_expand "vec_widen_smult_even_v8hi"
- [(use (match_operand:V4SI 0 "register_operand" ""))
- (use (match_operand:V8HI 1 "register_operand" ""))
- (use (match_operand:V8HI 2 "register_operand" ""))]
+ [(use (match_operand:V4SI 0 "register_operand"))
+ (use (match_operand:V8HI 1 "register_operand"))
+ (use (match_operand:V8HI 2 "register_operand"))]
"TARGET_ALTIVEC"
{
if (VECTOR_ELT_ORDER_BIG)
@@ -1488,9 +1488,9 @@
})
(define_expand "vec_widen_umult_odd_v16qi"
- [(use (match_operand:V8HI 0 "register_operand" ""))
- (use (match_operand:V16QI 1 "register_operand" ""))
- (use (match_operand:V16QI 2 "register_operand" ""))]
+ [(use (match_operand:V8HI 0 "register_operand"))
+ (use (match_operand:V16QI 1 "register_operand"))
+ (use (match_operand:V16QI 2 "register_operand"))]
"TARGET_ALTIVEC"
{
if (VECTOR_ELT_ORDER_BIG)
@@ -1501,9 +1501,9 @@
})
(define_expand "vec_widen_smult_odd_v16qi"
- [(use (match_operand:V8HI 0 "register_operand" ""))
- (use (match_operand:V16QI 1 "register_operand" ""))
- (use (match_operand:V16QI 2 "register_operand" ""))]
+ [(use (match_operand:V8HI 0 "register_operand"))
+ (use (match_operand:V16QI 1 "register_operand"))
+ (use (match_operand:V16QI 2 "register_operand"))]
"TARGET_ALTIVEC"
{
if (VECTOR_ELT_ORDER_BIG)
@@ -1514,9 +1514,9 @@
})
(define_expand "vec_widen_umult_odd_v8hi"
- [(use (match_operand:V4SI 0 "register_operand" ""))
- (use (match_operand:V8HI 1 "register_operand" ""))
- (use (match_operand:V8HI 2 "register_operand" ""))]
+ [(use (match_operand:V4SI 0 "register_operand"))
+ (use (match_operand:V8HI 1 "register_operand"))
+ (use (match_operand:V8HI 2 "register_operand"))]
"TARGET_ALTIVEC"
{
if (VECTOR_ELT_ORDER_BIG)
@@ -1527,9 +1527,9 @@
})
(define_expand "vec_widen_smult_odd_v8hi"
- [(use (match_operand:V4SI 0 "register_operand" ""))
- (use (match_operand:V8HI 1 "register_operand" ""))
- (use (match_operand:V8HI 2 "register_operand" ""))]
+ [(use (match_operand:V4SI 0 "register_operand"))
+ (use (match_operand:V8HI 1 "register_operand"))
+ (use (match_operand:V8HI 2 "register_operand"))]
"TARGET_ALTIVEC"
{
if (VECTOR_ELT_ORDER_BIG)
@@ -1680,13 +1680,12 @@
(match_operand:V4SI 2 "register_operand" "v")]
UNSPEC_VPKPX))]
"TARGET_ALTIVEC"
- "*
- {
- if (VECTOR_ELT_ORDER_BIG)
- return \"vpkpx %0,%1,%2\";
- else
- return \"vpkpx %0,%2,%1\";
- }"
+{
+ if (VECTOR_ELT_ORDER_BIG)
+ return "vpkpx %0,%1,%2";
+ else
+ return "vpkpx %0,%2,%1";
+}
[(set_attr "type" "vecperm")])
(define_insn "altivec_vpks<VI_char>ss"
@@ -1695,13 +1694,12 @@
(match_operand:VP 2 "register_operand" "v")]
UNSPEC_VPACK_SIGN_SIGN_SAT))]
"<VI_unit>"
- "*
- {
- if (VECTOR_ELT_ORDER_BIG)
- return \"vpks<VI_char>ss %0,%1,%2\";
- else
- return \"vpks<VI_char>ss %0,%2,%1\";
- }"
+{
+ if (VECTOR_ELT_ORDER_BIG)
+ return "vpks<VI_char>ss %0,%1,%2";
+ else
+ return "vpks<VI_char>ss %0,%2,%1";
+}
[(set_attr "type" "vecperm")])
(define_insn "altivec_vpks<VI_char>us"
@@ -1710,13 +1708,12 @@
(match_operand:VP 2 "register_operand" "v")]
UNSPEC_VPACK_SIGN_UNS_SAT))]
"<VI_unit>"
- "*
- {
- if (VECTOR_ELT_ORDER_BIG)
- return \"vpks<VI_char>us %0,%1,%2\";
- else
- return \"vpks<VI_char>us %0,%2,%1\";
- }"
+{
+ if (VECTOR_ELT_ORDER_BIG)
+ return "vpks<VI_char>us %0,%1,%2";
+ else
+ return "vpks<VI_char>us %0,%2,%1";
+}
[(set_attr "type" "vecperm")])
(define_insn "altivec_vpku<VI_char>us"
@@ -1725,13 +1722,12 @@
(match_operand:VP 2 "register_operand" "v")]
UNSPEC_VPACK_UNS_UNS_SAT))]
"<VI_unit>"
- "*
- {
- if (VECTOR_ELT_ORDER_BIG)
- return \"vpku<VI_char>us %0,%1,%2\";
- else
- return \"vpku<VI_char>us %0,%2,%1\";
- }"
+{
+ if (VECTOR_ELT_ORDER_BIG)
+ return "vpku<VI_char>us %0,%1,%2";
+ else
+ return "vpku<VI_char>us %0,%2,%1";
+}
[(set_attr "type" "vecperm")])
(define_insn "altivec_vpku<VI_char>um"
@@ -1740,13 +1736,12 @@
(match_operand:VP 2 "register_operand" "v")]
UNSPEC_VPACK_UNS_UNS_MOD))]
"<VI_unit>"
- "*
- {
- if (VECTOR_ELT_ORDER_BIG)
- return \"vpku<VI_char>um %0,%1,%2\";
- else
- return \"vpku<VI_char>um %0,%2,%1\";
- }"
+{
+ if (VECTOR_ELT_ORDER_BIG)
+ return "vpku<VI_char>um %0,%1,%2";
+ else
+ return "vpku<VI_char>um %0,%2,%1";
+}
[(set_attr "type" "vecperm")])
(define_insn "altivec_vpku<VI_char>um_direct"
@@ -1755,13 +1750,12 @@
(match_operand:VP 2 "register_operand" "v")]
UNSPEC_VPACK_UNS_UNS_MOD_DIRECT))]
"<VI_unit>"
- "*
- {
- if (BYTES_BIG_ENDIAN)
- return \"vpku<VI_char>um %0,%1,%2\";
- else
- return \"vpku<VI_char>um %0,%2,%1\";
- }"
+{
+ if (BYTES_BIG_ENDIAN)
+ return "vpku<VI_char>um %0,%1,%2";
+ else
+ return "vpku<VI_char>um %0,%2,%1";
+}
[(set_attr "type" "vecperm")])
(define_insn "*altivec_vrl<VI_char>"
@@ -1955,9 +1949,9 @@
[(set_attr "type" "veccomplex")])
(define_expand "altivec_vspltb"
- [(use (match_operand:V16QI 0 "register_operand" ""))
- (use (match_operand:V16QI 1 "register_operand" ""))
- (use (match_operand:QI 2 "u5bit_cint_operand" ""))]
+ [(use (match_operand:V16QI 0 "register_operand"))
+ (use (match_operand:V16QI 1 "register_operand"))
+ (use (match_operand:QI 2 "u5bit_cint_operand"))]
"TARGET_ALTIVEC"
{
rtvec v;
@@ -2003,9 +1997,9 @@
[(set_attr "type" "vecperm")])
(define_expand "altivec_vsplth"
- [(use (match_operand:V8HI 0 "register_operand" ""))
- (use (match_operand:V8HI 1 "register_operand" ""))
- (use (match_operand:QI 2 "u5bit_cint_operand" ""))]
+ [(use (match_operand:V8HI 0 "register_operand"))
+ (use (match_operand:V8HI 1 "register_operand"))
+ (use (match_operand:QI 2 "u5bit_cint_operand"))]
"TARGET_ALTIVEC"
{
rtvec v;
@@ -2051,9 +2045,9 @@
[(set_attr "type" "vecperm")])
(define_expand "altivec_vspltw"
- [(use (match_operand:V4SI 0 "register_operand" ""))
- (use (match_operand:V4SI 1 "register_operand" ""))
- (use (match_operand:QI 2 "u5bit_cint_operand" ""))]
+ [(use (match_operand:V4SI 0 "register_operand"))
+ (use (match_operand:V4SI 1 "register_operand"))
+ (use (match_operand:QI 2 "u5bit_cint_operand"))]
"TARGET_ALTIVEC"
{
rtvec v;
@@ -2099,9 +2093,9 @@
[(set_attr "type" "vecperm")])
(define_expand "altivec_vspltsf"
- [(use (match_operand:V4SF 0 "register_operand" ""))
- (use (match_operand:V4SF 1 "register_operand" ""))
- (use (match_operand:QI 2 "u5bit_cint_operand" ""))]
+ [(use (match_operand:V4SF 0 "register_operand"))
+ (use (match_operand:V4SF 1 "register_operand"))
+ (use (match_operand:QI 2 "u5bit_cint_operand"))]
"TARGET_ALTIVEC"
{
rtvec v;
@@ -2153,10 +2147,10 @@
[(set_attr "type" "vecfloat")])
(define_expand "altivec_vperm_<mode>"
- [(set (match_operand:VM 0 "register_operand" "")
- (unspec:VM [(match_operand:VM 1 "register_operand" "")
- (match_operand:VM 2 "register_operand" "")
- (match_operand:V16QI 3 "register_operand" "")]
+ [(set (match_operand:VM 0 "register_operand")
+ (unspec:VM [(match_operand:VM 1 "register_operand")
+ (match_operand:VM 2 "register_operand")
+ (match_operand:V16QI 3 "register_operand")]
UNSPEC_VPERM))]
"TARGET_ALTIVEC"
{
@@ -2195,10 +2189,10 @@
(set_attr "length" "4")])
(define_expand "altivec_vperm_<mode>_uns"
- [(set (match_operand:VM 0 "register_operand" "")
- (unspec:VM [(match_operand:VM 1 "register_operand" "")
- (match_operand:VM 2 "register_operand" "")
- (match_operand:V16QI 3 "register_operand" "")]
+ [(set (match_operand:VM 0 "register_operand")
+ (unspec:VM [(match_operand:VM 1 "register_operand")
+ (match_operand:VM 2 "register_operand")
+ (match_operand:V16QI 3 "register_operand")]
UNSPEC_VPERM_UNS))]
"TARGET_ALTIVEC"
{
@@ -2223,10 +2217,10 @@
(set_attr "length" "4")])
(define_expand "vec_permv16qi"
- [(set (match_operand:V16QI 0 "register_operand" "")
- (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "")
- (match_operand:V16QI 2 "register_operand" "")
- (match_operand:V16QI 3 "register_operand" "")]
+ [(set (match_operand:V16QI 0 "register_operand")
+ (unspec:V16QI [(match_operand:V16QI 1 "register_operand")
+ (match_operand:V16QI 2 "register_operand")
+ (match_operand:V16QI 3 "register_operand")]
UNSPEC_VPERM))]
"TARGET_ALTIVEC"
{
@@ -2344,11 +2338,10 @@
[(set_attr "type" "vecfloat")])
(define_expand "altivec_copysign_v4sf3"
- [(use (match_operand:V4SF 0 "register_operand" ""))
- (use (match_operand:V4SF 1 "register_operand" ""))
- (use (match_operand:V4SF 2 "register_operand" ""))]
+ [(use (match_operand:V4SF 0 "register_operand"))
+ (use (match_operand:V4SF 1 "register_operand"))
+ (use (match_operand:V4SF 2 "register_operand"))]
"VECTOR_UNIT_ALTIVEC_P (V4SFmode)"
- "
{
rtx mask = gen_reg_rtx (V4SImode);
rtvec v = rtvec_alloc (4);
@@ -2363,7 +2356,7 @@
emit_insn (gen_vector_select_v4sf (operands[0], operands[1], operands[2],
gen_lowpart (V4SFmode, mask)));
DONE;
-}")
+})
(define_insn "altivec_vsldoi_<mode>"
[(set (match_operand:VM 0 "register_operand" "=v")
@@ -2591,8 +2584,8 @@
[(set_attr "type" "vecsimple")])
(define_expand "altivec_lvsl"
- [(use (match_operand:V16QI 0 "register_operand" ""))
- (use (match_operand:V16QI 1 "memory_operand" ""))]
+ [(use (match_operand:V16QI 0 "register_operand"))
+ (use (match_operand:V16QI 1 "memory_operand"))]
"TARGET_ALTIVEC"
{
if (VECTOR_ELT_ORDER_BIG)
@@ -2667,11 +2660,10 @@
[(set_attr "type" "vecload")])
(define_expand "build_vector_mask_for_load"
- [(set (match_operand:V16QI 0 "register_operand" "")
- (unspec:V16QI [(match_operand 1 "memory_operand" "")] UNSPEC_LVSR))]
+ [(set (match_operand:V16QI 0 "register_operand")
+ (unspec:V16QI [(match_operand 1 "memory_operand")] UNSPEC_LVSR))]
"TARGET_ALTIVEC"
- "
-{
+{
rtx addr;
rtx temp;
@@ -2683,7 +2675,7 @@
emit_insn (gen_altivec_lvsr (operands[0],
replace_equiv_address (operands[1], temp)));
DONE;
-}")
+})
;; Parallel some of the LVE* and STV*'s with unspecs because some have
;; identical rtl but different instructions-- and gcc gets confused.
@@ -3339,8 +3331,8 @@
[(set_attr "type" "vecsimple")])
(define_expand "neg<mode>2"
- [(set (match_operand:VI2 0 "register_operand" "")
- (neg:VI2 (match_operand:VI2 1 "register_operand" "")))]
+ [(set (match_operand:VI2 0 "register_operand")
+ (neg:VI2 (match_operand:VI2 1 "register_operand")))]
"<VI_unit>"
{
if (!TARGET_P9_VECTOR || (<MODE>mode != V4SImode && <MODE>mode != V2DImode))
@@ -3361,12 +3353,11 @@
(match_operand:VIshort 2 "register_operand" "v")]
UNSPEC_VMSUMU)))]
"TARGET_ALTIVEC"
- "
-{
+{
emit_insn (gen_altivec_vmsumu<VI_char>m (operands[0], operands[1], operands[2], operands[3]));
DONE;
-}")
-
+})
+
(define_expand "sdot_prodv8hi"
[(set (match_operand:V4SI 0 "register_operand" "=v")
(plus:V4SI (match_operand:V4SI 3 "register_operand" "v")
@@ -3374,11 +3365,10 @@
(match_operand:V8HI 2 "register_operand" "v")]
UNSPEC_VMSUMSHM)))]
"TARGET_ALTIVEC"
- "
{
emit_insn (gen_altivec_vmsumshm (operands[0], operands[1], operands[2], operands[3]));
DONE;
-}")
+})
(define_expand "widen_usum<mode>3"
[(set (match_operand:V4SI 0 "register_operand" "=v")
@@ -3386,14 +3376,13 @@
(unspec:V4SI [(match_operand:VIshort 1 "register_operand" "v")]
UNSPEC_VMSUMU)))]
"TARGET_ALTIVEC"
- "
{
rtx vones = gen_reg_rtx (GET_MODE (operands[1]));
emit_insn (gen_altivec_vspltis<VI_char> (vones, const1_rtx));
emit_insn (gen_altivec_vmsumu<VI_char>m (operands[0], operands[1], vones, operands[2]));
DONE;
-}")
+})
(define_expand "widen_ssumv16qi3"
[(set (match_operand:V4SI 0 "register_operand" "=v")
@@ -3401,14 +3390,13 @@
(unspec:V4SI [(match_operand:V16QI 1 "register_operand" "v")]
UNSPEC_VMSUMM)))]
"TARGET_ALTIVEC"
- "
{
rtx vones = gen_reg_rtx (V16QImode);
emit_insn (gen_altivec_vspltisb (vones, const1_rtx));
emit_insn (gen_altivec_vmsummbm (operands[0], operands[1], vones, operands[2]));
DONE;
-}")
+})
(define_expand "widen_ssumv8hi3"
[(set (match_operand:V4SI 0 "register_operand" "=v")
@@ -3416,14 +3404,13 @@
(unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")]
UNSPEC_VMSUMSHM)))]
"TARGET_ALTIVEC"
- "
{
rtx vones = gen_reg_rtx (V8HImode);
emit_insn (gen_altivec_vspltish (vones, const1_rtx));
emit_insn (gen_altivec_vmsumshm (operands[0], operands[1], vones, operands[2]));
DONE;
-}")
+})
(define_expand "vec_unpacks_hi_<VP_small_lc>"
[(set (match_operand:VP 0 "register_operand" "=v")
@@ -3471,7 +3458,6 @@
(unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")]
UNSPEC_VUPKHUB))]
"TARGET_ALTIVEC"
- "
{
rtx vzero = gen_reg_rtx (V8HImode);
rtx mask = gen_reg_rtx (V16QImode);
@@ -3500,14 +3486,13 @@
emit_insn (gen_vec_initv16qiqi (mask, gen_rtx_PARALLEL (V16QImode, v)));
emit_insn (gen_vperm_v16qiv8hi (operands[0], operands[1], vzero, mask));
DONE;
-}")
+})
(define_expand "vec_unpacku_hi_v8hi"
[(set (match_operand:V4SI 0 "register_operand" "=v")
(unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")]
UNSPEC_VUPKHUH))]
"TARGET_ALTIVEC"
- "
{
rtx vzero = gen_reg_rtx (V4SImode);
rtx mask = gen_reg_rtx (V16QImode);
@@ -3536,14 +3521,13 @@
emit_insn (gen_vec_initv16qiqi (mask, gen_rtx_PARALLEL (V16QImode, v)));
emit_insn (gen_vperm_v8hiv4si (operands[0], operands[1], vzero, mask));
DONE;
-}")
+})
(define_expand "vec_unpacku_lo_v16qi"
[(set (match_operand:V8HI 0 "register_operand" "=v")
(unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")]
UNSPEC_VUPKLUB))]
"TARGET_ALTIVEC"
- "
{
rtx vzero = gen_reg_rtx (V8HImode);
rtx mask = gen_reg_rtx (V16QImode);
@@ -3572,14 +3556,13 @@
emit_insn (gen_vec_initv16qiqi (mask, gen_rtx_PARALLEL (V16QImode, v)));
emit_insn (gen_vperm_v16qiv8hi (operands[0], operands[1], vzero, mask));
DONE;
-}")
+})
(define_expand "vec_unpacku_lo_v8hi"
[(set (match_operand:V4SI 0 "register_operand" "=v")
(unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")]
UNSPEC_VUPKLUH))]
"TARGET_ALTIVEC"
- "
{
rtx vzero = gen_reg_rtx (V4SImode);
rtx mask = gen_reg_rtx (V16QImode);
@@ -3608,7 +3591,7 @@
emit_insn (gen_vec_initv16qiqi (mask, gen_rtx_PARALLEL (V16QImode, v)));
emit_insn (gen_vperm_v8hiv4si (operands[0], operands[1], vzero, mask));
DONE;
-}")
+})
(define_expand "vec_widen_umult_hi_v16qi"
[(set (match_operand:V8HI 0 "register_operand" "=v")
@@ -3616,7 +3599,6 @@
(match_operand:V16QI 2 "register_operand" "v")]
UNSPEC_VMULWHUB))]
"TARGET_ALTIVEC"
- "
{
rtx ve = gen_reg_rtx (V8HImode);
rtx vo = gen_reg_rtx (V8HImode);
@@ -3634,7 +3616,7 @@
emit_insn (gen_altivec_vmrghh_direct (operands[0], vo, ve));
}
DONE;
-}")
+})
(define_expand "vec_widen_umult_lo_v16qi"
[(set (match_operand:V8HI 0 "register_operand" "=v")
@@ -3642,7 +3624,6 @@
(match_operand:V16QI 2 "register_operand" "v")]
UNSPEC_VMULWLUB))]
"TARGET_ALTIVEC"
- "
{
rtx ve = gen_reg_rtx (V8HImode);
rtx vo = gen_reg_rtx (V8HImode);
@@ -3660,7 +3641,7 @@
emit_insn (gen_altivec_vmrglh_direct (operands[0], vo, ve));
}
DONE;
-}")
+})
(define_expand "vec_widen_smult_hi_v16qi"
[(set (match_operand:V8HI 0 "register_operand" "=v")
@@ -3668,7 +3649,6 @@
(match_operand:V16QI 2 "register_operand" "v")]
UNSPEC_VMULWHSB))]
"TARGET_ALTIVEC"
- "
{
rtx ve = gen_reg_rtx (V8HImode);
rtx vo = gen_reg_rtx (V8HImode);
@@ -3686,7 +3666,7 @@
emit_insn (gen_altivec_vmrghh_direct (operands[0], vo, ve));
}
DONE;
-}")
+})
(define_expand "vec_widen_smult_lo_v16qi"
[(set (match_operand:V8HI 0 "register_operand" "=v")
@@ -3694,7 +3674,6 @@
(match_operand:V16QI 2 "register_operand" "v")]
UNSPEC_VMULWLSB))]
"TARGET_ALTIVEC"
- "
{
rtx ve = gen_reg_rtx (V8HImode);
rtx vo = gen_reg_rtx (V8HImode);
@@ -3712,7 +3691,7 @@
emit_insn (gen_altivec_vmrglh_direct (operands[0], vo, ve));
}
DONE;
-}")
+})
(define_expand "vec_widen_umult_hi_v8hi"
[(set (match_operand:V4SI 0 "register_operand" "=v")
@@ -3720,7 +3699,6 @@
(match_operand:V8HI 2 "register_operand" "v")]
UNSPEC_VMULWHUH))]
"TARGET_ALTIVEC"
- "
{
rtx ve = gen_reg_rtx (V4SImode);
rtx vo = gen_reg_rtx (V4SImode);
@@ -3738,7 +3716,7 @@
emit_insn (gen_altivec_vmrghw_direct (operands[0], vo, ve));
}
DONE;
-}")
+})
(define_expand "vec_widen_umult_lo_v8hi"
[(set (match_operand:V4SI 0 "register_operand" "=v")
@@ -3746,7 +3724,6 @@
(match_operand:V8HI 2 "register_operand" "v")]
UNSPEC_VMULWLUH))]
"TARGET_ALTIVEC"
- "
{
rtx ve = gen_reg_rtx (V4SImode);
rtx vo = gen_reg_rtx (V4SImode);
@@ -3764,7 +3741,7 @@
emit_insn (gen_altivec_vmrglw_direct (operands[0], vo, ve));
}
DONE;
-}")
+})
(define_expand "vec_widen_smult_hi_v8hi"
[(set (match_operand:V4SI 0 "register_operand" "=v")
@@ -3772,7 +3749,6 @@
(match_operand:V8HI 2 "register_operand" "v")]
UNSPEC_VMULWHSH))]
"TARGET_ALTIVEC"
- "
{
rtx ve = gen_reg_rtx (V4SImode);
rtx vo = gen_reg_rtx (V4SImode);
@@ -3790,7 +3766,7 @@
emit_insn (gen_altivec_vmrghw_direct (operands[0], vo, ve));
}
DONE;
-}")
+})
(define_expand "vec_widen_smult_lo_v8hi"
[(set (match_operand:V4SI 0 "register_operand" "=v")
@@ -3798,7 +3774,6 @@
(match_operand:V8HI 2 "register_operand" "v")]
UNSPEC_VMULWLSH))]
"TARGET_ALTIVEC"
- "
{
rtx ve = gen_reg_rtx (V4SImode);
rtx vo = gen_reg_rtx (V4SImode);
@@ -3816,7 +3791,7 @@
emit_insn (gen_altivec_vmrglw_direct (operands[0], vo, ve));
}
DONE;
-}")
+})
(define_expand "vec_pack_trunc_<mode>"
[(set (match_operand:<VP_small> 0 "register_operand" "=v")
@@ -3831,7 +3806,6 @@
(mult:V16QI (match_operand:V16QI 1 "register_operand" "v")
(match_operand:V16QI 2 "register_operand" "v")))]
"TARGET_ALTIVEC"
- "
{
rtx even = gen_reg_rtx (V8HImode);
rtx odd = gen_reg_rtx (V8HImode);
@@ -3851,13 +3825,12 @@
emit_insn (gen_altivec_vmulosb (odd, operands[1], operands[2]));
emit_insn (gen_altivec_vperm_v8hiv16qi (operands[0], even, odd, mask));
DONE;
-}")
+})
(define_expand "altivec_negv4sf2"
- [(use (match_operand:V4SF 0 "register_operand" ""))
- (use (match_operand:V4SF 1 "register_operand" ""))]
+ [(use (match_operand:V4SF 0 "register_operand"))
+ (use (match_operand:V4SF 1 "register_operand"))]
"TARGET_ALTIVEC"
- "
{
rtx neg0;
@@ -3871,7 +3844,7 @@
gen_lowpart (V4SFmode, neg0), operands[1]));
DONE;
-}")
+})
;; Vector reverse elements
(define_expand "altivec_vreve<mode>2"
@@ -3969,60 +3942,56 @@
[(set_attr "type" "vecstore")])
(define_expand "vec_unpacks_float_hi_v8hi"
- [(set (match_operand:V4SF 0 "register_operand" "")
- (unspec:V4SF [(match_operand:V8HI 1 "register_operand" "")]
+ [(set (match_operand:V4SF 0 "register_operand")
+ (unspec:V4SF [(match_operand:V8HI 1 "register_operand")]
UNSPEC_VUPKHS_V4SF))]
"TARGET_ALTIVEC"
- "
{
rtx tmp = gen_reg_rtx (V4SImode);
emit_insn (gen_vec_unpacks_hi_v8hi (tmp, operands[1]));
emit_insn (gen_altivec_vcfsx (operands[0], tmp, const0_rtx));
DONE;
-}")
+})
(define_expand "vec_unpacks_float_lo_v8hi"
- [(set (match_operand:V4SF 0 "register_operand" "")
- (unspec:V4SF [(match_operand:V8HI 1 "register_operand" "")]
+ [(set (match_operand:V4SF 0 "register_operand")
+ (unspec:V4SF [(match_operand:V8HI 1 "register_operand")]
UNSPEC_VUPKLS_V4SF))]
"TARGET_ALTIVEC"
- "
{
rtx tmp = gen_reg_rtx (V4SImode);
emit_insn (gen_vec_unpacks_lo_v8hi (tmp, operands[1]));
emit_insn (gen_altivec_vcfsx (operands[0], tmp, const0_rtx));
DONE;
-}")
+})
(define_expand "vec_unpacku_float_hi_v8hi"
- [(set (match_operand:V4SF 0 "register_operand" "")
- (unspec:V4SF [(match_operand:V8HI 1 "register_operand" "")]
+ [(set (match_operand:V4SF 0 "register_operand")
+ (unspec:V4SF [(match_operand:V8HI 1 "register_operand")]
UNSPEC_VUPKHU_V4SF))]
"TARGET_ALTIVEC"
- "
{
rtx tmp = gen_reg_rtx (V4SImode);
emit_insn (gen_vec_unpacku_hi_v8hi (tmp, operands[1]));
emit_insn (gen_altivec_vcfux (operands[0], tmp, const0_rtx));
DONE;
-}")
+})
(define_expand "vec_unpacku_float_lo_v8hi"
- [(set (match_operand:V4SF 0 "register_operand" "")
- (unspec:V4SF [(match_operand:V8HI 1 "register_operand" "")]
+ [(set (match_operand:V4SF 0 "register_operand")
+ (unspec:V4SF [(match_operand:V8HI 1 "register_operand")]
UNSPEC_VUPKLU_V4SF))]
"TARGET_ALTIVEC"
- "
{
rtx tmp = gen_reg_rtx (V4SImode);
emit_insn (gen_vec_unpacku_lo_v8hi (tmp, operands[1]));
emit_insn (gen_altivec_vcfux (operands[0], tmp, const0_rtx));
DONE;
-}")
+})
;; Power8/power9 vector instructions encoded as Altivec instructions
@@ -4529,13 +4498,13 @@
(define_expand "bcd<bcd_add_sub>_<code>"
[(parallel [(set (reg:CCFP CR6_REGNO)
(compare:CCFP
- (unspec:V2DF [(match_operand:V1TI 1 "register_operand" "")
- (match_operand:V1TI 2 "register_operand" "")
- (match_operand:QI 3 "const_0_to_1_operand" "")]
+ (unspec:V2DF [(match_operand:V1TI 1 "register_operand")
+ (match_operand:V1TI 2 "register_operand")
+ (match_operand:QI 3 "const_0_to_1_operand")]
UNSPEC_BCD_ADD_SUB)
(match_dup 4)))
- (clobber (match_scratch:V1TI 5 ""))])
- (set (match_operand:SI 0 "register_operand" "")
+ (clobber (match_scratch:V1TI 5))])
+ (set (match_operand:SI 0 "register_operand")
(BCD_TEST:SI (reg:CCFP CR6_REGNO)
(const_int 0)))]
"TARGET_P8_VECTOR"
@@ -4550,10 +4519,10 @@
;; a register class for CR6.
(define_peephole2
- [(parallel [(set (match_operand:V1TI 0 "register_operand" "")
- (unspec:V1TI [(match_operand:V1TI 1 "register_operand" "")
- (match_operand:V1TI 2 "register_operand" "")
- (match_operand:QI 3 "const_0_to_1_operand" "")]
+ [(parallel [(set (match_operand:V1TI 0 "register_operand")
+ (unspec:V1TI [(match_operand:V1TI 1 "register_operand")
+ (match_operand:V1TI 2 "register_operand")
+ (match_operand:QI 3 "const_0_to_1_operand")]
UNSPEC_BCD_ADD_SUB))
(clobber (reg:CCFP CR6_REGNO))])
(parallel [(set (reg:CCFP CR6_REGNO)
@@ -4562,8 +4531,8 @@
(match_dup 2)
(match_dup 3)]
UNSPEC_BCD_ADD_SUB)
- (match_operand:V2DF 4 "zero_constant" "")))
- (clobber (match_operand:V1TI 5 "register_operand" ""))])]
+ (match_operand:V2DF 4 "zero_constant")))
+ (clobber (match_operand:V1TI 5 "register_operand"))])]
"TARGET_P8_VECTOR"
[(parallel [(set (match_dup 0)
(unspec:V1TI [(match_dup 1)
View Lorry Controller Status