diff options
Diffstat (limited to 'gcc/config/rs6000/rs6000.md')
| -rw-r--r-- | gcc/config/rs6000/rs6000.md | 1126 |
1 files changed, 530 insertions, 596 deletions
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index 5f44d80ef0e..0976d50d845 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -1576,12 +1576,12 @@ "dlmzb. %0,%1,%2") (define_expand "strlensi" - [(set (match_operand:SI 0 "gpc_reg_operand" "") - (unspec:SI [(match_operand:BLK 1 "general_operand" "") - (match_operand:QI 2 "const_int_operand" "") - (match_operand 3 "const_int_operand" "")] + [(set (match_operand:SI 0 "gpc_reg_operand") + (unspec:SI [(match_operand:BLK 1 "general_operand") + (match_operand:QI 2 "const_int_operand") + (match_operand 3 "const_int_operand")] UNSPEC_DLMZB_STRLEN)) - (clobber (match_scratch:CC 4 "=x"))] + (clobber (match_scratch:CC 4))] "TARGET_DLMZB && WORDS_BIG_ENDIAN && !optimize_size" { rtx result = operands[0]; @@ -1630,9 +1630,9 @@ ;; Fixed-point arithmetic insns. (define_expand "add<mode>3" - [(set (match_operand:SDI 0 "gpc_reg_operand" "") - (plus:SDI (match_operand:SDI 1 "gpc_reg_operand" "") - (match_operand:SDI 2 "reg_or_add_cint_operand" "")))] + [(set (match_operand:SDI 0 "gpc_reg_operand") + (plus:SDI (match_operand:SDI 1 "gpc_reg_operand") + (match_operand:SDI 2 "reg_or_add_cint_operand")))] "" { if (<MODE>mode == DImode && !TARGET_POWERPC64) @@ -1805,9 +1805,9 @@ ;; add should be last in case the result gets used in an address. (define_split - [(set (match_operand:GPR 0 "gpc_reg_operand" "") - (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "") - (match_operand:GPR 2 "non_add_cint_operand" "")))] + [(set (match_operand:GPR 0 "gpc_reg_operand") + (plus:GPR (match_operand:GPR 1 "gpc_reg_operand") + (match_operand:GPR 2 "non_add_cint_operand")))] "" [(set (match_dup 0) (plus:GPR (match_dup 1) (match_dup 3))) (set (match_dup 0) (plus:GPR (match_dup 0) (match_dup 4)))] @@ -1950,8 +1950,8 @@ (define_expand "one_cmpl<mode>2" - [(set (match_operand:SDI 0 "gpc_reg_operand" "") - (not:SDI (match_operand:SDI 1 "gpc_reg_operand" "")))] + [(set (match_operand:SDI 0 "gpc_reg_operand") + (not:SDI (match_operand:SDI 1 "gpc_reg_operand")))] "" { if (<MODE>mode == DImode && !TARGET_POWERPC64) @@ -2010,9 +2010,9 @@ (define_expand "sub<mode>3" - [(set (match_operand:SDI 0 "gpc_reg_operand" "") - (minus:SDI (match_operand:SDI 1 "reg_or_short_operand" "") - (match_operand:SDI 2 "gpc_reg_operand" "")))] + [(set (match_operand:SDI 0 "gpc_reg_operand") + (minus:SDI (match_operand:SDI 1 "reg_or_short_operand") + (match_operand:SDI 2 "gpc_reg_operand")))] "" { if (<MODE>mode == DImode && !TARGET_POWERPC64) @@ -2338,8 +2338,8 @@ (define_expand "popcount<mode>2" - [(set (match_operand:GPR 0 "gpc_reg_operand" "") - (popcount:GPR (match_operand:GPR 1 "gpc_reg_operand" "")))] + [(set (match_operand:GPR 0 "gpc_reg_operand") + (popcount:GPR (match_operand:GPR 1 "gpc_reg_operand")))] "TARGET_POPCNTB || TARGET_POPCNTD" { rs6000_emit_popcount (operands[0], operands[1]); @@ -2363,8 +2363,8 @@ (define_expand "parity<mode>2" - [(set (match_operand:GPR 0 "gpc_reg_operand" "") - (parity:GPR (match_operand:GPR 1 "gpc_reg_operand" "")))] + [(set (match_operand:GPR 0 "gpc_reg_operand") + (parity:GPR (match_operand:GPR 1 "gpc_reg_operand")))] "TARGET_POPCNTB" { rs6000_emit_parity (operands[0], operands[1]); @@ -2508,11 +2508,11 @@ ;; complex code. (define_expand "bswapdi2" - [(parallel [(set (match_operand:DI 0 "reg_or_mem_operand" "") + [(parallel [(set (match_operand:DI 0 "reg_or_mem_operand") (bswap:DI - (match_operand:DI 1 "reg_or_mem_operand" ""))) - (clobber (match_scratch:DI 2 "")) - (clobber (match_scratch:DI 3 ""))])] + (match_operand:DI 1 "reg_or_mem_operand"))) + (clobber (match_scratch:DI 2)) + (clobber (match_scratch:DI 3))])] "" { rtx dest = operands[0]; @@ -2589,13 +2589,12 @@ [(set_attr "length" "16,12,36")]) (define_split - [(set (match_operand:DI 0 "gpc_reg_operand" "") - (bswap:DI (match_operand:DI 1 "indexed_or_indirect_operand" ""))) - (clobber (match_operand:DI 2 "gpc_reg_operand" "")) - (clobber (match_operand:DI 3 "gpc_reg_operand" ""))] + [(set (match_operand:DI 0 "gpc_reg_operand") + (bswap:DI (match_operand:DI 1 "indexed_or_indirect_operand"))) + (clobber (match_operand:DI 2 "gpc_reg_operand")) + (clobber (match_operand:DI 3 "gpc_reg_operand"))] "TARGET_POWERPC64 && !TARGET_LDBRX && reload_completed" [(const_int 0)] - " { rtx dest = operands[0]; rtx src = operands[1]; @@ -2650,16 +2649,15 @@ emit_insn (gen_ashldi3 (op3, op3, GEN_INT (32))); emit_insn (gen_iordi3 (dest, dest, op3)); DONE; -}") +}) (define_split - [(set (match_operand:DI 0 "indexed_or_indirect_operand" "") - (bswap:DI (match_operand:DI 1 "gpc_reg_operand" ""))) - (clobber (match_operand:DI 2 "gpc_reg_operand" "")) - (clobber (match_operand:DI 3 "gpc_reg_operand" ""))] + [(set (match_operand:DI 0 "indexed_or_indirect_operand") + (bswap:DI (match_operand:DI 1 "gpc_reg_operand"))) + (clobber (match_operand:DI 2 "gpc_reg_operand")) + (clobber (match_operand:DI 3 "gpc_reg_operand"))] "TARGET_POWERPC64 && !TARGET_LDBRX && reload_completed" [(const_int 0)] - " { rtx dest = operands[0]; rtx src = operands[1]; @@ -2713,16 +2711,15 @@ emit_insn (gen_bswapsi2 (word1, op3_si)); } DONE; -}") +}) (define_split - [(set (match_operand:DI 0 "gpc_reg_operand" "") - (bswap:DI (match_operand:DI 1 "gpc_reg_operand" ""))) - (clobber (match_operand:DI 2 "gpc_reg_operand" "")) - (clobber (match_operand:DI 3 "gpc_reg_operand" ""))] + [(set (match_operand:DI 0 "gpc_reg_operand") + (bswap:DI (match_operand:DI 1 "gpc_reg_operand"))) + (clobber (match_operand:DI 2 "gpc_reg_operand")) + (clobber (match_operand:DI 3 "gpc_reg_operand"))] "TARGET_POWERPC64 && !TARGET_P9_VECTOR && reload_completed" [(const_int 0)] - " { rtx dest = operands[0]; rtx src = operands[1]; @@ -2740,7 +2737,7 @@ emit_insn (gen_ashldi3 (dest, dest, GEN_INT (32))); emit_insn (gen_iordi3 (dest, dest, op3)); DONE; -}") +}) (define_insn "bswapdi2_32bit" [(set (match_operand:DI 0 "reg_or_mem_operand" "=r,Z,?&r") @@ -2751,12 +2748,11 @@ [(set_attr "length" "16,12,36")]) (define_split - [(set (match_operand:DI 0 "gpc_reg_operand" "") - (bswap:DI (match_operand:DI 1 "indexed_or_indirect_operand" ""))) - (clobber (match_operand:SI 2 "gpc_reg_operand" ""))] + [(set (match_operand:DI 0 "gpc_reg_operand") + (bswap:DI (match_operand:DI 1 "indexed_or_indirect_operand"))) + (clobber (match_operand:SI 2 "gpc_reg_operand"))] "!TARGET_POWERPC64 && reload_completed" [(const_int 0)] - " { rtx dest = operands[0]; rtx src = operands[1]; @@ -2801,15 +2797,14 @@ thus allowing us to omit an early clobber on the output. */ emit_insn (gen_bswapsi2 (dest1, word2)); DONE; -}") +}) (define_split - [(set (match_operand:DI 0 "indexed_or_indirect_operand" "") - (bswap:DI (match_operand:DI 1 "gpc_reg_operand" ""))) - (clobber (match_operand:SI 2 "gpc_reg_operand" ""))] + [(set (match_operand:DI 0 "indexed_or_indirect_operand") + (bswap:DI (match_operand:DI 1 "gpc_reg_operand"))) + (clobber (match_operand:SI 2 "gpc_reg_operand"))] "!TARGET_POWERPC64 && reload_completed" [(const_int 0)] - " { rtx dest = operands[0]; rtx src = operands[1]; @@ -2850,15 +2845,14 @@ emit_insn (gen_bswapsi2 (word2, src1)); emit_insn (gen_bswapsi2 (word1, src2)); DONE; -}") +}) (define_split - [(set (match_operand:DI 0 "gpc_reg_operand" "") - (bswap:DI (match_operand:DI 1 "gpc_reg_operand" ""))) - (clobber (match_operand:SI 2 "" ""))] + [(set (match_operand:DI 0 "gpc_reg_operand") + (bswap:DI (match_operand:DI 1 "gpc_reg_operand"))) + (clobber (match_operand:SI 2 ""))] "!TARGET_POWERPC64 && reload_completed" [(const_int 0)] - " { rtx dest = operands[0]; rtx src = operands[1]; @@ -2870,7 +2864,7 @@ emit_insn (gen_bswapsi2 (dest1, src2)); emit_insn (gen_bswapsi2 (dest2, src1)); DONE; -}") +}) (define_insn "mul<mode>3" @@ -2883,9 +2877,9 @@ mulli %0,%1,%2" [(set_attr "type" "mul") (set (attr "size") - (cond [(match_operand:GPR 2 "s8bit_cint_operand" "") + (cond [(match_operand:GPR 2 "s8bit_cint_operand") (const_string "8") - (match_operand:GPR 2 "short_cint_operand" "") + (match_operand:GPR 2 "short_cint_operand") (const_string "16")] (const_string "<bits>")))]) @@ -3054,9 +3048,9 @@ ;; modulus. If it isn't a power of two, force operands into register and do ;; a normal divide. (define_expand "div<mode>3" - [(set (match_operand:GPR 0 "gpc_reg_operand" "") - (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "") - (match_operand:GPR 2 "reg_or_cint_operand" "")))] + [(set (match_operand:GPR 0 "gpc_reg_operand") + (div:GPR (match_operand:GPR 1 "gpc_reg_operand") + (match_operand:GPR 2 "reg_or_cint_operand")))] "" { if (CONST_INT_P (operands[2]) @@ -3196,10 +3190,10 @@ ;; after a divide. (define_peephole2 - [(set (match_operand:GPR 0 "gpc_reg_operand" "") - (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "") - (match_operand:GPR 2 "gpc_reg_operand" ""))) - (set (match_operand:GPR 3 "gpc_reg_operand" "") + [(set (match_operand:GPR 0 "gpc_reg_operand") + (div:GPR (match_operand:GPR 1 "gpc_reg_operand") + (match_operand:GPR 2 "gpc_reg_operand"))) + (set (match_operand:GPR 3 "gpc_reg_operand") (mod:GPR (match_dup 1) (match_dup 2)))] "TARGET_MODULO @@ -3218,10 +3212,10 @@ (match_dup 3)))]) (define_peephole2 - [(set (match_operand:GPR 0 "gpc_reg_operand" "") - (udiv:GPR (match_operand:GPR 1 "gpc_reg_operand" "") - (match_operand:GPR 2 "gpc_reg_operand" ""))) - (set (match_operand:GPR 3 "gpc_reg_operand" "") + [(set (match_operand:GPR 0 "gpc_reg_operand") + (udiv:GPR (match_operand:GPR 1 "gpc_reg_operand") + (match_operand:GPR 2 "gpc_reg_operand"))) + (set (match_operand:GPR 3 "gpc_reg_operand") (umod:GPR (match_dup 1) (match_dup 2)))] "TARGET_MODULO @@ -3247,9 +3241,9 @@ ;; those rotate-and-mask operations. Thus, the AND insns come first. (define_expand "and<mode>3" - [(set (match_operand:SDI 0 "gpc_reg_operand" "") - (and:SDI (match_operand:SDI 1 "gpc_reg_operand" "") - (match_operand:SDI 2 "reg_or_cint_operand" "")))] + [(set (match_operand:SDI 0 "gpc_reg_operand") + (and:SDI (match_operand:SDI 1 "gpc_reg_operand") + (match_operand:SDI 2 "reg_or_cint_operand")))] "" { if (<MODE>mode == DImode && !TARGET_POWERPC64) @@ -3545,9 +3539,9 @@ (define_expand "<code><mode>3" - [(set (match_operand:SDI 0 "gpc_reg_operand" "") - (iorxor:SDI (match_operand:SDI 1 "gpc_reg_operand" "") - (match_operand:SDI 2 "reg_or_cint_operand" "")))] + [(set (match_operand:SDI 0 "gpc_reg_operand") + (iorxor:SDI (match_operand:SDI 1 "gpc_reg_operand") + (match_operand:SDI 2 "reg_or_cint_operand")))] "" { if (<MODE>mode == DImode && !TARGET_POWERPC64) @@ -3576,9 +3570,9 @@ }) (define_split - [(set (match_operand:GPR 0 "gpc_reg_operand" "") - (iorxor:GPR (match_operand:GPR 1 "gpc_reg_operand" "") - (match_operand:GPR 2 "non_logical_cint_operand" "")))] + [(set (match_operand:GPR 0 "gpc_reg_operand") + (iorxor:GPR (match_operand:GPR 1 "gpc_reg_operand") + (match_operand:GPR 2 "non_logical_cint_operand")))] "" [(set (match_dup 3) (iorxor:GPR (match_dup 1) @@ -4479,9 +4473,9 @@ ;; Builtins to replace a division to generate FRE reciprocal estimate ;; instructions and the necessary fixup instructions (define_expand "recip<mode>3" - [(match_operand:RECIPF 0 "gpc_reg_operand" "") - (match_operand:RECIPF 1 "gpc_reg_operand" "") - (match_operand:RECIPF 2 "gpc_reg_operand" "")] + [(match_operand:RECIPF 0 "gpc_reg_operand") + (match_operand:RECIPF 1 "gpc_reg_operand") + (match_operand:RECIPF 2 "gpc_reg_operand")] "RS6000_RECIP_HAVE_RE_P (<MODE>mode)" { rs6000_emit_swdiv (operands[0], operands[1], operands[2], false); @@ -4494,9 +4488,9 @@ ;; We used to also check optimize_insn_for_speed_p () but problems with guessed ;; frequencies (pr68212/pr77536) yields that unreliable so it was removed. (define_split - [(set (match_operand:RECIPF 0 "gpc_reg_operand" "") - (div:RECIPF (match_operand 1 "gpc_reg_operand" "") - (match_operand 2 "gpc_reg_operand" "")))] + [(set (match_operand:RECIPF 0 "gpc_reg_operand") + (div:RECIPF (match_operand 1 "gpc_reg_operand") + (match_operand 2 "gpc_reg_operand")))] "RS6000_RECIP_AUTO_RE_P (<MODE>mode) && can_create_pseudo_p () && flag_finite_math_only && !flag_trapping_math && flag_reciprocal_math" @@ -4509,8 +4503,8 @@ ;; Builtins to replace 1/sqrt(x) with instructions using RSQRTE and the ;; appropriate fixup. (define_expand "rsqrt<mode>2" - [(match_operand:RECIPF 0 "gpc_reg_operand" "") - (match_operand:RECIPF 1 "gpc_reg_operand" "")] + [(match_operand:RECIPF 0 "gpc_reg_operand") + (match_operand:RECIPF 1 "gpc_reg_operand")] "RS6000_RECIP_HAVE_RSQRTE_P (<MODE>mode)" { rs6000_emit_swsqrt (operands[0], operands[1], 1); @@ -4523,8 +4517,8 @@ ;; -mupper-regs-{df,sf} option is enabled. (define_expand "abs<mode>2" - [(set (match_operand:SFDF 0 "gpc_reg_operand" "") - (abs:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "")))] + [(set (match_operand:SFDF 0 "gpc_reg_operand") + (abs:SFDF (match_operand:SFDF 1 "gpc_reg_operand")))] "TARGET_<MODE>_INSN" "") @@ -4551,8 +4545,8 @@ (set_attr "fp_type" "fp_addsub_<Fs>")]) (define_expand "neg<mode>2" - [(set (match_operand:SFDF 0 "gpc_reg_operand" "") - (neg:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "")))] + [(set (match_operand:SFDF 0 "gpc_reg_operand") + (neg:SFDF (match_operand:SFDF 1 "gpc_reg_operand")))] "TARGET_<MODE>_INSN" "") @@ -4567,9 +4561,9 @@ (set_attr "fp_type" "fp_addsub_<Fs>")]) (define_expand "add<mode>3" - [(set (match_operand:SFDF 0 "gpc_reg_operand" "") - (plus:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "") - (match_operand:SFDF 2 "gpc_reg_operand" "")))] + [(set (match_operand:SFDF 0 "gpc_reg_operand") + (plus:SFDF (match_operand:SFDF 1 "gpc_reg_operand") + (match_operand:SFDF 2 "gpc_reg_operand")))] "TARGET_<MODE>_INSN" "") @@ -4585,9 +4579,9 @@ (set_attr "fp_type" "fp_addsub_<Fs>")]) (define_expand "sub<mode>3" - [(set (match_operand:SFDF 0 "gpc_reg_operand" "") - (minus:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "") - (match_operand:SFDF 2 "gpc_reg_operand" "")))] + [(set (match_operand:SFDF 0 "gpc_reg_operand") + (minus:SFDF (match_operand:SFDF 1 "gpc_reg_operand") + (match_operand:SFDF 2 "gpc_reg_operand")))] "TARGET_<MODE>_INSN" "") @@ -4603,9 +4597,9 @@ (set_attr "fp_type" "fp_addsub_<Fs>")]) (define_expand "mul<mode>3" - [(set (match_operand:SFDF 0 "gpc_reg_operand" "") - (mult:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "") - (match_operand:SFDF 2 "gpc_reg_operand" "")))] + [(set (match_operand:SFDF 0 "gpc_reg_operand") + (mult:SFDF (match_operand:SFDF 1 "gpc_reg_operand") + (match_operand:SFDF 2 "gpc_reg_operand")))] "TARGET_<MODE>_INSN" "") @@ -4621,9 +4615,9 @@ (set_attr "fp_type" "fp_mul_<Fs>")]) (define_expand "div<mode>3" - [(set (match_operand:SFDF 0 "gpc_reg_operand" "") - (div:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "") - (match_operand:SFDF 2 "gpc_reg_operand" "")))] + [(set (match_operand:SFDF 0 "gpc_reg_operand") + (div:SFDF (match_operand:SFDF 1 "gpc_reg_operand") + (match_operand:SFDF 2 "gpc_reg_operand")))] "TARGET_<MODE>_INSN && !TARGET_SIMPLE_FPU" { if (RS6000_RECIP_AUTO_RE_P (<MODE>mode) @@ -4658,8 +4652,8 @@ (set_attr "fp_type" "fp_sqrt_<Fs>")]) (define_expand "sqrt<mode>2" - [(set (match_operand:SFDF 0 "gpc_reg_operand" "") - (sqrt:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "")))] + [(set (match_operand:SFDF 0 "gpc_reg_operand") + (sqrt:SFDF (match_operand:SFDF 1 "gpc_reg_operand")))] "TARGET_<MODE>_FPR && !TARGET_SIMPLE_FPU && (TARGET_PPC_GPOPT || (<MODE>mode == SFmode && TARGET_XILINX_FPU))" { @@ -4747,8 +4741,8 @@ [(set_attr "type" "fp")]) (define_expand "truncdfsf2" - [(set (match_operand:SF 0 "gpc_reg_operand" "") - (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "")))] + [(set (match_operand:SF 0 "gpc_reg_operand") + (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand")))] "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT" "") @@ -4766,12 +4760,12 @@ ;; when little-endian. (define_expand "signbit<mode>2" [(set (match_dup 2) - (float_truncate:DF (match_operand:FLOAT128 1 "gpc_reg_operand" ""))) + (float_truncate:DF (match_operand:FLOAT128 1 "gpc_reg_operand"))) (set (match_dup 3) (subreg:DI (match_dup 2) 0)) (set (match_dup 4) (match_dup 5)) - (set (match_operand:SI 0 "gpc_reg_operand" "") + (set (match_operand:SI 0 "gpc_reg_operand") (match_dup 6))] "TARGET_HARD_FLOAT && (!FLOAT128_IEEE_P (<MODE>mode) @@ -4874,11 +4868,11 @@ (define_expand "copysign<mode>3" [(set (match_dup 3) - (abs:SFDF (match_operand:SFDF 1 "gpc_reg_operand" ""))) + (abs:SFDF (match_operand:SFDF 1 "gpc_reg_operand"))) (set (match_dup 4) (neg:SFDF (abs:SFDF (match_dup 1)))) - (set (match_operand:SFDF 0 "gpc_reg_operand" "") - (if_then_else:SFDF (ge (match_operand:SFDF 2 "gpc_reg_operand" "") + (set (match_operand:SFDF 0 "gpc_reg_operand") + (if_then_else:SFDF (ge (match_operand:SFDF 2 "gpc_reg_operand") (match_dup 5)) (match_dup 3) (match_dup 4)))] @@ -4928,9 +4922,9 @@ ;; to allow either DF/SF to use only traditional registers. (define_expand "s<minmax><mode>3" - [(set (match_operand:SFDF 0 "gpc_reg_operand" "") - (fp_minmax:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "") - (match_operand:SFDF 2 "gpc_reg_operand" "")))] + [(set (match_operand:SFDF 0 "gpc_reg_operand") + (fp_minmax:SFDF (match_operand:SFDF 1 "gpc_reg_operand") + (match_operand:SFDF 2 "gpc_reg_operand")))] "TARGET_MINMAX_<MODE>" { rs6000_emit_minmax (operands[0], <SMINMAX>, operands[1], operands[2]); @@ -4954,9 +4948,9 @@ ;; instruction. (define_insn_and_split "*s<minmax><mode>3_fpr" - [(set (match_operand:SFDF 0 "gpc_reg_operand" "") - (fp_minmax:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "") - (match_operand:SFDF 2 "gpc_reg_operand" "")))] + [(set (match_operand:SFDF 0 "gpc_reg_operand") + (fp_minmax:SFDF (match_operand:SFDF 1 "gpc_reg_operand") + (match_operand:SFDF 2 "gpc_reg_operand")))] "!TARGET_VSX && TARGET_MINMAX_<MODE>" "#" "&& 1" @@ -4967,18 +4961,17 @@ }) (define_expand "mov<mode>cc" - [(set (match_operand:GPR 0 "gpc_reg_operand" "") - (if_then_else:GPR (match_operand 1 "comparison_operator" "") - (match_operand:GPR 2 "gpc_reg_operand" "") - (match_operand:GPR 3 "gpc_reg_operand" "")))] + [(set (match_operand:GPR 0 "gpc_reg_operand") + (if_then_else:GPR (match_operand 1 "comparison_operator") + (match_operand:GPR 2 "gpc_reg_operand") + (match_operand:GPR 3 "gpc_reg_operand")))] "TARGET_ISEL" - " { if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3])) DONE; else FAIL; -}") +}) ;; We use the BASE_REGS for the isel input operands because, if rA is ;; 0, the value of 0 is placed in rD upon truth. Similarly for rB @@ -5048,18 +5041,17 @@ ;; Floating point conditional move (define_expand "mov<mode>cc" - [(set (match_operand:SFDF 0 "gpc_reg_operand" "") - (if_then_else:SFDF (match_operand 1 "comparison_operator" "") - (match_operand:SFDF 2 "gpc_reg_operand" "") - (match_operand:SFDF 3 "gpc_reg_operand" "")))] + [(set (match_operand:SFDF 0 "gpc_reg_operand") + (if_then_else:SFDF (match_operand 1 "comparison_operator") + (match_operand:SFDF 2 "gpc_reg_operand") + (match_operand:SFDF 3 "gpc_reg_operand")))] "TARGET_<MODE>_FPR && TARGET_PPC_GFXOPT" - " { if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3])) DONE; else FAIL; -}") +}) (define_insn "*fsel<SFDF:mode><SFDF2:mode>4" [(set (match_operand:SFDF 0 "gpc_reg_operand" "=&<SFDF:rreg2>") @@ -5193,7 +5185,6 @@ "#" "" [(pc)] - " { rtx dest = operands[0]; rtx src = operands[1]; @@ -5221,7 +5212,7 @@ } emit_insn (gen_floatdi<mode>2 (dest, tmp)); DONE; -}" +} [(set_attr "length" "12") (set_attr "type" "fpload")]) @@ -5235,7 +5226,6 @@ "#" "" [(pc)] - " { operands[1] = rs6000_address_for_fpconvert (operands[1]); if (GET_CODE (operands[2]) == SCRATCH) @@ -5246,7 +5236,7 @@ emit_insn (gen_lfiwax (operands[2], operands[1])); emit_insn (gen_floatdi<mode>2 (operands[0], operands[2])); DONE; -}" +} [(set_attr "length" "8") (set_attr "type" "fpload")]) @@ -5270,7 +5260,6 @@ "#" "" [(pc)] - " { rtx dest = operands[0]; rtx src = operands[1]; @@ -5298,7 +5287,7 @@ } emit_insn (gen_floatdi<mode>2 (dest, tmp)); DONE; -}" +} [(set_attr "length" "12") (set_attr "type" "fpload")]) @@ -5312,7 +5301,6 @@ "#" "" [(pc)] - " { operands[1] = rs6000_address_for_fpconvert (operands[1]); if (GET_CODE (operands[2]) == SCRATCH) @@ -5323,7 +5311,7 @@ emit_insn (gen_lfiwzx (operands[2], operands[1])); emit_insn (gen_floatdi<mode>2 (operands[0], operands[2])); DONE; -}" +} [(set_attr "length" "8") (set_attr "type" "fpload")]) @@ -5333,15 +5321,14 @@ ; then to have the insns split later (between sched1 and final). (define_expand "floatsidf2" - [(parallel [(set (match_operand:DF 0 "gpc_reg_operand" "") - (float:DF (match_operand:SI 1 "nonimmediate_operand" ""))) + [(parallel [(set (match_operand:DF 0 "gpc_reg_operand") + (float:DF (match_operand:SI 1 "nonimmediate_operand"))) (use (match_dup 2)) (use (match_dup 3)) (clobber (match_dup 4)) (clobber (match_dup 5)) (clobber (match_dup 6))])] "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT" - " { if (TARGET_LFIWAX && TARGET_FCFID) { @@ -5365,7 +5352,7 @@ operands[4] = rs6000_allocate_stack_temp (DFmode, true, false); operands[5] = gen_reg_rtx (DFmode); operands[6] = gen_reg_rtx (SImode); -}") +}) (define_insn_and_split "*floatsidf2_internal" [(set (match_operand:DF 0 "gpc_reg_operand" "=&d") @@ -5379,7 +5366,6 @@ "#" "" [(pc)] - " { rtx lowword, highword; gcc_assert (MEM_P (operands[4])); @@ -5395,7 +5381,7 @@ emit_move_insn (operands[5], operands[4]); emit_insn (gen_subdf3 (operands[0], operands[5], operands[3])); DONE; -}" +} [(set_attr "length" "24") (set_attr "type" "fp")]) @@ -5403,13 +5389,12 @@ ;; conversion for 32-bit without fast math, because we don't have the insn to ;; generate the fixup swizzle to avoid double rounding problems. (define_expand "floatunssisf2" - [(set (match_operand:SF 0 "gpc_reg_operand" "") - (unsigned_float:SF (match_operand:SI 1 "nonimmediate_operand" "")))] + [(set (match_operand:SF 0 "gpc_reg_operand") + (unsigned_float:SF (match_operand:SI 1 "nonimmediate_operand")))] "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT && ((TARGET_FCFIDUS && TARGET_LFIWZX) || (TARGET_DOUBLE_FLOAT && TARGET_FCFID && (TARGET_POWERPC64 || flag_unsafe_math_optimizations)))" - " { if (TARGET_LFIWZX && TARGET_FCFIDUS) { @@ -5425,17 +5410,16 @@ emit_insn (gen_floatdisf2 (operands[0], dreg)); DONE; } -}") +}) (define_expand "floatunssidf2" - [(parallel [(set (match_operand:DF 0 "gpc_reg_operand" "") - (unsigned_float:DF (match_operand:SI 1 "nonimmediate_operand" ""))) + [(parallel [(set (match_operand:DF 0 "gpc_reg_operand") + (unsigned_float:DF (match_operand:SI 1 "nonimmediate_operand"))) (use (match_dup 2)) (use (match_dup 3)) (clobber (match_dup 4)) (clobber (match_dup 5))])] "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT" - " { if (TARGET_LFIWZX && TARGET_FCFID) { @@ -5458,7 +5442,7 @@ operands[3] = force_reg (DFmode, CONST_DOUBLE_ATOF (\"4503599627370496\", DFmode)); operands[4] = rs6000_allocate_stack_temp (DFmode, true, false); operands[5] = gen_reg_rtx (DFmode); -}") +}) (define_insn_and_split "*floatunssidf2_internal" [(set (match_operand:DF 0 "gpc_reg_operand" "=&d") @@ -5472,7 +5456,6 @@ "#" "" [(pc)] - " { rtx lowword, highword; gcc_assert (MEM_P (operands[4])); @@ -5486,7 +5469,7 @@ emit_move_insn (operands[5], operands[4]); emit_insn (gen_subdf3 (operands[0], operands[5], operands[3])); DONE; -}" +} [(set_attr "length" "20") (set_attr "type" "fp")]) @@ -5551,9 +5534,9 @@ (define_expand "floatuns<QHI:mode><FP_ISA3:mode>2" [(parallel [(set (match_operand:FP_ISA3 0 "vsx_register_operand") (unsigned_float:FP_ISA3 - (match_operand:QHI 1 "input_operand" ""))) - (clobber (match_scratch:DI 2 "")) - (clobber (match_scratch:DI 3 ""))])] + (match_operand:QHI 1 "input_operand"))) + (clobber (match_scratch:DI 2)) + (clobber (match_scratch:DI 3))])] "TARGET_P9_VECTOR && TARGET_DIRECT_MOVE && TARGET_POWERPC64" { if (MEM_P (operands[1])) @@ -5594,10 +5577,9 @@ }) (define_expand "fix_trunc<mode>si2" - [(set (match_operand:SI 0 "gpc_reg_operand" "") - (fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "")))] + [(set (match_operand:SI 0 "gpc_reg_operand") + (fix:SI (match_operand:SFDF 1 "gpc_reg_operand")))] "TARGET_HARD_FLOAT && <TARGET_FLOAT>" - " { if (!TARGET_P8_VECTOR) { @@ -5614,7 +5596,7 @@ } DONE; } -}") +}) ; Like the convert to float patterns, this insn must be split before ; register allocation so that it can allocate the memory slot if it @@ -5671,7 +5653,6 @@ "#" "" [(pc)] - " { rtx lowword; gcc_assert (MEM_P (operands[3])); @@ -5681,13 +5662,13 @@ emit_move_insn (operands[3], operands[2]); emit_move_insn (operands[0], lowword); DONE; -}" +} [(set_attr "length" "16") (set_attr "type" "fp")]) (define_expand "fix_trunc<mode>di2" - [(set (match_operand:DI 0 "gpc_reg_operand" "") - (fix:DI (match_operand:SFDF 1 "gpc_reg_operand" "")))] + [(set (match_operand:DI 0 "gpc_reg_operand") + (fix:DI (match_operand:SFDF 1 "gpc_reg_operand")))] "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FCFID" "") @@ -5756,17 +5737,16 @@ }) (define_expand "fixuns_trunc<mode>si2" - [(set (match_operand:SI 0 "gpc_reg_operand" "") - (unsigned_fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "")))] + [(set (match_operand:SI 0 "gpc_reg_operand") + (unsigned_fix:SI (match_operand:SFDF 1 "gpc_reg_operand")))] "TARGET_HARD_FLOAT && <TARGET_FLOAT> && TARGET_FCTIWUZ && TARGET_STFIWX" - " { if (!TARGET_P8_VECTOR) { emit_insn (gen_fixuns_trunc<mode>si2_stfiwx (operands[0], operands[1])); DONE; } -}") +}) (define_insn_and_split "fixuns_trunc<mode>si2_stfiwx" [(set (match_operand:SI 0 "nonimmediate_operand" "=rm") @@ -6001,9 +5981,9 @@ (define_expand "lround<mode>di2" [(set (match_dup 2) - (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "")] + (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand")] UNSPEC_XSRDPI)) - (set (match_operand:DI 0 "gpc_reg_operand" "") + (set (match_operand:DI 0 "gpc_reg_operand") (unspec:DI [(match_dup 2)] UNSPEC_FCTID))] "TARGET_<MODE>_FPR && TARGET_VSX" @@ -6028,13 +6008,12 @@ ;; conversion for 32-bit without fast math, because we don't have the insn to ;; generate the fixup swizzle to avoid double rounding problems. (define_expand "floatsisf2" - [(set (match_operand:SF 0 "gpc_reg_operand" "") - (float:SF (match_operand:SI 1 "nonimmediate_operand" "")))] + [(set (match_operand:SF 0 "gpc_reg_operand") + (float:SF (match_operand:SI 1 "nonimmediate_operand")))] "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT && ((TARGET_FCFIDS && TARGET_LFIWAX) || (TARGET_DOUBLE_FLOAT && TARGET_FCFID && (TARGET_POWERPC64 || flag_unsafe_math_optimizations)))" - " { if (TARGET_FCFIDS && TARGET_LFIWAX) { @@ -6057,7 +6036,7 @@ emit_insn (gen_floatdisf2 (operands[0], dreg)); DONE; } -}") +}) (define_insn "floatdidf2" [(set (match_operand:DF 0 "gpc_reg_operand" "=d,ws") @@ -6087,9 +6066,9 @@ (set_attr "type" "fpload")]) (define_expand "floatunsdidf2" - [(set (match_operand:DF 0 "gpc_reg_operand" "") + [(set (match_operand:DF 0 "gpc_reg_operand") (unsigned_float:DF - (match_operand:DI 1 "gpc_reg_operand" "")))] + (match_operand:DI 1 "gpc_reg_operand")))] "TARGET_HARD_FLOAT && TARGET_FCFIDU" "") @@ -6117,11 +6096,10 @@ (set_attr "type" "fpload")]) (define_expand "floatdisf2" - [(set (match_operand:SF 0 "gpc_reg_operand" "") - (float:SF (match_operand:DI 1 "gpc_reg_operand" "")))] + [(set (match_operand:SF 0 "gpc_reg_operand") + (float:SF (match_operand:DI 1 "gpc_reg_operand")))] "TARGET_FCFID && TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT && (TARGET_FCFIDS || TARGET_POWERPC64 || flag_unsafe_math_optimizations)" - " { if (!TARGET_FCFIDS) { @@ -6136,7 +6114,7 @@ emit_insn (gen_floatdisf2_internal1 (operands[0], val)); DONE; } -}") +}) (define_insn "floatdisf2_fcfids" [(set (match_operand:SF 0 "gpc_reg_operand" "=f,wy") @@ -6157,12 +6135,11 @@ "#" "&& reload_completed" [(pc)] - " { emit_move_insn (operands[2], operands[1]); emit_insn (gen_floatdisf2_fcfids (operands[0], operands[2])); DONE; -}" +} [(set_attr "length" "8")]) ;; This is not IEEE compliant if rounding mode is "round to nearest". @@ -6189,11 +6166,11 @@ ;; by a bit that won't be lost at that stage, but is below the SFmode ;; rounding position. (define_expand "floatdisf2_internal2" - [(parallel [(set (match_dup 3) (ashiftrt:DI (match_operand:DI 1 "" "") + [(parallel [(set (match_dup 3) (ashiftrt:DI (match_operand:DI 1 "") (const_int 53))) (clobber (reg:DI CA_REGNO))]) - (set (match_operand:DI 0 "" "") (and:DI (match_dup 1) - (const_int 2047))) + (set (match_operand:DI 0 "") (and:DI (match_dup 1) + (const_int 2047))) (set (match_dup 3) (plus:DI (match_dup 3) (const_int 1))) (set (match_dup 0) (plus:DI (match_dup 0) @@ -6205,20 +6182,19 @@ (set (match_dup 0) (and:DI (match_dup 0) (const_int -2048))) (set (pc) (if_then_else (geu (match_dup 4) (const_int 0)) - (label_ref (match_operand:DI 2 "" "")) + (label_ref (match_operand:DI 2 "")) (pc))) (set (match_dup 0) (match_dup 1))] "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT && !TARGET_FCFIDS" - " { operands[3] = gen_reg_rtx (DImode); operands[4] = gen_reg_rtx (CCUNSmode); -}") +}) (define_expand "floatunsdisf2" - [(set (match_operand:SF 0 "gpc_reg_operand" "") - (unsigned_float:SF (match_operand:DI 1 "gpc_reg_operand" "")))] + [(set (match_operand:SF 0 "gpc_reg_operand") + (unsigned_float:SF (match_operand:DI 1 "gpc_reg_operand")))] "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FCFIDUS" "") @@ -6242,12 +6218,11 @@ "#" "&& reload_completed" [(pc)] - " { emit_move_insn (operands[2], operands[1]); emit_insn (gen_floatunsdisf2_fcfidus (operands[0], operands[2])); DONE; -}" +} [(set_attr "length" "8") (set_attr "type" "fpload")]) @@ -6258,9 +6233,9 @@ ;; also allow for the output being the same as one of the inputs. (define_expand "addti3" - [(set (match_operand:TI 0 "gpc_reg_operand" "") - (plus:TI (match_operand:TI 1 "gpc_reg_operand" "") - (match_operand:TI 2 "reg_or_short_operand" "")))] + [(set (match_operand:TI 0 "gpc_reg_operand") + (plus:TI (match_operand:TI 1 "gpc_reg_operand") + (match_operand:TI 2 "reg_or_short_operand")))] "TARGET_64BIT" { rtx lo0 = gen_lowpart (DImode, operands[0]); @@ -6281,9 +6256,9 @@ }) (define_expand "subti3" - [(set (match_operand:TI 0 "gpc_reg_operand" "") - (minus:TI (match_operand:TI 1 "reg_or_short_operand" "") - (match_operand:TI 2 "gpc_reg_operand" "")))] + [(set (match_operand:TI 0 "gpc_reg_operand") + (minus:TI (match_operand:TI 1 "reg_or_short_operand") + (match_operand:TI 2 "gpc_reg_operand")))] "TARGET_64BIT" { rtx lo0 = gen_lowpart (DImode, operands[0]); @@ -6306,73 +6281,73 @@ ;; 128-bit logical operations expanders (define_expand "and<mode>3" - [(set (match_operand:BOOL_128 0 "vlogical_operand" "") - (and:BOOL_128 (match_operand:BOOL_128 1 "vlogical_operand" "") - (match_operand:BOOL_128 2 "vlogical_operand" "")))] + [(set (match_operand:BOOL_128 0 "vlogical_operand") + (and:BOOL_128 (match_operand:BOOL_128 1 "vlogical_operand") + (match_operand:BOOL_128 2 "vlogical_operand")))] "" "") (define_expand "ior<mode>3" - [(set (match_operand:BOOL_128 0 "vlogical_operand" "") - (ior:BOOL_128 (match_operand:BOOL_128 1 "vlogical_operand" "") - (match_operand:BOOL_128 2 "vlogical_operand" "")))] + [(set (match_operand:BOOL_128 0 "vlogical_operand") + (ior:BOOL_128 (match_operand:BOOL_128 1 "vlogical_operand") + (match_operand:BOOL_128 2 "vlogical_operand")))] "" "") (define_expand "xor<mode>3" - [(set (match_operand:BOOL_128 0 "vlogical_operand" "") - (xor:BOOL_128 (match_operand:BOOL_128 1 "vlogical_operand" "") - (match_operand:BOOL_128 2 "vlogical_operand" "")))] + [(set (match_operand:BOOL_128 0 "vlogical_operand") + (xor:BOOL_128 (match_operand:BOOL_128 1 "vlogical_operand") + (match_operand:BOOL_128 2 "vlogical_operand")))] "" "") (define_expand "one_cmpl<mode>2" - [(set (match_operand:BOOL_128 0 "vlogical_operand" "") - (not:BOOL_128 (match_operand:BOOL_128 1 "vlogical_operand" "")))] + [(set (match_operand:BOOL_128 0 "vlogical_operand") + (not:BOOL_128 (match_operand:BOOL_128 1 "vlogical_operand")))] "" "") (define_expand "nor<mode>3" - [(set (match_operand:BOOL_128 0 "vlogical_operand" "") + [(set (match_operand:BOOL_128 0 "vlogical_operand") (and:BOOL_128 - (not:BOOL_128 (match_operand:BOOL_128 1 "vlogical_operand" "")) - (not:BOOL_128 (match_operand:BOOL_128 2 "vlogical_operand" ""))))] + (not:BOOL_128 (match_operand:BOOL_128 1 "vlogical_operand")) + (not:BOOL_128 (match_operand:BOOL_128 2 "vlogical_operand"))))] "" "") (define_expand "andc<mode>3" - [(set (match_operand:BOOL_128 0 "vlogical_operand" "") + [(set (match_operand:BOOL_128 0 "vlogical_operand") (and:BOOL_128 - (not:BOOL_128 (match_operand:BOOL_128 2 "vlogical_operand" "")) - (match_operand:BOOL_128 1 "vlogical_operand" "")))] + (not:BOOL_128 (match_operand:BOOL_128 2 "vlogical_operand")) + (match_operand:BOOL_128 1 "vlogical_operand")))] "" "") ;; Power8 vector logical instructions. (define_expand "eqv<mode>3" - [(set (match_operand:BOOL_128 0 "vlogical_operand" "") + [(set (match_operand:BOOL_128 0 "vlogical_operand") (not:BOOL_128 - (xor:BOOL_128 (match_operand:BOOL_128 1 "vlogical_operand" "") - (match_operand:BOOL_128 2 "vlogical_operand" ""))))] + (xor:BOOL_128 (match_operand:BOOL_128 1 "vlogical_operand") + (match_operand:BOOL_128 2 "vlogical_operand"))))] "<MODE>mode == TImode || <MODE>mode == PTImode || TARGET_P8_VECTOR" "") ;; Rewrite nand into canonical form (define_expand "nand<mode>3" - [(set (match_operand:BOOL_128 0 "vlogical_operand" "") + [(set (match_operand:BOOL_128 0 "vlogical_operand") (ior:BOOL_128 - (not:BOOL_128 (match_operand:BOOL_128 1 "vlogical_operand" "")) - (not:BOOL_128 (match_operand:BOOL_128 2 "vlogical_operand" ""))))] + (not:BOOL_128 (match_operand:BOOL_128 1 "vlogical_operand")) + (not:BOOL_128 (match_operand:BOOL_128 2 "vlogical_operand"))))] "<MODE>mode == TImode || <MODE>mode == PTImode || TARGET_P8_VECTOR" "") ;; The canonical form is to have the negated element first, so we need to ;; reverse arguments. (define_expand "orc<mode>3" - [(set (match_operand:BOOL_128 0 "vlogical_operand" "") + [(set (match_operand:BOOL_128 0 "vlogical_operand") (ior:BOOL_128 - (not:BOOL_128 (match_operand:BOOL_128 2 "vlogical_operand" "")) - (match_operand:BOOL_128 1 "vlogical_operand" "")))] + (not:BOOL_128 (match_operand:BOOL_128 2 "vlogical_operand")) + (match_operand:BOOL_128 1 "vlogical_operand")))] "<MODE>mode == TImode || <MODE>mode == PTImode || TARGET_P8_VECTOR" "") @@ -6666,11 +6641,10 @@ ;; Set up a register with a value from the GOT table (define_expand "movsi_got" - [(set (match_operand:SI 0 "gpc_reg_operand" "") - (unspec:SI [(match_operand:SI 1 "got_operand" "") + [(set (match_operand:SI 0 "gpc_reg_operand") + (unspec:SI [(match_operand:SI 1 "got_operand") (match_dup 2)] UNSPEC_MOVSI_GOT))] "DEFAULT_ABI == ABI_V4 && flag_pic == 1" - " { if (GET_CODE (operands[1]) == CONST) { @@ -6691,7 +6665,7 @@ } operands[2] = rs6000_got_register (operands[1]); -}") +}) (define_insn "*movsi_got_internal" [(set (match_operand:SI 0 "gpc_reg_operand" "=r") @@ -6705,9 +6679,9 @@ ;; Used by sched, shorten_branches and final when the GOT pseudo reg ;; didn't get allocated to a hard register. (define_split - [(set (match_operand:SI 0 "gpc_reg_operand" "") - (unspec:SI [(match_operand:SI 1 "got_no_const_operand" "") - (match_operand:SI 2 "memory_operand" "")] + [(set (match_operand:SI 0 "gpc_reg_operand") + (unspec:SI [(match_operand:SI 1 "got_no_const_operand") + (match_operand:SI 2 "memory_operand")] UNSPEC_MOVSI_GOT))] "DEFAULT_ABI == ABI_V4 && flag_pic == 1 @@ -6966,8 +6940,8 @@ ;; sequence. (define_split - [(set (match_operand:SI 0 "gpc_reg_operand" "") - (match_operand:SI 1 "const_int_operand" ""))] + [(set (match_operand:SI 0 "gpc_reg_operand") + (match_operand:SI 1 "const_int_operand"))] "(unsigned HOST_WIDE_INT) (INTVAL (operands[1]) + 0x8000) >= 0x10000 && (INTVAL (operands[1]) & 0xffff) != 0" [(set (match_dup 0) @@ -6975,13 +6949,12 @@ (set (match_dup 0) (ior:SI (match_dup 0) (match_dup 3)))] - " { if (rs6000_emit_set_const (operands[0], operands[1])) DONE; else FAIL; -}") +}) ;; Split loading -128..127 to use XXSPLITB and VEXTSW2D (define_split @@ -7027,10 +7000,13 @@ "") (define_expand "mov<mode>" - [(set (match_operand:INT 0 "general_operand" "") - (match_operand:INT 1 "any_operand" ""))] + [(set (match_operand:INT 0 "general_operand") + (match_operand:INT 1 "any_operand"))] "" - "{ rs6000_emit_move (operands[0], operands[1], <MODE>mode); DONE; }") +{ + rs6000_emit_move (operands[0], operands[1], <MODE>mode); + DONE; +}) ;; MR LHZ/LBZ LXSI*ZX STH/STB STXSI*X LI ;; XXLOR load 0 load -1 VSPLTI* # MFVSRWZ @@ -7080,8 +7056,8 @@ ;; an integer register or memory, we store just the high-order 4 bits. ;; This lets us not shift in the most common case of CR0. (define_expand "movcc" - [(set (match_operand:CC 0 "nonimmediate_operand" "") - (match_operand:CC 1 "nonimmediate_operand" ""))] + [(set (match_operand:CC 0 "nonimmediate_operand") + (match_operand:CC 1 "nonimmediate_operand"))] "" "") @@ -7134,21 +7110,23 @@ ;; Move 32-bit binary/decimal floating point (define_expand "mov<mode>" - [(set (match_operand:FMOVE32 0 "nonimmediate_operand" "") - (match_operand:FMOVE32 1 "any_operand" ""))] + [(set (match_operand:FMOVE32 0 "nonimmediate_operand") + (match_operand:FMOVE32 1 "any_operand"))] "<fmove_ok>" - "{ rs6000_emit_move (operands[0], operands[1], <MODE>mode); DONE; }") +{ + rs6000_emit_move (operands[0], operands[1], <MODE>mode); + DONE; +}) (define_split - [(set (match_operand:FMOVE32 0 "gpc_reg_operand" "") - (match_operand:FMOVE32 1 "const_double_operand" ""))] + [(set (match_operand:FMOVE32 0 "gpc_reg_operand") + (match_operand:FMOVE32 1 "const_double_operand"))] "reload_completed && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31) || (GET_CODE (operands[0]) == SUBREG && GET_CODE (SUBREG_REG (operands[0])) == REG && REGNO (SUBREG_REG (operands[0])) <= 31))" [(set (match_dup 2) (match_dup 3))] - " { long l; @@ -7160,7 +7138,7 @@ operands[2] = gen_lowpart (SImode, operands[0]); operands[3] = gen_int_mode (l, SImode); -}") +}) ;; Originally, we tried to keep movsf and movsd common, but the differences ;; addressing was making it rather difficult to hide with mode attributes. In @@ -7331,14 +7309,17 @@ ;; Move 64-bit binary/decimal floating point (define_expand "mov<mode>" - [(set (match_operand:FMOVE64 0 "nonimmediate_operand" "") - (match_operand:FMOVE64 1 "any_operand" ""))] + [(set (match_operand:FMOVE64 0 "nonimmediate_operand") + (match_operand:FMOVE64 1 "any_operand"))] "" - "{ rs6000_emit_move (operands[0], operands[1], <MODE>mode); DONE; }") +{ + rs6000_emit_move (operands[0], operands[1], <MODE>mode); + DONE; +}) (define_split - [(set (match_operand:FMOVE64 0 "gpc_reg_operand" "") - (match_operand:FMOVE64 1 "const_int_operand" ""))] + [(set (match_operand:FMOVE64 0 "gpc_reg_operand") + (match_operand:FMOVE64 1 "const_int_operand"))] "! TARGET_POWERPC64 && reload_completed && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31) || (GET_CODE (operands[0]) == SUBREG @@ -7346,7 +7327,6 @@ && REGNO (SUBREG_REG (operands[0])) <= 31))" [(set (match_dup 2) (match_dup 4)) (set (match_dup 3) (match_dup 1))] - " { int endian = (WORDS_BIG_ENDIAN == 0); HOST_WIDE_INT value = INTVAL (operands[1]); @@ -7355,11 +7335,11 @@ operands[3] = operand_subword (operands[0], 1 - endian, 0, <MODE>mode); operands[4] = GEN_INT (value >> 32); operands[1] = GEN_INT (((value & 0xffffffff) ^ 0x80000000) - 0x80000000); -}") +}) (define_split - [(set (match_operand:FMOVE64 0 "gpc_reg_operand" "") - (match_operand:FMOVE64 1 "const_double_operand" ""))] + [(set (match_operand:FMOVE64 0 "gpc_reg_operand") + (match_operand:FMOVE64 1 "const_double_operand"))] "! TARGET_POWERPC64 && reload_completed && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31) || (GET_CODE (operands[0]) == SUBREG @@ -7367,7 +7347,6 @@ && REGNO (SUBREG_REG (operands[0])) <= 31))" [(set (match_dup 2) (match_dup 4)) (set (match_dup 3) (match_dup 5))] - " { int endian = (WORDS_BIG_ENDIAN == 0); long l[2]; @@ -7378,18 +7357,17 @@ operands[3] = operand_subword (operands[0], 1 - endian, 0, <MODE>mode); operands[4] = gen_int_mode (l[endian], SImode); operands[5] = gen_int_mode (l[1 - endian], SImode); -}") +}) (define_split - [(set (match_operand:FMOVE64 0 "gpc_reg_operand" "") - (match_operand:FMOVE64 1 "const_double_operand" ""))] + [(set (match_operand:FMOVE64 0 "gpc_reg_operand") + (match_operand:FMOVE64 1 "const_double_operand"))] "TARGET_POWERPC64 && reload_completed && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31) || (GET_CODE (operands[0]) == SUBREG && GET_CODE (SUBREG_REG (operands[0])) == REG && REGNO (SUBREG_REG (operands[0])) <= 31))" [(set (match_dup 2) (match_dup 3))] - " { int endian = (WORDS_BIG_ENDIAN == 0); long l[2]; @@ -7403,7 +7381,7 @@ | ((HOST_WIDE_INT)(unsigned long)l[1 - endian])); operands[3] = gen_int_mode (val, DImode); -}") +}) ;; Don't have reload use general registers to load a constant. It is ;; less efficient than loading the constant into an FP register, since @@ -7508,10 +7486,13 @@ (set_attr "length" "4,4,4,4,4,8,12,16,4")]) (define_expand "mov<mode>" - [(set (match_operand:FMOVE128 0 "general_operand" "") - (match_operand:FMOVE128 1 "any_operand" ""))] + [(set (match_operand:FMOVE128 0 "general_operand") + (match_operand:FMOVE128 1 "any_operand"))] "" - "{ rs6000_emit_move (operands[0], operands[1], <MODE>mode); DONE; }") +{ + rs6000_emit_move (operands[0], operands[1], <MODE>mode); + DONE; +}) ;; It's important to list Y->r and r->Y before r->r because otherwise ;; reload, given m->r, will try to pick r->r and reload it, which @@ -7574,8 +7555,8 @@ [(set_attr "length" "20,20,16")]) (define_expand "extenddf<mode>2" - [(set (match_operand:FLOAT128 0 "gpc_reg_operand" "") - (float_extend:FLOAT128 (match_operand:DF 1 "gpc_reg_operand" "")))] + [(set (match_operand:FLOAT128 0 "gpc_reg_operand") + (float_extend:FLOAT128 (match_operand:DF 1 "gpc_reg_operand")))] "TARGET_HARD_FLOAT && TARGET_LONG_DOUBLE_128" { if (FLOAT128_IEEE_P (<MODE>mode)) @@ -7643,8 +7624,8 @@ }) (define_expand "extendsf<mode>2" - [(set (match_operand:FLOAT128 0 "gpc_reg_operand" "") - (float_extend:FLOAT128 (match_operand:SF 1 "gpc_reg_operand" "")))] + [(set (match_operand:FLOAT128 0 "gpc_reg_operand") + (float_extend:FLOAT128 (match_operand:SF 1 "gpc_reg_operand")))] "TARGET_HARD_FLOAT && TARGET_LONG_DOUBLE_128" { if (FLOAT128_IEEE_P (<MODE>mode)) @@ -7659,8 +7640,8 @@ }) (define_expand "trunc<mode>df2" - [(set (match_operand:DF 0 "gpc_reg_operand" "") - (float_truncate:DF (match_operand:FLOAT128 1 "gpc_reg_operand" "")))] + [(set (match_operand:DF 0 "gpc_reg_operand") + (float_truncate:DF (match_operand:FLOAT128 1 "gpc_reg_operand")))] "TARGET_HARD_FLOAT && TARGET_LONG_DOUBLE_128" { if (FLOAT128_IEEE_P (<MODE>mode)) @@ -7697,8 +7678,8 @@ (set_attr "fp_type" "fp_addsub_d")]) (define_expand "trunc<mode>sf2" - [(set (match_operand:SF 0 "gpc_reg_operand" "") - (float_truncate:SF (match_operand:FLOAT128 1 "gpc_reg_operand" "")))] + [(set (match_operand:SF 0 "gpc_reg_operand") + (float_truncate:SF (match_operand:FLOAT128 1 "gpc_reg_operand")))] "TARGET_HARD_FLOAT && TARGET_LONG_DOUBLE_128" { if (FLOAT128_IEEE_P (<MODE>mode)) @@ -7769,8 +7750,8 @@ (set_attr "length" "20")]) (define_expand "fix_trunc<mode>si2" - [(set (match_operand:SI 0 "gpc_reg_operand" "") - (fix:SI (match_operand:FLOAT128 1 "gpc_reg_operand" "")))] + [(set (match_operand:SI 0 "gpc_reg_operand") + (fix:SI (match_operand:FLOAT128 1 "gpc_reg_operand")))] "TARGET_HARD_FLOAT && TARGET_LONG_DOUBLE_128" { rtx op0 = operands[0]; @@ -7793,8 +7774,8 @@ }) (define_expand "fix_trunc<mode>si2_fprs" - [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "") - (fix:SI (match_operand:IBM128 1 "gpc_reg_operand" ""))) + [(parallel [(set (match_operand:SI 0 "gpc_reg_operand") + (fix:SI (match_operand:IBM128 1 "gpc_reg_operand"))) (clobber (match_dup 2)) (clobber (match_dup 3)) (clobber (match_dup 4)) @@ -7833,8 +7814,8 @@ }) (define_expand "fix_trunc<mode>di2" - [(set (match_operand:DI 0 "gpc_reg_operand" "") - (fix:DI (match_operand:IEEE128 1 "gpc_reg_operand" "")))] + [(set (match_operand:DI 0 "gpc_reg_operand") + (fix:DI (match_operand:IEEE128 1 "gpc_reg_operand")))] "TARGET_FLOAT128_TYPE" { if (!TARGET_FLOAT128_HW) @@ -7845,8 +7826,8 @@ }) (define_expand "fixuns_trunc<IEEE128:mode><SDI:mode>2" - [(set (match_operand:SDI 0 "gpc_reg_operand" "") - (unsigned_fix:SDI (match_operand:IEEE128 1 "gpc_reg_operand" "")))] + [(set (match_operand:SDI 0 "gpc_reg_operand") + (unsigned_fix:SDI (match_operand:IEEE128 1 "gpc_reg_operand")))] "TARGET_FLOAT128_TYPE" { rs6000_expand_float128_convert (operands[0], operands[1], true); @@ -7854,8 +7835,8 @@ }) (define_expand "floatdi<mode>2" - [(set (match_operand:IEEE128 0 "gpc_reg_operand" "") - (float:IEEE128 (match_operand:DI 1 "gpc_reg_operand" "")))] + [(set (match_operand:IEEE128 0 "gpc_reg_operand") + (float:IEEE128 (match_operand:DI 1 "gpc_reg_operand")))] "TARGET_FLOAT128_TYPE" { if (!TARGET_FLOAT128_HW) @@ -7866,8 +7847,8 @@ }) (define_expand "floatunsdi<IEEE128:mode>2" - [(set (match_operand:IEEE128 0 "gpc_reg_operand" "") - (unsigned_float:IEEE128 (match_operand:DI 1 "gpc_reg_operand" "")))] + [(set (match_operand:IEEE128 0 "gpc_reg_operand") + (unsigned_float:IEEE128 (match_operand:DI 1 "gpc_reg_operand")))] "TARGET_FLOAT128_TYPE" { if (!TARGET_FLOAT128_HW) @@ -7878,8 +7859,8 @@ }) (define_expand "floatuns<IEEE128:mode>2" - [(set (match_operand:IEEE128 0 "gpc_reg_operand" "") - (unsigned_float:IEEE128 (match_operand:SI 1 "gpc_reg_operand" "")))] + [(set (match_operand:IEEE128 0 "gpc_reg_operand") + (unsigned_float:IEEE128 (match_operand:SI 1 "gpc_reg_operand")))] "TARGET_FLOAT128_TYPE" { rtx op0 = operands[0]; @@ -7893,11 +7874,10 @@ }) (define_expand "neg<mode>2" - [(set (match_operand:FLOAT128 0 "gpc_reg_operand" "") - (neg:FLOAT128 (match_operand:FLOAT128 1 "gpc_reg_operand" "")))] + [(set (match_operand:FLOAT128 0 "gpc_reg_operand") + (neg:FLOAT128 (match_operand:FLOAT128 1 "gpc_reg_operand")))] "FLOAT128_IEEE_P (<MODE>mode) || (FLOAT128_IBM_P (<MODE>mode) && TARGET_HARD_FLOAT)" - " { if (FLOAT128_IEEE_P (<MODE>mode)) { @@ -7931,28 +7911,26 @@ } DONE; } -}") +}) (define_insn "neg<mode>2_internal" [(set (match_operand:IBM128 0 "gpc_reg_operand" "=d") (neg:IBM128 (match_operand:IBM128 1 "gpc_reg_operand" "d")))] "TARGET_HARD_FLOAT && FLOAT128_IBM_P (TFmode)" - "* { if (REGNO (operands[0]) == REGNO (operands[1]) + 1) - return \"fneg %L0,%L1\;fneg %0,%1\"; + return "fneg %L0,%L1\;fneg %0,%1"; else - return \"fneg %0,%1\;fneg %L0,%L1\"; -}" + return "fneg %0,%1\;fneg %L0,%L1"; +} [(set_attr "type" "fpsimple") (set_attr "length" "8")]) (define_expand "abs<mode>2" - [(set (match_operand:FLOAT128 0 "gpc_reg_operand" "") - (abs:FLOAT128 (match_operand:FLOAT128 1 "gpc_reg_operand" "")))] + [(set (match_operand:FLOAT128 0 "gpc_reg_operand") + (abs:FLOAT128 (match_operand:FLOAT128 1 "gpc_reg_operand")))] "FLOAT128_IEEE_P (<MODE>mode) || (FLOAT128_IBM_P (<MODE>mode) && TARGET_HARD_FLOAT)" - " { rtx label; @@ -7991,20 +7969,19 @@ FAIL; emit_label (label); DONE; -}") +}) (define_expand "abs<mode>2_internal" - [(set (match_operand:IBM128 0 "gpc_reg_operand" "") - (match_operand:IBM128 1 "gpc_reg_operand" "")) + [(set (match_operand:IBM128 0 "gpc_reg_operand") + (match_operand:IBM128 1 "gpc_reg_operand")) (set (match_dup 3) (match_dup 5)) (set (match_dup 5) (abs:DF (match_dup 5))) (set (match_dup 4) (compare:CCFP (match_dup 3) (match_dup 5))) (set (pc) (if_then_else (eq (match_dup 4) (const_int 0)) - (label_ref (match_operand 2 "" "")) + (label_ref (match_operand 2 "")) (pc))) (set (match_dup 6) (neg:DF (match_dup 6)))] "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_LONG_DOUBLE_128" - " { const int hi_word = LONG_DOUBLE_LARGE_FIRST ? 0 : GET_MODE_SIZE (DFmode); const int lo_word = LONG_DOUBLE_LARGE_FIRST ? GET_MODE_SIZE (DFmode) : 0; @@ -8012,14 +7989,14 @@ operands[4] = gen_reg_rtx (CCFPmode); operands[5] = simplify_gen_subreg (DFmode, operands[0], <MODE>mode, hi_word); operands[6] = simplify_gen_subreg (DFmode, operands[0], <MODE>mode, lo_word); -}") +}) ;; Generate IEEE 128-bit -0.0 (0x80000000000000000000000000000000) in a vector ;; register (define_expand "ieee_128bit_negative_zero" - [(set (match_operand:V16QI 0 "register_operand" "") (match_dup 1))] + [(set (match_operand:V16QI 0 "register_operand") (match_dup 1))] "TARGET_FLOAT128_TYPE" { rtvec v = rtvec_alloc (16); @@ -8138,8 +8115,8 @@ ;; We use expand to convert from IBM double double to IEEE 128-bit ;; and trunc for the opposite. (define_expand "extendiftf2" - [(set (match_operand:TF 0 "gpc_reg_operand" "") - (float_extend:TF (match_operand:IF 1 "gpc_reg_operand" "")))] + [(set (match_operand:TF 0 "gpc_reg_operand") + (float_extend:TF (match_operand:IF 1 "gpc_reg_operand")))] "TARGET_FLOAT128_TYPE" { rs6000_expand_float128_convert (operands[0], operands[1], false); @@ -8147,8 +8124,8 @@ }) (define_expand "extendifkf2" - [(set (match_operand:KF 0 "gpc_reg_operand" "") - (float_extend:KF (match_operand:IF 1 "gpc_reg_operand" "")))] + [(set (match_operand:KF 0 "gpc_reg_operand") + (float_extend:KF (match_operand:IF 1 "gpc_reg_operand")))] "TARGET_FLOAT128_TYPE" { rs6000_expand_float128_convert (operands[0], operands[1], false); @@ -8156,8 +8133,8 @@ }) (define_expand "extendtfkf2" - [(set (match_operand:KF 0 "gpc_reg_operand" "") - (float_extend:KF (match_operand:TF 1 "gpc_reg_operand" "")))] + [(set (match_operand:KF 0 "gpc_reg_operand") + (float_extend:KF (match_operand:TF 1 "gpc_reg_operand")))] "TARGET_FLOAT128_TYPE" { rs6000_expand_float128_convert (operands[0], operands[1], false); @@ -8165,8 +8142,8 @@ }) (define_expand "trunciftf2" - [(set (match_operand:IF 0 "gpc_reg_operand" "") - (float_truncate:IF (match_operand:TF 1 "gpc_reg_operand" "")))] + [(set (match_operand:IF 0 "gpc_reg_operand") + (float_truncate:IF (match_operand:TF 1 "gpc_reg_operand")))] "TARGET_FLOAT128_TYPE" { rs6000_expand_float128_convert (operands[0], operands[1], false); @@ -8174,8 +8151,8 @@ }) (define_expand "truncifkf2" - [(set (match_operand:IF 0 "gpc_reg_operand" "") - (float_truncate:IF (match_operand:KF 1 "gpc_reg_operand" "")))] + [(set (match_operand:IF 0 "gpc_reg_operand") + (float_truncate:IF (match_operand:KF 1 "gpc_reg_operand")))] "TARGET_FLOAT128_TYPE" { rs6000_expand_float128_convert (operands[0], operands[1], false); @@ -8183,8 +8160,8 @@ }) (define_expand "trunckftf2" - [(set (match_operand:TF 0 "gpc_reg_operand" "") - (float_truncate:TF (match_operand:KF 1 "gpc_reg_operand" "")))] + [(set (match_operand:TF 0 "gpc_reg_operand") + (float_truncate:TF (match_operand:KF 1 "gpc_reg_operand")))] "TARGET_FLOAT128_TYPE" { rs6000_expand_float128_convert (operands[0], operands[1], false); @@ -8192,8 +8169,8 @@ }) (define_expand "trunctfif2" - [(set (match_operand:IF 0 "gpc_reg_operand" "") - (float_truncate:IF (match_operand:TF 1 "gpc_reg_operand" "")))] + [(set (match_operand:IF 0 "gpc_reg_operand") + (float_truncate:IF (match_operand:TF 1 "gpc_reg_operand")))] "TARGET_FLOAT128_TYPE" { rs6000_expand_float128_convert (operands[0], operands[1], false); @@ -8372,8 +8349,8 @@ (set_attr "type" "three")]) (define_split - [(set (match_operand:FMOVE128_GPR 0 "nonimmediate_operand" "") - (match_operand:FMOVE128_GPR 1 "input_operand" ""))] + [(set (match_operand:FMOVE128_GPR 0 "nonimmediate_operand") + (match_operand:FMOVE128_GPR 1 "input_operand"))] "reload_completed && (int_reg_operand (operands[0], <MODE>mode) || int_reg_operand (operands[1], <MODE>mode)) @@ -8539,14 +8516,13 @@ (set_attr "size" "64")]) (define_split - [(set (match_operand:DI 0 "gpc_reg_operand" "") - (match_operand:DI 1 "const_int_operand" ""))] + [(set (match_operand:DI 0 "gpc_reg_operand") + (match_operand:DI 1 "const_int_operand"))] "! TARGET_POWERPC64 && reload_completed && gpr_or_gpr_p (operands[0], operands[1]) && !direct_move_p (operands[0], operands[1])" [(set (match_dup 2) (match_dup 4)) (set (match_dup 3) (match_dup 1))] - " { HOST_WIDE_INT value = INTVAL (operands[1]); operands[2] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN == 0, @@ -8555,11 +8531,11 @@ DImode); operands[4] = GEN_INT (value >> 32); operands[1] = GEN_INT (((value & 0xffffffff) ^ 0x80000000) - 0x80000000); -}") +}) (define_split - [(set (match_operand:DIFD 0 "nonimmediate_operand" "") - (match_operand:DIFD 1 "input_operand" ""))] + [(set (match_operand:DIFD 0 "nonimmediate_operand") + (match_operand:DIFD 1 "input_operand"))] "reload_completed && !TARGET_POWERPC64 && gpr_or_gpr_p (operands[0], operands[1]) && !direct_move_p (operands[0], operands[1])" @@ -8654,36 +8630,34 @@ ;; When non-easy constants can go in the TOC, this should use ;; easy_fp_constant predicate. (define_split - [(set (match_operand:DI 0 "int_reg_operand_not_pseudo" "") - (match_operand:DI 1 "const_int_operand" ""))] + [(set (match_operand:DI 0 "int_reg_operand_not_pseudo") + (match_operand:DI 1 "const_int_operand"))] "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1" [(set (match_dup 0) (match_dup 2)) (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))] - " { if (rs6000_emit_set_const (operands[0], operands[1])) DONE; else FAIL; -}") +}) (define_split - [(set (match_operand:DI 0 "int_reg_operand_not_pseudo" "") - (match_operand:DI 1 "const_scalar_int_operand" ""))] + [(set (match_operand:DI 0 "int_reg_operand_not_pseudo") + (match_operand:DI 1 "const_scalar_int_operand"))] "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1" [(set (match_dup 0) (match_dup 2)) (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))] - " { if (rs6000_emit_set_const (operands[0], operands[1])) DONE; else FAIL; -}") +}) (define_split - [(set (match_operand:DI 0 "altivec_register_operand" "") - (match_operand:DI 1 "s5bit_cint_operand" ""))] + [(set (match_operand:DI 0 "altivec_register_operand") + (match_operand:DI 1 "s5bit_cint_operand"))] "TARGET_VSX && reload_completed" [(const_int 0)] { @@ -8704,8 +8678,8 @@ ;; Split integer constants that can be loaded with XXSPLTIB and a ;; sign extend operation. (define_split - [(set (match_operand:INT_ISA3 0 "altivec_register_operand" "") - (match_operand:INT_ISA3 1 "xxspltib_constant_split" ""))] + [(set (match_operand:INT_ISA3 0 "altivec_register_operand") + (match_operand:INT_ISA3 1 "xxspltib_constant_split"))] "TARGET_P9_VECTOR && reload_completed" [(const_int 0)] { @@ -8757,14 +8731,13 @@ (set_attr "length" "8")]) (define_split - [(set (match_operand:TI2 0 "int_reg_operand" "") - (match_operand:TI2 1 "const_scalar_int_operand" ""))] + [(set (match_operand:TI2 0 "int_reg_operand") + (match_operand:TI2 1 "const_scalar_int_operand"))] "TARGET_POWERPC64 && (VECTOR_MEM_NONE_P (<MODE>mode) || (reload_completed && INT_REGNO_P (REGNO (operands[0]))))" [(set (match_dup 2) (match_dup 4)) (set (match_dup 3) (match_dup 5))] - " { operands[2] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN == 0, <MODE>mode); @@ -8782,11 +8755,11 @@ } else FAIL; -}") +}) (define_split - [(set (match_operand:TI2 0 "nonimmediate_operand" "") - (match_operand:TI2 1 "input_operand" ""))] + [(set (match_operand:TI2 0 "nonimmediate_operand") + (match_operand:TI2 1 "input_operand"))] "reload_completed && gpr_or_gpr_p (operands[0], operands[1]) && !direct_move_p (operands[0], operands[1]) @@ -8795,12 +8768,11 @@ { rs6000_split_multireg_move (operands[0], operands[1]); DONE; }) (define_expand "setmemsi" - [(parallel [(set (match_operand:BLK 0 "" "") - (match_operand 2 "const_int_operand" "")) - (use (match_operand:SI 1 "" "")) - (use (match_operand:SI 3 "" ""))])] + [(parallel [(set (match_operand:BLK 0 "") + (match_operand 2 "const_int_operand")) + (use (match_operand:SI 1 "")) + (use (match_operand:SI 3 ""))])] "" - " { /* If value to set is not zero, use the library routine. */ if (operands[2] != const0_rtx) @@ -8810,7 +8782,7 @@ DONE; else FAIL; -}") +}) ;; String compare N insn. ;; Argument 0 is the target (result) @@ -8886,18 +8858,17 @@ ;; Argument 3 is the alignment (define_expand "movmemsi" - [(parallel [(set (match_operand:BLK 0 "" "") - (match_operand:BLK 1 "" "")) - (use (match_operand:SI 2 "" "")) - (use (match_operand:SI 3 "" ""))])] + [(parallel [(set (match_operand:BLK 0 "") + (match_operand:BLK 1 "")) + (use (match_operand:SI 2 "")) + (use (match_operand:SI 3 ""))])] "" - " { if (expand_block_move (operands)) DONE; else FAIL; -}") +}) ;; Define insns that do load or store with update. Some of these we can ;; get by using pre-decrement or pre-increment, but the hardware can also @@ -9245,18 +9216,18 @@ ;; Also this optimization interferes with scalars going into ;; altivec registers (the code does reloading through the FPRs). (define_peephole2 - [(set (match_operand:DF 0 "gpc_reg_operand" "") - (match_operand:DF 1 "any_operand" "")) - (set (match_operand:DF 2 "gpc_reg_operand" "") + [(set (match_operand:DF 0 "gpc_reg_operand") + (match_operand:DF 1 "any_operand")) + (set (match_operand:DF 2 "gpc_reg_operand") (match_dup 0))] "!TARGET_VSX && peep2_reg_dead_p (2, operands[0])" [(set (match_dup 2) (match_dup 1))]) (define_peephole2 - [(set (match_operand:SF 0 "gpc_reg_operand" "") - (match_operand:SF 1 "any_operand" "")) - (set (match_operand:SF 2 "gpc_reg_operand" "") + [(set (match_operand:SF 0 "gpc_reg_operand") + (match_operand:SF 1 "any_operand")) + (set (match_operand:SF 2 "gpc_reg_operand") (match_dup 0))] "!TARGET_P8_VECTOR && peep2_reg_dead_p (2, operands[0])" @@ -9352,10 +9323,9 @@ (set (match_dup 0) (lo_sum:TLSmode (match_dup 3) (unspec:TLSmode [(match_dup 1) (match_dup 2)] UNSPEC_TLSGD)))] - " { operands[3] = gen_reg_rtx (TARGET_64BIT ? DImode : SImode); -}" +} [(set (attr "length") (if_then_else (ne (symbol_ref "TARGET_CMODEL") (symbol_ref "CMODEL_SMALL")) (const_int 8) @@ -9489,10 +9459,9 @@ (set (match_dup 0) (lo_sum:TLSmode (match_dup 2) (unspec:TLSmode [(const_int 0) (match_dup 1)] UNSPEC_TLSLD)))] - " { operands[2] = gen_reg_rtx (TARGET_64BIT ? DImode : SImode); -}" +} [(set (attr "length") (if_then_else (ne (symbol_ref "TARGET_CMODEL") (symbol_ref "CMODEL_SMALL")) (const_int 8) @@ -9587,10 +9556,9 @@ (set (match_dup 0) (lo_sum:TLSmode (match_dup 3) (unspec:TLSmode [(match_dup 1) (match_dup 2)] UNSPEC_TLSGOTDTPREL)))] - " { operands[3] = gen_reg_rtx (TARGET_64BIT ? DImode : SImode); -}" +} [(set (attr "length") (if_then_else (ne (symbol_ref "TARGET_CMODEL") (symbol_ref "CMODEL_SMALL")) (const_int 8) @@ -9657,10 +9625,9 @@ (set (match_dup 0) (lo_sum:TLSmode (match_dup 3) (unspec:TLSmode [(match_dup 1) (match_dup 2)] UNSPEC_TLSGOTTPREL)))] - " { operands[3] = gen_reg_rtx (TARGET_64BIT ? DImode : SImode); -}" +} [(set (attr "length") (if_then_else (ne (symbol_ref "TARGET_CMODEL") (symbol_ref "CMODEL_SMALL")) (const_int 8) @@ -9695,15 +9662,14 @@ "add %0,%1,%2@tls") (define_expand "tls_get_tpointer" - [(set (match_operand:SI 0 "gpc_reg_operand" "") + [(set (match_operand:SI 0 "gpc_reg_operand") (unspec:SI [(const_int 0)] UNSPEC_TLSTLS))] "TARGET_XCOFF && HAVE_AS_TLS" - " { emit_insn (gen_tls_get_tpointer_internal ()); emit_move_insn (operands[0], gen_rtx_REG (SImode, 3)); DONE; -}") +}) (define_insn "tls_get_tpointer_internal" [(set (reg:SI 3) @@ -9713,18 +9679,17 @@ "bla __get_tpointer") (define_expand "tls_get_addr<mode>" - [(set (match_operand:P 0 "gpc_reg_operand" "") - (unspec:P [(match_operand:P 1 "gpc_reg_operand" "") - (match_operand:P 2 "gpc_reg_operand" "")] UNSPEC_TLSTLS))] + [(set (match_operand:P 0 "gpc_reg_operand") + (unspec:P [(match_operand:P 1 "gpc_reg_operand") + (match_operand:P 2 "gpc_reg_operand")] UNSPEC_TLSTLS))] "TARGET_XCOFF && HAVE_AS_TLS" - " { emit_move_insn (gen_rtx_REG (Pmode, 3), operands[1]); emit_move_insn (gen_rtx_REG (Pmode, 4), operands[2]); emit_insn (gen_tls_get_addr_internal<mode> ()); emit_move_insn (operands[0], gen_rtx_REG (Pmode, 3)); DONE; -}") +}) (define_insn "tls_get_addr_internal<mode>" [(set (reg:P 3) @@ -9754,13 +9719,13 @@ ;; the constant size. The value is forced into a register if necessary. ;; (define_expand "allocate_stack" - [(set (match_operand 0 "gpc_reg_operand" "") - (minus (reg 1) (match_operand 1 "reg_or_cint_operand" ""))) + [(set (match_operand 0 "gpc_reg_operand") + (minus (reg 1) (match_operand 1 "reg_or_cint_operand"))) (set (reg 1) (minus (reg 1) (match_dup 1)))] "" - " -{ rtx chain = gen_reg_rtx (Pmode); +{ + rtx chain = gen_reg_rtx (Pmode); rtx stack_bot = gen_rtx_MEM (Pmode, stack_pointer_rtx); rtx neg_op0; rtx insn, par, set, mem; @@ -9864,7 +9829,7 @@ emit_move_insn (operands[0], virtual_stack_dynamic_rtx); DONE; -}") +}) ;; These patterns say how to save and restore the stack pointer. We need not ;; save the stack pointer at function level since we are careful to @@ -9876,14 +9841,14 @@ ;; save area is a memory location. (define_expand "save_stack_function" - [(match_operand 0 "any_operand" "") - (match_operand 1 "any_operand" "")] + [(match_operand 0 "any_operand") + (match_operand 1 "any_operand")] "" "DONE;") (define_expand "restore_stack_function" - [(match_operand 0 "any_operand" "") - (match_operand 1 "any_operand" "")] + [(match_operand 0 "any_operand") + (match_operand 1 "any_operand")] "" "DONE;") @@ -9894,10 +9859,9 @@ [(set (match_dup 2) (match_dup 3)) (set (match_dup 4) (match_dup 2)) (match_dup 5) - (set (match_operand 0 "register_operand" "") - (match_operand 1 "register_operand" ""))] + (set (match_operand 0 "register_operand") + (match_operand 1 "register_operand"))] "" - " { rtvec p; @@ -9909,14 +9873,13 @@ RTVEC_ELT (p, 0) = gen_rtx_SET (gen_frame_mem (BLKmode, operands[0]), const0_rtx); operands[5] = gen_rtx_PARALLEL (VOIDmode, p); -}") +}) (define_expand "save_stack_nonlocal" [(set (match_dup 3) (match_dup 4)) - (set (match_operand 0 "memory_operand" "") (match_dup 3)) - (set (match_dup 2) (match_operand 1 "register_operand" ""))] + (set (match_operand 0 "memory_operand") (match_dup 3)) + (set (match_dup 2) (match_operand 1 "register_operand"))] "" - " { int units_per_word = (TARGET_32BIT) ? 4 : 8; @@ -9925,16 +9888,15 @@ operands[2] = adjust_address_nv (operands[0], Pmode, units_per_word); operands[3] = gen_reg_rtx (Pmode); operands[4] = gen_frame_mem (Pmode, operands[1]); -}") +}) (define_expand "restore_stack_nonlocal" - [(set (match_dup 2) (match_operand 1 "memory_operand" "")) + [(set (match_dup 2) (match_operand 1 "memory_operand")) (set (match_dup 3) (match_dup 4)) (set (match_dup 5) (match_dup 2)) (match_dup 6) - (set (match_operand 0 "register_operand" "") (match_dup 3))] + (set (match_operand 0 "register_operand") (match_dup 3))] "" - " { int units_per_word = (TARGET_32BIT) ? 4 : 8; rtvec p; @@ -9949,7 +9911,7 @@ RTVEC_ELT (p, 0) = gen_rtx_SET (gen_frame_mem (BLKmode, operands[0]), const0_rtx); operands[6] = gen_rtx_PARALLEL (VOIDmode, p); -}") +}) ;; TOC register handling. @@ -9960,16 +9922,15 @@ (unspec:SI [(const_int 0)] UNSPEC_TOC)) (use (reg:SI 2))])] "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2) && TARGET_32BIT" - "* { char buf[30]; extern int need_toc_init; need_toc_init = 1; - ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\", 1); + ASM_GENERATE_INTERNAL_LABEL (buf, "LCTOC", 1); operands[1] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf)); operands[2] = gen_rtx_REG (Pmode, 2); - return \"lwz %0,%1(%2)\"; -}" + return "lwz %0,%1(%2)"; +} [(set_attr "type" "load") (set_attr "update" "no") (set_attr "indexed" "no")]) @@ -9979,19 +9940,18 @@ (unspec:DI [(const_int 0)] UNSPEC_TOC)) (use (reg:DI 2))])] "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2) && TARGET_64BIT" - "* { char buf[30]; extern int need_toc_init; need_toc_init = 1; - ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\", + ASM_GENERATE_INTERNAL_LABEL (buf, "LCTOC", !TARGET_ELF || !TARGET_MINIMAL_TOC); if (TARGET_ELF) - strcat (buf, \"@toc\"); + strcat (buf, "@toc"); operands[1] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf)); operands[2] = gen_rtx_REG (Pmode, 2); - return \"ld %0,%1(%2)\"; -}" + return "ld %0,%1(%2)"; +} [(set_attr "type" "load") (set_attr "update" "no") (set_attr "indexed" "no")]) @@ -10018,7 +9978,7 @@ (use (unspec [(match_dup 0)] UNSPEC_TOC))] "!TARGET_LINK_STACK && TARGET_ELF && DEFAULT_ABI == ABI_V4 && (flag_pic == 2 || (flag_pic && TARGET_SECURE_PLT))" - "bcl 20,31,%0\\n%0:" + "bcl 20,31,%0\n%0:" [(set_attr "type" "branch") (set_attr "length" "4") (set_attr "cannot_copy" "yes")]) @@ -10029,15 +9989,14 @@ (use (unspec [(match_dup 0)] UNSPEC_TOC))] "TARGET_LINK_STACK && TARGET_ELF && DEFAULT_ABI == ABI_V4 && (flag_pic == 2 || (flag_pic && TARGET_SECURE_PLT))" - "* { char name[32]; static char templ[32]; get_ppc476_thunk_name (name); - sprintf (templ, \"bl %s\\n%%0:\", name); + sprintf (templ, "bl %s\n%%0:", name); return templ; -}" +} [(set_attr "type" "branch") (set_attr "length" "4") (set_attr "cannot_copy" "yes")]) @@ -10045,7 +10004,7 @@ (define_expand "load_toc_v4_PIC_1b" [(parallel [(set (reg:SI LR_REGNO) (unspec:SI [(match_operand:SI 0 "immediate_operand" "s") - (label_ref (match_operand 1 "" ""))] + (label_ref (match_operand 1 ""))] UNSPEC_TOCPTR)) (match_dup 1)])] "TARGET_ELF && DEFAULT_ABI == ABI_V4 && flag_pic == 2" @@ -10069,15 +10028,14 @@ UNSPEC_TOCPTR)) (match_dup 1)] "TARGET_LINK_STACK && TARGET_ELF && DEFAULT_ABI == ABI_V4 && flag_pic == 2" - "* { char name[32]; static char templ[32]; get_ppc476_thunk_name (name); - sprintf (templ, \"bl %s\\n\\tb $+8\\n\\t.long %%0-$\", name); + sprintf (templ, "bl %s\;b $+8\;.long %%0-$", name); return templ; -}" +} [(set_attr "type" "branch") (set_attr "length" "16")]) @@ -10119,11 +10077,10 @@ ;; On Darwin, we need to reload the picbase. (define_expand "builtin_setjmp_receiver" - [(use (label_ref (match_operand 0 "" "")))] + [(use (label_ref (match_operand 0 "")))] "(DEFAULT_ABI == ABI_V4 && flag_pic == 1) || (TARGET_TOC && TARGET_MINIMAL_TOC) || (DEFAULT_ABI == ABI_DARWIN && flag_pic)" - " { #if TARGET_MACHO if (DEFAULT_ABI == ABI_DARWIN) @@ -10134,7 +10091,7 @@ char tmplab[20]; crtl->uses_pic_offset_table = 1; - ASM_GENERATE_INTERNAL_LABEL(tmplab, \"LSJR\", + ASM_GENERATE_INTERNAL_LABEL(tmplab, "LSJR", CODE_LABEL_NUMBER (operands[0])); tmplabrtx = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (tmplab)); @@ -10146,7 +10103,7 @@ #endif rs6000_emit_load_toc_table (FALSE); DONE; -}") +}) ;; Largetoc support (define_insn "*largetoc_high" @@ -10231,12 +10188,11 @@ ;; Call and call_value insns (define_expand "call" - [(parallel [(call (mem:SI (match_operand 0 "address_operand" "")) - (match_operand 1 "" "")) - (use (match_operand 2 "" "")) + [(parallel [(call (mem:SI (match_operand 0 "address_operand")) + (match_operand 1 "")) + (use (match_operand 2 "")) (clobber (reg:SI LR_REGNO))])] "" - " { #if TARGET_MACHO if (MACHOPIC_INDIRECT) @@ -10271,16 +10227,15 @@ gcc_unreachable (); } } -}") +}) (define_expand "call_value" - [(parallel [(set (match_operand 0 "" "") - (call (mem:SI (match_operand 1 "address_operand" "")) - (match_operand 2 "" ""))) - (use (match_operand 3 "" "")) + [(parallel [(set (match_operand 0 "") + (call (mem:SI (match_operand 1 "address_operand")) + (match_operand 2 ""))) + (use (match_operand 3 "")) (clobber (reg:SI LR_REGNO))])] "" - " { #if TARGET_MACHO if (MACHOPIC_INDIRECT) @@ -10315,7 +10270,7 @@ gcc_unreachable (); } } -}") +}) ;; Call to function in current module. No TOC pointer reload needed. ;; Operand2 is nonzero if we are using the V.4 calling sequence and @@ -10329,16 +10284,15 @@ (use (match_operand:SI 2 "immediate_operand" "O,n")) (clobber (reg:SI LR_REGNO))] "(INTVAL (operands[2]) & CALL_LONG) == 0" - "* { if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS) - output_asm_insn (\"crxor 6,6,6\", operands); + output_asm_insn ("crxor 6,6,6", operands); else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS) - output_asm_insn (\"creqv 6,6,6\", operands); + output_asm_insn ("creqv 6,6,6", operands); - return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z0@local\" : \"bl %z0\"; -}" + return (DEFAULT_ABI == ABI_V4 && flag_pic) ? "bl %z0@local" : "bl %z0"; +} [(set_attr "type" "branch") (set_attr "length" "4,8")]) @@ -10348,16 +10302,15 @@ (use (match_operand:SI 2 "immediate_operand" "O,n")) (clobber (reg:SI LR_REGNO))] "TARGET_64BIT && (INTVAL (operands[2]) & CALL_LONG) == 0" - "* { if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS) - output_asm_insn (\"crxor 6,6,6\", operands); + output_asm_insn ("crxor 6,6,6", operands); else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS) - output_asm_insn (\"creqv 6,6,6\", operands); + output_asm_insn ("creqv 6,6,6", operands); - return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z0@local\" : \"bl %z0\"; -}" + return (DEFAULT_ABI == ABI_V4 && flag_pic) ? "bl %z0@local" : "bl %z0"; +} [(set_attr "type" "branch") (set_attr "length" "4,8")]) @@ -10368,16 +10321,15 @@ (use (match_operand:SI 3 "immediate_operand" "O,n")) (clobber (reg:SI LR_REGNO))] "(INTVAL (operands[3]) & CALL_LONG) == 0" - "* { if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS) - output_asm_insn (\"crxor 6,6,6\", operands); + output_asm_insn ("crxor 6,6,6", operands); else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS) - output_asm_insn (\"creqv 6,6,6\", operands); + output_asm_insn ("creqv 6,6,6", operands); - return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z1@local\" : \"bl %z1\"; -}" + return (DEFAULT_ABI == ABI_V4 && flag_pic) ? "bl %z1@local" : "bl %z1"; +} [(set_attr "type" "branch") (set_attr "length" "4,8")]) @@ -10389,16 +10341,15 @@ (use (match_operand:SI 3 "immediate_operand" "O,n")) (clobber (reg:SI LR_REGNO))] "TARGET_64BIT && (INTVAL (operands[3]) & CALL_LONG) == 0" - "* { if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS) - output_asm_insn (\"crxor 6,6,6\", operands); + output_asm_insn ("crxor 6,6,6", operands); else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS) - output_asm_insn (\"creqv 6,6,6\", operands); + output_asm_insn ("creqv 6,6,6", operands); - return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z1@local\" : \"bl %z1\"; -}" + return (DEFAULT_ABI == ABI_V4 && flag_pic) ? "bl %z1@local" : "bl %z1"; +} [(set_attr "type" "branch") (set_attr "length" "4,8")]) @@ -10767,12 +10718,11 @@ ;; Call subroutine returning any type. (define_expand "untyped_call" - [(parallel [(call (match_operand 0 "" "") + [(parallel [(call (match_operand 0 "") (const_int 0)) - (match_operand 1 "" "") - (match_operand 2 "" "")])] + (match_operand 1 "") + (match_operand 2 "")])] "" - " { int i; @@ -10791,16 +10741,15 @@ emit_insn (gen_blockage ()); DONE; -}") +}) ;; sibling call patterns (define_expand "sibcall" - [(parallel [(call (mem:SI (match_operand 0 "address_operand" "")) - (match_operand 1 "" "")) - (use (match_operand 2 "" "")) + [(parallel [(call (mem:SI (match_operand 0 "address_operand")) + (match_operand 1 "")) + (use (match_operand 2 "")) (simple_return)])] "" - " { #if TARGET_MACHO if (MACHOPIC_INDIRECT) @@ -10817,16 +10766,15 @@ rs6000_sibcall_aix (NULL_RTX, operands[0], operands[1], operands[2]); DONE; } -}") +}) (define_expand "sibcall_value" - [(parallel [(set (match_operand 0 "register_operand" "") - (call (mem:SI (match_operand 1 "address_operand" "")) - (match_operand 2 "" ""))) - (use (match_operand 3 "" "")) + [(parallel [(set (match_operand 0 "register_operand") + (call (mem:SI (match_operand 1 "address_operand")) + (match_operand 2 ""))) + (use (match_operand 3 "")) (simple_return)])] "" - " { #if TARGET_MACHO if (MACHOPIC_INDIRECT) @@ -10843,7 +10791,7 @@ rs6000_sibcall_aix (operands[0], operands[1], operands[2], operands[3]); DONE; } -}") +}) (define_insn "*sibcall_local32" [(call (mem:SI (match_operand:SI 0 "current_file_function_operand" "s,s")) @@ -10851,16 +10799,15 @@ (use (match_operand:SI 2 "immediate_operand" "O,n")) (simple_return)] "(INTVAL (operands[2]) & CALL_LONG) == 0" - "* { if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS) - output_asm_insn (\"crxor 6,6,6\", operands); + output_asm_insn ("crxor 6,6,6", operands); else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS) - output_asm_insn (\"creqv 6,6,6\", operands); + output_asm_insn ("creqv 6,6,6", operands); - return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z0@local\" : \"b %z0\"; -}" + return (DEFAULT_ABI == ABI_V4 && flag_pic) ? "b %z0@local" : "b %z0"; +} [(set_attr "type" "branch") (set_attr "length" "4,8")]) @@ -10870,16 +10817,15 @@ (use (match_operand:SI 2 "immediate_operand" "O,n")) (simple_return)] "TARGET_64BIT && (INTVAL (operands[2]) & CALL_LONG) == 0" - "* { if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS) - output_asm_insn (\"crxor 6,6,6\", operands); + output_asm_insn ("crxor 6,6,6", operands); else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS) - output_asm_insn (\"creqv 6,6,6\", operands); + output_asm_insn ("creqv 6,6,6", operands); - return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z0@local\" : \"b %z0\"; -}" + return (DEFAULT_ABI == ABI_V4 && flag_pic) ? "b %z0@local" : "b %z0"; +} [(set_attr "type" "branch") (set_attr "length" "4,8")]) @@ -10890,16 +10836,15 @@ (use (match_operand:SI 3 "immediate_operand" "O,n")) (simple_return)] "(INTVAL (operands[3]) & CALL_LONG) == 0" - "* { if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS) - output_asm_insn (\"crxor 6,6,6\", operands); + output_asm_insn ("crxor 6,6,6", operands); else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS) - output_asm_insn (\"creqv 6,6,6\", operands); + output_asm_insn ("creqv 6,6,6", operands); - return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z1@local\" : \"b %z1\"; -}" + return (DEFAULT_ABI == ABI_V4 && flag_pic) ? "b %z1@local" : "b %z1"; +} [(set_attr "type" "branch") (set_attr "length" "4,8")]) @@ -10910,16 +10855,15 @@ (use (match_operand:SI 3 "immediate_operand" "O,n")) (simple_return)] "TARGET_64BIT && (INTVAL (operands[3]) & CALL_LONG) == 0" - "* { if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS) - output_asm_insn (\"crxor 6,6,6\", operands); + output_asm_insn ("crxor 6,6,6", operands); else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS) - output_asm_insn (\"creqv 6,6,6\", operands); + output_asm_insn ("creqv 6,6,6", operands); - return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z1@local\" : \"b %z1\"; -}" + return (DEFAULT_ABI == ABI_V4 && flag_pic) ? "b %z1@local" : "b %z1"; +} [(set_attr "type" "branch") (set_attr "length" "4,8")]) @@ -11117,11 +11061,10 @@ (define_expand "cbranch<mode>4" [(use (match_operator 0 "comparison_operator" - [(match_operand:GPR 1 "gpc_reg_operand" "") - (match_operand:GPR 2 "reg_or_short_operand" "")])) - (use (match_operand 3 ""))] + [(match_operand:GPR 1 "gpc_reg_operand") + (match_operand:GPR 2 "reg_or_short_operand")])) + (use (match_operand 3))] "" - " { /* Take care of the possibility that operands[2] might be negative but this might be a logical operation. That insn doesn't exist. */ @@ -11136,19 +11079,18 @@ rs6000_emit_cbranch (<MODE>mode, operands); DONE; -}") +}) (define_expand "cbranch<mode>4" [(use (match_operator 0 "comparison_operator" - [(match_operand:FP 1 "gpc_reg_operand" "") - (match_operand:FP 2 "gpc_reg_operand" "")])) - (use (match_operand 3 ""))] + [(match_operand:FP 1 "gpc_reg_operand") + (match_operand:FP 2 "gpc_reg_operand")])) + (use (match_operand 3))] "" - " { rs6000_emit_cbranch (<MODE>mode, operands); DONE; -}") +}) (define_expand "cstore<mode>4_signed" [(use (match_operator 1 "signed_comparison_operator" @@ -11560,18 +11502,18 @@ (define_peephole2 [(set (match_operand:SI 0 "register_operand") - (match_operand:SI 1 "logical_const_operand" "")) + (match_operand:SI 1 "logical_const_operand")) (set (match_dup 0) (match_operator:SI 3 "boolean_or_operator" [(match_dup 0) - (match_operand:SI 2 "logical_const_operand" "")])) - (set (match_operand:CC 4 "cc_reg_operand" "") - (compare:CC (match_operand:SI 5 "gpc_reg_operand" "") + (match_operand:SI 2 "logical_const_operand")])) + (set (match_operand:CC 4 "cc_reg_operand") + (compare:CC (match_operand:SI 5 "gpc_reg_operand") (match_dup 0))) (set (pc) (if_then_else (match_operator 6 "equality_operator" [(match_dup 4) (const_int 0)]) - (match_operand 7 "" "") - (match_operand 8 "" "")))] + (match_operand 7 "") + (match_operand 8 "")))] "peep2_reg_dead_p (3, operands[0]) && peep2_reg_dead_p (4, operands[4]) && REGNO (operands[0]) != REGNO (operands[5])" @@ -11620,21 +11562,21 @@ [(set_attr "length" "8")]) (define_split - [(set (match_operand:CC 3 "cc_reg_operand" "") - (compare:CC (match_operand:SI 1 "gpc_reg_operand" "") - (match_operand:SI 2 "short_cint_operand" ""))) - (set (match_operand:SI 0 "gpc_reg_operand" "") - (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))] + [(set (match_operand:CC 3 "cc_reg_operand") + (compare:CC (match_operand:SI 1 "gpc_reg_operand") + (match_operand:SI 2 "short_cint_operand"))) + (set (match_operand:SI 0 "gpc_reg_operand") + (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand")))] "" [(set (match_dup 3) (compare:CC (match_dup 1) (match_dup 2))) (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))]) (define_split - [(set (match_operand:CCUNS 3 "cc_reg_operand" "") - (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "") - (match_operand:SI 2 "u_short_cint_operand" ""))) - (set (match_operand:SI 0 "gpc_reg_operand" "") - (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))] + [(set (match_operand:CCUNS 3 "cc_reg_operand") + (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand") + (match_operand:SI 2 "u_short_cint_operand"))) + (set (match_operand:SI 0 "gpc_reg_operand") + (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand")))] "" [(set (match_dup 3) (compare:CCUNS (match_dup 1) (match_dup 2))) (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))]) @@ -11773,12 +11715,12 @@ (set_attr "length" "8,16")]) (define_split - [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") + [(set (match_operand:CC 0 "cc_reg_not_cr0_operand") (compare:CC (match_operator:SI 1 "scc_comparison_operator" - [(match_operand 2 "cc_reg_operand" "") + [(match_operand 2 "cc_reg_operand") (const_int 0)]) (const_int 0))) - (set (match_operand:SI 3 "gpc_reg_operand" "") + (set (match_operand:SI 3 "gpc_reg_operand") (match_op_dup 1 [(match_dup 2) (const_int 0)]))] "TARGET_32BIT && reload_completed" [(set (match_dup 3) @@ -11795,7 +11737,6 @@ (const_int 0)]) (match_operand:SI 3 "const_int_operand" "n")))] "" - "* { int is_bit = ccr_bit (operands[1], 1); int put_bit = 31 - (INTVAL (operands[3]) & 31); @@ -11809,8 +11750,8 @@ operands[4] = GEN_INT (count); operands[5] = GEN_INT (put_bit); - return \"mfcr %0%Q2\;rlwinm %0,%0,%4,%5,%5\"; -}" + return "mfcr %0%Q2\;rlwinm %0,%0,%4,%5,%5"; +} [(set (attr "type") (cond [(match_test "TARGET_MFCRF") (const_string "mfcrf") @@ -11830,7 +11771,6 @@ (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)]) (match_dup 3)))] "" - "* { int is_bit = ccr_bit (operands[1], 1); int put_bit = 31 - (INTVAL (operands[3]) & 31); @@ -11838,7 +11778,7 @@ /* Force split for non-cc0 compare. */ if (which_alternative == 1) - return \"#\"; + return "#"; if (is_bit >= put_bit) count = is_bit - put_bit; @@ -11848,8 +11788,8 @@ operands[5] = GEN_INT (count); operands[6] = GEN_INT (put_bit); - return \"mfcr %4%Q2\;rlwinm. %4,%4,%5,%6,%6\"; -}" + return "mfcr %4%Q2\;rlwinm. %4,%4,%5,%6,%6"; +} [(set_attr "type" "shift") (set_attr "dot" "yes") (set_attr "length" "8,16")]) @@ -12433,7 +12373,6 @@ "" [(set (match_dup 0) (compare:CCEQ (xor:SI (match_dup 1) (match_dup 3)) (match_dup 5)))] - " { int positive_1, positive_2; @@ -12469,7 +12408,7 @@ { operands[5] = const1_rtx; } -}") +}) ;; Unconditional branch and return. @@ -12894,7 +12833,6 @@ (match_operand 3 "immediate_operand" "n")] UNSPEC_MOVESI_FROM_CR))])] "TARGET_MFCRF" - "* { int mask = 0; int i; @@ -12902,10 +12840,10 @@ { mask = INTVAL (XVECEXP (SET_SRC (XVECEXP (operands[0], 0, i)), 0, 1)); operands[4] = GEN_INT (mask); - output_asm_insn (\"mfcr %1,%4\", operands); + output_asm_insn ("mfcr %1,%4", operands); } - return \"\"; -}" + return ""; +} [(set_attr "type" "mfcrf")]) ;; Don't include the volatile CRs since their values are not used wrt CR save @@ -13064,8 +13002,8 @@ ; faster; for instance, on the 601 and 750. (define_expand "movsi_to_cr_one" - [(set (match_operand:CC 0 "cc_reg_operand" "") - (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "") + [(set (match_operand:CC 0 "cc_reg_operand") + (unspec:CC [(match_operand:SI 1 "gpc_reg_operand") (match_dup 2)] UNSPEC_MOVESI_TO_CR))] "" "operands[2] = GEN_INT (1 << (75 - REGNO (operands[0])));") @@ -13077,15 +13015,14 @@ (match_operand 3 "immediate_operand" "n")] UNSPEC_MOVESI_TO_CR))])] "" - "* { int mask = 0; int i; for (i = 0; i < XVECLEN (operands[0], 0); i++) mask |= INTVAL (XVECEXP (SET_SRC (XVECEXP (operands[0], 0, i)), 0, 1)); operands[4] = GEN_INT (mask); - return \"mtcrf %4,%2\"; -}" + return "mtcrf %4,%2"; +} [(set_attr "type" "mtcr")]) (define_insn "*mtcrfsi" @@ -13273,16 +13210,15 @@ ; This is used in compiling the unwind routines. (define_expand "eh_return" - [(use (match_operand 0 "general_operand" ""))] + [(use (match_operand 0 "general_operand"))] "" - " { if (TARGET_32BIT) emit_insn (gen_eh_set_lr_si (operands[0])); else emit_insn (gen_eh_set_lr_di (operands[0])); DONE; -}") +}) ; We can't expand this before we know where the link register is stored. (define_insn "eh_set_lr_<mode>" @@ -13293,27 +13229,25 @@ "#") (define_split - [(unspec_volatile [(match_operand 0 "register_operand" "")] UNSPECV_EH_RR) - (clobber (match_scratch 1 ""))] + [(unspec_volatile [(match_operand 0 "register_operand")] UNSPECV_EH_RR) + (clobber (match_scratch 1))] "reload_completed" [(const_int 0)] - " { rs6000_emit_eh_reg_restore (operands[0], operands[1]); DONE; -}") +}) (define_insn "prefetch" [(prefetch (match_operand 0 "indexed_or_indirect_address" "a") (match_operand:SI 1 "const_int_operand" "n") (match_operand:SI 2 "const_int_operand" "n"))] "" - "* { if (GET_CODE (operands[0]) == REG) - return INTVAL (operands[1]) ? \"dcbtst 0,%0\" : \"dcbt 0,%0\"; - return INTVAL (operands[1]) ? \"dcbtst %a0\" : \"dcbt %a0\"; -}" + return INTVAL (operands[1]) ? "dcbtst 0,%0" : "dcbt 0,%0"; + return INTVAL (operands[1]) ? "dcbtst %a0" : "dcbt %a0"; +} [(set_attr "type" "load")]) ;; Handle -fsplit-stack. @@ -13397,11 +13331,11 @@ ;; Note that the conditions for expansion are in the FMA_F iterator. (define_expand "fma<mode>4" - [(set (match_operand:FMA_F 0 "gpc_reg_operand" "") + [(set (match_operand:FMA_F 0 "gpc_reg_operand") (fma:FMA_F - (match_operand:FMA_F 1 "gpc_reg_operand" "") - (match_operand:FMA_F 2 "gpc_reg_operand" "") - (match_operand:FMA_F 3 "gpc_reg_operand" "")))] + (match_operand:FMA_F 1 "gpc_reg_operand") + (match_operand:FMA_F 2 "gpc_reg_operand") + (match_operand:FMA_F 3 "gpc_reg_operand")))] "" "") @@ -13421,11 +13355,11 @@ ; Altivec only has fma and nfms. (define_expand "fms<mode>4" - [(set (match_operand:FMA_F 0 "gpc_reg_operand" "") + [(set (match_operand:FMA_F 0 "gpc_reg_operand") (fma:FMA_F - (match_operand:FMA_F 1 "gpc_reg_operand" "") - (match_operand:FMA_F 2 "gpc_reg_operand" "") - (neg:FMA_F (match_operand:FMA_F 3 "gpc_reg_operand" ""))))] + (match_operand:FMA_F 1 "gpc_reg_operand") + (match_operand:FMA_F 2 "gpc_reg_operand") + (neg:FMA_F (match_operand:FMA_F 3 "gpc_reg_operand"))))] "!VECTOR_UNIT_ALTIVEC_P (<MODE>mode)" "") @@ -13445,34 +13379,34 @@ ;; If signed zeros are ignored, -(a * b - c) = -a * b + c. (define_expand "fnma<mode>4" - [(set (match_operand:FMA_F 0 "gpc_reg_operand" "") + [(set (match_operand:FMA_F 0 "gpc_reg_operand") (neg:FMA_F (fma:FMA_F - (match_operand:FMA_F 1 "gpc_reg_operand" "") - (match_operand:FMA_F 2 "gpc_reg_operand" "") - (neg:FMA_F (match_operand:FMA_F 3 "gpc_reg_operand" "")))))] + (match_operand:FMA_F 1 "gpc_reg_operand") + (match_operand:FMA_F 2 "gpc_reg_operand") + (neg:FMA_F (match_operand:FMA_F 3 "gpc_reg_operand")))))] "!HONOR_SIGNED_ZEROS (<MODE>mode)" "") ;; If signed zeros are ignored, -(a * b + c) = -a * b - c. (define_expand "fnms<mode>4" - [(set (match_operand:FMA_F 0 "gpc_reg_operand" "") + [(set (match_operand:FMA_F 0 "gpc_reg_operand") (neg:FMA_F (fma:FMA_F - (match_operand:FMA_F 1 "gpc_reg_operand" "") - (match_operand:FMA_F 2 "gpc_reg_operand" "") - (match_operand:FMA_F 3 "gpc_reg_operand" ""))))] + (match_operand:FMA_F 1 "gpc_reg_operand") + (match_operand:FMA_F 2 "gpc_reg_operand") + (match_operand:FMA_F 3 "gpc_reg_operand"))))] "!HONOR_SIGNED_ZEROS (<MODE>mode) && !VECTOR_UNIT_ALTIVEC_P (<MODE>mode)" "") ; Not an official optab name, but used from builtins. (define_expand "nfma<mode>4" - [(set (match_operand:FMA_F 0 "gpc_reg_operand" "") + [(set (match_operand:FMA_F 0 "gpc_reg_operand") (neg:FMA_F (fma:FMA_F - (match_operand:FMA_F 1 "gpc_reg_operand" "") - (match_operand:FMA_F 2 "gpc_reg_operand" "") - (match_operand:FMA_F 3 "gpc_reg_operand" ""))))] + (match_operand:FMA_F 1 "gpc_reg_operand") + (match_operand:FMA_F 2 "gpc_reg_operand") + (match_operand:FMA_F 3 "gpc_reg_operand"))))] "!VECTOR_UNIT_ALTIVEC_P (<MODE>mode)" "") @@ -13493,12 +13427,12 @@ ; Not an official optab name, but used from builtins. (define_expand "nfms<mode>4" - [(set (match_operand:FMA_F 0 "gpc_reg_operand" "") + [(set (match_operand:FMA_F 0 "gpc_reg_operand") (neg:FMA_F (fma:FMA_F - (match_operand:FMA_F 1 "gpc_reg_operand" "") - (match_operand:FMA_F 2 "gpc_reg_operand" "") - (neg:FMA_F (match_operand:FMA_F 3 "gpc_reg_operand" "")))))] + (match_operand:FMA_F 1 "gpc_reg_operand") + (match_operand:FMA_F 2 "gpc_reg_operand") + (neg:FMA_F (match_operand:FMA_F 3 "gpc_reg_operand")))))] "" "") @@ -13520,7 +13454,7 @@ (define_expand "rs6000_get_timebase" - [(use (match_operand:DI 0 "gpc_reg_operand" ""))] + [(use (match_operand:DI 0 "gpc_reg_operand"))] "" { if (TARGET_POWERPC64) @@ -13618,8 +13552,8 @@ ;; (addis followed by load) even on power8. (define_split - [(set (match_operand:INT1 0 "toc_fusion_or_p9_reg_operand" "") - (match_operand:INT1 1 "toc_fusion_mem_raw" ""))] + [(set (match_operand:INT1 0 "toc_fusion_or_p9_reg_operand") + (match_operand:INT1 1 "toc_fusion_mem_raw"))] "TARGET_TOC_FUSION_INT && can_create_pseudo_p ()" [(parallel [(set (match_dup 0) (match_dup 2)) (unspec [(const_int 0)] UNSPEC_FUSION_ADDIS) @@ -13669,10 +13603,10 @@ ;; insn (define_peephole2 - [(set (match_operand:P 0 "base_reg_operand" "") - (match_operand:P 1 "fusion_gpr_addis" "")) - (set (match_operand:INT1 2 "base_reg_operand" "") - (match_operand:INT1 3 "fusion_gpr_mem_load" ""))] + [(set (match_operand:P 0 "base_reg_operand") + (match_operand:P 1 "fusion_gpr_addis")) + (set (match_operand:INT1 2 "base_reg_operand") + (match_operand:INT1 3 "fusion_gpr_mem_load"))] "TARGET_P8_FUSION && fusion_gpr_load_p (operands[0], operands[1], operands[2], operands[3])" @@ -13700,10 +13634,10 @@ ;; ISA 3.0 (power9) fusion support ;; Merge addis with floating load/store to FPRs (or GPRs). (define_peephole2 - [(set (match_operand:P 0 "base_reg_operand" "") - (match_operand:P 1 "fusion_gpr_addis" "")) - (set (match_operand:SFDF 2 "toc_fusion_or_p9_reg_operand" "") - (match_operand:SFDF 3 "fusion_offsettable_mem_operand" ""))] + [(set (match_operand:P 0 "base_reg_operand") + (match_operand:P 1 "fusion_gpr_addis")) + (set (match_operand:SFDF 2 "toc_fusion_or_p9_reg_operand") + (match_operand:SFDF 3 "fusion_offsettable_mem_operand"))] "TARGET_P9_FUSION && peep2_reg_dead_p (2, operands[0]) && fusion_p9_p (operands[0], operands[1], operands[2], operands[3])" [(const_int 0)] @@ -13713,10 +13647,10 @@ }) (define_peephole2 - [(set (match_operand:P 0 "base_reg_operand" "") - (match_operand:P 1 "fusion_gpr_addis" "")) - (set (match_operand:SFDF 2 "offsettable_mem_operand" "") - (match_operand:SFDF 3 "toc_fusion_or_p9_reg_operand" ""))] + [(set (match_operand:P 0 "base_reg_operand") + (match_operand:P 1 "fusion_gpr_addis")) + (set (match_operand:SFDF 2 "offsettable_mem_operand") + (match_operand:SFDF 3 "toc_fusion_or_p9_reg_operand"))] "TARGET_P9_FUSION && peep2_reg_dead_p (2, operands[0]) && fusion_p9_p (operands[0], operands[1], operands[2], operands[3]) && !rtx_equal_p (operands[0], operands[3])" @@ -13727,22 +13661,22 @@ }) (define_peephole2 - [(set (match_operand:SDI 0 "int_reg_operand" "") - (match_operand:SDI 1 "upper16_cint_operand" "")) + [(set (match_operand:SDI 0 "int_reg_operand") + (match_operand:SDI 1 "upper16_cint_operand")) (set (match_dup 0) (ior:SDI (match_dup 0) - (match_operand:SDI 2 "u_short_cint_operand" "")))] + (match_operand:SDI 2 "u_short_cint_operand")))] "TARGET_P9_FUSION" [(set (match_dup 0) (unspec:SDI [(match_dup 1) (match_dup 2)] UNSPEC_FUSION_P9))]) (define_peephole2 - [(set (match_operand:SDI 0 "int_reg_operand" "") - (match_operand:SDI 1 "upper16_cint_operand" "")) - (set (match_operand:SDI 2 "int_reg_operand" "") + [(set (match_operand:SDI 0 "int_reg_operand") + (match_operand:SDI 1 "upper16_cint_operand")) + (set (match_operand:SDI 2 "int_reg_operand") (ior:SDI (match_dup 0) - (match_operand:SDI 3 "u_short_cint_operand" "")))] + (match_operand:SDI 3 "u_short_cint_operand")))] "TARGET_P9_FUSION && !rtx_equal_p (operands[0], operands[2]) && peep2_reg_dead_p (2, operands[0])" @@ -13958,10 +13892,10 @@ (KF "DI")]) (define_expand "unpack<mode>" - [(set (match_operand:<FP128_64> 0 "nonimmediate_operand" "") + [(set (match_operand:<FP128_64> 0 "nonimmediate_operand") (unspec:<FP128_64> - [(match_operand:FMOVE128 1 "register_operand" "") - (match_operand:QI 2 "const_0_to_1_operand" "")] + [(match_operand:FMOVE128 1 "register_operand") + (match_operand:QI 2 "const_0_to_1_operand")] UNSPEC_UNPACK_128BIT))] "FLOAT128_2REG_P (<MODE>mode)" "") |