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-rw-r--r--gcc/config/rs6000/altivec.md8
-rw-r--r--gcc/config/rs6000/dfp.md10
-rw-r--r--gcc/config/rs6000/linux64.h2
-rw-r--r--gcc/config/rs6000/paired.md4
-rw-r--r--gcc/config/rs6000/rs6000.c21
-rw-r--r--gcc/config/rs6000/rs6000.md20
-rw-r--r--gcc/config/rs6000/sync.md2
-rw-r--r--gcc/config/rs6000/vsx.md8
8 files changed, 30 insertions, 45 deletions
diff --git a/gcc/config/rs6000/altivec.md b/gcc/config/rs6000/altivec.md
index 7ca496f937a..5384d0297dc 100644
--- a/gcc/config/rs6000/altivec.md
+++ b/gcc/config/rs6000/altivec.md
@@ -165,8 +165,8 @@
;; Vector move instructions.
(define_insn "*altivec_mov<mode>"
- [(set (match_operand:VM2 0 "nonimmediate_operand" "=Z,v,v,*o,*r,*r,v,v")
- (match_operand:VM2 1 "input_operand" "v,Z,v,r,o,r,j,W"))]
+ [(set (match_operand:VM2 0 "nonimmediate_operand" "=Z,v,v,*Y,*r,*r,v,v")
+ (match_operand:VM2 1 "input_operand" "v,Z,v,r,Y,r,j,W"))]
"VECTOR_MEM_ALTIVEC_P (<MODE>mode)
&& (register_operand (operands[0], <MODE>mode)
|| register_operand (operands[1], <MODE>mode))"
@@ -190,8 +190,8 @@
;; is for unions. However for plain data movement, slightly favor the vector
;; loads
(define_insn "*altivec_movti"
- [(set (match_operand:TI 0 "nonimmediate_operand" "=Z,v,v,?o,?r,?r,v,v")
- (match_operand:TI 1 "input_operand" "v,Z,v,r,o,r,j,W"))]
+ [(set (match_operand:TI 0 "nonimmediate_operand" "=Z,v,v,?Y,?r,?r,v,v")
+ (match_operand:TI 1 "input_operand" "v,Z,v,r,Y,r,j,W"))]
"VECTOR_MEM_ALTIVEC_P (TImode)
&& (register_operand (operands[0], TImode)
|| register_operand (operands[1], TImode))"
diff --git a/gcc/config/rs6000/dfp.md b/gcc/config/rs6000/dfp.md
index 9dadf6fa4a5..7dd62b71736 100644
--- a/gcc/config/rs6000/dfp.md
+++ b/gcc/config/rs6000/dfp.md
@@ -426,12 +426,12 @@
"TARGET_HARD_FLOAT && TARGET_FPRS"
"{ rs6000_emit_move (operands[0], operands[1], TDmode); DONE; }")
-; It's important to list the o->f and f->o moves before f->f because
-; otherwise reload, given m->f, will try to pick f->f and reload it,
-; which doesn't make progress. Likewise r->Y must be before r->r.
+; It's important to list the Y->r and r->Y moves before r->r because
+; otherwise reload, given m->r, will try to pick r->r and reload it,
+; which doesn't make progress.
(define_insn_and_split "*movtd_internal"
- [(set (match_operand:TD 0 "nonimmediate_operand" "=o,d,d,r,Y,r")
- (match_operand:TD 1 "input_operand" "d,o,d,YGHF,r,r"))]
+ [(set (match_operand:TD 0 "nonimmediate_operand" "=m,d,d,Y,r,r")
+ (match_operand:TD 1 "input_operand" "d,m,d,r,YGHF,r"))]
"TARGET_HARD_FLOAT && TARGET_FPRS
&& (gpc_reg_operand (operands[0], TDmode)
|| gpc_reg_operand (operands[1], TDmode))"
diff --git a/gcc/config/rs6000/linux64.h b/gcc/config/rs6000/linux64.h
index 28ba8f8f6a8..4d2c36503fb 100644
--- a/gcc/config/rs6000/linux64.h
+++ b/gcc/config/rs6000/linux64.h
@@ -318,6 +318,8 @@ extern int dot_symbols;
builtin_define ("__PPC64__"); \
builtin_define ("__powerpc__"); \
builtin_define ("__powerpc64__"); \
+ if (!DOT_SYMBOLS) \
+ builtin_define ("_CALL_LINUX"); \
builtin_assert ("cpu=powerpc64"); \
builtin_assert ("machine=powerpc64"); \
} \
diff --git a/gcc/config/rs6000/paired.md b/gcc/config/rs6000/paired.md
index 9dce18d8149..cfce1992b4e 100644
--- a/gcc/config/rs6000/paired.md
+++ b/gcc/config/rs6000/paired.md
@@ -201,8 +201,8 @@
[(set_attr "type" "fp")])
(define_insn "*movv2sf_paired"
- [(set (match_operand:V2SF 0 "nonimmediate_operand" "=Z,f,f,o,r,r,f")
- (match_operand:V2SF 1 "input_operand" "f,Z,f,r,o,r,W"))]
+ [(set (match_operand:V2SF 0 "nonimmediate_operand" "=Z,f,f,Y,r,r,f")
+ (match_operand:V2SF 1 "input_operand" "f,Z,f,r,Y,r,W"))]
"TARGET_PAIRED_FLOAT
&& (register_operand (operands[0], V2SFmode)
|| register_operand (operands[1], V2SFmode))"
diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c
index 0c67411f7fa..3fa7b5166a9 100644
--- a/gcc/config/rs6000/rs6000.c
+++ b/gcc/config/rs6000/rs6000.c
@@ -6197,27 +6197,6 @@ rs6000_legitimize_reload_address (rtx x, enum machine_mode mode,
return x;
}
- /* Force ld/std non-word aligned offset into base register by wrapping
- in offset 0. */
- if (GET_CODE (x) == PLUS
- && GET_CODE (XEXP (x, 0)) == REG
- && REGNO (XEXP (x, 0)) < 32
- && INT_REG_OK_FOR_BASE_P (XEXP (x, 0), 1)
- && GET_CODE (XEXP (x, 1)) == CONST_INT
- && reg_offset_p
- && (INTVAL (XEXP (x, 1)) & 3) != 0
- && VECTOR_MEM_NONE_P (mode)
- && GET_MODE_SIZE (mode) >= UNITS_PER_WORD
- && TARGET_POWERPC64)
- {
- x = gen_rtx_PLUS (GET_MODE (x), x, GEN_INT (0));
- push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
- BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0,
- opnum, (enum reload_type) type);
- *win = 1;
- return x;
- }
-
if (GET_CODE (x) == PLUS
&& GET_CODE (XEXP (x, 0)) == REG
&& REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index 2625bd72c07..25fed1ffa8f 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -3126,13 +3126,15 @@
FAIL;
if (TARGET_POWERPC64 && GET_MODE (operands[0]) == DImode)
- emit_insn (gen_insvdi (operands[0], operands[1], operands[2], operands[3]));
+ emit_insn (gen_insvdi_internal (operands[0], operands[1], operands[2],
+ operands[3]));
else
- emit_insn (gen_insvsi (operands[0], operands[1], operands[2], operands[3]));
+ emit_insn (gen_insvsi_internal (operands[0], operands[1], operands[2],
+ operands[3]));
DONE;
}")
-(define_insn "insvsi"
+(define_insn "insvsi_internal"
[(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
(match_operand:SI 1 "const_int_operand" "i")
(match_operand:SI 2 "const_int_operand" "i"))
@@ -3267,7 +3269,7 @@
}"
[(set_attr "type" "insert_word")])
-(define_insn "insvdi"
+(define_insn "insvdi_internal"
[(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r")
(match_operand:SI 1 "const_int_operand" "i")
(match_operand:SI 2 "const_int_operand" "i"))
@@ -3339,13 +3341,15 @@
FAIL;
if (TARGET_POWERPC64 && GET_MODE (operands[1]) == DImode)
- emit_insn (gen_extzvdi (operands[0], operands[1], operands[2], operands[3]));
+ emit_insn (gen_extzvdi_internal (operands[0], operands[1], operands[2],
+ operands[3]));
else
- emit_insn (gen_extzvsi (operands[0], operands[1], operands[2], operands[3]));
+ emit_insn (gen_extzvsi_internal (operands[0], operands[1], operands[2],
+ operands[3]));
DONE;
}")
-(define_insn "extzvsi"
+(define_insn "extzvsi_internal"
[(set (match_operand:SI 0 "gpc_reg_operand" "=r")
(zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r")
(match_operand:SI 2 "const_int_operand" "i")
@@ -3472,7 +3476,7 @@
(const_int 0)))]
"")
-(define_insn "extzvdi"
+(define_insn "extzvdi_internal"
[(set (match_operand:DI 0 "gpc_reg_operand" "=r")
(zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
(match_operand:SI 2 "const_int_operand" "i")
diff --git a/gcc/config/rs6000/sync.md b/gcc/config/rs6000/sync.md
index 42ac90373e5..ddf2ae74945 100644
--- a/gcc/config/rs6000/sync.md
+++ b/gcc/config/rs6000/sync.md
@@ -174,7 +174,7 @@
;; opcode that is "phased-in". Not implemented as of Power7, so not yet used,
;; but let's prepare the macros anyway.
-(define_mode_iterator ATOMIC [SI (DI "TARGET_64BIT")])
+(define_mode_iterator ATOMIC [SI (DI "TARGET_POWERPC64")])
(define_insn "load_locked<mode>"
[(set (match_operand:ATOMIC 0 "gpc_reg_operand" "=r")
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index 58db3cfb9bf..39374b2c2ba 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -209,8 +209,8 @@
;; VSX moves
(define_insn "*vsx_mov<mode>"
- [(set (match_operand:VSX_M 0 "nonimmediate_operand" "=Z,<VSr>,<VSr>,?Z,?wa,?wa,*o,*r,*r,<VSr>,?wa,v,wZ,v")
- (match_operand:VSX_M 1 "input_operand" "<VSr>,Z,<VSr>,wa,Z,wa,r,o,r,j,j,W,v,wZ"))]
+ [(set (match_operand:VSX_M 0 "nonimmediate_operand" "=Z,<VSr>,<VSr>,?Z,?wa,?wa,*Y,*r,*r,<VSr>,?wa,v,wZ,v")
+ (match_operand:VSX_M 1 "input_operand" "<VSr>,Z,<VSr>,wa,Z,wa,r,Y,r,j,j,W,v,wZ"))]
"VECTOR_MEM_VSX_P (<MODE>mode)
&& (register_operand (operands[0], <MODE>mode)
|| register_operand (operands[1], <MODE>mode))"
@@ -272,8 +272,8 @@
;; Unlike other VSX moves, allow the GPRs, since a normal use of TImode is for
;; unions. However for plain data movement, slightly favor the vector loads
(define_insn "*vsx_movti"
- [(set (match_operand:TI 0 "nonimmediate_operand" "=Z,wa,wa,?o,?r,?r,wa,v,v,wZ")
- (match_operand:TI 1 "input_operand" "wa,Z,wa,r,o,r,j,W,wZ,v"))]
+ [(set (match_operand:TI 0 "nonimmediate_operand" "=Z,wa,wa,?Y,?r,?r,wa,v,v,wZ")
+ (match_operand:TI 1 "input_operand" "wa,Z,wa,r,Y,r,j,W,wZ,v"))]
"VECTOR_MEM_VSX_P (TImode)
&& (register_operand (operands[0], TImode)
|| register_operand (operands[1], TImode))"
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