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-rw-r--r--gcc/config/sparc/sparc.h18
1 files changed, 2 insertions, 16 deletions
diff --git a/gcc/config/sparc/sparc.h b/gcc/config/sparc/sparc.h
index e8707f50577..32f8c1074ae 100644
--- a/gcc/config/sparc/sparc.h
+++ b/gcc/config/sparc/sparc.h
@@ -716,8 +716,7 @@ extern enum cmodel sparc_cmodel;
/* Due to the ARCH64 discrepancy above we must override this next
macro too. */
-#define REGMODE_NATURAL_SIZE(MODE) \
- ((TARGET_ARCH64 && FLOAT_MODE_P (MODE)) ? 4 : UNITS_PER_WORD)
+#define REGMODE_NATURAL_SIZE(MODE) sparc_regmode_natural_size (MODE)
/* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
See sparc.c for how we initialize this. */
@@ -735,20 +734,7 @@ extern int sparc_mode_class[];
register window instruction in the prologue. */
#define HARD_REGNO_RENAME_OK(FROM, TO) ((FROM) != 1)
-/* Value is 1 if it is a good idea to tie two pseudo registers
- when one has mode MODE1 and one has mode MODE2.
- If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
- for any hard reg, then this must be 0 for correct output.
-
- For V9: SFmode can't be combined with other float modes, because they can't
- be allocated to the %d registers. Also, DFmode won't fit in odd %f
- registers, but SFmode will. */
-#define MODES_TIEABLE_P(MODE1, MODE2) \
- ((MODE1) == (MODE2) \
- || (GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2) \
- && (! TARGET_V9 \
- || (GET_MODE_CLASS (MODE1) != MODE_FLOAT \
- || (MODE1 != SFmode && MODE2 != SFmode)))))
+#define MODES_TIEABLE_P(MODE1, MODE2) sparc_modes_tieable_p (MODE1, MODE2)
/* Specify the registers used for certain standard purposes.
The values of these macros are register numbers. */