diff options
Diffstat (limited to 'gcc/config')
44 files changed, 891 insertions, 467 deletions
diff --git a/gcc/config/arc/arc.c b/gcc/config/arc/arc.c index 6c7eae63dd1..2b12844cdb7 100644 --- a/gcc/config/arc/arc.c +++ b/gcc/config/arc/arc.c @@ -2134,7 +2134,7 @@ arc_save_restore (rtx base_reg, if (*first_offset) { /* "reg_size" won't be more than 127 . */ - gcc_assert (epilogue_p || abs (*first_offset <= 127)); + gcc_assert (epilogue_p || abs (*first_offset) <= 127); frame_add (base_reg, *first_offset); *first_offset = 0; } diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c index 5a5290220e9..bb7dc6f0b77 100644 --- a/gcc/config/arm/arm.c +++ b/gcc/config/arm/arm.c @@ -72,6 +72,7 @@ struct four_ints }; /* Forward function declarations. */ +static bool arm_const_not_ok_for_debug_p (rtx); static bool arm_lra_p (void); static bool arm_needs_doubleword_align (enum machine_mode, const_tree); static int arm_compute_static_chain_stack_bytes (void); @@ -674,6 +675,9 @@ static const struct attribute_spec arm_attribute_table[] = #undef TARGET_CAN_USE_DOLOOP_P #define TARGET_CAN_USE_DOLOOP_P can_use_doloop_if_innermost +#undef TARGET_CONST_NOT_OK_FOR_DEBUG_P +#define TARGET_CONST_NOT_OK_FOR_DEBUG_P arm_const_not_ok_for_debug_p + struct gcc_target targetm = TARGET_INITIALIZER; /* Obstack for minipool constant handling. */ @@ -10666,10 +10670,16 @@ arm_new_rtx_costs (rtx x, enum rtx_code code, enum rtx_code outer_code, return true; case ASM_OPERANDS: - /* Just a guess. Cost one insn per input. */ - *cost = COSTS_N_INSNS (ASM_OPERANDS_INPUT_LENGTH (x)); - return true; + { + /* Just a guess. Guess number of instructions in the asm + plus one insn per input. Always a minimum of COSTS_N_INSNS (1) + though (see PR60663). */ + int asm_length = MAX (1, asm_str_count (ASM_OPERANDS_TEMPLATE (x))); + int num_operands = ASM_OPERANDS_INPUT_LENGTH (x); + *cost = COSTS_N_INSNS (asm_length + num_operands); + return true; + } default: if (mode != VOIDmode) *cost = COSTS_N_INSNS (ARM_NUM_REGS (mode)); @@ -31116,4 +31126,46 @@ arm_asan_shadow_offset (void) return (unsigned HOST_WIDE_INT) 1 << 29; } + +/* This is a temporary fix for PR60655. Ideally we need + to handle most of these cases in the generic part but + currently we reject minus (..) (sym_ref). We try to + ameliorate the case with minus (sym_ref1) (sym_ref2) + where they are in the same section. */ + +static bool +arm_const_not_ok_for_debug_p (rtx p) +{ + tree decl_op0 = NULL; + tree decl_op1 = NULL; + + if (GET_CODE (p) == MINUS) + { + if (GET_CODE (XEXP (p, 1)) == SYMBOL_REF) + { + decl_op1 = SYMBOL_REF_DECL (XEXP (p, 1)); + if (decl_op1 + && GET_CODE (XEXP (p, 0)) == SYMBOL_REF + && (decl_op0 = SYMBOL_REF_DECL (XEXP (p, 0)))) + { + if ((TREE_CODE (decl_op1) == VAR_DECL + || TREE_CODE (decl_op1) == CONST_DECL) + && (TREE_CODE (decl_op0) == VAR_DECL + || TREE_CODE (decl_op0) == CONST_DECL)) + return (get_variable_section (decl_op1, false) + != get_variable_section (decl_op0, false)); + + if (TREE_CODE (decl_op1) == LABEL_DECL + && TREE_CODE (decl_op0) == LABEL_DECL) + return (DECL_CONTEXT (decl_op1) + != DECL_CONTEXT (decl_op0)); + } + + return true; + } + } + + return false; +} + #include "gt-arm.h" diff --git a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h index 7ca47a7ec70..597e69c6e03 100644 --- a/gcc/config/arm/arm.h +++ b/gcc/config/arm/arm.h @@ -937,13 +937,13 @@ extern int arm_arch_crc; #ifndef ARM_TARGET2_DWARF_FORMAT #define ARM_TARGET2_DWARF_FORMAT DW_EH_PE_pcrel +#endif /* ttype entries (the only interesting data references used) use TARGET2 relocations. */ #define ASM_PREFERRED_EH_DATA_FORMAT(code, data) \ (((code) == 0 && (data) == 1 && ARM_UNWIND_INFO) ? ARM_TARGET2_DWARF_FORMAT \ : DW_EH_PE_absptr) -#endif /* The native (Norcroft) Pascal compiler for the ARM passes the static chain as an invisible last argument (possible since varargs don't exist in @@ -2194,14 +2194,9 @@ extern int making_const_table; #undef ASM_OUTPUT_BEFORE_CASE_LABEL #define ASM_OUTPUT_BEFORE_CASE_LABEL(FILE, PREFIX, NUM, TABLE) /* Empty. */ -/* Make sure subsequent insns are aligned after a TBB. */ -#define ASM_OUTPUT_CASE_END(FILE, NUM, JUMPTABLE) \ - do \ - { \ - if (GET_MODE (PATTERN (JUMPTABLE)) == QImode) \ - ASM_OUTPUT_ALIGN (FILE, 1); \ - } \ - while (0) +#define LABEL_ALIGN_AFTER_BARRIER(LABEL) \ + (GET_CODE (PATTERN (prev_active_insn (LABEL))) == ADDR_DIFF_VEC \ + ? 1 : 0) #define ARM_DECLARE_FUNCTION_NAME(STREAM, NAME, DECL) \ do \ diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md index 4df24a236a2..4b81ee27211 100644 --- a/gcc/config/arm/arm.md +++ b/gcc/config/arm/arm.md @@ -2784,8 +2784,8 @@ (define_insn "insv_zero" [(set (zero_extract:SI (match_operand:SI 0 "s_register_operand" "+r") - (match_operand:SI 1 "const_int_operand" "M") - (match_operand:SI 2 "const_int_operand" "M")) + (match_operand:SI 1 "const_int_M_operand" "M") + (match_operand:SI 2 "const_int_M_operand" "M")) (const_int 0))] "arm_arch_thumb2" "bfc%?\t%0, %2, %1" @@ -2797,8 +2797,8 @@ (define_insn "insv_t2" [(set (zero_extract:SI (match_operand:SI 0 "s_register_operand" "+r") - (match_operand:SI 1 "const_int_operand" "M") - (match_operand:SI 2 "const_int_operand" "M")) + (match_operand:SI 1 "const_int_M_operand" "M") + (match_operand:SI 2 "const_int_M_operand" "M")) (match_operand:SI 3 "s_register_operand" "r"))] "arm_arch_thumb2" "bfi%?\t%0, %3, %2, %1" @@ -4480,8 +4480,8 @@ (define_insn "*extv_reg" [(set (match_operand:SI 0 "s_register_operand" "=r") (sign_extract:SI (match_operand:SI 1 "s_register_operand" "r") - (match_operand:SI 2 "const_int_operand" "M") - (match_operand:SI 3 "const_int_operand" "M")))] + (match_operand:SI 2 "const_int_M_operand" "M") + (match_operand:SI 3 "const_int_M_operand" "M")))] "arm_arch_thumb2" "sbfx%?\t%0, %1, %3, %2" [(set_attr "length" "4") @@ -4493,8 +4493,8 @@ (define_insn "extzv_t2" [(set (match_operand:SI 0 "s_register_operand" "=r") (zero_extract:SI (match_operand:SI 1 "s_register_operand" "r") - (match_operand:SI 2 "const_int_operand" "M") - (match_operand:SI 3 "const_int_operand" "M")))] + (match_operand:SI 2 "const_int_M_operand" "M") + (match_operand:SI 3 "const_int_M_operand" "M")))] "arm_arch_thumb2" "ubfx%?\t%0, %1, %3, %2" [(set_attr "length" "4") @@ -12073,7 +12073,7 @@ [(match_parallel 0 "load_multiple_operation" [(set (match_operand:SI 1 "s_register_operand" "+rk") (plus:SI (match_dup 1) - (match_operand:SI 2 "const_int_operand" "I"))) + (match_operand:SI 2 "const_int_I_operand" "I"))) (set (match_operand:SI 3 "s_register_operand" "=rk") (mem:SI (match_dup 1))) ])] @@ -12102,7 +12102,7 @@ [(return) (set (match_operand:SI 1 "s_register_operand" "+rk") (plus:SI (match_dup 1) - (match_operand:SI 2 "const_int_operand" "I"))) + (match_operand:SI 2 "const_int_I_operand" "I"))) (set (match_operand:SI 3 "s_register_operand" "=rk") (mem:SI (match_dup 1))) ])] @@ -12155,7 +12155,7 @@ [(match_parallel 0 "pop_multiple_fp" [(set (match_operand:SI 1 "s_register_operand" "+rk") (plus:SI (match_dup 1) - (match_operand:SI 2 "const_int_operand" "I"))) + (match_operand:SI 2 "const_int_I_operand" "I"))) (set (match_operand:DF 3 "vfp_hard_register_operand" "") (mem:DF (match_dup 1)))])] "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP" diff --git a/gcc/config/arm/cortex-a53.md b/gcc/config/arm/cortex-a53.md index b131c814d07..a629bd61dae 100644 --- a/gcc/config/arm/cortex-a53.md +++ b/gcc/config/arm/cortex-a53.md @@ -245,12 +245,12 @@ (define_insn_reservation "cortex_a53_fdivs" 14 (and (eq_attr "tune" "cortexa53") (eq_attr "type" "fdivs, fsqrts")) - "cortex_a53_slot0, cortex_a53_fp_div_sqrt * 13") + "cortex_a53_slot0, cortex_a53_fp_div_sqrt * 5") (define_insn_reservation "cortex_a53_fdivd" 29 (and (eq_attr "tune" "cortexa53") (eq_attr "type" "fdivd, fsqrtd")) - "cortex_a53_slot0, cortex_a53_fp_div_sqrt * 28") + "cortex_a53_slot0, cortex_a53_fp_div_sqrt * 8") ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;; ARMv8-A Cryptographic extensions. diff --git a/gcc/config/arm/predicates.md b/gcc/config/arm/predicates.md index ce5c9a830cd..6273e8820c6 100644 --- a/gcc/config/arm/predicates.md +++ b/gcc/config/arm/predicates.md @@ -153,6 +153,14 @@ (ior (match_operand 0 "arm_rhs_operand") (match_operand 0 "memory_operand"))) +(define_predicate "const_int_I_operand" + (and (match_operand 0 "const_int_operand") + (match_test "satisfies_constraint_I (op)"))) + +(define_predicate "const_int_M_operand" + (and (match_operand 0 "const_int_operand") + (match_test "satisfies_constraint_M (op)"))) + ;; This doesn't have to do much because the constant is already checked ;; in the shift_operator predicate. (define_predicate "shift_amount_operand" diff --git a/gcc/config/avr/avr-arch.h b/gcc/config/avr/avr-arch.h index 6357e997cad..b3c7cc0855e 100644 --- a/gcc/config/avr/avr-arch.h +++ b/gcc/config/avr/avr-arch.h @@ -100,32 +100,12 @@ typedef struct /* Index in avr_arch_types[]. */ enum avr_arch arch; + /* device specific feature */ + int dev_attribute; + /* Must lie outside user's namespace. NULL == no macro. */ const char *const macro; - /* Stack pointer have 8 bits width. */ - int short_sp; - - /* Some AVR devices have a core erratum when skipping a 2-word instruction. - Skip instructions are: SBRC, SBRS, SBIC, SBIS, CPSE. - Problems will occur with return address is IRQ executes during the - skip sequence. - - A support ticket from Atmel returned the following information: - - Subject: (ATTicket:644469) On AVR skip-bug core Erratum - From: avr@atmel.com Date: 2011-07-27 - (Please keep the subject when replying to this mail) - - This errata exists only in AT90S8515 and ATmega103 devices. - - For information please refer the following respective errata links - http://www.atmel.com/dyn/resources/prod_documents/doc2494.pdf - http://www.atmel.com/dyn/resources/prod_documents/doc1436.pdf */ - - /* Core Erratum: Must not skip 2-word instruction. */ - int errata_skip; - /* Start of data section. */ int data_section_start; @@ -136,6 +116,42 @@ typedef struct const char *const library_name; } avr_mcu_t; +/* AVR device specific features. + +AVR_ISA_RMW + Only few avr devices have Read-Modify-Write (RMW) instructions + (XCH, LAC, LAS and LAT) + +AVR_SHORT_SP + Stack Pointer has only 8 bit width. + The device / multilib has an 8-bit stack pointer (no SPH). + +AVR_ERRATA_SKIP + Some AVR devices have a core erratum when skipping a 2-word instruction. + Skip instructions are: SBRC, SBRS, SBIC, SBIS, CPSE. + Problems will occur with return address is IRQ executes during the + skip sequence. + + A support ticket from Atmel returned the following information: + + Subject: (ATTicket:644469) On AVR skip-bug core Erratum + From: avr@atmel.com Date: 2011-07-27 + (Please keep the subject when replying to this mail) + + This errata exists only in AT90S8515 and ATmega103 devices. + + For information please refer the following respective errata links + http://www.atmel.com/dyn/resources/prod_documents/doc2494.pdf + http://www.atmel.com/dyn/resources/prod_documents/doc1436.pdf */ + +enum avr_device_specific_features +{ + AVR_ISA_NONE, + AVR_ISA_RMW = 0x1, /* device has RMW instructions. */ + AVR_SHORT_SP = 0x2, /* Stack Pointer has 8 bits width. */ + AVR_ERRATA_SKIP = 0x4 /* device has a core erratum. */ +}; + /* Map architecture to its texinfo string. */ typedef struct diff --git a/gcc/config/avr/avr-c.c b/gcc/config/avr/avr-c.c index 101d28092e7..c6a2f1f9471 100644 --- a/gcc/config/avr/avr-c.c +++ b/gcc/config/avr/avr-c.c @@ -347,7 +347,7 @@ avr_cpu_cpp_builtins (struct cpp_reader *pfile) if (TARGET_NO_INTERRUPTS) cpp_define (pfile, "__NO_INTERRUPTS__"); - if (avr_current_device->errata_skip) + if (avr_current_device->dev_attribute & AVR_ERRATA_SKIP) { cpp_define (pfile, "__AVR_ERRATA_SKIP__"); @@ -355,6 +355,9 @@ avr_cpu_cpp_builtins (struct cpp_reader *pfile) cpp_define (pfile, "__AVR_ERRATA_SKIP_JMP_CALL__"); } + if (avr_current_device->dev_attribute & AVR_ISA_RMW) + cpp_define (pfile, "__AVR_ISA_RMW__"); + cpp_define_formatted (pfile, "__AVR_SFR_OFFSET__=0x%x", avr_current_arch->sfr_offset); diff --git a/gcc/config/avr/avr-devices.c b/gcc/config/avr/avr-devices.c index 177f1961f14..2485cad65c4 100644 --- a/gcc/config/avr/avr-devices.c +++ b/gcc/config/avr/avr-devices.c @@ -104,11 +104,11 @@ avr_texinfo[] = const avr_mcu_t avr_mcu_types[] = { -#define AVR_MCU(NAME, ARCH, MACRO, SP8, ERR_SKIP, DATA_SEC, N_FLASH, LIBNAME)\ - { NAME, ARCH, MACRO, SP8, ERR_SKIP, DATA_SEC, N_FLASH, LIBNAME }, +#define AVR_MCU(NAME, ARCH, DEV_ATTRIBUTE, MACRO, DATA_SEC, N_FLASH, LIBNAME)\ + { NAME, ARCH, DEV_ATTRIBUTE, MACRO, DATA_SEC, N_FLASH, LIBNAME }, #include "avr-mcus.def" #undef AVR_MCU /* End of list. */ - { NULL, ARCH_UNKNOWN, NULL, 0, 0, 0, 0, NULL } + { NULL, ARCH_UNKNOWN, AVR_ISA_NONE, NULL, 0, 0, NULL } }; diff --git a/gcc/config/avr/avr-mcus.def b/gcc/config/avr/avr-mcus.def index d068f5e8017..483a3032173 100644 --- a/gcc/config/avr/avr-mcus.def +++ b/gcc/config/avr/avr-mcus.def @@ -33,291 +33,288 @@ Before including this file, define a macro: - AVR_MCU (NAME, ARCH, MACRO, SHORT_SP, ERRATA_SKIP, DATA_SEC, N_FLASH, - LIBRARY_NAME) + AVR_MCU (NAME, ARCH, DEV_ATTRIBUTE, MACRO, DATA_SEC, N_FLASH, LIBRARY_NAME) where the arguments are the fields of avr_mcu_t: - NAME Accept -mmcu=<NAME> + NAME Accept -mmcu=<NAME> - ARCH Specifies the multilib variant together with SHORT_SP + ARCH Specifies the multilib variant together with SHORT_SP - MACRO If NULL, this is a core and not a device. If non-NULL, - supply respective built-in macro. + DEV_ATTRIBUTE Specifies the device specific features + - additional ISA, short SP, errata skip etc., - SHORT_SP The device / multilib has an 8-bit stack pointer (no SPH). + MACRO If NULL, this is a core and not a device. If non-NULL, + supply respective built-in macro. - ERRATA_SKIP Apply work-around for the "skip 32-bit instruction" - silicon bug: Don't skip 32-bit instrctions. + DATA_SEC First address of SRAM, used in -Tdata= by the driver. - DATA_SEC First address of SRAM, used in -Tdata= by the driver. + N_FLASH Number of 64 KiB flash segments, rounded up. - N_FLASH Number of 64 KiB flash segments, rounded up. - - LIBRARY_NAME Used by the driver to linke startup code from avr-libc - as of crt<LIBRARY_NAME>.o + LIBRARY_NAME Used by the driver to linke startup code from avr-libc + as of crt<LIBRARY_NAME>.o "avr2" must be first for the "0" default to work as intended. */ /* Classic, <= 8K. */ -AVR_MCU ("avr2", ARCH_AVR2, NULL, 0, 1, 0x0060, 6, "s8515") -AVR_MCU ("at90s2313", ARCH_AVR2, "__AVR_AT90S2313__", 1, 0, 0x0060, 1, "s2313") -AVR_MCU ("at90s2323", ARCH_AVR2, "__AVR_AT90S2323__", 1, 0, 0x0060, 1, "s2323") -AVR_MCU ("at90s2333", ARCH_AVR2, "__AVR_AT90S2333__", 1, 0, 0x0060, 1, "s2333") -AVR_MCU ("at90s2343", ARCH_AVR2, "__AVR_AT90S2343__", 1, 0, 0x0060, 1, "s2343") -AVR_MCU ("attiny22", ARCH_AVR2, "__AVR_ATtiny22__", 1, 0, 0x0060, 1, "tn22") -AVR_MCU ("attiny26", ARCH_AVR2, "__AVR_ATtiny26__", 1, 0, 0x0060, 1, "tn26") -AVR_MCU ("at90s4414", ARCH_AVR2, "__AVR_AT90S4414__", 0, 0, 0x0060, 1, "s4414") -AVR_MCU ("at90s4433", ARCH_AVR2, "__AVR_AT90S4433__", 1, 0, 0x0060, 1, "s4433") -AVR_MCU ("at90s4434", ARCH_AVR2, "__AVR_AT90S4434__", 0, 0, 0x0060, 1, "s4434") -AVR_MCU ("at90s8515", ARCH_AVR2, "__AVR_AT90S8515__", 0, 1, 0x0060, 1, "s8515") -AVR_MCU ("at90c8534", ARCH_AVR2, "__AVR_AT90C8534__", 0, 0, 0x0060, 1, "c8534") -AVR_MCU ("at90s8535", ARCH_AVR2, "__AVR_AT90S8535__", 0, 0, 0x0060, 1, "s8535") +AVR_MCU ("avr2", ARCH_AVR2, AVR_ERRATA_SKIP, NULL, 0x0060, 6, "s8515") +AVR_MCU ("at90s2313", ARCH_AVR2, AVR_SHORT_SP, "__AVR_AT90S2313__", 0x0060, 1, "s2313") +AVR_MCU ("at90s2323", ARCH_AVR2, AVR_SHORT_SP, "__AVR_AT90S2323__", 0x0060, 1, "s2323") +AVR_MCU ("at90s2333", ARCH_AVR2, AVR_SHORT_SP, "__AVR_AT90S2333__", 0x0060, 1, "s2333") +AVR_MCU ("at90s2343", ARCH_AVR2, AVR_SHORT_SP, "__AVR_AT90S2343__", 0x0060, 1, "s2343") +AVR_MCU ("attiny22", ARCH_AVR2, AVR_SHORT_SP, "__AVR_ATtiny22__", 0x0060, 1, "tn22") +AVR_MCU ("attiny26", ARCH_AVR2, AVR_SHORT_SP, "__AVR_ATtiny26__", 0x0060, 1, "tn26") +AVR_MCU ("at90s4414", ARCH_AVR2, AVR_ISA_NONE, "__AVR_AT90S4414__", 0x0060, 1, "s4414") +AVR_MCU ("at90s4433", ARCH_AVR2, AVR_SHORT_SP, "__AVR_AT90S4433__", 0x0060, 1, "s4433") +AVR_MCU ("at90s4434", ARCH_AVR2, AVR_ISA_NONE, "__AVR_AT90S4434__", 0x0060, 1, "s4434") +AVR_MCU ("at90s8515", ARCH_AVR2, AVR_ERRATA_SKIP, "__AVR_AT90S8515__", 0x0060, 1, "s8515") +AVR_MCU ("at90c8534", ARCH_AVR2, AVR_ISA_NONE, "__AVR_AT90C8534__", 0x0060, 1, "c8534") +AVR_MCU ("at90s8535", ARCH_AVR2, AVR_ISA_NONE, "__AVR_AT90S8535__", 0x0060, 1, "s8535") /* Classic + MOVW, <= 8K. */ -AVR_MCU ("avr25", ARCH_AVR25, NULL, 0, 0, 0x0060, 1, "tn85") -AVR_MCU ("ata6289", ARCH_AVR25, "__AVR_ATA6289__", 0, 0, 0x0100, 1, "a6289") -AVR_MCU ("ata5272", ARCH_AVR25, "__AVR_ATA5272__", 0, 0, 0x0100, 1, "a5272") -AVR_MCU ("attiny13", ARCH_AVR25, "__AVR_ATtiny13__", 1, 0, 0x0060, 1, "tn13") -AVR_MCU ("attiny13a", ARCH_AVR25, "__AVR_ATtiny13A__", 1, 0, 0x0060, 1, "tn13a") -AVR_MCU ("attiny2313", ARCH_AVR25, "__AVR_ATtiny2313__", 1, 0, 0x0060, 1, "tn2313") -AVR_MCU ("attiny2313a", ARCH_AVR25, "__AVR_ATtiny2313A__", 1, 0, 0x0060, 1, "tn2313a") -AVR_MCU ("attiny24", ARCH_AVR25, "__AVR_ATtiny24__", 1, 0, 0x0060, 1, "tn24") -AVR_MCU ("attiny24a", ARCH_AVR25, "__AVR_ATtiny24A__", 1, 0, 0x0060, 1, "tn24a") -AVR_MCU ("attiny4313", ARCH_AVR25, "__AVR_ATtiny4313__", 0, 0, 0x0060, 1, "tn4313") -AVR_MCU ("attiny44", ARCH_AVR25, "__AVR_ATtiny44__", 0, 0, 0x0060, 1, "tn44") -AVR_MCU ("attiny44a", ARCH_AVR25, "__AVR_ATtiny44A__", 0, 0, 0x0060, 1, "tn44a") -AVR_MCU ("attiny84", ARCH_AVR25, "__AVR_ATtiny84__", 0, 0, 0x0060, 1, "tn84") -AVR_MCU ("attiny84a", ARCH_AVR25, "__AVR_ATtiny84A__", 0, 0, 0x0060, 1, "tn84") -AVR_MCU ("attiny25", ARCH_AVR25, "__AVR_ATtiny25__", 1, 0, 0x0060, 1, "tn25") -AVR_MCU ("attiny45", ARCH_AVR25, "__AVR_ATtiny45__", 0, 0, 0x0060, 1, "tn45") -AVR_MCU ("attiny85", ARCH_AVR25, "__AVR_ATtiny85__", 0, 0, 0x0060, 1, "tn85") -AVR_MCU ("attiny261", ARCH_AVR25, "__AVR_ATtiny261__", 1, 0, 0x0060, 1, "tn261") -AVR_MCU ("attiny261a", ARCH_AVR25, "__AVR_ATtiny261A__", 1, 0, 0x0060, 1, "tn261a") -AVR_MCU ("attiny461", ARCH_AVR25, "__AVR_ATtiny461__", 0, 0, 0x0060, 1, "tn461") -AVR_MCU ("attiny461a", ARCH_AVR25, "__AVR_ATtiny461A__", 0, 0, 0x0060, 1, "tn461a") -AVR_MCU ("attiny861", ARCH_AVR25, "__AVR_ATtiny861__", 0, 0, 0x0060, 1, "tn861") -AVR_MCU ("attiny861a", ARCH_AVR25, "__AVR_ATtiny861A__", 0, 0, 0x0060, 1, "tn861a") -AVR_MCU ("attiny43u", ARCH_AVR25, "__AVR_ATtiny43U__", 0, 0, 0x0060, 1, "tn43u") -AVR_MCU ("attiny87", ARCH_AVR25, "__AVR_ATtiny87__", 0, 0, 0x0100, 1, "tn87") -AVR_MCU ("attiny48", ARCH_AVR25, "__AVR_ATtiny48__", 0, 0, 0x0100, 1, "tn48") -AVR_MCU ("attiny88", ARCH_AVR25, "__AVR_ATtiny88__", 0, 0, 0x0100, 1, "tn88") -AVR_MCU ("at86rf401", ARCH_AVR25, "__AVR_AT86RF401__", 0, 0, 0x0060, 1, "86401") +AVR_MCU ("avr25", ARCH_AVR25, AVR_ISA_NONE, NULL, 0x0060, 1, "tn85") +AVR_MCU ("ata6289", ARCH_AVR25, AVR_ISA_NONE, "__AVR_ATA6289__", 0x0100, 1, "a6289") +AVR_MCU ("ata5272", ARCH_AVR25, AVR_ISA_NONE, "__AVR_ATA5272__", 0x0100, 1, "a5272") +AVR_MCU ("attiny13", ARCH_AVR25, AVR_SHORT_SP, "__AVR_ATtiny13__", 0x0060, 1, "tn13") +AVR_MCU ("attiny13a", ARCH_AVR25, AVR_SHORT_SP, "__AVR_ATtiny13A__", 0x0060, 1, "tn13a") +AVR_MCU ("attiny2313", ARCH_AVR25, AVR_SHORT_SP, "__AVR_ATtiny2313__", 0x0060, 1, "tn2313") +AVR_MCU ("attiny2313a", ARCH_AVR25, AVR_SHORT_SP, "__AVR_ATtiny2313A__", 0x0060, 1, "tn2313a") +AVR_MCU ("attiny24", ARCH_AVR25, AVR_SHORT_SP, "__AVR_ATtiny24__", 0x0060, 1, "tn24") +AVR_MCU ("attiny24a", ARCH_AVR25, AVR_SHORT_SP, "__AVR_ATtiny24A__", 0x0060, 1, "tn24a") +AVR_MCU ("attiny4313", ARCH_AVR25, AVR_ISA_NONE, "__AVR_ATtiny4313__", 0x0060, 1, "tn4313") +AVR_MCU ("attiny44", ARCH_AVR25, AVR_ISA_NONE, "__AVR_ATtiny44__", 0x0060, 1, "tn44") +AVR_MCU ("attiny44a", ARCH_AVR25, AVR_ISA_NONE, "__AVR_ATtiny44A__", 0x0060, 1, "tn44a") +AVR_MCU ("attiny84", ARCH_AVR25, AVR_ISA_NONE, "__AVR_ATtiny84__", 0x0060, 1, "tn84") +AVR_MCU ("attiny84a", ARCH_AVR25, AVR_ISA_NONE, "__AVR_ATtiny84A__", 0x0060, 1, "tn84") +AVR_MCU ("attiny25", ARCH_AVR25, AVR_SHORT_SP, "__AVR_ATtiny25__", 0x0060, 1, "tn25") +AVR_MCU ("attiny45", ARCH_AVR25, AVR_ISA_NONE, "__AVR_ATtiny45__", 0x0060, 1, "tn45") +AVR_MCU ("attiny85", ARCH_AVR25, AVR_ISA_NONE, "__AVR_ATtiny85__", 0x0060, 1, "tn85") +AVR_MCU ("attiny261", ARCH_AVR25, AVR_SHORT_SP, "__AVR_ATtiny261__", 0x0060, 1, "tn261") +AVR_MCU ("attiny261a", ARCH_AVR25, AVR_SHORT_SP, "__AVR_ATtiny261A__", 0x0060, 1, "tn261a") +AVR_MCU ("attiny461", ARCH_AVR25, AVR_ISA_NONE, "__AVR_ATtiny461__", 0x0060, 1, "tn461") +AVR_MCU ("attiny461a", ARCH_AVR25, AVR_ISA_NONE, "__AVR_ATtiny461A__", 0x0060, 1, "tn461a") +AVR_MCU ("attiny861", ARCH_AVR25, AVR_ISA_NONE, "__AVR_ATtiny861__", 0x0060, 1, "tn861") +AVR_MCU ("attiny861a", ARCH_AVR25, AVR_ISA_NONE, "__AVR_ATtiny861A__", 0x0060, 1, "tn861a") +AVR_MCU ("attiny43u", ARCH_AVR25, AVR_ISA_NONE, "__AVR_ATtiny43U__", 0x0060, 1, "tn43u") +AVR_MCU ("attiny87", ARCH_AVR25, AVR_ISA_NONE, "__AVR_ATtiny87__", 0x0100, 1, "tn87") +AVR_MCU ("attiny48", ARCH_AVR25, AVR_ISA_NONE, "__AVR_ATtiny48__", 0x0100, 1, "tn48") +AVR_MCU ("attiny88", ARCH_AVR25, AVR_ISA_NONE, "__AVR_ATtiny88__", 0x0100, 1, "tn88") +AVR_MCU ("at86rf401", ARCH_AVR25, AVR_ISA_NONE, "__AVR_AT86RF401__", 0x0060, 1, "86401") /* Classic, > 8K, <= 64K. */ -AVR_MCU ("avr3", ARCH_AVR3, NULL, 0, 0, 0x0060, 1, "43355") -AVR_MCU ("at43usb355", ARCH_AVR3, "__AVR_AT43USB355__", 0, 0, 0x0060, 1, "43355") -AVR_MCU ("at76c711", ARCH_AVR3, "__AVR_AT76C711__", 0, 0, 0x0060, 1, "76711") +AVR_MCU ("avr3", ARCH_AVR3, AVR_ISA_NONE, NULL, 0x0060, 1, "43355") +AVR_MCU ("at43usb355", ARCH_AVR3, AVR_ISA_NONE, "__AVR_AT43USB355__", 0x0060, 1, "43355") +AVR_MCU ("at76c711", ARCH_AVR3, AVR_ISA_NONE, "__AVR_AT76C711__", 0x0060, 1, "76711") /* Classic, == 128K. */ -AVR_MCU ("avr31", ARCH_AVR31, NULL, 0, 1, 0x0060, 2, "m103") -AVR_MCU ("atmega103", ARCH_AVR31, "__AVR_ATmega103__", 0, 1, 0x0060, 2, "m103") -AVR_MCU ("at43usb320", ARCH_AVR31, "__AVR_AT43USB320__", 0, 0, 0x0060, 2, "43320") +AVR_MCU ("avr31", ARCH_AVR31, AVR_ERRATA_SKIP, NULL, 0x0060, 2, "m103") +AVR_MCU ("atmega103", ARCH_AVR31, AVR_ERRATA_SKIP, "__AVR_ATmega103__", 0x0060, 2, "m103") +AVR_MCU ("at43usb320", ARCH_AVR31, AVR_ISA_NONE, "__AVR_AT43USB320__", 0x0060, 2, "43320") /* Classic + MOVW + JMP/CALL. */ -AVR_MCU ("avr35", ARCH_AVR35, NULL, 0, 0, 0x0100, 1, "usb162") -AVR_MCU ("ata5505", ARCH_AVR35, "__AVR_ATA5505__", 0, 0, 0x0100, 1, "a5505") -AVR_MCU ("at90usb82", ARCH_AVR35, "__AVR_AT90USB82__", 0, 0, 0x0100, 1, "usb82") -AVR_MCU ("at90usb162", ARCH_AVR35, "__AVR_AT90USB162__", 0, 0, 0x0100, 1, "usb162") -AVR_MCU ("atmega8u2", ARCH_AVR35, "__AVR_ATmega8U2__", 0, 0, 0x0100, 1, "m8u2") -AVR_MCU ("atmega16u2", ARCH_AVR35, "__AVR_ATmega16U2__", 0, 0, 0x0100, 1, "m16u2") -AVR_MCU ("atmega32u2", ARCH_AVR35, "__AVR_ATmega32U2__", 0, 0, 0x0100, 1, "m32u2") -AVR_MCU ("attiny167", ARCH_AVR35, "__AVR_ATtiny167__", 0, 0, 0x0100, 1, "tn167") -AVR_MCU ("attiny1634", ARCH_AVR35, "__AVR_ATtiny1634__", 0, 0, 0x0100, 1, "tn1634") +AVR_MCU ("avr35", ARCH_AVR35, AVR_ISA_NONE, NULL, 0x0100, 1, "usb162") +AVR_MCU ("ata5505", ARCH_AVR35, AVR_ISA_NONE, "__AVR_ATA5505__", 0x0100, 1, "a5505") +AVR_MCU ("at90usb82", ARCH_AVR35, AVR_ISA_NONE, "__AVR_AT90USB82__", 0x0100, 1, "usb82") +AVR_MCU ("at90usb162", ARCH_AVR35, AVR_ISA_NONE, "__AVR_AT90USB162__", 0x0100, 1, "usb162") +AVR_MCU ("atmega8u2", ARCH_AVR35, AVR_ISA_NONE, "__AVR_ATmega8U2__", 0x0100, 1, "m8u2") +AVR_MCU ("atmega16u2", ARCH_AVR35, AVR_ISA_NONE, "__AVR_ATmega16U2__", 0x0100, 1, "m16u2") +AVR_MCU ("atmega32u2", ARCH_AVR35, AVR_ISA_NONE, "__AVR_ATmega32U2__", 0x0100, 1, "m32u2") +AVR_MCU ("attiny167", ARCH_AVR35, AVR_ISA_NONE, "__AVR_ATtiny167__", 0x0100, 1, "tn167") +AVR_MCU ("attiny1634", ARCH_AVR35, AVR_ISA_NONE, "__AVR_ATtiny1634__", 0x0100, 1, "tn1634") /* Enhanced, <= 8K. */ -AVR_MCU ("avr4", ARCH_AVR4, NULL, 0, 0, 0x0060, 1, "m8") -AVR_MCU ("ata6285", ARCH_AVR4, "__AVR_ATA6285__", 0, 0, 0x0100, 1, "a6285") -AVR_MCU ("ata6286", ARCH_AVR4, "__AVR_ATA6286__", 0, 0, 0x0100, 1, "a6286") -AVR_MCU ("atmega8", ARCH_AVR4, "__AVR_ATmega8__", 0, 0, 0x0060, 1, "m8") -AVR_MCU ("atmega8a", ARCH_AVR4, "__AVR_ATmega8A__", 0, 0, 0x0060, 1, "m8a") -AVR_MCU ("atmega48", ARCH_AVR4, "__AVR_ATmega48__", 0, 0, 0x0100, 1, "m48") -AVR_MCU ("atmega48a", ARCH_AVR4, "__AVR_ATmega48A__", 0, 0, 0x0100, 1, "m48a") -AVR_MCU ("atmega48p", ARCH_AVR4, "__AVR_ATmega48P__", 0, 0, 0x0100, 1, "m48p") -AVR_MCU ("atmega48pa", ARCH_AVR4, "__AVR_ATmega48PA__", 0, 0, 0x0100, 1, "m48pa") -AVR_MCU ("atmega88", ARCH_AVR4, "__AVR_ATmega88__", 0, 0, 0x0100, 1, "m88") -AVR_MCU ("atmega88a", ARCH_AVR4, "__AVR_ATmega88A__", 0, 0, 0x0100, 1, "m88a") -AVR_MCU ("atmega88p", ARCH_AVR4, "__AVR_ATmega88P__", 0, 0, 0x0100, 1, "m88p") -AVR_MCU ("atmega88pa", ARCH_AVR4, "__AVR_ATmega88PA__", 0, 0, 0x0100, 1, "m88pa") -AVR_MCU ("atmega8515", ARCH_AVR4, "__AVR_ATmega8515__", 0, 0, 0x0060, 1, "m8515") -AVR_MCU ("atmega8535", ARCH_AVR4, "__AVR_ATmega8535__", 0, 0, 0x0060, 1, "m8535") -AVR_MCU ("atmega8hva", ARCH_AVR4, "__AVR_ATmega8HVA__", 0, 0, 0x0100, 1, "m8hva") -AVR_MCU ("at90pwm1", ARCH_AVR4, "__AVR_AT90PWM1__", 0, 0, 0x0100, 1, "90pwm1") -AVR_MCU ("at90pwm2", ARCH_AVR4, "__AVR_AT90PWM2__", 0, 0, 0x0100, 1, "90pwm2") -AVR_MCU ("at90pwm2b", ARCH_AVR4, "__AVR_AT90PWM2B__", 0, 0, 0x0100, 1, "90pwm2b") -AVR_MCU ("at90pwm3", ARCH_AVR4, "__AVR_AT90PWM3__", 0, 0, 0x0100, 1, "90pwm3") -AVR_MCU ("at90pwm3b", ARCH_AVR4, "__AVR_AT90PWM3B__", 0, 0, 0x0100, 1, "90pwm3b") -AVR_MCU ("at90pwm81", ARCH_AVR4, "__AVR_AT90PWM81__", 0, 0, 0x0100, 1, "90pwm81") +AVR_MCU ("avr4", ARCH_AVR4, AVR_ISA_NONE, NULL, 0x0060, 1, "m8") +AVR_MCU ("ata6285", ARCH_AVR4, AVR_ISA_NONE, "__AVR_ATA6285__", 0x0100, 1, "a6285") +AVR_MCU ("ata6286", ARCH_AVR4, AVR_ISA_NONE, "__AVR_ATA6286__", 0x0100, 1, "a6286") +AVR_MCU ("atmega8", ARCH_AVR4, AVR_ISA_NONE, "__AVR_ATmega8__", 0x0060, 1, "m8") +AVR_MCU ("atmega8a", ARCH_AVR4, AVR_ISA_NONE, "__AVR_ATmega8A__", 0x0060, 1, "m8a") +AVR_MCU ("atmega48", ARCH_AVR4, AVR_ISA_NONE, "__AVR_ATmega48__", 0x0100, 1, "m48") +AVR_MCU ("atmega48a", ARCH_AVR4, AVR_ISA_NONE, "__AVR_ATmega48A__", 0x0100, 1, "m48a") +AVR_MCU ("atmega48p", ARCH_AVR4, AVR_ISA_NONE, "__AVR_ATmega48P__", 0x0100, 1, "m48p") +AVR_MCU ("atmega48pa", ARCH_AVR4, AVR_ISA_NONE, "__AVR_ATmega48PA__", 0x0100, 1, "m48pa") +AVR_MCU ("atmega88", ARCH_AVR4, AVR_ISA_NONE, "__AVR_ATmega88__", 0x0100, 1, "m88") +AVR_MCU ("atmega88a", ARCH_AVR4, AVR_ISA_NONE, "__AVR_ATmega88A__", 0x0100, 1, "m88a") +AVR_MCU ("atmega88p", ARCH_AVR4, AVR_ISA_NONE, "__AVR_ATmega88P__", 0x0100, 1, "m88p") +AVR_MCU ("atmega88pa", ARCH_AVR4, AVR_ISA_NONE, "__AVR_ATmega88PA__", 0x0100, 1, "m88pa") +AVR_MCU ("atmega8515", ARCH_AVR4, AVR_ISA_NONE, "__AVR_ATmega8515__", 0x0060, 1, "m8515") +AVR_MCU ("atmega8535", ARCH_AVR4, AVR_ISA_NONE, "__AVR_ATmega8535__", 0x0060, 1, "m8535") +AVR_MCU ("atmega8hva", ARCH_AVR4, AVR_ISA_NONE, "__AVR_ATmega8HVA__", 0x0100, 1, "m8hva") +AVR_MCU ("at90pwm1", ARCH_AVR4, AVR_ISA_NONE, "__AVR_AT90PWM1__", 0x0100, 1, "90pwm1") +AVR_MCU ("at90pwm2", ARCH_AVR4, AVR_ISA_NONE, "__AVR_AT90PWM2__", 0x0100, 1, "90pwm2") +AVR_MCU ("at90pwm2b", ARCH_AVR4, AVR_ISA_NONE, "__AVR_AT90PWM2B__", 0x0100, 1, "90pwm2b") +AVR_MCU ("at90pwm3", ARCH_AVR4, AVR_ISA_NONE, "__AVR_AT90PWM3__", 0x0100, 1, "90pwm3") +AVR_MCU ("at90pwm3b", ARCH_AVR4, AVR_ISA_NONE, "__AVR_AT90PWM3B__", 0x0100, 1, "90pwm3b") +AVR_MCU ("at90pwm81", ARCH_AVR4, AVR_ISA_NONE, "__AVR_AT90PWM81__", 0x0100, 1, "90pwm81") /* Enhanced, > 8K, <= 64K. */ -AVR_MCU ("avr5", ARCH_AVR5, NULL, 0, 0, 0x0060, 1, "m16") -AVR_MCU ("ata5790", ARCH_AVR5, "__AVR_ATA5790__", 0, 0, 0x0100, 1, "a5790") -AVR_MCU ("ata5790n", ARCH_AVR5, "__AVR_ATA5790N__", 0, 0, 0x0100, 1, "a5790n") -AVR_MCU ("ata5795", ARCH_AVR5, "__AVR_ATA5795__", 0, 0, 0x0100, 1, "a5795") -AVR_MCU ("atmega16", ARCH_AVR5, "__AVR_ATmega16__", 0, 0, 0x0060, 1, "m16") -AVR_MCU ("atmega16a", ARCH_AVR5, "__AVR_ATmega16A__", 0, 0, 0x0060, 1, "m16a") -AVR_MCU ("atmega161", ARCH_AVR5, "__AVR_ATmega161__", 0, 0, 0x0060, 1, "m161") -AVR_MCU ("atmega162", ARCH_AVR5, "__AVR_ATmega162__", 0, 0, 0x0100, 1, "m162") -AVR_MCU ("atmega163", ARCH_AVR5, "__AVR_ATmega163__", 0, 0, 0x0060, 1, "m163") -AVR_MCU ("atmega164a", ARCH_AVR5, "__AVR_ATmega164A__", 0, 0, 0x0100, 1, "m164a") -AVR_MCU ("atmega164p", ARCH_AVR5, "__AVR_ATmega164P__", 0, 0, 0x0100, 1, "m164p") -AVR_MCU ("atmega164pa", ARCH_AVR5, "__AVR_ATmega164PA__", 0, 0, 0x0100, 1, "m164pa") -AVR_MCU ("atmega165", ARCH_AVR5, "__AVR_ATmega165__", 0, 0, 0x0100, 1, "m165") -AVR_MCU ("atmega165a", ARCH_AVR5, "__AVR_ATmega165A__", 0, 0, 0x0100, 1, "m165a") -AVR_MCU ("atmega165p", ARCH_AVR5, "__AVR_ATmega165P__", 0, 0, 0x0100, 1, "m165p") -AVR_MCU ("atmega165pa", ARCH_AVR5, "__AVR_ATmega165PA__", 0, 0, 0x0100, 1, "m165pa") -AVR_MCU ("atmega168", ARCH_AVR5, "__AVR_ATmega168__", 0, 0, 0x0100, 1, "m168") -AVR_MCU ("atmega168a", ARCH_AVR5, "__AVR_ATmega168A__", 0, 0, 0x0100, 1, "m168a") -AVR_MCU ("atmega168p", ARCH_AVR5, "__AVR_ATmega168P__", 0, 0, 0x0100, 1, "m168p") -AVR_MCU ("atmega168pa", ARCH_AVR5, "__AVR_ATmega168PA__", 0, 0, 0x0100, 1, "m168pa") -AVR_MCU ("atmega169", ARCH_AVR5, "__AVR_ATmega169__", 0, 0, 0x0100, 1, "m169") -AVR_MCU ("atmega169a", ARCH_AVR5, "__AVR_ATmega169A__", 0, 0, 0x0100, 1, "m169a") -AVR_MCU ("atmega169p", ARCH_AVR5, "__AVR_ATmega169P__", 0, 0, 0x0100, 1, "m169p") -AVR_MCU ("atmega169pa", ARCH_AVR5, "__AVR_ATmega169PA__", 0, 0, 0x0100, 1, "m169pa") -AVR_MCU ("atmega16hvb", ARCH_AVR5, "__AVR_ATmega16HVB__", 0, 0, 0x0100, 1, "m16hvb") -AVR_MCU ("atmega16hvbrevb", ARCH_AVR5, "__AVR_ATmega16HVBREVB__", 0, 0, 0x0100, 1, "m16hvbrevb") -AVR_MCU ("atmega16m1", ARCH_AVR5, "__AVR_ATmega16M1__", 0, 0, 0x0100, 1, "m16m1") -AVR_MCU ("atmega16u4", ARCH_AVR5, "__AVR_ATmega16U4__", 0, 0, 0x0100, 1, "m16u4") -AVR_MCU ("atmega26hvg", ARCH_AVR5, "__AVR_ATmega26HVG__", 0, 0, 0x0100, 1, "m26hvg") -AVR_MCU ("atmega32a", ARCH_AVR5, "__AVR_ATmega32A__", 0, 0, 0x0060, 1, "m32a") -AVR_MCU ("atmega32", ARCH_AVR5, "__AVR_ATmega32__", 0, 0, 0x0060, 1, "m32") -AVR_MCU ("atmega323", ARCH_AVR5, "__AVR_ATmega323__", 0, 0, 0x0060, 1, "m323") -AVR_MCU ("atmega324a", ARCH_AVR5, "__AVR_ATmega324A__", 0, 0, 0x0100, 1, "m324a") -AVR_MCU ("atmega324p", ARCH_AVR5, "__AVR_ATmega324P__", 0, 0, 0x0100, 1, "m324p") -AVR_MCU ("atmega324pa", ARCH_AVR5, "__AVR_ATmega324PA__", 0, 0, 0x0100, 1, "m324pa") -AVR_MCU ("atmega325", ARCH_AVR5, "__AVR_ATmega325__", 0, 0, 0x0100, 1, "m325") -AVR_MCU ("atmega325a", ARCH_AVR5, "__AVR_ATmega325A__", 0, 0, 0x0100, 1, "m325a") -AVR_MCU ("atmega325p", ARCH_AVR5, "__AVR_ATmega325P__", 0, 0, 0x0100, 1, "m325p") -AVR_MCU ("atmega3250", ARCH_AVR5, "__AVR_ATmega3250__", 0, 0, 0x0100, 1, "m3250") -AVR_MCU ("atmega3250a", ARCH_AVR5, "__AVR_ATmega3250A__", 0, 0, 0x0100, 1, "m3250a") -AVR_MCU ("atmega3250p", ARCH_AVR5, "__AVR_ATmega3250P__", 0, 0, 0x0100, 1, "m3250p") -AVR_MCU ("atmega3250pa", ARCH_AVR5, "__AVR_ATmega3250PA__", 0, 0, 0x0100, 1, "m3250pa") -AVR_MCU ("atmega328", ARCH_AVR5, "__AVR_ATmega328__", 0, 0, 0x0100, 1, "m328") -AVR_MCU ("atmega328p", ARCH_AVR5, "__AVR_ATmega328P__", 0, 0, 0x0100, 1, "m328p") -AVR_MCU ("atmega329", ARCH_AVR5, "__AVR_ATmega329__", 0, 0, 0x0100, 1, "m329") -AVR_MCU ("atmega329a", ARCH_AVR5, "__AVR_ATmega329A__", 0, 0, 0x0100, 1, "m329a") -AVR_MCU ("atmega329p", ARCH_AVR5, "__AVR_ATmega329P__", 0, 0, 0x0100, 1, "m329p") -AVR_MCU ("atmega329pa", ARCH_AVR5, "__AVR_ATmega329PA__", 0, 0, 0x0100, 1, "m329pa") -AVR_MCU ("atmega3290", ARCH_AVR5, "__AVR_ATmega3290__", 0, 0, 0x0100, 1, "m3290") -AVR_MCU ("atmega3290a", ARCH_AVR5, "__AVR_ATmega3290A__", 0, 0, 0x0100, 1, "m3290a") -AVR_MCU ("atmega3290p", ARCH_AVR5, "__AVR_ATmega3290P__", 0, 0, 0x0100, 1, "m3290p") -AVR_MCU ("atmega3290pa", ARCH_AVR5, "__AVR_ATmega3290PA__", 0, 0, 0x0100, 1, "m3290pa") -AVR_MCU ("atmega32c1", ARCH_AVR5, "__AVR_ATmega32C1__", 0, 0, 0x0100, 1, "m32c1") -AVR_MCU ("atmega32m1", ARCH_AVR5, "__AVR_ATmega32M1__", 0, 0, 0x0100, 1, "m32m1") -AVR_MCU ("atmega32u4", ARCH_AVR5, "__AVR_ATmega32U4__", 0, 0, 0x0100, 1, "m32u4") -AVR_MCU ("atmega32u6", ARCH_AVR5, "__AVR_ATmega32U6__", 0, 0, 0x0100, 1, "m32u6") -AVR_MCU ("atmega406", ARCH_AVR5, "__AVR_ATmega406__", 0, 0, 0x0100, 1, "m406") -AVR_MCU ("atmega64", ARCH_AVR5, "__AVR_ATmega64__", 0, 0, 0x0100, 1, "m64") -AVR_MCU ("atmega64a", ARCH_AVR5, "__AVR_ATmega64A__", 0, 0, 0x0100, 1, "m64a") -AVR_MCU ("atmega640", ARCH_AVR5, "__AVR_ATmega640__", 0, 0, 0x0200, 1, "m640") -AVR_MCU ("atmega644", ARCH_AVR5, "__AVR_ATmega644__", 0, 0, 0x0100, 1, "m644") -AVR_MCU ("atmega644a", ARCH_AVR5, "__AVR_ATmega644A__", 0, 0, 0x0100, 1, "m644a") -AVR_MCU ("atmega644p", ARCH_AVR5, "__AVR_ATmega644P__", 0, 0, 0x0100, 1, "m644p") -AVR_MCU ("atmega644pa", ARCH_AVR5, "__AVR_ATmega644PA__", 0, 0, 0x0100, 1, "m644pa") -AVR_MCU ("atmega645", ARCH_AVR5, "__AVR_ATmega645__", 0, 0, 0x0100, 1, "m645") -AVR_MCU ("atmega645a", ARCH_AVR5, "__AVR_ATmega645A__", 0, 0, 0x0100, 1, "m645a") -AVR_MCU ("atmega645p", ARCH_AVR5, "__AVR_ATmega645P__", 0, 0, 0x0100, 1, "m645p") -AVR_MCU ("atmega6450", ARCH_AVR5, "__AVR_ATmega6450__", 0, 0, 0x0100, 1, "m6450") -AVR_MCU ("atmega6450a", ARCH_AVR5, "__AVR_ATmega6450A__", 0, 0, 0x0100, 1, "m6450a") -AVR_MCU ("atmega6450p", ARCH_AVR5, "__AVR_ATmega6450P__", 0, 0, 0x0100, 1, "m6450p") -AVR_MCU ("atmega649", ARCH_AVR5, "__AVR_ATmega649__", 0, 0, 0x0100, 1, "m649") -AVR_MCU ("atmega649a", ARCH_AVR5, "__AVR_ATmega649A__", 0, 0, 0x0100, 1, "m649a") -AVR_MCU ("atmega649p", ARCH_AVR5, "__AVR_ATmega649P__", 0, 0, 0x0100, 1, "m649p") -AVR_MCU ("atmega6490", ARCH_AVR5, "__AVR_ATmega6490__", 0, 0, 0x0100, 1, "m6490") -AVR_MCU ("atmega16hva", ARCH_AVR5, "__AVR_ATmega16HVA__", 0, 0, 0x0100, 1, "m16hva") -AVR_MCU ("atmega16hva2", ARCH_AVR5, "__AVR_ATmega16HVA2__", 0, 0, 0x0100, 1, "m16hva2") -AVR_MCU ("atmega32hvb", ARCH_AVR5, "__AVR_ATmega32HVB__", 0, 0, 0x0100, 1, "m32hvb") -AVR_MCU ("atmega6490a", ARCH_AVR5, "__AVR_ATmega6490A__", 0, 0, 0x0100, 1, "m6490a") -AVR_MCU ("atmega6490p", ARCH_AVR5, "__AVR_ATmega6490P__", 0, 0, 0x0100, 1, "m6490p") -AVR_MCU ("atmega64c1", ARCH_AVR5, "__AVR_ATmega64C1__", 0, 0, 0x0100, 1, "m64c1") -AVR_MCU ("atmega64m1", ARCH_AVR5, "__AVR_ATmega64M1__", 0, 0, 0x0100, 1, "m64m1") -AVR_MCU ("atmega64hve", ARCH_AVR5, "__AVR_ATmega64HVE__", 0, 0, 0x0100, 1, "m64hve") -AVR_MCU ("atmega64rfa2", ARCH_AVR5, "__AVR_ATmega64RFA2__", 0, 0, 0x0200, 1, "m64rfa2") -AVR_MCU ("atmega64rfr2", ARCH_AVR5, "__AVR_ATmega64RFR2__", 0, 0, 0x0200, 1, "m64rfr2") -AVR_MCU ("atmega32hvbrevb", ARCH_AVR5, "__AVR_ATmega32HVBREVB__", 0, 0, 0x0100, 1, "m32hvbrevb") -AVR_MCU ("atmega48hvf", ARCH_AVR5, "__AVR_ATmega48HVF__", 0, 0, 0x0100, 1, "m48hvf") -AVR_MCU ("at90can32", ARCH_AVR5, "__AVR_AT90CAN32__", 0, 0, 0x0100, 1, "can32") -AVR_MCU ("at90can64", ARCH_AVR5, "__AVR_AT90CAN64__", 0, 0, 0x0100, 1, "can64") -AVR_MCU ("at90pwm161", ARCH_AVR5, "__AVR_AT90PWM161__", 0, 0, 0x0100, 1, "90pwm161") -AVR_MCU ("at90pwm216", ARCH_AVR5, "__AVR_AT90PWM216__", 0, 0, 0x0100, 1, "90pwm216") -AVR_MCU ("at90pwm316", ARCH_AVR5, "__AVR_AT90PWM316__", 0, 0, 0x0100, 1, "90pwm316") -AVR_MCU ("at90scr100", ARCH_AVR5, "__AVR_AT90SCR100__", 0, 0, 0x0100, 1, "90scr100") -AVR_MCU ("at90usb646", ARCH_AVR5, "__AVR_AT90USB646__", 0, 0, 0x0100, 1, "usb646") -AVR_MCU ("at90usb647", ARCH_AVR5, "__AVR_AT90USB647__", 0, 0, 0x0100, 1, "usb647") -AVR_MCU ("at94k", ARCH_AVR5, "__AVR_AT94K__", 0, 0, 0x0060, 1, "at94k") -AVR_MCU ("m3000", ARCH_AVR5, "__AVR_M3000__", 0, 0, 0x1000, 1, "m3000") +AVR_MCU ("avr5", ARCH_AVR5, AVR_ISA_NONE, NULL, 0x0060, 1, "m16") +AVR_MCU ("ata5790", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATA5790__", 0x0100, 1, "a5790") +AVR_MCU ("ata5790n", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATA5790N__", 0x0100, 1, "a5790n") +AVR_MCU ("ata5795", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATA5795__", 0x0100, 1, "a5795") +AVR_MCU ("atmega16", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega16__", 0x0060, 1, "m16") +AVR_MCU ("atmega16a", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega16A__", 0x0060, 1, "m16a") +AVR_MCU ("atmega161", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega161__", 0x0060, 1, "m161") +AVR_MCU ("atmega162", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega162__", 0x0100, 1, "m162") +AVR_MCU ("atmega163", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega163__", 0x0060, 1, "m163") +AVR_MCU ("atmega164a", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega164A__", 0x0100, 1, "m164a") +AVR_MCU ("atmega164p", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega164P__", 0x0100, 1, "m164p") +AVR_MCU ("atmega164pa", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega164PA__", 0x0100, 1, "m164pa") +AVR_MCU ("atmega165", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega165__", 0x0100, 1, "m165") +AVR_MCU ("atmega165a", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega165A__", 0x0100, 1, "m165a") +AVR_MCU ("atmega165p", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega165P__", 0x0100, 1, "m165p") +AVR_MCU ("atmega165pa", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega165PA__", 0x0100, 1, "m165pa") +AVR_MCU ("atmega168", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega168__", 0x0100, 1, "m168") +AVR_MCU ("atmega168a", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega168A__", 0x0100, 1, "m168a") +AVR_MCU ("atmega168p", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega168P__", 0x0100, 1, "m168p") +AVR_MCU ("atmega168pa", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega168PA__", 0x0100, 1, "m168pa") +AVR_MCU ("atmega169", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega169__", 0x0100, 1, "m169") +AVR_MCU ("atmega169a", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega169A__", 0x0100, 1, "m169a") +AVR_MCU ("atmega169p", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega169P__", 0x0100, 1, "m169p") +AVR_MCU ("atmega169pa", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega169PA__", 0x0100, 1, "m169pa") +AVR_MCU ("atmega16hvb", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega16HVB__", 0x0100, 1, "m16hvb") +AVR_MCU ("atmega16hvbrevb", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega16HVBREVB__", 0x0100, 1, "m16hvbrevb") +AVR_MCU ("atmega16m1", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega16M1__", 0x0100, 1, "m16m1") +AVR_MCU ("atmega16u4", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega16U4__", 0x0100, 1, "m16u4") +AVR_MCU ("atmega26hvg", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega26HVG__", 0x0100, 1, "m26hvg") +AVR_MCU ("atmega32a", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega32A__", 0x0060, 1, "m32a") +AVR_MCU ("atmega32", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega32__", 0x0060, 1, "m32") +AVR_MCU ("atmega323", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega323__", 0x0060, 1, "m323") +AVR_MCU ("atmega324a", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega324A__", 0x0100, 1, "m324a") +AVR_MCU ("atmega324p", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega324P__", 0x0100, 1, "m324p") +AVR_MCU ("atmega324pa", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega324PA__", 0x0100, 1, "m324pa") +AVR_MCU ("atmega325", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega325__", 0x0100, 1, "m325") +AVR_MCU ("atmega325a", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega325A__", 0x0100, 1, "m325a") +AVR_MCU ("atmega325p", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega325P__", 0x0100, 1, "m325p") +AVR_MCU ("atmega3250", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega3250__", 0x0100, 1, "m3250") +AVR_MCU ("atmega3250a", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega3250A__", 0x0100, 1, "m3250a") +AVR_MCU ("atmega3250p", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega3250P__", 0x0100, 1, "m3250p") +AVR_MCU ("atmega3250pa", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega3250PA__", 0x0100, 1, "m3250pa") +AVR_MCU ("atmega328", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega328__", 0x0100, 1, "m328") +AVR_MCU ("atmega328p", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega328P__", 0x0100, 1, "m328p") +AVR_MCU ("atmega329", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega329__", 0x0100, 1, "m329") +AVR_MCU ("atmega329a", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega329A__", 0x0100, 1, "m329a") +AVR_MCU ("atmega329p", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega329P__", 0x0100, 1, "m329p") +AVR_MCU ("atmega329pa", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega329PA__", 0x0100, 1, "m329pa") +AVR_MCU ("atmega3290", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega3290__", 0x0100, 1, "m3290") +AVR_MCU ("atmega3290a", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega3290A__", 0x0100, 1, "m3290a") +AVR_MCU ("atmega3290p", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega3290P__", 0x0100, 1, "m3290p") +AVR_MCU ("atmega3290pa", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega3290PA__", 0x0100, 1, "m3290pa") +AVR_MCU ("atmega32c1", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega32C1__", 0x0100, 1, "m32c1") +AVR_MCU ("atmega32m1", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega32M1__", 0x0100, 1, "m32m1") +AVR_MCU ("atmega32u4", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega32U4__", 0x0100, 1, "m32u4") +AVR_MCU ("atmega32u6", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega32U6__", 0x0100, 1, "m32u6") +AVR_MCU ("atmega406", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega406__", 0x0100, 1, "m406") +AVR_MCU ("atmega64", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega64__", 0x0100, 1, "m64") +AVR_MCU ("atmega64a", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega64A__", 0x0100, 1, "m64a") +AVR_MCU ("atmega640", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega640__", 0x0200, 1, "m640") +AVR_MCU ("atmega644", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega644__", 0x0100, 1, "m644") +AVR_MCU ("atmega644a", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega644A__", 0x0100, 1, "m644a") +AVR_MCU ("atmega644p", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega644P__", 0x0100, 1, "m644p") +AVR_MCU ("atmega644pa", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega644PA__", 0x0100, 1, "m644pa") +AVR_MCU ("atmega645", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega645__", 0x0100, 1, "m645") +AVR_MCU ("atmega645a", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega645A__", 0x0100, 1, "m645a") +AVR_MCU ("atmega645p", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega645P__", 0x0100, 1, "m645p") +AVR_MCU ("atmega6450", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega6450__", 0x0100, 1, "m6450") +AVR_MCU ("atmega6450a", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega6450A__", 0x0100, 1, "m6450a") +AVR_MCU ("atmega6450p", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega6450P__", 0x0100, 1, "m6450p") +AVR_MCU ("atmega649", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega649__", 0x0100, 1, "m649") +AVR_MCU ("atmega649a", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega649A__", 0x0100, 1, "m649a") +AVR_MCU ("atmega649p", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega649P__", 0x0100, 1, "m649p") +AVR_MCU ("atmega6490", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega6490__", 0x0100, 1, "m6490") +AVR_MCU ("atmega16hva", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega16HVA__", 0x0100, 1, "m16hva") +AVR_MCU ("atmega16hva2", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega16HVA2__", 0x0100, 1, "m16hva2") +AVR_MCU ("atmega32hvb", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega32HVB__", 0x0100, 1, "m32hvb") +AVR_MCU ("atmega6490a", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega6490A__", 0x0100, 1, "m6490a") +AVR_MCU ("atmega6490p", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega6490P__", 0x0100, 1, "m6490p") +AVR_MCU ("atmega64c1", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega64C1__", 0x0100, 1, "m64c1") +AVR_MCU ("atmega64m1", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega64M1__", 0x0100, 1, "m64m1") +AVR_MCU ("atmega64hve", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega64HVE__", 0x0100, 1, "m64hve") +AVR_MCU ("atmega64rfa2", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega64RFA2__", 0x0200, 1, "m64rfa2") +AVR_MCU ("atmega64rfr2", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega64RFR2__", 0x0200, 1, "m64rfr2") +AVR_MCU ("atmega32hvbrevb", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega32HVBREVB__", 0x0100, 1, "m32hvbrevb") +AVR_MCU ("atmega48hvf", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega48HVF__", 0x0100, 1, "m48hvf") +AVR_MCU ("at90can32", ARCH_AVR5, AVR_ISA_NONE, "__AVR_AT90CAN32__", 0x0100, 1, "can32") +AVR_MCU ("at90can64", ARCH_AVR5, AVR_ISA_NONE, "__AVR_AT90CAN64__", 0x0100, 1, "can64") +AVR_MCU ("at90pwm161", ARCH_AVR5, AVR_ISA_NONE, "__AVR_AT90PWM161__", 0x0100, 1, "90pwm161") +AVR_MCU ("at90pwm216", ARCH_AVR5, AVR_ISA_NONE, "__AVR_AT90PWM216__", 0x0100, 1, "90pwm216") +AVR_MCU ("at90pwm316", ARCH_AVR5, AVR_ISA_NONE, "__AVR_AT90PWM316__", 0x0100, 1, "90pwm316") +AVR_MCU ("at90scr100", ARCH_AVR5, AVR_ISA_NONE, "__AVR_AT90SCR100__", 0x0100, 1, "90scr100") +AVR_MCU ("at90usb646", ARCH_AVR5, AVR_ISA_NONE, "__AVR_AT90USB646__", 0x0100, 1, "usb646") +AVR_MCU ("at90usb647", ARCH_AVR5, AVR_ISA_NONE, "__AVR_AT90USB647__", 0x0100, 1, "usb647") +AVR_MCU ("at94k", ARCH_AVR5, AVR_ISA_NONE, "__AVR_AT94K__", 0x0060, 1, "at94k") +AVR_MCU ("m3000", ARCH_AVR5, AVR_ISA_NONE, "__AVR_M3000__", 0x1000, 1, "m3000") /* Enhanced, == 128K. */ -AVR_MCU ("avr51", ARCH_AVR51, NULL, 0, 0, 0x0100, 2, "m128") -AVR_MCU ("atmega128", ARCH_AVR51, "__AVR_ATmega128__", 0, 0, 0x0100, 2, "m128") -AVR_MCU ("atmega128a", ARCH_AVR51, "__AVR_ATmega128A__", 0, 0, 0x0100, 2, "m128a") -AVR_MCU ("atmega1280", ARCH_AVR51, "__AVR_ATmega1280__", 0, 0, 0x0200, 2, "m1280") -AVR_MCU ("atmega1281", ARCH_AVR51, "__AVR_ATmega1281__", 0, 0, 0x0200, 2, "m1281") -AVR_MCU ("atmega1284", ARCH_AVR51, "__AVR_ATmega1284__", 0, 0, 0x0100, 2, "m1284") -AVR_MCU ("atmega1284p", ARCH_AVR51, "__AVR_ATmega1284P__", 0, 0, 0x0100, 2, "m1284p") -AVR_MCU ("atmega128rfa1", ARCH_AVR51, "__AVR_ATmega128RFA1__", 0, 0, 0x0200, 2, "m128rfa1") -AVR_MCU ("at90can128", ARCH_AVR51, "__AVR_AT90CAN128__", 0, 0, 0x0100, 2, "can128") -AVR_MCU ("at90usb1286", ARCH_AVR51, "__AVR_AT90USB1286__", 0, 0, 0x0100, 2, "usb1286") -AVR_MCU ("at90usb1287", ARCH_AVR51, "__AVR_AT90USB1287__", 0, 0, 0x0100, 2, "usb1287") +AVR_MCU ("avr51", ARCH_AVR51, AVR_ISA_NONE, NULL, 0x0100, 2, "m128") +AVR_MCU ("atmega128", ARCH_AVR51, AVR_ISA_NONE, "__AVR_ATmega128__", 0x0100, 2, "m128") +AVR_MCU ("atmega128a", ARCH_AVR51, AVR_ISA_NONE, "__AVR_ATmega128A__", 0x0100, 2, "m128a") +AVR_MCU ("atmega1280", ARCH_AVR51, AVR_ISA_NONE, "__AVR_ATmega1280__", 0x0200, 2, "m1280") +AVR_MCU ("atmega1281", ARCH_AVR51, AVR_ISA_NONE, "__AVR_ATmega1281__", 0x0200, 2, "m1281") +AVR_MCU ("atmega1284", ARCH_AVR51, AVR_ISA_NONE, "__AVR_ATmega1284__", 0x0100, 2, "m1284") +AVR_MCU ("atmega1284p", ARCH_AVR51, AVR_ISA_NONE, "__AVR_ATmega1284P__", 0x0100, 2, "m1284p") +AVR_MCU ("atmega128rfa1", ARCH_AVR51, AVR_ISA_NONE, "__AVR_ATmega128RFA1__", 0x0200, 2, "m128rfa1") +AVR_MCU ("at90can128", ARCH_AVR51, AVR_ISA_NONE, "__AVR_AT90CAN128__", 0x0100, 2, "can128") +AVR_MCU ("at90usb1286", ARCH_AVR51, AVR_ISA_NONE, "__AVR_AT90USB1286__", 0x0100, 2, "usb1286") +AVR_MCU ("at90usb1287", ARCH_AVR51, AVR_ISA_NONE, "__AVR_AT90USB1287__", 0x0100, 2, "usb1287") /* 3-Byte PC. */ -AVR_MCU ("avr6", ARCH_AVR6, NULL, 0, 0, 0x0200, 4, "m2561") -AVR_MCU ("atmega2560", ARCH_AVR6, "__AVR_ATmega2560__", 0, 0, 0x0200, 4, "m2560") -AVR_MCU ("atmega2561", ARCH_AVR6, "__AVR_ATmega2561__", 0, 0, 0x0200, 4, "m2561") +AVR_MCU ("avr6", ARCH_AVR6, AVR_ISA_NONE, NULL, 0x0200, 4, "m2561") +AVR_MCU ("atmega2560", ARCH_AVR6, AVR_ISA_NONE, "__AVR_ATmega2560__", 0x0200, 4, "m2560") +AVR_MCU ("atmega2561", ARCH_AVR6, AVR_ISA_NONE, "__AVR_ATmega2561__", 0x0200, 4, "m2561") /* Xmega, 16K <= Flash < 64K, RAM <= 64K */ -AVR_MCU ("avrxmega2", ARCH_AVRXMEGA2, NULL, 0, 0, 0x2000, 1, "x32a4") -AVR_MCU ("atxmega16a4", ARCH_AVRXMEGA2, "__AVR_ATxmega16A4__", 0, 0, 0x2000, 1, "x16a4") -AVR_MCU ("atxmega16d4", ARCH_AVRXMEGA2, "__AVR_ATxmega16D4__", 0, 0, 0x2000, 1, "x16d4") -AVR_MCU ("atxmega32a4", ARCH_AVRXMEGA2, "__AVR_ATxmega32A4__", 0, 0, 0x2000, 1, "x32a4") -AVR_MCU ("atxmega32d4", ARCH_AVRXMEGA2, "__AVR_ATxmega32D4__", 0, 0, 0x2000, 1, "x32d4") -AVR_MCU ("atxmega32x1", ARCH_AVRXMEGA2, "__AVR_ATxmega32X1__", 0, 0, 0x2000, 1, "x32x1") -AVR_MCU ("atmxt112sl", ARCH_AVRXMEGA2, "__AVR_ATMXT112SL__", 0, 0, 0x2000, 1, "mxt112sl") -AVR_MCU ("atmxt224", ARCH_AVRXMEGA2, "__AVR_ATMXT224__", 0, 0, 0x2000, 1, "mxt224") -AVR_MCU ("atmxt224e", ARCH_AVRXMEGA2, "__AVR_ATMXT224E__", 0, 0, 0x2000, 1, "mxt224e") -AVR_MCU ("atmxt336s", ARCH_AVRXMEGA2, "__AVR_ATMXT336S__", 0, 0, 0x2000, 1, "mxt336s") -AVR_MCU ("atxmega16a4u", ARCH_AVRXMEGA2, "__AVR_ATxmega16A4U__", 0, 0, 0x2000, 1, "x16a4u") -AVR_MCU ("atxmega16c4", ARCH_AVRXMEGA2, "__AVR_ATxmega16C4__", 0, 0, 0x2000, 1, "x16c4") -AVR_MCU ("atxmega32a4u", ARCH_AVRXMEGA2, "__AVR_ATxmega32A4U__", 0, 0, 0x2000, 1, "x32a4u") -AVR_MCU ("atxmega32c4", ARCH_AVRXMEGA2, "__AVR_ATxmega32C4__", 0, 0, 0x2000, 1, "x32c4") -AVR_MCU ("atxmega32e5", ARCH_AVRXMEGA2, "__AVR_ATxmega32E5__", 0, 0, 0x2000, 1, "x32e5") +AVR_MCU ("avrxmega2", ARCH_AVRXMEGA2, AVR_ISA_NONE, NULL, 0x2000, 1, "x32a4") +AVR_MCU ("atxmega16a4", ARCH_AVRXMEGA2, AVR_ISA_NONE, "__AVR_ATxmega16A4__", 0x2000, 1, "x16a4") +AVR_MCU ("atxmega16d4", ARCH_AVRXMEGA2, AVR_ISA_NONE, "__AVR_ATxmega16D4__", 0x2000, 1, "x16d4") +AVR_MCU ("atxmega32a4", ARCH_AVRXMEGA2, AVR_ISA_NONE, "__AVR_ATxmega32A4__", 0x2000, 1, "x32a4") +AVR_MCU ("atxmega32d4", ARCH_AVRXMEGA2, AVR_ISA_NONE, "__AVR_ATxmega32D4__", 0x2000, 1, "x32d4") +AVR_MCU ("atxmega32x1", ARCH_AVRXMEGA2, AVR_ISA_NONE, "__AVR_ATxmega32X1__", 0x2000, 1, "x32x1") +AVR_MCU ("atmxt112sl", ARCH_AVRXMEGA2, AVR_ISA_NONE, "__AVR_ATMXT112SL__", 0x2000, 1, "mxt112sl") +AVR_MCU ("atmxt224", ARCH_AVRXMEGA2, AVR_ISA_NONE, "__AVR_ATMXT224__", 0x2000, 1, "mxt224") +AVR_MCU ("atmxt224e", ARCH_AVRXMEGA2, AVR_ISA_NONE, "__AVR_ATMXT224E__", 0x2000, 1, "mxt224e") +AVR_MCU ("atmxt336s", ARCH_AVRXMEGA2, AVR_ISA_NONE, "__AVR_ATMXT336S__", 0x2000, 1, "mxt336s") +AVR_MCU ("atxmega16a4u", ARCH_AVRXMEGA2, AVR_ISA_RMW, "__AVR_ATxmega16A4U__", 0x2000, 1, "x16a4u") +AVR_MCU ("atxmega16c4", ARCH_AVRXMEGA2, AVR_ISA_RMW, "__AVR_ATxmega16C4__", 0x2000, 1, "x16c4") +AVR_MCU ("atxmega32a4u", ARCH_AVRXMEGA2, AVR_ISA_RMW, "__AVR_ATxmega32A4U__", 0x2000, 1, "x32a4u") +AVR_MCU ("atxmega32c4", ARCH_AVRXMEGA2, AVR_ISA_RMW, "__AVR_ATxmega32C4__", 0x2000, 1, "x32c4") +AVR_MCU ("atxmega32e5", ARCH_AVRXMEGA2, AVR_ISA_NONE, "__AVR_ATxmega32E5__", 0x2000, 1, "x32e5") /* Xmega, 64K < Flash <= 128K, RAM <= 64K */ -AVR_MCU ("avrxmega4", ARCH_AVRXMEGA4, NULL, 0, 0, 0x2000, 2, "x64a4") -AVR_MCU ("atxmega64a3", ARCH_AVRXMEGA4, "__AVR_ATxmega64A3__", 0, 0, 0x2000, 2, "x64a3") -AVR_MCU ("atxmega64d3", ARCH_AVRXMEGA4, "__AVR_ATxmega64D3__", 0, 0, 0x2000, 2, "x64d3") -AVR_MCU ("atxmega64a3u", ARCH_AVRXMEGA4, "__AVR_ATxmega64A3U__", 0, 0, 0x2000, 2, "x64a3u") -AVR_MCU ("atxmega64a4u", ARCH_AVRXMEGA4, "__AVR_ATxmega64A4U__", 0, 0, 0x2000, 2, "x64a4u") -AVR_MCU ("atxmega64b1", ARCH_AVRXMEGA4, "__AVR_ATxmega64B1__", 0, 0, 0x2000, 2, "x64b1") -AVR_MCU ("atxmega64b3", ARCH_AVRXMEGA4, "__AVR_ATxmega64B3__", 0, 0, 0x2000, 2, "x64b3") -AVR_MCU ("atxmega64c3", ARCH_AVRXMEGA4, "__AVR_ATxmega64C3__", 0, 0, 0x2000, 2, "x64c3") -AVR_MCU ("atxmega64d4", ARCH_AVRXMEGA4, "__AVR_ATxmega64D4__", 0, 0, 0x2000, 2, "x64d4") +AVR_MCU ("avrxmega4", ARCH_AVRXMEGA4, AVR_ISA_NONE, NULL, 0x2000, 2, "x64a4") +AVR_MCU ("atxmega64a3", ARCH_AVRXMEGA4, AVR_ISA_NONE, "__AVR_ATxmega64A3__", 0x2000, 2, "x64a3") +AVR_MCU ("atxmega64d3", ARCH_AVRXMEGA4, AVR_ISA_NONE, "__AVR_ATxmega64D3__", 0x2000, 2, "x64d3") +AVR_MCU ("atxmega64a3u", ARCH_AVRXMEGA4, AVR_ISA_RMW, "__AVR_ATxmega64A3U__", 0x2000, 2, "x64a3u") +AVR_MCU ("atxmega64a4u", ARCH_AVRXMEGA4, AVR_ISA_RMW, "__AVR_ATxmega64A4U__", 0x2000, 2, "x64a4u") +AVR_MCU ("atxmega64b1", ARCH_AVRXMEGA4, AVR_ISA_RMW, "__AVR_ATxmega64B1__", 0x2000, 2, "x64b1") +AVR_MCU ("atxmega64b3", ARCH_AVRXMEGA4, AVR_ISA_RMW, "__AVR_ATxmega64B3__", 0x2000, 2, "x64b3") +AVR_MCU ("atxmega64c3", ARCH_AVRXMEGA4, AVR_ISA_RMW, "__AVR_ATxmega64C3__", 0x2000, 2, "x64c3") +AVR_MCU ("atxmega64d4", ARCH_AVRXMEGA4, AVR_ISA_NONE, "__AVR_ATxmega64D4__", 0x2000, 2, "x64d4") /* Xmega, 64K < Flash <= 128K, RAM > 64K */ -AVR_MCU ("avrxmega5", ARCH_AVRXMEGA5, NULL, 0, 0, 0x2000, 2, "x64a1") -AVR_MCU ("atxmega64a1", ARCH_AVRXMEGA5, "__AVR_ATxmega64A1__", 0, 0, 0x2000, 2, "x64a1") -AVR_MCU ("atxmega64a1u", ARCH_AVRXMEGA5, "__AVR_ATxmega64A1U__", 0, 0, 0x2000, 2, "x64a1u") +AVR_MCU ("avrxmega5", ARCH_AVRXMEGA5, AVR_ISA_NONE, NULL, 0x2000, 2, "x64a1") +AVR_MCU ("atxmega64a1", ARCH_AVRXMEGA5, AVR_ISA_NONE, "__AVR_ATxmega64A1__", 0x2000, 2, "x64a1") +AVR_MCU ("atxmega64a1u", ARCH_AVRXMEGA5, AVR_ISA_RMW, "__AVR_ATxmega64A1U__", 0x2000, 2, "x64a1u") /* Xmega, 128K < Flash, RAM <= 64K */ -AVR_MCU ("avrxmega6", ARCH_AVRXMEGA6, NULL, 0, 0, 0x2000, 6, "x128a3") -AVR_MCU ("atxmega128a3", ARCH_AVRXMEGA6, "__AVR_ATxmega128A3__", 0, 0, 0x2000, 3, "x128a3") -AVR_MCU ("atxmega128d3", ARCH_AVRXMEGA6, "__AVR_ATxmega128D3__", 0, 0, 0x2000, 3, "x128d3") -AVR_MCU ("atxmega192a3", ARCH_AVRXMEGA6, "__AVR_ATxmega192A3__", 0, 0, 0x2000, 4, "x192a3") -AVR_MCU ("atxmega192d3", ARCH_AVRXMEGA6, "__AVR_ATxmega192D3__", 0, 0, 0x2000, 4, "x192d3") -AVR_MCU ("atxmega256a3", ARCH_AVRXMEGA6, "__AVR_ATxmega256A3__", 0, 0, 0x2000, 5, "x256a3") -AVR_MCU ("atxmega256a3b", ARCH_AVRXMEGA6, "__AVR_ATxmega256A3B__", 0, 0, 0x2000, 5, "x256a3b") -AVR_MCU ("atxmega256a3bu", ARCH_AVRXMEGA6, "__AVR_ATxmega256A3BU__", 0, 0, 0x2000, 5, "x256a3bu") -AVR_MCU ("atxmega256d3", ARCH_AVRXMEGA6, "__AVR_ATxmega256D3__", 0, 0, 0x2000, 5, "x256d3") -AVR_MCU ("atxmega128a3u", ARCH_AVRXMEGA6, "__AVR_ATxmega128A3U__", 0, 0, 0x2000, 3, "x128a3u") -AVR_MCU ("atxmega128b1", ARCH_AVRXMEGA6, "__AVR_ATxmega128B1__", 0, 0, 0x2000, 3, "x128b1") -AVR_MCU ("atxmega128b3", ARCH_AVRXMEGA6, "__AVR_ATxmega128B3__", 0, 0, 0x2000, 3, "x128b3") -AVR_MCU ("atxmega128c3", ARCH_AVRXMEGA6, "__AVR_ATxmega128C3__", 0, 0, 0x2000, 3, "x128c3") -AVR_MCU ("atxmega128d4", ARCH_AVRXMEGA6, "__AVR_ATxmega128D4__", 0, 0, 0x2000, 3, "x128d4") -AVR_MCU ("atmxt540s", ARCH_AVRXMEGA6, "__AVR_ATMXT540S__", 0, 0, 0x2000, 2, "mxt540s") -AVR_MCU ("atmxt540sreva", ARCH_AVRXMEGA6, "__AVR_ATMXT540SREVA__", 0, 0, 0x2000, 2, "mxt540sreva") -AVR_MCU ("atxmega192a3u", ARCH_AVRXMEGA6, "__AVR_ATxmega192A3U__", 0, 0, 0x2000, 4, "x192a3u") -AVR_MCU ("atxmega192c3", ARCH_AVRXMEGA6, "__AVR_ATxmega192C3__", 0, 0, 0x2000, 4, "x192c3") -AVR_MCU ("atxmega256a3u", ARCH_AVRXMEGA6, "__AVR_ATxmega256A3U__", 0, 0, 0x2000, 5, "x256a3u") -AVR_MCU ("atxmega256c3", ARCH_AVRXMEGA6, "__AVR_ATxmega256C3__", 0, 0, 0x2000, 5, "x256c3") -AVR_MCU ("atxmega384c3", ARCH_AVRXMEGA6, "__AVR_ATxmega384C3__", 0, 0, 0x2000, 6, "x384c3") -AVR_MCU ("atxmega384d3", ARCH_AVRXMEGA6, "__AVR_ATxmega384D3__", 0, 0, 0x2000, 6, "x384d3") +AVR_MCU ("avrxmega6", ARCH_AVRXMEGA6, AVR_ISA_NONE, NULL, 0x2000, 6, "x128a3") +AVR_MCU ("atxmega128a3", ARCH_AVRXMEGA6, AVR_ISA_NONE, "__AVR_ATxmega128A3__", 0x2000, 3, "x128a3") +AVR_MCU ("atxmega128d3", ARCH_AVRXMEGA6, AVR_ISA_NONE, "__AVR_ATxmega128D3__", 0x2000, 3, "x128d3") +AVR_MCU ("atxmega192a3", ARCH_AVRXMEGA6, AVR_ISA_NONE, "__AVR_ATxmega192A3__", 0x2000, 4, "x192a3") +AVR_MCU ("atxmega192d3", ARCH_AVRXMEGA6, AVR_ISA_NONE, "__AVR_ATxmega192D3__", 0x2000, 4, "x192d3") +AVR_MCU ("atxmega256a3", ARCH_AVRXMEGA6, AVR_ISA_NONE, "__AVR_ATxmega256A3__", 0x2000, 5, "x256a3") +AVR_MCU ("atxmega256a3b", ARCH_AVRXMEGA6, AVR_ISA_NONE, "__AVR_ATxmega256A3B__", 0x2000, 5, "x256a3b") +AVR_MCU ("atxmega256a3bu", ARCH_AVRXMEGA6, AVR_ISA_NONE, "__AVR_ATxmega256A3BU__", 0x2000, 5, "x256a3bu") +AVR_MCU ("atxmega256d3", ARCH_AVRXMEGA6, AVR_ISA_NONE, "__AVR_ATxmega256D3__", 0x2000, 5, "x256d3") +AVR_MCU ("atxmega128a3u", ARCH_AVRXMEGA6, AVR_ISA_RMW, "__AVR_ATxmega128A3U__", 0x2000, 3, "x128a3u") +AVR_MCU ("atxmega128b1", ARCH_AVRXMEGA6, AVR_ISA_RMW, "__AVR_ATxmega128B1__", 0x2000, 3, "x128b1") +AVR_MCU ("atxmega128b3", ARCH_AVRXMEGA6, AVR_ISA_RMW, "__AVR_ATxmega128B3__", 0x2000, 3, "x128b3") +AVR_MCU ("atxmega128c3", ARCH_AVRXMEGA6, AVR_ISA_RMW, "__AVR_ATxmega128C3__", 0x2000, 3, "x128c3") +AVR_MCU ("atxmega128d4", ARCH_AVRXMEGA6, AVR_ISA_NONE, "__AVR_ATxmega128D4__", 0x2000, 3, "x128d4") +AVR_MCU ("atmxt540s", ARCH_AVRXMEGA6, AVR_ISA_NONE, "__AVR_ATMXT540S__", 0x2000, 2, "mxt540s") +AVR_MCU ("atmxt540sreva", ARCH_AVRXMEGA6, AVR_ISA_NONE, "__AVR_ATMXT540SREVA__", 0x2000, 2, "mxt540sreva") +AVR_MCU ("atxmega192a3u", ARCH_AVRXMEGA6, AVR_ISA_RMW, "__AVR_ATxmega192A3U__", 0x2000, 4, "x192a3u") +AVR_MCU ("atxmega192c3", ARCH_AVRXMEGA6, AVR_ISA_RMW, "__AVR_ATxmega192C3__", 0x2000, 4, "x192c3") +AVR_MCU ("atxmega256a3u", ARCH_AVRXMEGA6, AVR_ISA_RMW, "__AVR_ATxmega256A3U__", 0x2000, 5, "x256a3u") +AVR_MCU ("atxmega256c3", ARCH_AVRXMEGA6, AVR_ISA_RMW, "__AVR_ATxmega256C3__", 0x2000, 5, "x256c3") +AVR_MCU ("atxmega384c3", ARCH_AVRXMEGA6, AVR_ISA_RMW, "__AVR_ATxmega384C3__", 0x2000, 6, "x384c3") +AVR_MCU ("atxmega384d3", ARCH_AVRXMEGA6, AVR_ISA_NONE, "__AVR_ATxmega384D3__", 0x2000, 6, "x384d3") /* Xmega, 128K < Flash, RAM > 64K RAM. */ -AVR_MCU ("avrxmega7", ARCH_AVRXMEGA7, NULL, 0, 0, 0x2000, 3, "x128a1") -AVR_MCU ("atxmega128a1", ARCH_AVRXMEGA7, "__AVR_ATxmega128A1__", 0, 0, 0x2000, 3, "x128a1") -AVR_MCU ("atxmega128a1u", ARCH_AVRXMEGA7, "__AVR_ATxmega128A1U__", 0, 0, 0x2000, 3, "x128a1u") -AVR_MCU ("atxmega128a4u", ARCH_AVRXMEGA7, "__AVR_ATxmega128A4U__", 0, 0, 0x2000, 3, "x128a4u") +AVR_MCU ("avrxmega7", ARCH_AVRXMEGA7, AVR_ISA_NONE, NULL, 0x2000, 3, "x128a1") +AVR_MCU ("atxmega128a1", ARCH_AVRXMEGA7, AVR_ISA_NONE, "__AVR_ATxmega128A1__", 0x2000, 3, "x128a1") +AVR_MCU ("atxmega128a1u", ARCH_AVRXMEGA7, AVR_ISA_RMW, "__AVR_ATxmega128A1U__", 0x2000, 3, "x128a1u") +AVR_MCU ("atxmega128a4u", ARCH_AVRXMEGA7, AVR_ISA_RMW, "__AVR_ATxmega128A4U__", 0x2000, 3, "x128a4u") /* Assembler only. */ -AVR_MCU ("avr1", ARCH_AVR1, NULL, 0, 0, 0x0060, 1, "s1200") -AVR_MCU ("at90s1200", ARCH_AVR1, "__AVR_AT90S1200__", 0, 0, 0x0060, 1, "s1200") -AVR_MCU ("attiny11", ARCH_AVR1, "__AVR_ATtiny11__", 0, 0, 0x0060, 1, "tn11") -AVR_MCU ("attiny12", ARCH_AVR1, "__AVR_ATtiny12__", 0, 0, 0x0060, 1, "tn12") -AVR_MCU ("attiny15", ARCH_AVR1, "__AVR_ATtiny15__", 0, 0, 0x0060, 1, "tn15") -AVR_MCU ("attiny28", ARCH_AVR1, "__AVR_ATtiny28__", 0, 0, 0x0060, 1, "tn28") +AVR_MCU ("avr1", ARCH_AVR1, AVR_ISA_NONE, NULL, 0x0060, 1, "s1200") +AVR_MCU ("at90s1200", ARCH_AVR1, AVR_ISA_NONE, "__AVR_AT90S1200__", 0x0060, 1, "s1200") +AVR_MCU ("attiny11", ARCH_AVR1, AVR_ISA_NONE, "__AVR_ATtiny11__", 0x0060, 1, "tn11") +AVR_MCU ("attiny12", ARCH_AVR1, AVR_ISA_NONE, "__AVR_ATtiny12__", 0x0060, 1, "tn12") +AVR_MCU ("attiny15", ARCH_AVR1, AVR_ISA_NONE, "__AVR_ATtiny15__", 0x0060, 1, "tn15") +AVR_MCU ("attiny28", ARCH_AVR1, AVR_ISA_NONE, "__AVR_ATtiny28__", 0x0060, 1, "tn28") diff --git a/gcc/config/avr/avr.c b/gcc/config/avr/avr.c index a1fb8eeae86..25075b2f4b3 100644 --- a/gcc/config/avr/avr.c +++ b/gcc/config/avr/avr.c @@ -10122,7 +10122,7 @@ test_hard_reg_class (enum reg_class rclass, rtx x) static bool avr_2word_insn_p (rtx insn) { - if (avr_current_device->errata_skip + if ((avr_current_device->dev_attribute & AVR_ERRATA_SKIP) || !insn || 2 != get_attr_length (insn)) { diff --git a/gcc/config/avr/avr.h b/gcc/config/avr/avr.h index 74be83c8aa0..78434ec5e0d 100644 --- a/gcc/config/avr/avr.h +++ b/gcc/config/avr/avr.h @@ -88,8 +88,9 @@ enum __AVR_HAVE_8BIT_SP__ and __AVR_HAVE_16BIT_SP__. During multilib generation there is always __AVR_SP8__ == __AVR_HAVE_8BIT_SP__. */ -#define AVR_HAVE_8BIT_SP \ - (avr_current_device->short_sp || TARGET_TINY_STACK || avr_sp8) +#define AVR_HAVE_8BIT_SP \ + ((avr_current_device->dev_attribute & AVR_SHORT_SP) || \ + TARGET_TINY_STACK || avr_sp8) #define AVR_HAVE_SPH (!avr_sp8) diff --git a/gcc/config/avr/avr.md b/gcc/config/avr/avr.md index f2d8605cd20..d7baa4a8383 100644 --- a/gcc/config/avr/avr.md +++ b/gcc/config/avr/avr.md @@ -5342,7 +5342,7 @@ (label_ref (match_operand 0 "" "")) (pc)))] "!AVR_HAVE_JMP_CALL - || !avr_current_device->errata_skip" + || !(avr_current_device->dev_attribute & AVR_ERRATA_SKIP)" { if (operands[2] == CONST0_RTX (<MODE>mode)) operands[2] = zero_reg_rtx; diff --git a/gcc/config/avr/driver-avr.c b/gcc/config/avr/driver-avr.c index cb5dd1d1d89..76c8b398064 100644 --- a/gcc/config/avr/driver-avr.c +++ b/gcc/config/avr/driver-avr.c @@ -59,8 +59,8 @@ avr_device_to_as (int argc, const char **argv) avr_set_current_device (argv[0]); return concat ("-mmcu=", avr_current_arch->arch_name, - avr_current_device->errata_skip ? "" : " -mno-skip-bug", - NULL); + avr_current_device->dev_attribute & AVR_ERRATA_SKIP ? "" : " -mno-skip-bug", + avr_current_device->dev_attribute & AVR_ISA_RMW ? " -mrmw" : "", NULL); } /* Returns command line parameters to pass to ld. */ @@ -144,7 +144,7 @@ avr_device_to_sp8 (int argc, const char **argv) || avr_current_device->arch == ARCH_AVR25)) return ""; - return avr_current_device->short_sp + return (avr_current_device->dev_attribute & AVR_SHORT_SP) ? "-msp8" : "%<msp8"; } diff --git a/gcc/config/avr/genmultilib.awk b/gcc/config/avr/genmultilib.awk index 90e5e5cfd36..1dfeabbee49 100644 --- a/gcc/config/avr/genmultilib.awk +++ b/gcc/config/avr/genmultilib.awk @@ -86,7 +86,7 @@ BEGIN { name = $2 gsub ("\"", "", name) - if ($4 == "NULL") + if ($5 == "NULL") { core = name @@ -106,7 +106,17 @@ BEGIN { if (core == "avr1") next - tiny_stack[name] = $5 + # split device specific feature list + n = split($4,dev_attribute,"|") + + # set tiny_stack false by default + tiny_stack[name] = 0 + for (i=1; i <= n; i++) + if (dev_attribute[i] == "AVR_SHORT_SP") { + tiny_stack[name] = 1 + break + } + mcu[n_mcu] = name n_mcu++ option[name] = "mmcu=" name diff --git a/gcc/config/elfos.h b/gcc/config/elfos.h index 1fce7011b2b..c1d5553123d 100644 --- a/gcc/config/elfos.h +++ b/gcc/config/elfos.h @@ -287,7 +287,7 @@ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see /* Write the extra assembler code needed to declare an object properly. */ #ifdef HAVE_GAS_GNU_UNIQUE_OBJECT -#define USE_GNU_UNIQUE_OBJECT 1 +#define USE_GNU_UNIQUE_OBJECT flag_gnu_unique #else #define USE_GNU_UNIQUE_OBJECT 0 #endif diff --git a/gcc/config/epiphany/epiphany.c b/gcc/config/epiphany/epiphany.c index 59b24107a68..f3955b916e9 100644 --- a/gcc/config/epiphany/epiphany.c +++ b/gcc/config/epiphany/epiphany.c @@ -145,6 +145,13 @@ static rtx frame_insn (rtx); hook_bool_const_tree_hwi_hwi_const_tree_true #define TARGET_ASM_OUTPUT_MI_THUNK epiphany_output_mi_thunk +/* ??? we can use larger offsets for wider-mode sized accesses, but there + is no concept of anchors being dependent on the modes that they are used + for, so we can only use an offset range that would suit all modes. */ +#define TARGET_MAX_ANCHOR_OFFSET (optimize_size ? 31 : 2047) +/* We further restrict the minimum to be a multiple of eight. */ +#define TARGET_MIN_ANCHOR_OFFSET (optimize_size ? 0 : -2040) + #include "target-def.h" #undef TARGET_ASM_ALIGNED_HI_OP @@ -763,6 +770,28 @@ epiphany_rtx_costs (rtx x, int code, int outer_code, int opno ATTRIBUTE_UNUSED, *total = COSTS_N_INSNS (1); return true; + case COMPARE: + switch (GET_MODE (x)) + { + /* There are a number of single-insn combiner patterns that use + the flag side effects of arithmetic. */ + case CC_N_NEmode: + case CC_C_LTUmode: + case CC_C_GTUmode: + return true; + default: + return false; + } + + + case SET: + { + rtx src = SET_SRC (x); + if (BINARY_P (src)) + *total = 0; + return false; + } + default: return false; } @@ -2003,7 +2032,7 @@ epiphany_legitimate_address_p (enum machine_mode mode, rtx x, bool strict) && LEGITIMATE_OFFSET_ADDRESS_P (mode, XEXP ((x), 1))) return true; if (mode == BLKmode) - return true; + return epiphany_legitimate_address_p (SImode, x, strict); return false; } diff --git a/gcc/config/epiphany/epiphany.h b/gcc/config/epiphany/epiphany.h index cffb00c0354..1ca92e07b9e 100644 --- a/gcc/config/epiphany/epiphany.h +++ b/gcc/config/epiphany/epiphany.h @@ -942,4 +942,15 @@ extern rtl_opt_pass *make_pass_resolve_sw_modes (gcc::context *ctxt); #define ASM_DECLARE_FUNCTION_NAME(FILE, NAME, DECL) \ epiphany_start_function ((FILE), (NAME), (DECL)) +/* This is how we tell the assembler that two symbols have the same value. */ +#define ASM_OUTPUT_DEF(FILE, NAME1, NAME2) \ + do \ + { \ + assemble_name (FILE, NAME1); \ + fputs (" = ", FILE); \ + assemble_name (FILE, NAME2); \ + fputc ('\n', FILE); \ + } \ + while (0) + #endif /* !GCC_EPIPHANY_H */ diff --git a/gcc/config/epiphany/epiphany.md b/gcc/config/epiphany/epiphany.md index 2844eeea773..d8d5555b099 100644 --- a/gcc/config/epiphany/epiphany.md +++ b/gcc/config/epiphany/epiphany.md @@ -2380,7 +2380,7 @@ (plus:SI (reg:SI GPR_SP) (match_operand:SI 0 "arith_operand" "rL"))) (clobber (reg:CC CC_REGNUM)) (clobber (reg:SI STATUS_REGNUM)) - (clobber (match_operand:BLK 1 "memory_operand" "=m"))] + (clobber (match_operand:BLK 1 "memclob_operand" "=X"))] "reload_completed" "add sp,sp,%0") @@ -2396,7 +2396,7 @@ (match_operand 1 "any_gpr_operand" "r")) (set (reg:SI GPR_SP) (plus:SI (reg:SI GPR_SP) (match_operand:SI 2 "nonmemory_operand" "rn"))) - (clobber (match_operand:BLK 3 "memory_operand" "=m"))] + (clobber (match_operand:BLK 3 "memclob_operand" "=X"))] "reload_completed" { return (GET_MODE_SIZE (GET_MODE (operands[0])) <= 4 diff --git a/gcc/config/epiphany/predicates.md b/gcc/config/epiphany/predicates.md index fb8fd88ba7e..fb5ee1239c4 100644 --- a/gcc/config/epiphany/predicates.md +++ b/gcc/config/epiphany/predicates.md @@ -358,6 +358,11 @@ (and (match_code "mem") (match_test "post_modify_address (XEXP (op, 0), Pmode)"))) +; used in the memory clobber of stack_adjust_str, allows addresses with +; large offsets. +(define_predicate "memclob_operand" + (match_code "mem")) + (define_predicate "nonsymbolic_immediate_operand" (ior (match_test "immediate_operand (op, mode)") (match_code "const_vector"))) /* Is this specific enough? */ diff --git a/gcc/config/host-linux.c b/gcc/config/host-linux.c index 17048d7b585..41bee9276c8 100644 --- a/gcc/config/host-linux.c +++ b/gcc/config/host-linux.c @@ -86,6 +86,8 @@ # define TRY_EMPTY_VM_SPACE 0x60000000 #elif defined(__mc68000__) # define TRY_EMPTY_VM_SPACE 0x40000000 +#elif defined(__aarch64__) && defined(__ILP32__) +# define TRY_EMPTY_VM_SPACE 0x60000000 #elif defined(__aarch64__) # define TRY_EMPTY_VM_SPACE 0x1000000000 #elif defined(__ARM_EABI__) diff --git a/gcc/config/i386/bmiintrin.h b/gcc/config/i386/bmiintrin.h index b86adf179cf..b2d7c60eaf8 100644 --- a/gcc/config/i386/bmiintrin.h +++ b/gcc/config/i386/bmiintrin.h @@ -40,7 +40,6 @@ __tzcnt_u16 (unsigned short __X) return __builtin_ctzs (__X); } - extern __inline unsigned int __attribute__((__gnu_inline__, __always_inline__, __artificial__)) __andn_u32 (unsigned int __X, unsigned int __Y) { @@ -66,17 +65,34 @@ __blsi_u32 (unsigned int __X) } extern __inline unsigned int __attribute__((__gnu_inline__, __always_inline__, __artificial__)) +_blsi_u32 (unsigned int __X) +{ + return __blsi_u32 (__X); +} + +extern __inline unsigned int __attribute__((__gnu_inline__, __always_inline__, __artificial__)) __blsmsk_u32 (unsigned int __X) { return __X ^ (__X - 1); } extern __inline unsigned int __attribute__((__gnu_inline__, __always_inline__, __artificial__)) +_blsmsk_u32 (unsigned int __X) +{ + return __blsmsk_u32 (__X); +} + +extern __inline unsigned int __attribute__((__gnu_inline__, __always_inline__, __artificial__)) __blsr_u32 (unsigned int __X) { return __X & (__X - 1); } +extern __inline unsigned int __attribute__((__gnu_inline__, __always_inline__, __artificial__)) +_blsr_u32 (unsigned int __X) +{ + return __blsr_u32 (__X); +} extern __inline unsigned int __attribute__((__gnu_inline__, __always_inline__, __artificial__)) __tzcnt_u32 (unsigned int __X) @@ -84,6 +100,12 @@ __tzcnt_u32 (unsigned int __X) return __builtin_ctz (__X); } +extern __inline unsigned int __attribute__((__gnu_inline__, __always_inline__, __artificial__)) +_tzcnt_u32 (unsigned int __X) +{ + return __builtin_ctz (__X); +} + #ifdef __x86_64__ extern __inline unsigned long long __attribute__((__gnu_inline__, __always_inline__, __artificial__)) @@ -111,23 +133,47 @@ __blsi_u64 (unsigned long long __X) } extern __inline unsigned long long __attribute__((__gnu_inline__, __always_inline__, __artificial__)) +_blsi_u64 (unsigned long long __X) +{ + return __blsi_u64 (__X); +} + +extern __inline unsigned long long __attribute__((__gnu_inline__, __always_inline__, __artificial__)) __blsmsk_u64 (unsigned long long __X) { return __X ^ (__X - 1); } extern __inline unsigned long long __attribute__((__gnu_inline__, __always_inline__, __artificial__)) +_blsmsk_u64 (unsigned long long __X) +{ + return __blsmsk_u64 (__X); +} + +extern __inline unsigned long long __attribute__((__gnu_inline__, __always_inline__, __artificial__)) __blsr_u64 (unsigned long long __X) { return __X & (__X - 1); } extern __inline unsigned long long __attribute__((__gnu_inline__, __always_inline__, __artificial__)) +_blsr_u64 (unsigned long long __X) +{ + return __blsr_u64 (__X); +} + +extern __inline unsigned long long __attribute__((__gnu_inline__, __always_inline__, __artificial__)) __tzcnt_u64 (unsigned long long __X) { return __builtin_ctzll (__X); } +extern __inline unsigned long long __attribute__((__gnu_inline__, __always_inline__, __artificial__)) +_tzcnt_u64 (unsigned long long __X) +{ + return __builtin_ctzll (__X); +} + #endif /* __x86_64__ */ #ifdef __DISABLE_BMI__ diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c index 46a4d2e528d..3aa2ac4832c 100644 --- a/gcc/config/i386/i386.c +++ b/gcc/config/i386/i386.c @@ -82,6 +82,7 @@ along with GCC; see the file COPYING3. If not see #include "context.h" #include "pass_manager.h" #include "target-globals.h" +#include "tree-vectorizer.h" static rtx legitimize_dllimport_symbol (rtx, bool); static rtx legitimize_pe_coff_extern_decl (rtx, bool); @@ -1739,7 +1740,7 @@ struct processor_costs slm_cost = { 1, /* scalar load_cost. */ 1, /* scalar_store_cost. */ 1, /* vec_stmt_cost. */ - 1, /* vec_to_scalar_cost. */ + 4, /* vec_to_scalar_cost. */ 1, /* scalar_to_vec_cost. */ 1, /* vec_align_load_cost. */ 2, /* vec_unalign_load_cost. */ @@ -1816,7 +1817,7 @@ struct processor_costs intel_cost = { 1, /* scalar load_cost. */ 1, /* scalar_store_cost. */ 1, /* vec_stmt_cost. */ - 1, /* vec_to_scalar_cost. */ + 4, /* vec_to_scalar_cost. */ 1, /* scalar_to_vec_cost. */ 1, /* vec_align_load_cost. */ 2, /* vec_unalign_load_cost. */ @@ -6807,8 +6808,9 @@ classify_argument (enum machine_mode mode, const_tree type, } /* Examine the argument and return set number of register required in each - class. Return 0 iff parameter should be passed in memory. */ -static int + class. Return true iff parameter should be passed in memory. */ + +static bool examine_argument (enum machine_mode mode, const_tree type, int in_return, int *int_nregs, int *sse_nregs) { @@ -6817,8 +6819,9 @@ examine_argument (enum machine_mode mode, const_tree type, int in_return, *int_nregs = 0; *sse_nregs = 0; + if (!n) - return 0; + return true; for (n--; n >= 0; n--) switch (regclass[n]) { @@ -6836,15 +6839,15 @@ examine_argument (enum machine_mode mode, const_tree type, int in_return, break; case X86_64_X87_CLASS: case X86_64_X87UP_CLASS: + case X86_64_COMPLEX_X87_CLASS: if (!in_return) - return 0; + return true; break; - case X86_64_COMPLEX_X87_CLASS: - return in_return ? 2 : 0; case X86_64_MEMORY_CLASS: gcc_unreachable (); } - return 1; + + return false; } /* Construct container for the argument used by GCC interface. See @@ -6874,8 +6877,8 @@ construct_container (enum machine_mode mode, enum machine_mode orig_mode, n = classify_argument (mode, type, regclass, 0); if (!n) return NULL; - if (!examine_argument (mode, type, in_return, &needed_intregs, - &needed_sseregs)) + if (examine_argument (mode, type, in_return, &needed_intregs, + &needed_sseregs)) return NULL; if (needed_intregs > nintregs || needed_sseregs > nsseregs) return NULL; @@ -7194,7 +7197,7 @@ function_arg_advance_64 (CUMULATIVE_ARGS *cum, enum machine_mode mode, || VALID_AVX256_REG_MODE (mode))) return; - if (examine_argument (mode, type, 0, &int_nregs, &sse_nregs) + if (!examine_argument (mode, type, 0, &int_nregs, &sse_nregs) && sse_nregs <= cum->sse_nregs && int_nregs <= cum->nregs) { cum->nregs -= int_nregs; @@ -7989,95 +7992,87 @@ ix86_libcall_value (enum machine_mode mode) /* Return true iff type is returned in memory. */ -static bool ATTRIBUTE_UNUSED -return_in_memory_32 (const_tree type, enum machine_mode mode) +static bool +ix86_return_in_memory (const_tree type, const_tree fntype ATTRIBUTE_UNUSED) { +#ifdef SUBTARGET_RETURN_IN_MEMORY + return SUBTARGET_RETURN_IN_MEMORY (type, fntype); +#else + const enum machine_mode mode = type_natural_mode (type, NULL, true); HOST_WIDE_INT size; - if (mode == BLKmode) - return true; - - size = int_size_in_bytes (type); - - if (MS_AGGREGATE_RETURN && AGGREGATE_TYPE_P (type) && size <= 8) - return false; - - if (VECTOR_MODE_P (mode) || mode == TImode) + if (TARGET_64BIT) { - /* User-created vectors small enough to fit in EAX. */ - if (size < 8) - return false; - - /* MMX/3dNow values are returned in MM0, - except when it doesn't exits or the ABI prescribes otherwise. */ - if (size == 8) - return !TARGET_MMX || TARGET_VECT8_RETURNS; + if (ix86_function_type_abi (fntype) == MS_ABI) + { + size = int_size_in_bytes (type); - /* SSE values are returned in XMM0, except when it doesn't exist. */ - if (size == 16) - return !TARGET_SSE; + /* __m128 is returned in xmm0. */ + if ((!type || VECTOR_INTEGER_TYPE_P (type) + || INTEGRAL_TYPE_P (type) + || VECTOR_FLOAT_TYPE_P (type)) + && (SCALAR_INT_MODE_P (mode) || VECTOR_MODE_P (mode)) + && !COMPLEX_MODE_P (mode) + && (GET_MODE_SIZE (mode) == 16 || size == 16)) + return false; - /* AVX values are returned in YMM0, except when it doesn't exist. */ - if (size == 32) - return !TARGET_AVX; + /* Otherwise, the size must be exactly in [1248]. */ + return size != 1 && size != 2 && size != 4 && size != 8; + } + else + { + int needed_intregs, needed_sseregs; - /* AVX512F values are returned in ZMM0, except when it doesn't exist. */ - if (size == 64) - return !TARGET_AVX512F; + return examine_argument (mode, type, 1, + &needed_intregs, &needed_sseregs); + } } + else + { + if (mode == BLKmode) + return true; - if (mode == XFmode) - return false; + size = int_size_in_bytes (type); - if (size > 12) - return true; + if (MS_AGGREGATE_RETURN && AGGREGATE_TYPE_P (type) && size <= 8) + return false; - /* OImode shouldn't be used directly. */ - gcc_assert (mode != OImode); + if (VECTOR_MODE_P (mode) || mode == TImode) + { + /* User-created vectors small enough to fit in EAX. */ + if (size < 8) + return false; - return false; -} + /* Unless ABI prescibes otherwise, + MMX/3dNow values are returned in MM0 if available. */ + + if (size == 8) + return TARGET_VECT8_RETURNS || !TARGET_MMX; -static bool ATTRIBUTE_UNUSED -return_in_memory_64 (const_tree type, enum machine_mode mode) -{ - int needed_intregs, needed_sseregs; - return !examine_argument (mode, type, 1, &needed_intregs, &needed_sseregs); -} + /* SSE values are returned in XMM0 if available. */ + if (size == 16) + return !TARGET_SSE; -static bool ATTRIBUTE_UNUSED -return_in_memory_ms_64 (const_tree type, enum machine_mode mode) -{ - HOST_WIDE_INT size = int_size_in_bytes (type); + /* AVX values are returned in YMM0 if available. */ + if (size == 32) + return !TARGET_AVX; - /* __m128 is returned in xmm0. */ - if ((!type || VECTOR_INTEGER_TYPE_P (type) || INTEGRAL_TYPE_P (type) - || VECTOR_FLOAT_TYPE_P (type)) - && (SCALAR_INT_MODE_P (mode) || VECTOR_MODE_P (mode)) - && !COMPLEX_MODE_P (mode) && (GET_MODE_SIZE (mode) == 16 || size == 16)) - return false; + /* AVX512F values are returned in ZMM0 if available. */ + if (size == 64) + return !TARGET_AVX512F; + } - /* Otherwise, the size must be exactly in [1248]. */ - return size != 1 && size != 2 && size != 4 && size != 8; -} + if (mode == XFmode) + return false; -static bool -ix86_return_in_memory (const_tree type, const_tree fntype ATTRIBUTE_UNUSED) -{ -#ifdef SUBTARGET_RETURN_IN_MEMORY - return SUBTARGET_RETURN_IN_MEMORY (type, fntype); -#else - const enum machine_mode mode = type_natural_mode (type, NULL, true); + if (size > 12) + return true; - if (TARGET_64BIT) - { - if (ix86_function_type_abi (fntype) == MS_ABI) - return return_in_memory_ms_64 (type, mode); - else - return return_in_memory_64 (type, mode); + /* OImode shouldn't be used directly. */ + gcc_assert (mode != OImode); + + return false; } - else - return return_in_memory_32 (type, mode); #endif } @@ -44031,7 +44026,7 @@ expand_vec_perm_even_odd_1 (struct expand_vec_perm_d *d, unsigned odd) gcc_unreachable (); case V8HImode: - if (TARGET_SSSE3) + if (TARGET_SSSE3 && !TARGET_SLOW_PSHUFB) return expand_vec_perm_pshufb2 (d); else { @@ -44054,7 +44049,7 @@ expand_vec_perm_even_odd_1 (struct expand_vec_perm_d *d, unsigned odd) break; case V16QImode: - if (TARGET_SSSE3) + if (TARGET_SSSE3 && !TARGET_SLOW_PSHUFB) return expand_vec_perm_pshufb2 (d); else { @@ -46334,6 +46329,18 @@ ix86_add_stmt_cost (void *data, int count, enum vect_cost_for_stmt kind, count *= 50; /* FIXME. */ retval = (unsigned) (count * stmt_cost); + + /* We need to multiply all vector stmt cost by 1.7 (estimated cost) + for Silvermont as it has out of order integer pipeline and can execute + 2 scalar instruction per tick, but has in order SIMD pipeline. */ + if (TARGET_SILVERMONT || TARGET_INTEL) + if (stmt_info && stmt_info->stmt) + { + tree lhs_op = gimple_get_lhs (stmt_info->stmt); + if (lhs_op && TREE_CODE (TREE_TYPE (lhs_op)) == INTEGER_TYPE) + retval = (retval * 17) / 10; + } + cost[where] += retval; return retval; diff --git a/gcc/config/i386/i386.h b/gcc/config/i386/i386.h index 51659deb309..1a884d86c35 100644 --- a/gcc/config/i386/i386.h +++ b/gcc/config/i386/i386.h @@ -425,6 +425,8 @@ extern unsigned char ix86_tune_features[X86_TUNE_LAST]; ix86_tune_features[X86_TUNE_USE_VECTOR_FP_CONVERTS] #define TARGET_USE_VECTOR_CONVERTS \ ix86_tune_features[X86_TUNE_USE_VECTOR_CONVERTS] +#define TARGET_SLOW_PSHUFB \ + ix86_tune_features[X86_TUNE_SLOW_PSHUFB] #define TARGET_FUSE_CMP_AND_BRANCH_32 \ ix86_tune_features[X86_TUNE_FUSE_CMP_AND_BRANCH_32] #define TARGET_FUSE_CMP_AND_BRANCH_64 \ diff --git a/gcc/config/i386/x86-tune.def b/gcc/config/i386/x86-tune.def index 8399102671c..9b0ff360ab3 100644 --- a/gcc/config/i386/x86-tune.def +++ b/gcc/config/i386/x86-tune.def @@ -386,6 +386,10 @@ DEF_TUNE (X86_TUNE_USE_VECTOR_FP_CONVERTS, "use_vector_fp_converts", from integer to FP. */ DEF_TUNE (X86_TUNE_USE_VECTOR_CONVERTS, "use_vector_converts", m_AMDFAM10) +/* X86_TUNE_SLOW_SHUFB: Indicates tunings with slow pshufb instruction. */ +DEF_TUNE (X86_TUNE_SLOW_PSHUFB, "slow_pshufb", + m_BONNELL | m_SILVERMONT | m_INTEL) + /*****************************************************************************/ /* AVX instruction selection tuning (some of SSE flags affects AVX, too) */ /*****************************************************************************/ diff --git a/gcc/config/mips/constraints.md b/gcc/config/mips/constraints.md index 49e48954f51..f6834fd1e94 100644 --- a/gcc/config/mips/constraints.md +++ b/gcc/config/mips/constraints.md @@ -92,6 +92,9 @@ ;; but the DSP version allows any accumulator target. (define_register_constraint "ka" "ISA_HAS_DSP_MULT ? ACC_REGS : MD_REGS") +(define_register_constraint "kb" "M16_STORE_REGS" + "@internal") + (define_constraint "kf" "@internal" (match_operand 0 "force_to_mem_operand")) diff --git a/gcc/config/mips/mips.c b/gcc/config/mips/mips.c index 143169bc150..83fe55b6661 100644 --- a/gcc/config/mips/mips.c +++ b/gcc/config/mips/mips.c @@ -648,14 +648,15 @@ static mips_one_only_stub *mips16_set_fcsr_stub; /* Index R is the smallest register class that contains register R. */ const enum reg_class mips_regno_to_class[FIRST_PSEUDO_REGISTER] = { - LEA_REGS, LEA_REGS, M16_REGS, V1_REG, - M16_REGS, M16_REGS, M16_REGS, M16_REGS, - LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS, - LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS, - M16_REGS, M16_REGS, LEA_REGS, LEA_REGS, - LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS, - T_REG, PIC_FN_ADDR_REG, LEA_REGS, LEA_REGS, - LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS, + LEA_REGS, LEA_REGS, M16_STORE_REGS, V1_REG, + M16_STORE_REGS, M16_STORE_REGS, M16_STORE_REGS, M16_STORE_REGS, + LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS, + LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS, + M16_REGS, M16_STORE_REGS, LEA_REGS, LEA_REGS, + LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS, + T_REG, PIC_FN_ADDR_REG, LEA_REGS, LEA_REGS, + LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS, + FP_REGS, FP_REGS, FP_REGS, FP_REGS, FP_REGS, FP_REGS, FP_REGS, FP_REGS, FP_REGS, FP_REGS, FP_REGS, FP_REGS, diff --git a/gcc/config/mips/mips.h b/gcc/config/mips/mips.h index a786d4ce303..b25865b6dfb 100644 --- a/gcc/config/mips/mips.h +++ b/gcc/config/mips/mips.h @@ -1870,6 +1870,7 @@ struct mips_cpu_info { enum reg_class { NO_REGS, /* no registers in set */ + M16_STORE_REGS, /* microMIPS store registers */ M16_REGS, /* mips16 directly accessible registers */ T_REG, /* mips16 T register ($24) */ M16_T_REGS, /* mips16 registers plus T register */ @@ -1907,6 +1908,7 @@ enum reg_class #define REG_CLASS_NAMES \ { \ "NO_REGS", \ + "M16_STORE_REGS", \ "M16_REGS", \ "T_REG", \ "M16_T_REGS", \ @@ -1947,6 +1949,7 @@ enum reg_class #define REG_CLASS_CONTENTS \ { \ { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* NO_REGS */ \ + { 0x000200fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* M16_STORE_REGS */ \ { 0x000300fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* M16_REGS */ \ { 0x01000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* T_REG */ \ { 0x010300fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* M16_T_REGS */ \ diff --git a/gcc/config/mips/mips.md b/gcc/config/mips/mips.md index 1e3e9e65957..f914ab67d8a 100644 --- a/gcc/config/mips/mips.md +++ b/gcc/config/mips/mips.md @@ -4437,7 +4437,7 @@ (define_insn "*mov<mode>_internal" [(set (match_operand:IMOVE32 0 "nonimmediate_operand" "=d,!u,!u,d,e,!u,!ks,d,ZS,ZT,m,*f,*f,*d,*m,*d,*z,*a,*d,*B*C*D,*B*C*D,*d,*m") - (match_operand:IMOVE32 1 "move_operand" "d,J,Udb7,Yd,Yf,ZT,ZS,m,!ks,!u,dJ,*d*J,*m,*f,*f,*z,*d,*J*d,*a,*d,*m,*B*C*D,*B*C*D"))] + (match_operand:IMOVE32 1 "move_operand" "d,J,Udb7,Yd,Yf,ZT,ZS,m,!ks,!kbJ,dJ,*d*J,*m,*f,*f,*z,*d,*J*d,*a,*d,*m,*B*C*D,*B*C*D"))] "!TARGET_MIPS16 && (register_operand (operands[0], <MODE>mode) || reg_or_0_operand (operands[1], <MODE>mode))" @@ -4578,7 +4578,7 @@ (define_insn "*movhi_internal" [(set (match_operand:HI 0 "nonimmediate_operand" "=d,!u,d,!u,d,ZU,m,*a,*d") - (match_operand:HI 1 "move_operand" "d,J,I,ZU,m,!u,dJ,*d*J,*a"))] + (match_operand:HI 1 "move_operand" "d,J,I,ZU,m,!kbJ,dJ,*d*J,*a"))] "!TARGET_MIPS16 && (register_operand (operands[0], HImode) || reg_or_0_operand (operands[1], HImode))" @@ -4654,7 +4654,7 @@ (define_insn "*movqi_internal" [(set (match_operand:QI 0 "nonimmediate_operand" "=d,!u,d,!u,d,ZV,m,*a,*d") - (match_operand:QI 1 "move_operand" "d,J,I,ZW,m,!u,dJ,*d*J,*a"))] + (match_operand:QI 1 "move_operand" "d,J,I,ZW,m,!kbJ,dJ,*d*J,*a"))] "!TARGET_MIPS16 && (register_operand (operands[0], QImode) || reg_or_0_operand (operands[1], QImode))" diff --git a/gcc/config/moxie/moxie.h b/gcc/config/moxie/moxie.h index 5379a431140..3a01dbab46d 100644 --- a/gcc/config/moxie/moxie.h +++ b/gcc/config/moxie/moxie.h @@ -59,7 +59,7 @@ #define DOUBLE_TYPE_SIZE 64 #define LONG_DOUBLE_TYPE_SIZE 64 -#define DEFAULT_SIGNED_CHAR 1 +#define DEFAULT_SIGNED_CHAR 0 #undef SIZE_TYPE #define SIZE_TYPE "unsigned int" @@ -68,7 +68,7 @@ #define PTRDIFF_TYPE "int" #undef WCHAR_TYPE -#define WCHAR_TYPE "long int" +#define WCHAR_TYPE "unsigned int" #undef WCHAR_TYPE_SIZE #define WCHAR_TYPE_SIZE BITS_PER_WORD diff --git a/gcc/config/moxie/moxie.md b/gcc/config/moxie/moxie.md index 713f9b65dcf..793cac3f8ca 100644 --- a/gcc/config/moxie/moxie.md +++ b/gcc/config/moxie/moxie.md @@ -239,6 +239,56 @@ ldo.l %0, %1" [(set_attr "length" "2,2,6,2,6,2,6,6,6")]) +(define_insn_and_split "zero_extendqisi2" + [(set (match_operand:SI 0 "register_operand" "=r,r,r,r") + (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "0,W,A,B")))] + "" + "@ + ; + ld.b %0, %1 + lda.b %0, %1 + ldo.b %0, %1" + "reload_completed" + [(set (match_dup 2) (match_dup 1)) + (set (match_dup 0) (zero_extend:SI (match_dup 2)))] +{ + operands[2] = gen_lowpart (QImode, operands[0]); +} + [(set_attr "length" "0,2,6,6")]) + +(define_insn_and_split "zero_extendhisi2" + [(set (match_operand:SI 0 "register_operand" "=r,r,r,r") + (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "0,W,A,B")))] + "" + "@ + ; + ld.s %0, %1 + lda.s %0, %1 + ldo.s %0, %1" + "reload_completed" + [(set (match_dup 2) (match_dup 1)) + (set (match_dup 0) (zero_extend:SI (match_dup 2)))] +{ + operands[2] = gen_lowpart (HImode, operands[0]); +} + [(set_attr "length" "0,2,6,6")]) + +(define_insn "extendqisi2" + [(set (match_operand:SI 0 "register_operand" "=r") + (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "r")))] + "" + "@ + sex.b %0, %1" + [(set_attr "length" "2")]) + +(define_insn "extendhisi2" + [(set (match_operand:SI 0 "register_operand" "=r") + (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "r")))] + "" + "@ + sex.s %0, %1" + [(set_attr "length" "2")]) + (define_expand "movqi" [(set (match_operand:QI 0 "general_operand" "") (match_operand:QI 1 "general_operand" ""))] diff --git a/gcc/config/pa/pa.c b/gcc/config/pa/pa.c index fb698d20d80..871e4e5c6e8 100644 --- a/gcc/config/pa/pa.c +++ b/gcc/config/pa/pa.c @@ -4187,13 +4187,17 @@ pa_output_function_epilogue (FILE *file, HOST_WIDE_INT size ATTRIBUTE_UNUSED) if (TARGET_SOM && TARGET_GAS) { - /* We done with this subspace except possibly for some additional + /* We are done with this subspace except possibly for some additional debug information. Forget that we are in this subspace to ensure that the next function is output in its own subspace. */ in_section = NULL; cfun->machine->in_nsubspa = 2; } + /* Thunks do their own accounting. */ + if (cfun->is_thunk) + return; + if (INSN_ADDRESSES_SET_P ()) { insn = get_last_nonnote_insn (); @@ -8259,8 +8263,7 @@ pa_asm_output_mi_thunk (FILE *file, tree thunk_fndecl, HOST_WIDE_INT delta, xoperands[1] = XEXP (DECL_RTL (thunk_fndecl), 0); xoperands[2] = GEN_INT (delta); - ASM_OUTPUT_LABEL (file, XSTR (xoperands[1], 0)); - fprintf (file, "\t.PROC\n\t.CALLINFO FRAME=0,NO_CALLS\n\t.ENTRY\n"); + final_start_function (emit_barrier (), file, 1); /* Output the thunk. We know that the function is in the same translation unit (i.e., the same space) as the thunk, and that @@ -8466,16 +8469,7 @@ pa_asm_output_mi_thunk (FILE *file, tree thunk_fndecl, HOST_WIDE_INT delta, } } - fprintf (file, "\t.EXIT\n\t.PROCEND\n"); - - if (TARGET_SOM && TARGET_GAS) - { - /* We done with this subspace except possibly for some additional - debug information. Forget that we are in this subspace to ensure - that the next function is output in its own subspace. */ - in_section = NULL; - cfun->machine->in_nsubspa = 2; - } + final_end_function (); if (TARGET_SOM && flag_pic && TREE_PUBLIC (function)) { diff --git a/gcc/config/rl78/rl78-expand.md b/gcc/config/rl78/rl78-expand.md index f794d7cb13d..f61e444b5da 100644 --- a/gcc/config/rl78/rl78-expand.md +++ b/gcc/config/rl78/rl78-expand.md @@ -30,18 +30,23 @@ if (rl78_far_p (operands[0]) && rl78_far_p (operands[1])) operands[1] = copy_to_mode_reg (QImode, operands[1]); - /* FIXME: Not sure how GCC can generate (SUBREG (SYMBOL_REF)), - but it does. Since this makes no sense, reject it here. */ + /* GCC can generate (SUBREG (SYMBOL_REF)) when it has to store a symbol + into a bitfield, or a packed ordinary field. We can handle this + provided that the destination is a register. If not, then load the + source into a register first. */ if (GET_CODE (operands[1]) == SUBREG - && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF) - FAIL; + && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF + && ! REG_P (operands[0])) + operands[1] = copy_to_mode_reg (QImode, operands[1]); + /* Similarly for (SUBREG (CONST (PLUS (SYMBOL_REF)))). cf. g++.dg/abi/packed.C. */ if (GET_CODE (operands[1]) == SUBREG && GET_CODE (XEXP (operands[1], 0)) == CONST && GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == PLUS - && GET_CODE (XEXP (XEXP (XEXP (operands[1], 0), 0), 0)) == SYMBOL_REF) - FAIL; + && GET_CODE (XEXP (XEXP (XEXP (operands[1], 0), 0), 0)) == SYMBOL_REF + && ! REG_P (operands[0])) + operands[1] = copy_to_mode_reg (QImode, operands[1]); if (CONST_INT_P (operands[1]) && ! IN_RANGE (INTVAL (operands[1]), (-1 << 8) + 1, (1 << 8) - 1)) FAIL; diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c index 6724dcbe465..51283aae5f2 100644 --- a/gcc/config/rs6000/rs6000.c +++ b/gcc/config/rs6000/rs6000.c @@ -1752,9 +1752,6 @@ rs6000_hard_regno_mode_ok (int regno, enum machine_mode mode) modes and DImode. */ if (FP_REGNO_P (regno)) { - if (TARGET_SOFT_FLOAT || !TARGET_FPRS) - return 0; - if (SCALAR_FLOAT_MODE_P (mode) && (mode != TDmode || (regno % 2) == 0) && FP_REGNO_P (last_regno)) @@ -1783,6 +1780,10 @@ rs6000_hard_regno_mode_ok (int regno, enum machine_mode mode) return (VECTOR_MEM_ALTIVEC_OR_VSX_P (mode) || mode == V1TImode); + /* ...but GPRs can hold SIMD data on the SPE in one register. */ + if (SPE_SIMD_REGNO_P (regno) && TARGET_SPE && SPE_VECTOR_MODE (mode)) + return 1; + /* We cannot put non-VSX TImode or PTImode anywhere except general register and it must be able to fit within the register set. */ @@ -5638,11 +5639,15 @@ rs6000_expand_vector_set (rtx target, rtx val, int elt) UNSPEC_VPERM); else { - /* Invert selector. */ + /* Invert selector. We prefer to generate VNAND on P8 so + that future fusion opportunities can kick in, but must + generate VNOR elsewhere. */ rtx notx = gen_rtx_NOT (V16QImode, force_reg (V16QImode, x)); - rtx andx = gen_rtx_AND (V16QImode, notx, notx); + rtx iorx = (TARGET_P8_VECTOR + ? gen_rtx_IOR (V16QImode, notx, notx) + : gen_rtx_AND (V16QImode, notx, notx)); rtx tmp = gen_reg_rtx (V16QImode); - emit_move_insn (tmp, andx); + emit_insn (gen_rtx_SET (VOIDmode, tmp, iorx)); /* Permute with operands reversed and adjusted selector. */ x = gen_rtx_UNSPEC (mode, gen_rtvec (3, reg, target, tmp), @@ -30214,12 +30219,12 @@ altivec_expand_vec_perm_const_le (rtx operands[4]) /* Similarly to altivec_expand_vec_perm_const_le, we must adjust the permute control vector. But here it's not a constant, so we must - generate a vector NOR to do the adjustment. */ + generate a vector NAND or NOR to do the adjustment. */ void altivec_expand_vec_perm_le (rtx operands[4]) { - rtx notx, andx, unspec; + rtx notx, iorx, unspec; rtx target = operands[0]; rtx op0 = operands[1]; rtx op1 = operands[2]; @@ -30238,10 +30243,13 @@ altivec_expand_vec_perm_le (rtx operands[4]) if (!REG_P (target)) tmp = gen_reg_rtx (mode); - /* Invert the selector with a VNOR. */ + /* Invert the selector with a VNAND if available, else a VNOR. + The VNAND is preferred for future fusion opportunities. */ notx = gen_rtx_NOT (V16QImode, sel); - andx = gen_rtx_AND (V16QImode, notx, notx); - emit_move_insn (norreg, andx); + iorx = (TARGET_P8_VECTOR + ? gen_rtx_IOR (V16QImode, notx, notx) + : gen_rtx_AND (V16QImode, notx, notx)); + emit_insn (gen_rtx_SET (VOIDmode, norreg, iorx)); /* Permute with operands reversed and adjusted selector. */ unspec = gen_rtx_UNSPEC (mode, gen_rtvec (3, op1, op0, norreg), diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index aee6f4fce75..6fab081c36a 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -9394,9 +9394,8 @@ [(set (match_operand:FMOVE64 0 "nonimmediate_operand" "=Y,r,r,r,r,r") (match_operand:FMOVE64 1 "input_operand" "r,Y,r,G,H,F"))] "! TARGET_POWERPC64 - && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) - || TARGET_SOFT_FLOAT - || (<MODE>mode == DDmode && TARGET_E500_DOUBLE)) + && ((TARGET_FPRS && TARGET_SINGLE_FLOAT) + || TARGET_SOFT_FLOAT || TARGET_E500_SINGLE) && (gpc_reg_operand (operands[0], <MODE>mode) || gpc_reg_operand (operands[1], <MODE>mode))" "#" @@ -10029,13 +10028,16 @@ rtx op0 = operands[0]; rtx op1 = operands[1]; rtx op2 = operands[2]; - rtx op0_di = simplify_gen_subreg (DImode, op0, SFmode, 0); + /* Also use the destination register to hold the unconverted DImode value. + This is conceptually a separate value from OP0, so we use gen_rtx_REG + rather than simplify_gen_subreg. */ + rtx op0_di = gen_rtx_REG (DImode, REGNO (op0)); rtx op1_di = simplify_gen_subreg (DImode, op1, SFmode, 0); /* Move SF value to upper 32-bits for xscvspdpn. */ emit_insn (gen_ashldi3 (op2, op1_di, GEN_INT (32))); emit_move_insn (op0_di, op2); - emit_insn (gen_vsx_xscvspdpn_directmove (op0, op0)); + emit_insn (gen_vsx_xscvspdpn_directmove (op0, op0_di)); DONE; } [(set_attr "length" "8") diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md index a06cdd507e4..d83cdc3df34 100644 --- a/gcc/config/rs6000/vsx.md +++ b/gcc/config/rs6000/vsx.md @@ -1223,7 +1223,7 @@ ;; Used by direct move to move a SFmode value from GPR to VSX register (define_insn "vsx_xscvspdpn_directmove" [(set (match_operand:SF 0 "vsx_register_operand" "=wa") - (unspec:SF [(match_operand:SF 1 "vsx_register_operand" "wa")] + (unspec:SF [(match_operand:DI 1 "vsx_register_operand" "wa")] UNSPEC_VSX_CVSPDPN))] "TARGET_XSCVSPDPN" "xscvspdpn %x0,%x1" diff --git a/gcc/config/s390/s390.c b/gcc/config/s390/s390.c index bdb577c9748..aac8de848ac 100644 --- a/gcc/config/s390/s390.c +++ b/gcc/config/s390/s390.c @@ -4613,7 +4613,7 @@ s390_expand_insv (rtx dest, rtx op1, rtx op2, rtx src) int smode_bsize, mode_bsize; rtx op, clobber; - if (bitsize + bitpos > GET_MODE_SIZE (mode)) + if (bitsize + bitpos > GET_MODE_BITSIZE (mode)) return false; /* Generate INSERT IMMEDIATE (IILL et al). */ diff --git a/gcc/config/s390/s390.md b/gcc/config/s390/s390.md index 7d9d1ad7ecd..b17c1fac875 100644 --- a/gcc/config/s390/s390.md +++ b/gcc/config/s390/s390.md @@ -7001,6 +7001,21 @@ "" "s390_expand_logical_operator (XOR, <MODE>mode, operands); DONE;") +; Combine replaces (xor (x) (const_int -1)) with (not (x)) when doing +; simplifications. So its better to have something matching. +(define_split + [(set (match_operand:INT 0 "nonimmediate_operand" "") + (not:INT (match_operand:INT 1 "nonimmediate_operand" "")))] + "" + [(parallel + [(set (match_dup 0) (xor:INT (match_dup 1) (match_dup 2))) + (clobber (reg:CC CC_REGNUM))])] +{ + operands[2] = constm1_rtx; + if (!s390_logical_operator_ok_p (operands)) + FAIL; +}) + ; ; xordi3 instruction pattern(s). ; diff --git a/gcc/config/sh/sh-mem.cc b/gcc/config/sh/sh-mem.cc index 45af23acb48..1b84f9b63b7 100644 --- a/gcc/config/sh/sh-mem.cc +++ b/gcc/config/sh/sh-mem.cc @@ -586,9 +586,35 @@ sh_expand_strlen (rtx *operands) emit_move_insn (current_addr, plus_constant (Pmode, current_addr, -4)); - /* start byte loop. */ addr1 = adjust_address (addr1, QImode, 0); + /* unroll remaining bytes. */ + emit_insn (gen_extendqisi2 (tmp1, addr1)); + emit_insn (gen_cmpeqsi_t (tmp1, const0_rtx)); + jump = emit_jump_insn (gen_branch_true (L_return)); + add_int_reg_note (jump, REG_BR_PROB, prob_likely); + + emit_move_insn (current_addr, plus_constant (Pmode, current_addr, 1)); + + emit_insn (gen_extendqisi2 (tmp1, addr1)); + emit_insn (gen_cmpeqsi_t (tmp1, const0_rtx)); + jump = emit_jump_insn (gen_branch_true (L_return)); + add_int_reg_note (jump, REG_BR_PROB, prob_likely); + + emit_move_insn (current_addr, plus_constant (Pmode, current_addr, 1)); + + emit_insn (gen_extendqisi2 (tmp1, addr1)); + emit_insn (gen_cmpeqsi_t (tmp1, const0_rtx)); + jump = emit_jump_insn (gen_branch_true (L_return)); + add_int_reg_note (jump, REG_BR_PROB, prob_likely); + + emit_move_insn (current_addr, plus_constant (Pmode, current_addr, 1)); + + emit_insn (gen_extendqisi2 (tmp1, addr1)); + jump = emit_jump_insn (gen_jump_compact (L_return)); + emit_barrier_after (jump); + + /* start byte loop. */ emit_label (L_loop_byte); emit_insn (gen_extendqisi2 (tmp1, addr1)); @@ -600,11 +626,114 @@ sh_expand_strlen (rtx *operands) /* end loop. */ - emit_label (L_return); - emit_insn (gen_addsi3 (start_addr, start_addr, GEN_INT (1))); + emit_label (L_return); + emit_insn (gen_subsi3 (operands[0], current_addr, start_addr)); return true; } + +/* Emit code to perform a memset + + OPERANDS[0] is the destination. + OPERANDS[1] is the size; + OPERANDS[2] is the char to search. + OPERANDS[3] is the alignment. */ +void +sh_expand_setmem (rtx *operands) +{ + rtx L_loop_byte = gen_label_rtx (); + rtx L_loop_word = gen_label_rtx (); + rtx L_return = gen_label_rtx (); + rtx jump; + rtx dest = copy_rtx (operands[0]); + rtx dest_addr = copy_addr_to_reg (XEXP (dest, 0)); + rtx val = force_reg (SImode, operands[2]); + int align = INTVAL (operands[3]); + int count = 0; + rtx len = force_reg (SImode, operands[1]); + + if (! CONST_INT_P (operands[1])) + return; + + count = INTVAL (operands[1]); + + if (CONST_INT_P (operands[2]) + && (INTVAL (operands[2]) == 0 || INTVAL (operands[2]) == -1) && count > 8) + { + rtx lenw = gen_reg_rtx (SImode); + + if (align < 4) + { + emit_insn (gen_tstsi_t (GEN_INT (3), dest_addr)); + jump = emit_jump_insn (gen_branch_false (L_loop_byte)); + add_int_reg_note (jump, REG_BR_PROB, prob_likely); + } + + /* word count. Do we have iterations ? */ + emit_insn (gen_lshrsi3 (lenw, len, GEN_INT (2))); + + dest = adjust_automodify_address (dest, SImode, dest_addr, 0); + + /* start loop. */ + emit_label (L_loop_word); + + if (TARGET_SH2) + emit_insn (gen_dect (lenw, lenw)); + else + { + emit_insn (gen_addsi3 (lenw, lenw, GEN_INT (-1))); + emit_insn (gen_tstsi_t (lenw, lenw)); + } + + emit_move_insn (dest, val); + emit_move_insn (dest_addr, plus_constant (Pmode, dest_addr, + GET_MODE_SIZE (SImode))); + + + jump = emit_jump_insn (gen_branch_false (L_loop_word)); + add_int_reg_note (jump, REG_BR_PROB, prob_likely); + count = count % 4; + + dest = adjust_address (dest, QImode, 0); + + val = gen_lowpart (QImode, val); + + while (count--) + { + emit_move_insn (dest, val); + emit_move_insn (dest_addr, plus_constant (Pmode, dest_addr, + GET_MODE_SIZE (QImode))); + } + + jump = emit_jump_insn (gen_jump_compact (L_return)); + emit_barrier_after (jump); + } + + dest = adjust_automodify_address (dest, QImode, dest_addr, 0); + + /* start loop. */ + emit_label (L_loop_byte); + + if (TARGET_SH2) + emit_insn (gen_dect (len, len)); + else + { + emit_insn (gen_addsi3 (len, len, GEN_INT (-1))); + emit_insn (gen_tstsi_t (len, len)); + } + + val = gen_lowpart (QImode, val); + emit_move_insn (dest, val); + emit_move_insn (dest_addr, plus_constant (Pmode, dest_addr, + GET_MODE_SIZE (QImode))); + + jump = emit_jump_insn (gen_branch_false (L_loop_byte)); + add_int_reg_note (jump, REG_BR_PROB, prob_likely); + + emit_label (L_return); + + return; +} diff --git a/gcc/config/sh/sh-protos.h b/gcc/config/sh/sh-protos.h index defc76a3243..685cd23207c 100644 --- a/gcc/config/sh/sh-protos.h +++ b/gcc/config/sh/sh-protos.h @@ -119,6 +119,7 @@ extern void prepare_move_operands (rtx[], enum machine_mode mode); extern bool sh_expand_cmpstr (rtx *); extern bool sh_expand_cmpnstr (rtx *); extern bool sh_expand_strlen (rtx *); +extern void sh_expand_setmem (rtx *); extern enum rtx_code prepare_cbranch_operands (rtx *, enum machine_mode mode, enum rtx_code comparison); extern void expand_cbranchsi4 (rtx *operands, enum rtx_code comparison, int); diff --git a/gcc/config/sh/sh.h b/gcc/config/sh/sh.h index 8819300116e..8c30e5c14bd 100644 --- a/gcc/config/sh/sh.h +++ b/gcc/config/sh/sh.h @@ -1594,6 +1594,11 @@ struct sh_args { #define SET_BY_PIECES_P(SIZE, ALIGN) STORE_BY_PIECES_P(SIZE, ALIGN) +/* If a memory clear move would take CLEAR_RATIO or more simple + move-instruction pairs, we will do a setmem instead. */ + +#define CLEAR_RATIO(speed) ((speed) ? 15 : 3) + /* Macros to check register numbers against specific register classes. */ /* These assume that REGNO is a hard or pseudo reg number. diff --git a/gcc/config/sh/sh.md b/gcc/config/sh/sh.md index ab1f0a51c22..9035bfcb1a8 100644 --- a/gcc/config/sh/sh.md +++ b/gcc/config/sh/sh.md @@ -12089,6 +12089,20 @@ label: FAIL; }) +(define_expand "setmemqi" + [(parallel [(set (match_operand:BLK 0 "memory_operand") + (match_operand 2 "const_int_operand")) + (use (match_operand:QI 1 "const_int_operand")) + (use (match_operand:QI 3 "const_int_operand"))])] + "TARGET_SH1 && optimize" + { + if (optimize_insn_for_size_p ()) + FAIL; + + sh_expand_setmem (operands); + DONE; + }) + ;; ------------------------------------------------------------------------- ;; Floating point instructions. diff --git a/gcc/config/spu/spu.c b/gcc/config/spu/spu.c index 302d7e06b6d..88e3f5e5909 100644 --- a/gcc/config/spu/spu.c +++ b/gcc/config/spu/spu.c @@ -2064,7 +2064,7 @@ pad_bb(void) } hbr_insn = insn; } - if (INSN_CODE (insn) == CODE_FOR_blockage) + if (INSN_CODE (insn) == CODE_FOR_blockage && next_insn) { if (GET_MODE (insn) == TImode) PUT_MODE (next_insn, TImode); diff --git a/gcc/config/spu/spu.md b/gcc/config/spu/spu.md index 228b2285969..3ac4bfc0b7c 100644 --- a/gcc/config/spu/spu.md +++ b/gcc/config/spu/spu.md @@ -2851,7 +2851,13 @@ (match_operand:SI 2 "const_int_operand" "")) (match_operand 3 "nonmemory_operand" ""))] "" - { spu_expand_insv(operands); DONE; }) + { + if (INTVAL (operands[1]) + INTVAL (operands[2]) + > GET_MODE_BITSIZE (GET_MODE (operands[0]))) + FAIL; + spu_expand_insv(operands); + DONE; + }) ;; Simplify a number of patterns that get generated by extv, extzv, ;; insv, and loads. |