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Diffstat (limited to 'gcc/doc/invoke.texi')
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1 files changed, 147 insertions, 0 deletions
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index 0588c1a5b8f..cab5005f752 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -588,6 +588,15 @@ in the following sections. -msmall-exec -mno-small-exec -mmvcle -mno-mvcle @gol -m64 -m31 -mdebug -mno-debug} +@emph{CRIS Options} +@gccoptlist{ +-mcpu=@var{cpu} -march=@var{cpu} -mtune=@var{cpu} @gol +-mmax-stack-frame=@var{n} -melinux-stacksize=@var{n} @gol +-metrax4 -metrax100 -mpdebug -mcc-init -mno-side-effects @gol +-mstack-align -mdata-align -mconst-align @gol +-m32-bit -m16-bit -m8-bit -mno-prologue-epilogue -mno-gotplt @gol +-melf -maout -melinux -mlinux -sim -sim2} + @item Code Generation Options @xref{Code Gen Options,,Options for Code Generation Conventions}. @gccoptlist{ @@ -5096,6 +5105,7 @@ that macro, which enables you to change the defaults. * IA-64 Options:: * D30V Options:: * S/390 and zSeries Options:: +* CRIS Options:: @end menu @node M680x0 Options @@ -9464,6 +9474,143 @@ The default is to not print debug information. @end table +@node CRIS Options +@subsection CRIS Options +@cindex CRIS Options + +These options are defined specifically for the CRIS ports. + +@table @gcctabopt +@item -march=@var{architecture-type} +@itemx -mcpu=@var{architecture-type} +@opindex march +@opindex mcpu +Generate code for the specified architecture. The choices for +@var{architecture-type} are @samp{v3}, @samp{v8} and @samp{v10} for +respectively ETRAX@w{ }4, ETRAX@w{ }100, and ETRAX@w{ }100@w{ }LX. +Default is @samp{v0} except for cris-axis-linux-gnu, where the default is +@samp{v10}. + +@item -mtune=@var{architecture-type} +@opindex mtune +Tune to @var{architecture-type} everything applicable about the generated +code, except for the ABI and the set of available instructions. The +choices for @var{architecture-type} are the same as for +@option{-march=@var{architecture-type}}. + +@item -mmax-stack-frame=@var{n} +@opindex mmax-stack-frame +Warn when the stack frame of a function exceeds @var{n} bytes. + +@item -melinux-stacksize=@var{n} +@opindex melinux-stacksize +Only available with the @samp{cris-axis-aout} target. Arranges for +indications in the program to the kernel loader that the stack of the +program should be set to @var{n} bytes. + +@item -metrax4 +@itemx -metrax100 +@opindex metrax4 +@opindex metrax100 +The options @option{-metrax4} and @option{-metrax100} are synonyms for +@option{-march=v3} and @option{-march=v8} respectively. + +@item -mpdebug +@opindex mpdebug +Enable CRIS-specific verbose debug-related information in the assembly +code. This option also has the effect to turn off the @samp{#NO_APP} +formatted-code indicator to the assembler at the beginning of the +assembly file. + +@item -mcc-init +@opindex mcc-init +Do not use condition-code results from previous instruction; always emit +compare and test instructions before use of condition codes. + +@item -mno-side-effects +@opindex mno-side-effects +Do not emit instructions with side-effects in addressing modes other than +post-increment. + +@item -mstack-align +@itemx -mno-stack-align +@itemx -mdata-align +@itemx -mno-data-align +@itemx -mconst-align +@itemx -mno-const-align +@opindex mstack-align +@opindex mno-stack-align +@opindex mdata-align +@opindex mno-data-align +@opindex mconst-align +@opindex mno-const-align +These options (no-options) arranges (eliminate arrangements) for the +stack-frame, individual data and constants to be aligned for the maximum +single data access size for the chosen CPU model. The default is to +arrange for 32-bit alignment. ABI details such as structure layout are +not affected by these options. + +@item -m32-bit +@itemx -m16-bit +@itemx -m8-bit +@opindex m32-bit +@opindex m16-bit +@opindex m8-bit +Similar to the stack- data- and const-align options above, these options +arrange for stack-frame, writable data and constants to all be 32-bit, +16-bit or 8-bit aligned. The default is 32-bit alignment. + +@item -mno-prologue-epilogue +@itemx -mprologue-epilogue +@opindex mno-prologue-epilogue +@opindex mprologue-epilogue +With @option{-mno-prologue-epilogue}, the normal function prologue and +epilogue that sets up the stack-frame are omitted and no return +instructions or return sequences are generated in the code. Use this +option only together with visual inspection of the compiled code: no +warnings or errors are generated when call-saved registers must be saved, +or storage for local variable needs to be allocated. + +@item -mno-gotplt +@itemx -mgotplt +@opindex mno-gotplt +@opindex mgotplt +With @option{-fpic} and @option{-fPIC}, don't generate (do generate) +instruction sequences that load addresses for functions from the PLT part +of the GOT rather than (traditional on other architectures) calls to the +PLT. The default is @option{-mgotplt}. + +@item -maout +@opindex maout +Legacy no-op option only recognized with the cris-axis-aout target. + +@item -melf +@opindex melf +Legacy no-op option only recognized with the cris-axis-elf and +cris-axis-linux-gnu targets. + +@item -melinux +@opindex melinux +Only recognized with the cris-axis-aout target, where it selects a +GNU/linux-like multilib, include files and instruction set for +@option{-march=v8}. + +@item -mlinux +@opindex mlinux +Legacy no-op option only recognized with the cris-axis-linux-gnu target. + +@item -sim +@opindex sim +This option, recognized for the cris-axis-aout and cris-axis-elf arranges +to link with input-output functions from a simulator library. Code, +initialized data and zero-initialized data are allocated consecutively. + +@item -sim2 +@opindex sim2 +Like @option{-sim}, but pass linker options to locate initialized data at +0x40000000 and zero-initialized data at 0x80000000. +@end table + @node Code Gen Options @section Options for Code Generation Conventions |