diff options
Diffstat (limited to 'gcc/testsuite/gcc.target/riscv')
-rw-r--r-- | gcc/testsuite/gcc.target/riscv/shift-and-2.c | 6 | ||||
-rw-r--r-- | gcc/testsuite/gcc.target/riscv/zbb-rol-ror-01.c | 3 | ||||
-rw-r--r-- | gcc/testsuite/gcc.target/riscv/zbb-rol-ror-02.c | 3 | ||||
-rw-r--r-- | gcc/testsuite/gcc.target/riscv/zbb-rol-ror-03.c | 3 | ||||
-rw-r--r-- | gcc/testsuite/gcc.target/riscv/zbb-rol-ror-04.c | 1 | ||||
-rw-r--r-- | gcc/testsuite/gcc.target/riscv/zbb-rol-ror-05.c | 1 | ||||
-rw-r--r-- | gcc/testsuite/gcc.target/riscv/zbb-rol-ror-06.c | 1 | ||||
-rw-r--r-- | gcc/testsuite/gcc.target/riscv/zbb-rol-ror-07.c | 1 |
8 files changed, 13 insertions, 6 deletions
diff --git a/gcc/testsuite/gcc.target/riscv/shift-and-2.c b/gcc/testsuite/gcc.target/riscv/shift-and-2.c index 360d8417209..bc01e8ef992 100644 --- a/gcc/testsuite/gcc.target/riscv/shift-and-2.c +++ b/gcc/testsuite/gcc.target/riscv/shift-and-2.c @@ -11,10 +11,10 @@ sub2 (int i, long j) } /* Test for <optab>si3_extend_mask. */ -unsigned long -sub3 (int mask) +int +sub3 (short mask) { - return 1 << (mask & 0xff); + return 1 << ((int)mask & 0x1f); } /* Test for <optab>si3_extend_mask_1. */ diff --git a/gcc/testsuite/gcc.target/riscv/zbb-rol-ror-01.c b/gcc/testsuite/gcc.target/riscv/zbb-rol-ror-01.c index 20c1b2856ef..0a5b5e12eb2 100644 --- a/gcc/testsuite/gcc.target/riscv/zbb-rol-ror-01.c +++ b/gcc/testsuite/gcc.target/riscv/zbb-rol-ror-01.c @@ -14,4 +14,5 @@ unsigned long foo2(unsigned long rs1, unsigned long rs2) } /* { dg-final { scan-assembler-times "rol" 2 } } */ -/* { dg-final { scan-assembler-times "ror" 2 } } */
\ No newline at end of file +/* { dg-final { scan-assembler-times "ror" 2 } } */ +/* { dg-final { scan-assembler-not "and" } } */
\ No newline at end of file diff --git a/gcc/testsuite/gcc.target/riscv/zbb-rol-ror-02.c b/gcc/testsuite/gcc.target/riscv/zbb-rol-ror-02.c index 14196c11fb9..d0d58135809 100644 --- a/gcc/testsuite/gcc.target/riscv/zbb-rol-ror-02.c +++ b/gcc/testsuite/gcc.target/riscv/zbb-rol-ror-02.c @@ -14,4 +14,5 @@ unsigned int foo2(unsigned int rs1, unsigned int rs2) } /* { dg-final { scan-assembler-times "rol" 2 } } */ -/* { dg-final { scan-assembler-times "ror" 2 } } */
\ No newline at end of file +/* { dg-final { scan-assembler-times "ror" 2 } } */ +/* { dg-final { scan-assembler-not {and} { target { no-opts "-O0" } } } } */
\ No newline at end of file diff --git a/gcc/testsuite/gcc.target/riscv/zbb-rol-ror-03.c b/gcc/testsuite/gcc.target/riscv/zbb-rol-ror-03.c index ed4685dc7ac..b44d7fe8920 100644 --- a/gcc/testsuite/gcc.target/riscv/zbb-rol-ror-03.c +++ b/gcc/testsuite/gcc.target/riscv/zbb-rol-ror-03.c @@ -15,4 +15,5 @@ unsigned int ror(unsigned int rs1, unsigned int rs2) } /* { dg-final { scan-assembler-times "rolw" 1 } } */ -/* { dg-final { scan-assembler-times "rorw" 1 } } */
\ No newline at end of file +/* { dg-final { scan-assembler-times "rorw" 1 } } */ +/* { dg-final { scan-assembler-not "and" } } */
\ No newline at end of file diff --git a/gcc/testsuite/gcc.target/riscv/zbb-rol-ror-04.c b/gcc/testsuite/gcc.target/riscv/zbb-rol-ror-04.c index 08053484cb2..7ef4c29dd5b 100644 --- a/gcc/testsuite/gcc.target/riscv/zbb-rol-ror-04.c +++ b/gcc/testsuite/gcc.target/riscv/zbb-rol-ror-04.c @@ -2,6 +2,7 @@ /* { dg-options "-march=rv64gc_zbb -mabi=lp64d -fno-lto -O2" } */ /* { dg-skip-if "" { *-*-* } { "-g" } } */ /* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-final { scan-assembler-not "and" } } */ /* **foo1: diff --git a/gcc/testsuite/gcc.target/riscv/zbb-rol-ror-05.c b/gcc/testsuite/gcc.target/riscv/zbb-rol-ror-05.c index 85090b1b0fc..2108ccc3e77 100644 --- a/gcc/testsuite/gcc.target/riscv/zbb-rol-ror-05.c +++ b/gcc/testsuite/gcc.target/riscv/zbb-rol-ror-05.c @@ -2,6 +2,7 @@ /* { dg-options "-march=rv32gc_zbb -mabi=ilp32 -fno-lto -O2" } */ /* { dg-skip-if "" { *-*-* } { "-g" } } */ /* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-final { scan-assembler-not "and" } } */ /* **foo1: diff --git a/gcc/testsuite/gcc.target/riscv/zbb-rol-ror-06.c b/gcc/testsuite/gcc.target/riscv/zbb-rol-ror-06.c index 70b79abb6ed..8c0711d6f94 100644 --- a/gcc/testsuite/gcc.target/riscv/zbb-rol-ror-06.c +++ b/gcc/testsuite/gcc.target/riscv/zbb-rol-ror-06.c @@ -2,6 +2,7 @@ /* { dg-options "-march=rv64gc_zbb -mabi=lp64d -fno-lto -O2" } */ /* { dg-skip-if "" { *-*-* } { "-g" } } */ /* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-final { scan-assembler-not "and" } } */ /* **foo1: diff --git a/gcc/testsuite/gcc.target/riscv/zbb-rol-ror-07.c b/gcc/testsuite/gcc.target/riscv/zbb-rol-ror-07.c index 3b6ab385a85..bda3f0e474d 100644 --- a/gcc/testsuite/gcc.target/riscv/zbb-rol-ror-07.c +++ b/gcc/testsuite/gcc.target/riscv/zbb-rol-ror-07.c @@ -2,6 +2,7 @@ /* { dg-options "-march=rv64gc_zbb -mabi=lp64d -fno-lto -O2" } */ /* { dg-skip-if "" { *-*-* } { "-g" } } */ /* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-final { scan-assembler-not "and" } } */ /* **foo1: |