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-rw-r--r--gcc/testsuite/gcc.target/arm/div64-unwinding.c3
-rw-r--r--gcc/testsuite/gcc.target/arm/ftest-armv8a-arm.c14
-rw-r--r--gcc/testsuite/gcc.target/arm/ftest-armv8a-thumb.c14
-rw-r--r--gcc/testsuite/gcc.target/arm/ftest-support-arm.h3
-rw-r--r--gcc/testsuite/gcc.target/arm/ftest-support-thumb.h3
-rw-r--r--gcc/testsuite/gcc.target/arm/ftest-support.h1
-rw-r--r--gcc/testsuite/gcc.target/arm/neon/vfmaQf32.c22
-rw-r--r--gcc/testsuite/gcc.target/arm/neon/vfmaf32.c22
-rw-r--r--gcc/testsuite/gcc.target/arm/neon/vfmsQf32.c22
-rw-r--r--gcc/testsuite/gcc.target/arm/neon/vfmsf32.c22
-rw-r--r--gcc/testsuite/gcc.target/arm/pr54892.c7
-rw-r--r--gcc/testsuite/gcc.target/arm/synchronize.c2
-rw-r--r--gcc/testsuite/gcc.target/i386/avx256-unaligned-load-1.c4
-rw-r--r--gcc/testsuite/gcc.target/i386/avx256-unaligned-load-2.c4
-rw-r--r--gcc/testsuite/gcc.target/i386/avx256-unaligned-load-3.c4
-rw-r--r--gcc/testsuite/gcc.target/i386/avx256-unaligned-load-4.c4
-rw-r--r--gcc/testsuite/gcc.target/i386/avx256-unaligned-store-1.c2
-rw-r--r--gcc/testsuite/gcc.target/i386/avx256-unaligned-store-2.c2
-rw-r--r--gcc/testsuite/gcc.target/i386/avx256-unaligned-store-3.c2
-rw-r--r--gcc/testsuite/gcc.target/i386/avx256-unaligned-store-4.c4
-rw-r--r--gcc/testsuite/gcc.target/i386/l_fma_double_1.c16
-rw-r--r--gcc/testsuite/gcc.target/i386/l_fma_double_2.c8
-rw-r--r--gcc/testsuite/gcc.target/i386/l_fma_double_3.c16
-rw-r--r--gcc/testsuite/gcc.target/i386/l_fma_double_4.c8
-rw-r--r--gcc/testsuite/gcc.target/i386/l_fma_double_5.c8
-rw-r--r--gcc/testsuite/gcc.target/i386/l_fma_double_6.c8
-rw-r--r--gcc/testsuite/gcc.target/i386/l_fma_float_1.c16
-rw-r--r--gcc/testsuite/gcc.target/i386/l_fma_float_2.c8
-rw-r--r--gcc/testsuite/gcc.target/i386/l_fma_float_3.c16
-rw-r--r--gcc/testsuite/gcc.target/i386/l_fma_float_4.c8
-rw-r--r--gcc/testsuite/gcc.target/i386/l_fma_float_5.c8
-rw-r--r--gcc/testsuite/gcc.target/i386/l_fma_float_6.c8
-rw-r--r--gcc/testsuite/gcc.target/mips/mips32-dsp-accinit-2.c3
-rw-r--r--gcc/testsuite/gcc.target/sh/pr51244-13.c85
-rw-r--r--gcc/testsuite/gcc.target/sh/pr51244-14.c107
-rw-r--r--gcc/testsuite/gcc.target/sh/pr51244-15.c71
-rw-r--r--gcc/testsuite/gcc.target/sh/pr51244-16.c11
-rw-r--r--gcc/testsuite/gcc.target/sh/pr51244-17.c297
-rw-r--r--gcc/testsuite/gcc.target/sh/pr54602-1.c15
-rw-r--r--gcc/testsuite/gcc.target/sh/pr54602-2.c15
-rw-r--r--gcc/testsuite/gcc.target/sh/pr54602-3.c12
-rw-r--r--gcc/testsuite/gcc.target/sh/pr54602-4.c15
-rw-r--r--gcc/testsuite/gcc.target/sh/pr54680.c66
-rw-r--r--gcc/testsuite/gcc.target/sh/pr54760-2.c226
-rw-r--r--gcc/testsuite/gcc.target/sh/pr54760-4.c19
-rw-r--r--gcc/testsuite/gcc.target/sh/torture/pr34777.c30
-rw-r--r--gcc/testsuite/gcc.target/sh/torture/sh-torture.exp41
47 files changed, 1124 insertions, 178 deletions
diff --git a/gcc/testsuite/gcc.target/arm/div64-unwinding.c b/gcc/testsuite/gcc.target/arm/div64-unwinding.c
index d10fb2bdd5b..7f112eeab9f 100644
--- a/gcc/testsuite/gcc.target/arm/div64-unwinding.c
+++ b/gcc/testsuite/gcc.target/arm/div64-unwinding.c
@@ -1,7 +1,6 @@
/* Performing a 64-bit division should not pull in the unwinder. */
-/* The test is expected to fail for GNU/Linux; see PR54723. */
-/* { dg-do run { xfail *-*-linux* } } */
+/* { dg-do run { target { ! *-*-linux* } } } */
/* { dg-options "-O0" } */
#include <stdlib.h>
diff --git a/gcc/testsuite/gcc.target/arm/ftest-armv8a-arm.c b/gcc/testsuite/gcc.target/arm/ftest-armv8a-arm.c
new file mode 100644
index 00000000000..1fab3c8a497
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/ftest-armv8a-arm.c
@@ -0,0 +1,14 @@
+/* { dg-do run } */
+/* { dg-require-effective-target arm_nothumb } */
+/* { dg-require-effective-target arm_arch_v8a_multilib } */
+/* { dg-options "-marm" } */
+/* { dg-add-options arm_arch_v8a } */
+
+#include "ftest-support-arm.h"
+
+int
+main (void)
+{
+ return ftest (ARCH_V8A);
+}
+
diff --git a/gcc/testsuite/gcc.target/arm/ftest-armv8a-thumb.c b/gcc/testsuite/gcc.target/arm/ftest-armv8a-thumb.c
new file mode 100644
index 00000000000..c57f4cec2b3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/ftest-armv8a-thumb.c
@@ -0,0 +1,14 @@
+/* { dg-do run } */
+/* { dg-require-effective-target arm_eabi } */
+/* { dg-require-effective-target arm_arch_v8a_multilib } */
+/* { dg-options "-mthumb" } */
+/* { dg-add-options arm_arch_v8a } */
+
+#include "ftest-support-thumb.h"
+
+int
+main (void)
+{
+ return ftest (ARCH_V8A);
+}
+
diff --git a/gcc/testsuite/gcc.target/arm/ftest-support-arm.h b/gcc/testsuite/gcc.target/arm/ftest-support-arm.h
index 512d50e8364..25920743282 100644
--- a/gcc/testsuite/gcc.target/arm/ftest-support-arm.h
+++ b/gcc/testsuite/gcc.target/arm/ftest-support-arm.h
@@ -26,4 +26,5 @@ int feature_matrix[ARCH_COUNT][NUM_FEATURES] =
{7, 1, 2, 'A', 1, 15, 1, 1, 1, 1, 1}, /* ARCH_V7A. */
{7, 1, 2, 'R', 1, 15, 1, 1, 1, 1, 1}, /* ARCH_V7R. */
{7, 0, 2, 'M', 1, 7, 1, 0, 0, 1, 1}, /* ARCH_V7M. */
- {7, 0, 2, 'M', 1, 7, 1, 1, 0, 1, 1}}; /* ARCH_V7EM. */
+ {7, 0, 2, 'M', 1, 7, 1, 1, 0, 1, 1}, /* ARCH_V7EM. */
+ {8, 1, 2, 'A', 1, 15, 1, 1, 1, 1, 1}}; /* ARCH_V8A. */
diff --git a/gcc/testsuite/gcc.target/arm/ftest-support-thumb.h b/gcc/testsuite/gcc.target/arm/ftest-support-thumb.h
index 99918310e30..a587999687a 100644
--- a/gcc/testsuite/gcc.target/arm/ftest-support-thumb.h
+++ b/gcc/testsuite/gcc.target/arm/ftest-support-thumb.h
@@ -26,4 +26,5 @@ int feature_matrix[ARCH_COUNT][NUM_FEATURES] =
{7, 1, 2, 'A', 1, 15, 1, 1, 1, 1, 1}, /* ARCH_V7A. */
{7, 1, 2, 'R', 1, 15, 1, 1, 1, 1, 1}, /* ARCH_V7R. */
{7, 0, 2, 'M', 1, 7, 1, 0, 0, 1, 1}, /* ARCH_V7M. */
- {7, 0, 2, 'M', 1, 7, 1, 1, 1, 1, 1}}; /* ARCH_V7EM. */
+ {7, 0, 2, 'M', 1, 7, 1, 1, 1, 1, 1}, /* ARCH_V7EM. */
+ {8, 1, 2, 'A', 1, 15, 1, 1, 1, 1, 1}}; /* ARCH_V8A. */
diff --git a/gcc/testsuite/gcc.target/arm/ftest-support.h b/gcc/testsuite/gcc.target/arm/ftest-support.h
index c5f98105b78..5983760ee14 100644
--- a/gcc/testsuite/gcc.target/arm/ftest-support.h
+++ b/gcc/testsuite/gcc.target/arm/ftest-support.h
@@ -22,6 +22,7 @@ enum architecture {
ARCH_V7R,
ARCH_V7M,
ARCH_V7EM,
+ ARCH_V8A,
ARCH_COUNT
};
diff --git a/gcc/testsuite/gcc.target/arm/neon/vfmaQf32.c b/gcc/testsuite/gcc.target/arm/neon/vfmaQf32.c
new file mode 100644
index 00000000000..d400163a191
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vfmaQf32.c
@@ -0,0 +1,22 @@
+/* Test the `vfmaQf32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neonv2_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neonv2 } */
+
+#include "arm_neon.h"
+
+void test_vfmaQf32 (void)
+{
+ float32x4_t out_float32x4_t;
+ float32x4_t arg0_float32x4_t;
+ float32x4_t arg1_float32x4_t;
+ float32x4_t arg2_float32x4_t;
+
+ out_float32x4_t = vfmaq_f32 (arg0_float32x4_t, arg1_float32x4_t, arg2_float32x4_t);
+}
+
+/* { dg-final { scan-assembler "vfma\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vfmaf32.c b/gcc/testsuite/gcc.target/arm/neon/vfmaf32.c
new file mode 100644
index 00000000000..988328dd08e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vfmaf32.c
@@ -0,0 +1,22 @@
+/* Test the `vfmaf32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neonv2_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neonv2 } */
+
+#include "arm_neon.h"
+
+void test_vfmaf32 (void)
+{
+ float32x2_t out_float32x2_t;
+ float32x2_t arg0_float32x2_t;
+ float32x2_t arg1_float32x2_t;
+ float32x2_t arg2_float32x2_t;
+
+ out_float32x2_t = vfma_f32 (arg0_float32x2_t, arg1_float32x2_t, arg2_float32x2_t);
+}
+
+/* { dg-final { scan-assembler "vfma\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vfmsQf32.c b/gcc/testsuite/gcc.target/arm/neon/vfmsQf32.c
new file mode 100644
index 00000000000..247a8edfd23
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vfmsQf32.c
@@ -0,0 +1,22 @@
+/* Test the `vfmsQf32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neonv2_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neonv2 } */
+
+#include "arm_neon.h"
+
+void test_vfmsQf32 (void)
+{
+ float32x4_t out_float32x4_t;
+ float32x4_t arg0_float32x4_t;
+ float32x4_t arg1_float32x4_t;
+ float32x4_t arg2_float32x4_t;
+
+ out_float32x4_t = vfmsq_f32 (arg0_float32x4_t, arg1_float32x4_t, arg2_float32x4_t);
+}
+
+/* { dg-final { scan-assembler "vfms\.f32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vfmsf32.c b/gcc/testsuite/gcc.target/arm/neon/vfmsf32.c
new file mode 100644
index 00000000000..7f9e8570dc3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/neon/vfmsf32.c
@@ -0,0 +1,22 @@
+/* Test the `vfmsf32' ARM Neon intrinsic. */
+/* This file was autogenerated by neon-testgen. */
+
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neonv2_ok } */
+/* { dg-options "-save-temps -O0" } */
+/* { dg-add-options arm_neonv2 } */
+
+#include "arm_neon.h"
+
+void test_vfmsf32 (void)
+{
+ float32x2_t out_float32x2_t;
+ float32x2_t arg0_float32x2_t;
+ float32x2_t arg1_float32x2_t;
+ float32x2_t arg2_float32x2_t;
+
+ out_float32x2_t = vfms_f32 (arg0_float32x2_t, arg1_float32x2_t, arg2_float32x2_t);
+}
+
+/* { dg-final { scan-assembler "vfms\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/pr54892.c b/gcc/testsuite/gcc.target/arm/pr54892.c
new file mode 100644
index 00000000000..a7fe1bc6676
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/pr54892.c
@@ -0,0 +1,7 @@
+/* { dg-do compile } */
+
+int set_role(unsigned char role_id, short m_role)
+{
+ return __sync_bool_compare_and_swap(&m_role, -1, role_id);
+}
+
diff --git a/gcc/testsuite/gcc.target/arm/synchronize.c b/gcc/testsuite/gcc.target/arm/synchronize.c
index 8626d8ee0a3..7ef10e2d97a 100644
--- a/gcc/testsuite/gcc.target/arm/synchronize.c
+++ b/gcc/testsuite/gcc.target/arm/synchronize.c
@@ -1,4 +1,4 @@
-/* { dg-final { scan-assembler "__sync_synchronize|dmb|mcr" { target arm*-*-linux-*eabi } } } */
+/* { dg-final { scan-assembler "__sync_synchronize|dmb|mcr" { target arm*-*-linux-* } } } */
void *foo (void)
{
diff --git a/gcc/testsuite/gcc.target/i386/avx256-unaligned-load-1.c b/gcc/testsuite/gcc.target/i386/avx256-unaligned-load-1.c
index c2511c643b4..e7eef6d7a90 100644
--- a/gcc/testsuite/gcc.target/i386/avx256-unaligned-load-1.c
+++ b/gcc/testsuite/gcc.target/i386/avx256-unaligned-load-1.c
@@ -14,6 +14,6 @@ avx_test (void)
c[i] = a[i] * b[i+3];
}
-/* { dg-final { scan-assembler-not "avx_movups256/1" } } */
-/* { dg-final { scan-assembler "sse_movups/1" } } */
+/* { dg-final { scan-assembler-not "avx_loadups256" } } */
+/* { dg-final { scan-assembler "sse_loadups" } } */
/* { dg-final { scan-assembler "vinsertf128" } } */
diff --git a/gcc/testsuite/gcc.target/i386/avx256-unaligned-load-2.c b/gcc/testsuite/gcc.target/i386/avx256-unaligned-load-2.c
index 9d7167304e3..3f4fbf76479 100644
--- a/gcc/testsuite/gcc.target/i386/avx256-unaligned-load-2.c
+++ b/gcc/testsuite/gcc.target/i386/avx256-unaligned-load-2.c
@@ -24,6 +24,6 @@ avx_test (void)
}
}
-/* { dg-final { scan-assembler-not "avx_movdqu256/1" } } */
-/* { dg-final { scan-assembler "sse2_movdqu/1" } } */
+/* { dg-final { scan-assembler-not "avx_loaddqu256" } } */
+/* { dg-final { scan-assembler "sse2_loaddqu" } } */
/* { dg-final { scan-assembler "vinsert.128" } } */
diff --git a/gcc/testsuite/gcc.target/i386/avx256-unaligned-load-3.c b/gcc/testsuite/gcc.target/i386/avx256-unaligned-load-3.c
index efb5f573fae..b0e0e79bdd8 100644
--- a/gcc/testsuite/gcc.target/i386/avx256-unaligned-load-3.c
+++ b/gcc/testsuite/gcc.target/i386/avx256-unaligned-load-3.c
@@ -14,6 +14,6 @@ avx_test (void)
c[i] = a[i] * b[i+3];
}
-/* { dg-final { scan-assembler-not "avx_movupd256/1" } } */
-/* { dg-final { scan-assembler "sse2_movupd/1" } } */
+/* { dg-final { scan-assembler-not "avx_loadupd256" } } */
+/* { dg-final { scan-assembler "sse2_loadupd" } } */
/* { dg-final { scan-assembler "vinsertf128" } } */
diff --git a/gcc/testsuite/gcc.target/i386/avx256-unaligned-load-4.c b/gcc/testsuite/gcc.target/i386/avx256-unaligned-load-4.c
index e527b381625..e0eb92b57c9 100644
--- a/gcc/testsuite/gcc.target/i386/avx256-unaligned-load-4.c
+++ b/gcc/testsuite/gcc.target/i386/avx256-unaligned-load-4.c
@@ -14,6 +14,6 @@ avx_test (void)
b[i] = a[i+3] * 2;
}
-/* { dg-final { scan-assembler "avx_movups256/1" } } */
-/* { dg-final { scan-assembler-not "avx_movups/1" } } */
+/* { dg-final { scan-assembler "avx_loadups256" } } */
+/* { dg-final { scan-assembler-not "sse_loadups" } } */
/* { dg-final { scan-assembler-not "vinsertf128" } } */
diff --git a/gcc/testsuite/gcc.target/i386/avx256-unaligned-store-1.c b/gcc/testsuite/gcc.target/i386/avx256-unaligned-store-1.c
index 0b5839669a7..1a53ba14a00 100644
--- a/gcc/testsuite/gcc.target/i386/avx256-unaligned-store-1.c
+++ b/gcc/testsuite/gcc.target/i386/avx256-unaligned-store-1.c
@@ -17,6 +17,6 @@ avx_test (void)
d[i] = c[i] * 20.0;
}
-/* { dg-final { scan-assembler-not "avx_movups256/2" } } */
+/* { dg-final { scan-assembler-not "avx_storeups256" } } */
/* { dg-final { scan-assembler "vmovups.*\\*movv4sf_internal/3" } } */
/* { dg-final { scan-assembler "vextractf128" } } */
diff --git a/gcc/testsuite/gcc.target/i386/avx256-unaligned-store-2.c b/gcc/testsuite/gcc.target/i386/avx256-unaligned-store-2.c
index eac460fef97..e98d1b684de 100644
--- a/gcc/testsuite/gcc.target/i386/avx256-unaligned-store-2.c
+++ b/gcc/testsuite/gcc.target/i386/avx256-unaligned-store-2.c
@@ -24,6 +24,6 @@ avx_test (void)
}
}
-/* { dg-final { scan-assembler-not "avx_movdqu256/2" } } */
+/* { dg-final { scan-assembler-not "avx_storedqu256" } } */
/* { dg-final { scan-assembler "vmovdqu.*\\*movv16qi_internal/3" } } */
/* { dg-final { scan-assembler "vextract.128" } } */
diff --git a/gcc/testsuite/gcc.target/i386/avx256-unaligned-store-3.c b/gcc/testsuite/gcc.target/i386/avx256-unaligned-store-3.c
index 753625892d7..26c993be7e9 100644
--- a/gcc/testsuite/gcc.target/i386/avx256-unaligned-store-3.c
+++ b/gcc/testsuite/gcc.target/i386/avx256-unaligned-store-3.c
@@ -17,6 +17,6 @@ avx_test (void)
d[i] = c[i] * 20.0;
}
-/* { dg-final { scan-assembler-not "avx_movupd256/2" } } */
+/* { dg-final { scan-assembler-not "avx_storeupd256" } } */
/* { dg-final { scan-assembler "vmovupd.*\\*movv2df_internal/3" } } */
/* { dg-final { scan-assembler "vextractf128" } } */
diff --git a/gcc/testsuite/gcc.target/i386/avx256-unaligned-store-4.c b/gcc/testsuite/gcc.target/i386/avx256-unaligned-store-4.c
index 39b6f3bef16..6d734faa25e 100644
--- a/gcc/testsuite/gcc.target/i386/avx256-unaligned-store-4.c
+++ b/gcc/testsuite/gcc.target/i386/avx256-unaligned-store-4.c
@@ -14,7 +14,7 @@ avx_test (void)
b[i+3] = a[i] * c[i];
}
-/* { dg-final { scan-assembler "avx_movups256/2" } } */
-/* { dg-final { scan-assembler-not "avx_movups/2" } } */
+/* { dg-final { scan-assembler "avx_storeups256" } } */
+/* { dg-final { scan-assembler-not "sse_storeups" } } */
/* { dg-final { scan-assembler-not "\\*avx_movv4sf_internal/3" } } */
/* { dg-final { scan-assembler-not "vextractf128" } } */
diff --git a/gcc/testsuite/gcc.target/i386/l_fma_double_1.c b/gcc/testsuite/gcc.target/i386/l_fma_double_1.c
index 87225ba3e5d..716acfef65c 100644
--- a/gcc/testsuite/gcc.target/i386/l_fma_double_1.c
+++ b/gcc/testsuite/gcc.target/i386/l_fma_double_1.c
@@ -16,11 +16,11 @@
/* { dg-final { scan-assembler-times "vfnmadd231pd" 4 } } */
/* { dg-final { scan-assembler-times "vfnmsub132pd" 4 } } */
/* { dg-final { scan-assembler-times "vfnmsub231pd" 4 } } */
-/* { dg-final { scan-assembler-times "vfmadd132sd" 8 } } */
-/* { dg-final { scan-assembler-times "vfmadd213sd" 8 } } */
-/* { dg-final { scan-assembler-times "vfmsub132sd" 8 } } */
-/* { dg-final { scan-assembler-times "vfmsub213sd" 8 } } */
-/* { dg-final { scan-assembler-times "vfnmadd132sd" 8 } } */
-/* { dg-final { scan-assembler-times "vfnmadd213sd" 8 } } */
-/* { dg-final { scan-assembler-times "vfnmsub132sd" 8 } } */
-/* { dg-final { scan-assembler-times "vfnmsub213sd" 8 } } */
+/* { dg-final { scan-assembler-times "vfmadd132sd" 20 } } */
+/* { dg-final { scan-assembler-times "vfmadd213sd" 20 } } */
+/* { dg-final { scan-assembler-times "vfmsub132sd" 20 } } */
+/* { dg-final { scan-assembler-times "vfmsub213sd" 20 } } */
+/* { dg-final { scan-assembler-times "vfnmadd132sd" 20 } } */
+/* { dg-final { scan-assembler-times "vfnmadd213sd" 20 } } */
+/* { dg-final { scan-assembler-times "vfnmsub132sd" 20 } } */
+/* { dg-final { scan-assembler-times "vfnmsub213sd" 20 } } */
diff --git a/gcc/testsuite/gcc.target/i386/l_fma_double_2.c b/gcc/testsuite/gcc.target/i386/l_fma_double_2.c
index 8b00fe1ef85..01173afb223 100644
--- a/gcc/testsuite/gcc.target/i386/l_fma_double_2.c
+++ b/gcc/testsuite/gcc.target/i386/l_fma_double_2.c
@@ -12,7 +12,7 @@
/* { dg-final { scan-assembler-times "vfmsub132pd" 8 } } */
/* { dg-final { scan-assembler-times "vfnmadd132pd" 8 } } */
/* { dg-final { scan-assembler-times "vfnmsub132pd" 8 } } */
-/* { dg-final { scan-assembler-times "vfmadd132sd" 16 } } */
-/* { dg-final { scan-assembler-times "vfmsub132sd" 16 } } */
-/* { dg-final { scan-assembler-times "vfnmadd132sd" 16 } } */
-/* { dg-final { scan-assembler-times "vfnmsub132sd" 16 } } */
+/* { dg-final { scan-assembler-times "vfmadd132sd" 40 } } */
+/* { dg-final { scan-assembler-times "vfmsub132sd" 40 } } */
+/* { dg-final { scan-assembler-times "vfnmadd132sd" 40 } } */
+/* { dg-final { scan-assembler-times "vfnmsub132sd" 40 } } */
diff --git a/gcc/testsuite/gcc.target/i386/l_fma_double_3.c b/gcc/testsuite/gcc.target/i386/l_fma_double_3.c
index 37d062c3a2a..8cda521a870 100644
--- a/gcc/testsuite/gcc.target/i386/l_fma_double_3.c
+++ b/gcc/testsuite/gcc.target/i386/l_fma_double_3.c
@@ -16,11 +16,11 @@
/* { dg-final { scan-assembler-times "vfnmadd231pd" 4 } } */
/* { dg-final { scan-assembler-times "vfnmsub132pd" 4 } } */
/* { dg-final { scan-assembler-times "vfnmsub231pd" 4 } } */
-/* { dg-final { scan-assembler-times "vfmadd132sd" 8 } } */
-/* { dg-final { scan-assembler-times "vfmadd213sd" 8 } } */
-/* { dg-final { scan-assembler-times "vfmsub132sd" 8 } } */
-/* { dg-final { scan-assembler-times "vfmsub213sd" 8 } } */
-/* { dg-final { scan-assembler-times "vfnmadd132sd" 8 } } */
-/* { dg-final { scan-assembler-times "vfnmadd213sd" 8 } } */
-/* { dg-final { scan-assembler-times "vfnmsub132sd" 8 } } */
-/* { dg-final { scan-assembler-times "vfnmsub213sd" 8 } } */
+/* { dg-final { scan-assembler-times "vfmadd132sd" 20 } } */
+/* { dg-final { scan-assembler-times "vfmadd213sd" 20 } } */
+/* { dg-final { scan-assembler-times "vfmsub132sd" 20 } } */
+/* { dg-final { scan-assembler-times "vfmsub213sd" 20 } } */
+/* { dg-final { scan-assembler-times "vfnmadd132sd" 20 } } */
+/* { dg-final { scan-assembler-times "vfnmadd213sd" 20 } } */
+/* { dg-final { scan-assembler-times "vfnmsub132sd" 20 } } */
+/* { dg-final { scan-assembler-times "vfnmsub213sd" 20 } } */
diff --git a/gcc/testsuite/gcc.target/i386/l_fma_double_4.c b/gcc/testsuite/gcc.target/i386/l_fma_double_4.c
index 7311913e837..9f2331b51e8 100644
--- a/gcc/testsuite/gcc.target/i386/l_fma_double_4.c
+++ b/gcc/testsuite/gcc.target/i386/l_fma_double_4.c
@@ -12,7 +12,7 @@
/* { dg-final { scan-assembler-times "vfmsub132pd" 8 } } */
/* { dg-final { scan-assembler-times "vfnmadd132pd" 8 } } */
/* { dg-final { scan-assembler-times "vfnmsub132pd" 8 } } */
-/* { dg-final { scan-assembler-times "vfmadd132sd" 16 } } */
-/* { dg-final { scan-assembler-times "vfmsub132sd" 16 } } */
-/* { dg-final { scan-assembler-times "vfnmadd132sd" 16 } } */
-/* { dg-final { scan-assembler-times "vfnmsub132sd" 16 } } */
+/* { dg-final { scan-assembler-times "vfmadd132sd" 40 } } */
+/* { dg-final { scan-assembler-times "vfmsub132sd" 40 } } */
+/* { dg-final { scan-assembler-times "vfnmadd132sd" 40 } } */
+/* { dg-final { scan-assembler-times "vfnmsub132sd" 40 } } */
diff --git a/gcc/testsuite/gcc.target/i386/l_fma_double_5.c b/gcc/testsuite/gcc.target/i386/l_fma_double_5.c
index a7a337be1d9..9e33975b1e4 100644
--- a/gcc/testsuite/gcc.target/i386/l_fma_double_5.c
+++ b/gcc/testsuite/gcc.target/i386/l_fma_double_5.c
@@ -12,7 +12,7 @@
/* { dg-final { scan-assembler-times "vfmsub132pd" 8 } } */
/* { dg-final { scan-assembler-times "vfnmadd132pd" 8 } } */
/* { dg-final { scan-assembler-times "vfnmsub132pd" 8 } } */
-/* { dg-final { scan-assembler-times "vfmadd132sd" 16 } } */
-/* { dg-final { scan-assembler-times "vfmsub132sd" 16 } } */
-/* { dg-final { scan-assembler-times "vfnmadd132sd" 16 } } */
-/* { dg-final { scan-assembler-times "vfnmsub132sd" 16 } } */
+/* { dg-final { scan-assembler-times "vfmadd132sd" 40 } } */
+/* { dg-final { scan-assembler-times "vfmsub132sd" 40 } } */
+/* { dg-final { scan-assembler-times "vfnmadd132sd" 40 } } */
+/* { dg-final { scan-assembler-times "vfnmsub132sd" 40 } } */
diff --git a/gcc/testsuite/gcc.target/i386/l_fma_double_6.c b/gcc/testsuite/gcc.target/i386/l_fma_double_6.c
index fcb596c550d..28d264dd20d 100644
--- a/gcc/testsuite/gcc.target/i386/l_fma_double_6.c
+++ b/gcc/testsuite/gcc.target/i386/l_fma_double_6.c
@@ -12,7 +12,7 @@
/* { dg-final { scan-assembler-times "vfmsub132pd" 8 } } */
/* { dg-final { scan-assembler-times "vfnmadd132pd" 8 } } */
/* { dg-final { scan-assembler-times "vfnmsub132pd" 8 } } */
-/* { dg-final { scan-assembler-times "vfmadd132sd" 16 } } */
-/* { dg-final { scan-assembler-times "vfmsub132sd" 16 } } */
-/* { dg-final { scan-assembler-times "vfnmadd132sd" 16 } } */
-/* { dg-final { scan-assembler-times "vfnmsub132sd" 16 } } */
+/* { dg-final { scan-assembler-times "vfmadd132sd" 40 } } */
+/* { dg-final { scan-assembler-times "vfmsub132sd" 40 } } */
+/* { dg-final { scan-assembler-times "vfnmadd132sd" 40 } } */
+/* { dg-final { scan-assembler-times "vfnmsub132sd" 40 } } */
diff --git a/gcc/testsuite/gcc.target/i386/l_fma_float_1.c b/gcc/testsuite/gcc.target/i386/l_fma_float_1.c
index b85971ddb34..fea0b20619d 100644
--- a/gcc/testsuite/gcc.target/i386/l_fma_float_1.c
+++ b/gcc/testsuite/gcc.target/i386/l_fma_float_1.c
@@ -16,11 +16,11 @@
/* { dg-final { scan-assembler-times "vfnmadd231ps" 4 } } */
/* { dg-final { scan-assembler-times "vfnmsub132ps" 4 } } */
/* { dg-final { scan-assembler-times "vfnmsub231ps" 4 } } */
-/* { dg-final { scan-assembler-times "vfmadd132ss" 8 } } */
-/* { dg-final { scan-assembler-times "vfmadd213ss" 8 } } */
-/* { dg-final { scan-assembler-times "vfmsub132ss" 8 } } */
-/* { dg-final { scan-assembler-times "vfmsub213ss" 8 } } */
-/* { dg-final { scan-assembler-times "vfnmadd132ss" 8 } } */
-/* { dg-final { scan-assembler-times "vfnmadd213ss" 8 } } */
-/* { dg-final { scan-assembler-times "vfnmsub132ss" 8 } } */
-/* { dg-final { scan-assembler-times "vfnmsub213ss" 8 } } */
+/* { dg-final { scan-assembler-times "vfmadd132ss" 36 } } */
+/* { dg-final { scan-assembler-times "vfmadd213ss" 36 } } */
+/* { dg-final { scan-assembler-times "vfmsub132ss" 36 } } */
+/* { dg-final { scan-assembler-times "vfmsub213ss" 36 } } */
+/* { dg-final { scan-assembler-times "vfnmadd132ss" 36 } } */
+/* { dg-final { scan-assembler-times "vfnmadd213ss" 36 } } */
+/* { dg-final { scan-assembler-times "vfnmsub132ss" 36 } } */
+/* { dg-final { scan-assembler-times "vfnmsub213ss" 36 } } */
diff --git a/gcc/testsuite/gcc.target/i386/l_fma_float_2.c b/gcc/testsuite/gcc.target/i386/l_fma_float_2.c
index 9cd02495b1b..dd5f543f58c 100644
--- a/gcc/testsuite/gcc.target/i386/l_fma_float_2.c
+++ b/gcc/testsuite/gcc.target/i386/l_fma_float_2.c
@@ -12,7 +12,7 @@
/* { dg-final { scan-assembler-times "vfmsub132ps" 8 } } */
/* { dg-final { scan-assembler-times "vfnmadd132ps" 8 } } */
/* { dg-final { scan-assembler-times "vfnmsub132ps" 8 } } */
-/* { dg-final { scan-assembler-times "vfmadd132ss" 16 } } */
-/* { dg-final { scan-assembler-times "vfmsub132ss" 16 } } */
-/* { dg-final { scan-assembler-times "vfnmadd132ss" 16 } } */
-/* { dg-final { scan-assembler-times "vfnmsub132ss" 16 } } */
+/* { dg-final { scan-assembler-times "vfmadd132ss" 72 } } */
+/* { dg-final { scan-assembler-times "vfmsub132ss" 72 } } */
+/* { dg-final { scan-assembler-times "vfnmadd132ss" 72 } } */
+/* { dg-final { scan-assembler-times "vfnmsub132ss" 72 } } */
diff --git a/gcc/testsuite/gcc.target/i386/l_fma_float_3.c b/gcc/testsuite/gcc.target/i386/l_fma_float_3.c
index 8388cfe03f3..38853353b01 100644
--- a/gcc/testsuite/gcc.target/i386/l_fma_float_3.c
+++ b/gcc/testsuite/gcc.target/i386/l_fma_float_3.c
@@ -16,11 +16,11 @@
/* { dg-final { scan-assembler-times "vfnmadd231ps" 4 } } */
/* { dg-final { scan-assembler-times "vfnmsub132ps" 4 } } */
/* { dg-final { scan-assembler-times "vfnmsub231ps" 4 } } */
-/* { dg-final { scan-assembler-times "vfmadd132ss" 8 } } */
-/* { dg-final { scan-assembler-times "vfmadd213ss" 8 } } */
-/* { dg-final { scan-assembler-times "vfmsub132ss" 8 } } */
-/* { dg-final { scan-assembler-times "vfmsub213ss" 8 } } */
-/* { dg-final { scan-assembler-times "vfnmadd132ss" 8 } } */
-/* { dg-final { scan-assembler-times "vfnmadd213ss" 8 } } */
-/* { dg-final { scan-assembler-times "vfnmsub132ss" 8 } } */
-/* { dg-final { scan-assembler-times "vfnmsub213ss" 8 } } */
+/* { dg-final { scan-assembler-times "vfmadd132ss" 36 } } */
+/* { dg-final { scan-assembler-times "vfmadd213ss" 36 } } */
+/* { dg-final { scan-assembler-times "vfmsub132ss" 36 } } */
+/* { dg-final { scan-assembler-times "vfmsub213ss" 36 } } */
+/* { dg-final { scan-assembler-times "vfnmadd132ss" 36 } } */
+/* { dg-final { scan-assembler-times "vfnmadd213ss" 36 } } */
+/* { dg-final { scan-assembler-times "vfnmsub132ss" 36 } } */
+/* { dg-final { scan-assembler-times "vfnmsub213ss" 36 } } */
diff --git a/gcc/testsuite/gcc.target/i386/l_fma_float_4.c b/gcc/testsuite/gcc.target/i386/l_fma_float_4.c
index bb8df69893b..5a7bb217836 100644
--- a/gcc/testsuite/gcc.target/i386/l_fma_float_4.c
+++ b/gcc/testsuite/gcc.target/i386/l_fma_float_4.c
@@ -12,7 +12,7 @@
/* { dg-final { scan-assembler-times "vfmsub132ps" 8 } } */
/* { dg-final { scan-assembler-times "vfnmadd132ps" 8 } } */
/* { dg-final { scan-assembler-times "vfnmsub132ps" 8 } } */
-/* { dg-final { scan-assembler-times "vfmadd132ss" 16 } } */
-/* { dg-final { scan-assembler-times "vfmsub132ss" 16 } } */
-/* { dg-final { scan-assembler-times "vfnmadd132ss" 16 } } */
-/* { dg-final { scan-assembler-times "vfnmsub132ss" 16 } } */
+/* { dg-final { scan-assembler-times "vfmadd132ss" 72 } } */
+/* { dg-final { scan-assembler-times "vfmsub132ss" 72 } } */
+/* { dg-final { scan-assembler-times "vfnmadd132ss" 72 } } */
+/* { dg-final { scan-assembler-times "vfnmsub132ss" 72 } } */
diff --git a/gcc/testsuite/gcc.target/i386/l_fma_float_5.c b/gcc/testsuite/gcc.target/i386/l_fma_float_5.c
index 3adf99f57fc..0b0454ed336 100644
--- a/gcc/testsuite/gcc.target/i386/l_fma_float_5.c
+++ b/gcc/testsuite/gcc.target/i386/l_fma_float_5.c
@@ -12,7 +12,7 @@
/* { dg-final { scan-assembler-times "vfmsub132ps" 8 } } */
/* { dg-final { scan-assembler-times "vfnmadd132ps" 8 } } */
/* { dg-final { scan-assembler-times "vfnmsub132ps" 8 } } */
-/* { dg-final { scan-assembler-times "vfmadd132ss" 16 } } */
-/* { dg-final { scan-assembler-times "vfmsub132ss" 16 } } */
-/* { dg-final { scan-assembler-times "vfnmadd132ss" 16 } } */
-/* { dg-final { scan-assembler-times "vfnmsub132ss" 16 } } */
+/* { dg-final { scan-assembler-times "vfmadd132ss" 72 } } */
+/* { dg-final { scan-assembler-times "vfmsub132ss" 72 } } */
+/* { dg-final { scan-assembler-times "vfnmadd132ss" 72 } } */
+/* { dg-final { scan-assembler-times "vfnmsub132ss" 72 } } */
diff --git a/gcc/testsuite/gcc.target/i386/l_fma_float_6.c b/gcc/testsuite/gcc.target/i386/l_fma_float_6.c
index ddf05e200d8..03bf8e84835 100644
--- a/gcc/testsuite/gcc.target/i386/l_fma_float_6.c
+++ b/gcc/testsuite/gcc.target/i386/l_fma_float_6.c
@@ -12,7 +12,7 @@
/* { dg-final { scan-assembler-times "vfmsub132ps" 8 } } */
/* { dg-final { scan-assembler-times "vfnmadd132ps" 8 } } */
/* { dg-final { scan-assembler-times "vfnmsub132ps" 8 } } */
-/* { dg-final { scan-assembler-times "vfmadd132ss" 16 } } */
-/* { dg-final { scan-assembler-times "vfmsub132ss" 16 } } */
-/* { dg-final { scan-assembler-times "vfnmadd132ss" 16 } } */
-/* { dg-final { scan-assembler-times "vfnmsub132ss" 16 } } */
+/* { dg-final { scan-assembler-times "vfmadd132ss" 72 } } */
+/* { dg-final { scan-assembler-times "vfmsub132ss" 72 } } */
+/* { dg-final { scan-assembler-times "vfnmadd132ss" 72 } } */
+/* { dg-final { scan-assembler-times "vfnmsub132ss" 72 } } */
diff --git a/gcc/testsuite/gcc.target/mips/mips32-dsp-accinit-2.c b/gcc/testsuite/gcc.target/mips/mips32-dsp-accinit-2.c
index 8d06a8039a1..74608d943b9 100644
--- a/gcc/testsuite/gcc.target/mips/mips32-dsp-accinit-2.c
+++ b/gcc/testsuite/gcc.target/mips/mips32-dsp-accinit-2.c
@@ -5,7 +5,8 @@
/* { dg-skip-if "requires register frequencies" { *-*-* } { "-O0" "-Os" } { "" } } */
/* Check that the zero-initialization of the accumulator feeding into
- the madd is done by means of a mult instruction instead of mthi/mtlo. */
+ the madd is done by means of an mthi & mtlo pair instead of a
+ "mult $0,$0" instruction. */
NOMIPS16 long long f (int n, int *v, int m)
{
diff --git a/gcc/testsuite/gcc.target/sh/pr51244-13.c b/gcc/testsuite/gcc.target/sh/pr51244-13.c
new file mode 100644
index 00000000000..7e823dc030c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/sh/pr51244-13.c
@@ -0,0 +1,85 @@
+/* This is a case extracted from CSiBE which contained the following
+ sequence:
+ shll r0
+ movt r0
+ tst r0,r0
+ bf .L11
+ where the 'tst r0,r0' before the branch can be omitted by inverting the
+ branch condition. The tested function contains two other tst insns. If
+ everything goes as expected we will be seeing only those other two tst
+ insns. */
+/* { dg-do compile { target "sh*-*-*" } } */
+/* { dg-options "-O2" } */
+/* { dg-skip-if "" { "sh*-*-*" } { "-m5*" } { "" } } */
+/* { dg-final { scan-assembler-times "tst" 2 } } */
+
+static __inline__ int
+__test_bit (unsigned long nr, volatile void * addr)
+{
+ /* This is on purpose. */
+ int oldbit;
+ return oldbit & 1;
+}
+
+static __inline__ int
+__constant_test_bit (unsigned long nr, volatile void * addr)
+{
+ return (((volatile char *) addr)[(nr>>3)^7] & (1<<(nr&7))) != 0;
+}
+
+struct list_head
+{
+ struct list_head *next, *prev;
+};
+
+static inline void
+__list_del (struct list_head *prev, struct list_head *next)
+{
+ next->prev = prev;
+ prev->next = next;
+}
+
+static inline void
+list_del (struct list_head *entry)
+{
+ __list_del(entry->prev, entry->next);
+ entry->next = 0;
+ entry->prev = 0;
+}
+
+extern int nr_active_pages;
+extern int nr_inactive_pages;
+extern struct list_head active_list;
+
+typedef struct page
+{
+ unsigned long flags;
+ struct list_head lru;
+} mem_map_t;
+
+void
+activate_page_nolock (struct page * page)
+{
+ if ((__builtin_constant_p((6))
+ ? __constant_test_bit((6),(&(page)->flags))
+ : __test_bit((6),(&(page)->flags)) )
+ && !(__builtin_constant_p((7))
+ ? __constant_test_bit((7),(&(page)->flags))
+ : __test_bit((7),(&(page)->flags)) ))
+ {
+ list_del(&(page)->lru);
+ nr_inactive_pages--;
+ if (!(__builtin_constant_p(6) ? __constant_test_bit((6),(&(page)->flags))
+ : __test_bit((6),(&(page)->flags))))
+ printk("", "", 43);
+
+ if ((__builtin_constant_p(7) ? __constant_test_bit((7),(&(page)->flags))
+ : __test_bit((7),(&(page)->flags))))
+ printk("", "", 43);
+
+ (__builtin_constant_p(7) ? __constant_set_bit((7),(&(page)->flags))
+ : __set_bit((7),(&(page)->flags)) );
+ list_add(&(page)->lru, &active_list);
+ nr_active_pages++;
+ }
+}
diff --git a/gcc/testsuite/gcc.target/sh/pr51244-14.c b/gcc/testsuite/gcc.target/sh/pr51244-14.c
new file mode 100644
index 00000000000..0ff7008fbc9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/sh/pr51244-14.c
@@ -0,0 +1,107 @@
+/* This is a case extracted from CSiBE which would sometimes contain the
+ following sequence:
+ cmp/eq r12,r13
+ movt r0
+ xor #1,r0
+ extu.b r0,r0
+ movt r3
+ tst r0,r0
+ bf/s .L35
+ where the negated T bit store did not combine properly. Since there are
+ other movt insns we only check for the xor and the extu. */
+/* { dg-do compile { target "sh*-*-*" } } */
+/* { dg-options "-O2" } */
+/* { dg-skip-if "" { "sh*-*-*" } { "-m5*" } { "" } } */
+/* { dg-final { scan-assembler-not "xor|extu" } } */
+
+typedef struct transaction_s transaction_t;
+
+struct journal_head
+{
+ transaction_t * b_transaction;
+ struct journal_head *b_cpnext, *b_cpprev;
+};
+
+struct transaction_s
+{
+ struct journal_head * t_checkpoint_list;
+ transaction_t *t_cpnext, *t_cpprev;
+};
+
+struct journal_s
+{
+ transaction_t * j_checkpoint_transactions;
+ unsigned long j_first, j_last;
+};
+
+typedef struct journal_s journal_t;
+
+extern int __try_to_free_cp_buf (struct journal_head *jh);
+extern int __cleanup_transaction (journal_t *journal, transaction_t *transaction);
+extern void __flush_batch (void **bhs, int *batch_count);
+extern void* jh2bh (void*);
+
+static int
+__flush_buffer (journal_t *journal, struct journal_head *jh,
+ void **bhs, int *batch_count, int *drop_count)
+{
+ void *bh = jh2bh (jh);
+ int ret = 0;
+ if (bh)
+ {
+ bhs[*batch_count] = bh;
+ (*batch_count)++;
+ if (*batch_count == 64)
+ ret = 1;
+ }
+ else
+ {
+ int last_buffer = 0;
+ if (jh->b_cpnext == jh)
+ last_buffer = 1;
+ if (__try_to_free_cp_buf (jh))
+ {
+ (*drop_count)++;
+ ret = last_buffer;
+ }
+ }
+ return ret;
+}
+
+int
+log_do_checkpoint (journal_t *journal, int nblocks)
+{
+ transaction_t *transaction, *last_transaction, *next_transaction;
+ int batch_count = 0;
+ void *bhs[64];
+
+repeat:
+ transaction = journal->j_checkpoint_transactions;
+ if (transaction == ((void *)0))
+ return 0;
+ last_transaction = transaction->t_cpprev;
+ next_transaction = transaction;
+ do
+ {
+ struct journal_head *jh, *last_jh, *next_jh;
+ int drop_count = 0;
+ int cleanup_ret, retry = 0;
+ transaction = next_transaction;
+ next_transaction = transaction->t_cpnext;
+ jh = transaction->t_checkpoint_list;
+ last_jh = jh->b_cpprev;
+ next_jh = jh;
+ do
+ {
+ jh = next_jh;
+ next_jh = jh->b_cpnext;
+ retry = __flush_buffer(journal, jh, bhs, &batch_count, &drop_count);
+ } while (jh != last_jh && !retry);
+
+ if (retry)
+ goto repeat;
+
+ cleanup_ret = __cleanup_transaction(journal, transaction);
+ goto repeat;
+ } while (transaction != last_transaction);
+}
diff --git a/gcc/testsuite/gcc.target/sh/pr51244-15.c b/gcc/testsuite/gcc.target/sh/pr51244-15.c
new file mode 100644
index 00000000000..ec98d5e6138
--- /dev/null
+++ b/gcc/testsuite/gcc.target/sh/pr51244-15.c
@@ -0,0 +1,71 @@
+/* Check that the redundant test removal code in the *cbranch_t split works
+ as expected on non-SH2A targets. Because on SH2A the movrt instruction
+ is used, this test is re-used and checked differently in pr51244-16.c. */
+/* { dg-do compile { target "sh*-*-*" } } */
+/* { dg-options "-O2" } */
+/* { dg-skip-if "" { "sh*-*-*" } { "-m5*" "-m2a*" } { "" } } */
+/* { dg-final { scan-assembler-times "tst" 6 } } */
+/* { dg-final { scan-assembler-times "movt" 6 } } */
+/* { dg-final { scan-assembler-times "xor" 3 } } */
+/* { dg-final { scan-assembler-not "extu|exts|negc" } } */
+
+typedef char bool;
+
+int
+test_0 (int a, int b, int c, int* d)
+{
+ /* non SH2A: 1x tst, 1x movt, 1x xor
+ SH2A: 1x tst, 1x movrt */
+ bool x = a == 0;
+ d[2] = !x;
+ return x ? b : c;
+}
+
+int
+test_1 (int a, int b, int c, int* d)
+{
+ /* 1x tst, 1x movt */
+ bool x = a != 0;
+ d[2] = !x;
+ return x ? b : c;
+}
+
+int
+test_2 (int a, int b, int c, char* d)
+{
+ /* Check that there is no sign/zero-extension before the store.
+ non SH2A: 1x tst, 1x movt, 1x xor
+ SH2A: 1x tst, 1x movrt */
+ bool x = a == 0;
+ d[2] = !x;
+ return x ? b : c;
+}
+
+int
+test_3 (int a, int b, int c, char* d)
+{
+ /* Check that there is no sign/zero-extension before the store.
+ 1x tst, 1x movt */
+ bool x = a != 0;
+ d[2] = !x;
+ return x ? b : c;
+}
+
+int
+test_4 (int a, int b, int c, char* d)
+{
+ /* 1x tst, 1x movt */
+ bool x = a != 0;
+ d[2] = !x;
+ return !x ? b : c;
+}
+
+int
+test_5 (int a, int b, int c, char* d)
+{
+ /* non SH2A: 1x tst, 1x movt, 1x xor
+ SH2A: 1x tst, 1x movrt */
+ bool x = a == 0;
+ d[2] = !x;
+ return !x ? b : c;
+}
diff --git a/gcc/testsuite/gcc.target/sh/pr51244-16.c b/gcc/testsuite/gcc.target/sh/pr51244-16.c
new file mode 100644
index 00000000000..8717df7f34a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/sh/pr51244-16.c
@@ -0,0 +1,11 @@
+/* Check that the redundant test removal code in the *cbranch_t split works
+ as expected on SH2A targets. */
+/* { dg-do compile { target "sh*-*-*" } } */
+/* { dg-options "-O2" } */
+/* { dg-skip-if "" { "sh*-*-*" } { "*" } { "-m2a*" } } */
+/* { dg-final { scan-assembler-times "tst" 6 } } */
+/* { dg-final { scan-assembler-times "movt" 3 } } */
+/* { dg-final { scan-assembler-times "movrt" 3 } } */
+/* { dg-final { scan-assembler-not "extu|exts|negc" } } */
+
+#include "pr51244-15.c"
diff --git a/gcc/testsuite/gcc.target/sh/pr51244-17.c b/gcc/testsuite/gcc.target/sh/pr51244-17.c
new file mode 100644
index 00000000000..e7d1ddd2ad0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/sh/pr51244-17.c
@@ -0,0 +1,297 @@
+/* Check that no unnecessary zero extensions are done on values that are
+ results of arithmetic with T bit inputs. */
+/* { dg-do compile { target "sh*-*-*" } } */
+/* { dg-options "-O1" } */
+/* { dg-skip-if "" { "sh*-*-*" } { "-m5*" } { "" } } */
+/* { dg-final { scan-assembler-not "extu|exts" } } */
+
+int
+test00 (int a, int b, int c, int d)
+{
+ int x = a == b;
+ int y = c == 0;
+ return x == y;
+}
+
+int
+test01 (int a, int b, int c, int d)
+{
+ int x = a == b;
+ int y = c == d;
+ return x == y;
+}
+
+int
+test02 (int a, int b, int c, int d)
+{
+ int x = a != b;
+ int y = c == d;
+ return x == y;
+}
+
+int
+test03 (int a, int b, int c, int d)
+{
+ int x = a != b;
+ int y = c != d;
+ return x == y;
+}
+
+int
+test04 (int a, int b, int c, int d)
+{
+ int x = a != b;
+ int y = c != d;
+ return x == y;
+}
+
+int
+test05 (int a, int b, int c, int d)
+{
+ int x = a == b;
+ int y = c == 0;
+ return x != y;
+}
+
+int
+test06 (int a, int b, int c, int d)
+{
+ int x = a == b;
+ int y = c == 0;
+ return x ^ y;
+}
+
+int
+test07 (int a, int b, int c, int d)
+{
+ int x = a == b;
+ int y = c == 0;
+ return x | y;
+}
+
+int
+test08 (int a, int b, int c, int d)
+{
+ int x = a == b;
+ int y = c == 0;
+ return x & y;
+}
+
+int
+test09 (int a, int b, int c, int d)
+{
+ int x = a == b;
+ int y = c == d;
+ return x != y;
+}
+
+int
+test10 (int a, int b, int c, int d)
+{
+ int x = a != b;
+ int y = c == d;
+ return x != y;
+}
+
+int
+test11 (int a, int b, int c, int d)
+{
+ int x = a != b;
+ int y = c != d;
+ return x != y;
+}
+
+int
+test12 (int a, int b, int c, int d)
+{
+ int x = a != b;
+ int y = c != d;
+ return x != y;
+}
+
+int
+test13 (int a, int b, int c, int d, int e, int f)
+{
+ int x = a == b;
+ int y = c == 0;
+ int z = d == e;
+ return x == y || x == z;
+}
+
+int
+test14 (int a, int b, int c, int d, int e, int f)
+{
+ int x = a == b;
+ int y = c == 0;
+ int z = d == e;
+ return x == y && x == z;
+}
+
+int
+test15 (int a, int b, int c, int d, int e, int f)
+{
+ int x = a != b;
+ int y = c == 0;
+ int z = d == e;
+ return x == y || x == z;
+}
+
+int
+test16 (int a, int b, int c, int d, int e, int f)
+{
+ int x = a != b;
+ int y = c == 0;
+ int z = d == e;
+ return x == y && x == z;
+}
+
+int
+test17 (int a, int b, int c, int d, int e, int f)
+{
+ int x = a != b;
+ int y = c != 0;
+ int z = d == e;
+ return x == y || x == z;
+}
+
+int
+test18 (int a, int b, int c, int d, int e, int f)
+{
+ int x = a != b;
+ int y = c != 0;
+ int z = d == e;
+ return x == y && x == z;
+}
+
+int
+test19 (int a, int b, int c, int d, int e, int f)
+{
+ int x = a != b;
+ int y = c != 0;
+ int z = d == e;
+ return x == y || x == z;
+}
+
+int
+test20 (int a, int b, int c, int d, int e, int f)
+{
+ int x = a != b;
+ int y = c != 0;
+ int z = d != e;
+ return x == y && x == z;
+}
+
+int
+test21 (int a, int b, int c, int d)
+{
+ int x = a == b;
+ int y = c == 0;
+ return x + y;
+}
+
+int
+test22 (int a, int b, int c, int d)
+{
+ int x = a != b;
+ int y = c == 0;
+ return x + y;
+}
+
+int
+test23 (int a, int b, int c, int d)
+{
+ int x = a != b;
+ int y = c != 0;
+ return x + y;
+}
+
+int
+test24 (int a, int b, int c, int d)
+{
+ int x = a == b;
+ int y = c == 0;
+ return x - y;
+}
+
+int
+test25 (int a, int b, int c, int d)
+{
+ int x = a != b;
+ int y = c == 0;
+ return x - y;
+}
+
+int
+test26 (int a, int b, int c, int d)
+{
+ int x = a != b;
+ int y = c != 0;
+ return x - y;
+}
+
+int
+test27 (int a, int b, int c, int d)
+{
+ int x = a == b;
+ int y = c == 0;
+ return x * y;
+}
+
+int
+test28 (int a, int b, int c, int d)
+{
+ int x = a != b;
+ int y = c == 0;
+ return x * y;
+}
+
+int
+test29 (int a, int b, int c, int d)
+{
+ int x = a != b;
+ int y = c != 0;
+ return x * y;
+}
+
+int
+test30 (int a, int b)
+{
+ return ((a & 0x7F) == 1)
+ | ((a & 0xFF00) == 0x0200)
+ | ((a & 0xFF0000) == 0x030000);
+}
+
+int
+test31 (int a, int b)
+{
+ return ((a & 0x7F) == 1)
+ | ((a & 0xFF00) == 0x0200)
+ | ((a & 0xFF0000) == 0x030000)
+ | ((a & 0xFF000000) == 0x04000000);
+}
+
+int
+test32 (int* a, int b, int c, volatile char* d)
+{
+ d[1] = a[0] != 0;
+ return b;
+}
+
+int
+test33 (int* a, int b, int c, volatile char* d)
+{
+ d[1] = a[0] == 0;
+ return b;
+}
+
+char
+test34 (int a, int* b)
+{
+ return (b[4] & b[0] & a) == a;
+}
+
+unsigned char
+test35 (int a, int* b)
+{
+ return (b[4] & b[0] & a) == a;
+}
diff --git a/gcc/testsuite/gcc.target/sh/pr54602-1.c b/gcc/testsuite/gcc.target/sh/pr54602-1.c
new file mode 100644
index 00000000000..e5c035708e4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/sh/pr54602-1.c
@@ -0,0 +1,15 @@
+/* Verify that the delay slot is stuffed with register pop insns for normal
+ (i.e. not interrupt handler) function returns. If everything goes as
+ expected we won't see any nop insns. */
+/* { dg-do compile { target "sh*-*-*" } } */
+/* { dg-options "-O1" } */
+/* { dg-skip-if "" { "sh*-*-*" } { "-m5*"} { "" } } */
+/* { dg-final { scan-assembler-not "nop" } } */
+
+int test00 (int a, int b);
+
+int
+test01 (int a, int b, int c, int d)
+{
+ return test00 (a, b) + c;
+}
diff --git a/gcc/testsuite/gcc.target/sh/pr54602-2.c b/gcc/testsuite/gcc.target/sh/pr54602-2.c
new file mode 100644
index 00000000000..4f3877c41b1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/sh/pr54602-2.c
@@ -0,0 +1,15 @@
+/* Verify that the delay slot is not stuffed with register pop insns for
+ interrupt handler function returns on SH1* and SH2* targets, where the
+ rte insn uses the stack pointer. */
+/* { dg-do compile { target "sh*-*-*" } } */
+/* { dg-options "-O1" } */
+/* { dg-skip-if "" { "sh*-*-*" } { "*" } { "-m1*" "-m2*" } } */
+/* { dg-final { scan-assembler-times "nop" 1 } } */
+
+int test00 (int a, int b);
+
+int __attribute__ ((interrupt_handler))
+test01 (int a, int b, int c, int d)
+{
+ return test00 (a, b) + c;
+}
diff --git a/gcc/testsuite/gcc.target/sh/pr54602-3.c b/gcc/testsuite/gcc.target/sh/pr54602-3.c
new file mode 100644
index 00000000000..29292589c62
--- /dev/null
+++ b/gcc/testsuite/gcc.target/sh/pr54602-3.c
@@ -0,0 +1,12 @@
+/* Verify that the rte delay slot is not stuffed with register pop insns
+ which touch the banked registers r0..r7 on SH3* and SH4* targets. */
+/* { dg-do compile { target "sh*-*-*" } } */
+/* { dg-options "-O1" } */
+/* { dg-skip-if "" { "sh*-*-*" } { "*" } { "-m3*" "-m4*" } } */
+/* { dg-final { scan-assembler-times "nop" 1 } } */
+
+int __attribute__ ((interrupt_handler))
+test00 (int a, int b, int c, int d)
+{
+ return a + b;
+}
diff --git a/gcc/testsuite/gcc.target/sh/pr54602-4.c b/gcc/testsuite/gcc.target/sh/pr54602-4.c
new file mode 100644
index 00000000000..0b77d0983ae
--- /dev/null
+++ b/gcc/testsuite/gcc.target/sh/pr54602-4.c
@@ -0,0 +1,15 @@
+/* Verify that the delay slot is stuffed with register pop insns on SH3* and
+ SH4* targets, where the stack pointer is not used by the rte insn. If
+ everything works out, we won't see a nop insn. */
+/* { dg-do compile { target "sh*-*-*" } } */
+/* { dg-options "-O1" } */
+/* { dg-skip-if "" { "sh*-*-*" } { "*" } { "-m3*" "-m4*" } } */
+/* { dg-final { scan-assembler-not "nop" } } */
+
+int test00 (int a, int b);
+
+int __attribute__ ((interrupt_handler))
+test01 (int a, int b, int c, int d)
+{
+ return test00 (a, b) + c;
+}
diff --git a/gcc/testsuite/gcc.target/sh/pr54680.c b/gcc/testsuite/gcc.target/sh/pr54680.c
new file mode 100644
index 00000000000..27c44d3ca4d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/sh/pr54680.c
@@ -0,0 +1,66 @@
+/* Verify that the fsca input value is not converted to float and then back
+ to int. Notice that we can't count just "lds" insns because mode switches
+ use "lds.l". */
+/* { dg-do compile { target "sh*-*-*" } } */
+/* { dg-options "-O2 -mfsca -funsafe-math-optimizations" } */
+/* { dg-skip-if "" { "sh*-*-*" } { "-m1" "-m2*" "-m3*" "-m4al" "*nofpu" "-m4-340*" "-m4-400*" "-m4-500*" "-m5*" } { "" } } */
+/* { dg-final { scan-assembler-times "fsca" 7 } } */
+/* { dg-final { scan-assembler-times "shad" 1 } } */
+/* { dg-final { scan-assembler-times "lds\t" 6 } } */
+/* { dg-final { scan-assembler-times "fmul" 2 } } */
+/* { dg-final { scan-assembler-times "ftrc" 1 } } */
+
+#include <math.h>
+
+static const float pi = 3.14159265359f;
+
+float
+test00 (int x)
+{
+ /* 1x shad, 1x lds, 1x fsca */
+ return sinf ( (x >> 8) * (2*pi) / (1 << 16));
+}
+
+float
+test01 (int x)
+{
+ /* 1x lds, 1x fsca */
+ return sinf (x * (2*pi) / 65536);
+}
+
+float
+test02 (int x)
+{
+ /* 1x lds, 1x fsca */
+ return sinf (x * (2*pi / 65536));
+}
+
+float
+test03 (int x)
+{
+ /* 1x lds, 1x fsca */
+ float scale = 2*pi / 65536;
+ return sinf (x * scale);
+}
+
+float
+test04 (int x)
+{
+ /* 1x lds, 1x fsca */
+ return cosf (x / 65536.0f * 2*pi);
+}
+
+float
+test05 (int x)
+{
+ /* 1x lds, 1x fsca, 1x fmul */
+ float scale = 2*pi / 65536;
+ return sinf (x * scale) * cosf (x * scale);
+}
+
+float
+test_06 (float x)
+{
+ /* 1x fmul, 1x ftrc, 1x fsca */
+ return sinf (x);
+}
diff --git a/gcc/testsuite/gcc.target/sh/pr54760-2.c b/gcc/testsuite/gcc.target/sh/pr54760-2.c
index b8a50184785..91f3648a599 100644
--- a/gcc/testsuite/gcc.target/sh/pr54760-2.c
+++ b/gcc/testsuite/gcc.target/sh/pr54760-2.c
@@ -9,107 +9,129 @@
/* ---------------------------------------------------------------------------
Simple GBR load.
*/
-#define func(name, type, disp)\
- int \
+#define func(name, rettype, type, disp)\
+ rettype \
name ## _tp_load (void) \
{ \
type* tp = (type*)__builtin_thread_pointer (); \
return tp[disp]; \
}
-func (test00, int, 0)
-func (test01, int, 5)
-func (test02, int, 255)
+func (test00, int, int, 0)
+func (test01, int, int, 5)
+func (test02, int, int, 255)
-func (test03, short, 0)
-func (test04, short, 5)
-func (test05, short, 255)
+func (test03, int, short, 0)
+func (test04, int, short, 5)
+func (test05, int, short, 255)
-func (test06, char, 0)
-func (test07, char, 5)
-func (test08, char, 255)
+func (test06, int, char, 0)
+func (test07, int, char, 5)
+func (test08, int, char, 255)
-func (test09, unsigned int, 0)
-func (test10, unsigned int, 5)
-func (test11, unsigned int, 255)
+func (test09, int, unsigned int, 0)
+func (test10, int, unsigned int, 5)
+func (test11, int, unsigned int, 255)
-func (test12, unsigned short, 0)
-func (test13, unsigned short, 5)
-func (test14, unsigned short, 255)
+func (test12, int, unsigned short, 0)
+func (test13, int, unsigned short, 5)
+func (test14, int, unsigned short, 255)
-func (test15, unsigned char, 0)
-func (test16, unsigned char, 5)
-func (test17, unsigned char, 255)
+func (test15, int, unsigned char, 0)
+func (test16, int, unsigned char, 5)
+func (test17, int, unsigned char, 255)
+
+func (test18, long long, long long, 0)
+func (test19, long long, long long, 5)
+func (test20, long long, long long, 127)
+
+func (test21, long long, unsigned long long, 0)
+func (test22, long long, unsigned long long, 5)
+func (test23, long long, unsigned long long, 127)
#undef func
/* ---------------------------------------------------------------------------
Simple GBR store.
*/
-#define func(name, type, disp)\
+#define func(name, argtype, type, disp)\
void \
- name ## _tp_store (int a) \
+ name ## _tp_store (argtype a) \
{ \
type* tp = (type*)__builtin_thread_pointer (); \
tp[disp] = (type)a; \
}
-func (test00, int, 0)
-func (test01, int, 5)
-func (test02, int, 255)
+func (test00, int, int, 0)
+func (test01, int, int, 5)
+func (test02, int, int, 255)
+
+func (test03, int, short, 0)
+func (test04, int, short, 5)
+func (test05, int, short, 255)
+
+func (test06, int, char, 0)
+func (test07, int, char, 5)
+func (test08, int, char, 255)
-func (test03, short, 0)
-func (test04, short, 5)
-func (test05, short, 255)
+func (test09, int, unsigned int, 0)
+func (test10, int, unsigned int, 5)
+func (test11, int, unsigned int, 255)
-func (test06, char, 0)
-func (test07, char, 5)
-func (test08, char, 255)
+func (test12, int, unsigned short, 0)
+func (test13, int, unsigned short, 5)
+func (test14, int, unsigned short, 255)
-func (test09, unsigned int, 0)
-func (test10, unsigned int, 5)
-func (test11, unsigned int, 255)
+func (test15, int, unsigned char, 0)
+func (test16, int, unsigned char, 5)
+func (test17, int, unsigned char, 255)
-func (test12, unsigned short, 0)
-func (test13, unsigned short, 5)
-func (test14, unsigned short, 255)
+func (test18, long long, long long, 0)
+func (test19, long long, long long, 5)
+func (test20, long long, long long, 127)
-func (test15, unsigned char, 0)
-func (test16, unsigned char, 5)
-func (test17, unsigned char, 255)
+func (test21, long long, unsigned long long, 0)
+func (test22, long long, unsigned long long, 5)
+func (test23, long long, unsigned long long, 127)
#undef func
/* ---------------------------------------------------------------------------
Arithmetic on the result of a GBR load.
*/
-#define func(name, type, disp, op, opname)\
- int \
- name ## _tp_load_arith_ ##opname (int a) \
+#define func(name, retargtype, type, disp, op, opname)\
+ retargtype \
+ name ## _tp_load_arith_ ##opname (retargtype a) \
{ \
type* tp = (type*)__builtin_thread_pointer (); \
return tp[disp] op a; \
}
#define funcs(op, opname) \
- func (test00, int, 0, op, opname) \
- func (test01, int, 5, op, opname) \
- func (test02, int, 255, op, opname) \
- func (test03, short, 0, op, opname) \
- func (test04, short, 5, op, opname) \
- func (test05, short, 255, op, opname) \
- func (test06, char, 0, op, opname) \
- func (test07, char, 5, op, opname) \
- func (test08, char, 255, op, opname) \
- func (test09, unsigned int, 0, op, opname) \
- func (test10, unsigned int, 5, op, opname) \
- func (test11, unsigned int, 255, op, opname) \
- func (test12, unsigned short, 0, op, opname) \
- func (test13, unsigned short, 5, op, opname) \
- func (test14, unsigned short, 255, op, opname) \
- func (test15, unsigned char, 0, op, opname) \
- func (test16, unsigned char, 5, op, opname) \
- func (test17, unsigned char, 255, op, opname) \
+ func (test00, int, int, 0, op, opname) \
+ func (test01, int, int, 5, op, opname) \
+ func (test02, int, int, 255, op, opname) \
+ func (test03, int, short, 0, op, opname) \
+ func (test04, int, short, 5, op, opname) \
+ func (test05, int, short, 255, op, opname) \
+ func (test06, int, char, 0, op, opname) \
+ func (test07, int, char, 5, op, opname) \
+ func (test08, int, char, 255, op, opname) \
+ func (test09, int, unsigned int, 0, op, opname) \
+ func (test10, int, unsigned int, 5, op, opname) \
+ func (test11, int, unsigned int, 255, op, opname) \
+ func (test12, int, unsigned short, 0, op, opname) \
+ func (test13, int, unsigned short, 5, op, opname) \
+ func (test14, int, unsigned short, 255, op, opname) \
+ func (test15, int, unsigned char, 0, op, opname) \
+ func (test16, int, unsigned char, 5, op, opname) \
+ func (test17, int, unsigned char, 255, op, opname) \
+ func (test18, long long, long long, 0, op, opname) \
+ func (test19, long long, long long, 5, op, opname) \
+ func (test20, long long, long long, 127, op, opname) \
+ func (test21, long long, unsigned long long, 0, op, opname) \
+ func (test22, long long, unsigned long long, 5, op, opname) \
+ func (test23, long long, unsigned long long, 127, op, opname) \
funcs (+, plus)
funcs (-, minus)
@@ -124,8 +146,8 @@ funcs (^, xor)
/* ---------------------------------------------------------------------------
Arithmetic of the result of two GBR loads.
*/
-#define func(name, type, disp0, disp1, op, opname)\
- int \
+#define func(name, rettype, type, disp0, disp1, op, opname)\
+ rettype \
name ## _tp_load_load_arith_ ##opname (void) \
{ \
type* tp = (type*)__builtin_thread_pointer (); \
@@ -133,18 +155,22 @@ funcs (^, xor)
}
#define funcs(op, opname) \
- func (test00, int, 0, 5, op, opname) \
- func (test02, int, 1, 255, op, opname) \
- func (test03, short, 0, 5, op, opname) \
- func (test05, short, 1, 255, op, opname) \
- func (test06, char, 0, 5, op, opname) \
- func (test08, char, 1, 255, op, opname) \
- func (test09, unsigned int, 0, 5, op, opname) \
- func (test11, unsigned int, 1, 255, op, opname) \
- func (test12, unsigned short, 0, 5, op, opname) \
- func (test14, unsigned short, 1, 255, op, opname) \
- func (test15, unsigned char, 0, 5, op, opname) \
- func (test17, unsigned char, 1, 255, op, opname) \
+ func (test00, int, int, 0, 5, op, opname) \
+ func (test02, int, int, 1, 255, op, opname) \
+ func (test03, int, short, 0, 5, op, opname) \
+ func (test05, int, short, 1, 255, op, opname) \
+ func (test06, int, char, 0, 5, op, opname) \
+ func (test08, int, char, 1, 255, op, opname) \
+ func (test09, int, unsigned int, 0, 5, op, opname) \
+ func (test11, int, unsigned int, 1, 255, op, opname) \
+ func (test12, int, unsigned short, 0, 5, op, opname) \
+ func (test14, int, unsigned short, 1, 255, op, opname) \
+ func (test15, int, unsigned char, 0, 5, op, opname) \
+ func (test17, int, unsigned char, 1, 255, op, opname) \
+ func (test18, long long, long long, 0, 5, op, opname) \
+ func (test19, long long, long long, 1, 127, op, opname) \
+ func (test20, long long, unsigned long long, 0, 5, op, opname) \
+ func (test21, long long, unsigned long long, 1, 127, op, opname) \
funcs (+, plus)
funcs (-, minus)
@@ -180,6 +206,10 @@ func (test12, unsigned short, 0, 5)
func (test14, unsigned short, 1, 255)
func (test15, unsigned char, 0, 5)
func (test17, unsigned char, 1, 255)
+func (test18, long long, 0, 5)
+func (test19, long long, 1, 127)
+func (test20, unsigned long long, 0, 5)
+func (test21, unsigned long long, 1, 127)
#undef func
@@ -187,33 +217,39 @@ func (test17, unsigned char, 1, 255)
GBR load, arithmetic, GBR store
*/
-#define func(name, type, disp, op, opname)\
+#define func(name, argtype, type, disp, op, opname)\
void \
- name ## _tp_load_arith_store_ ##opname (int a) \
+ name ## _tp_load_arith_store_ ##opname (argtype a) \
{ \
type* tp = (type*)__builtin_thread_pointer (); \
tp[disp] op a; \
}
#define funcs(op, opname) \
- func (test00, int, 0, op, opname) \
- func (test01, int, 5, op, opname) \
- func (test02, int, 255, op, opname) \
- func (test03, short, 0, op, opname) \
- func (test04, short, 5, op, opname) \
- func (test05, short, 255, op, opname) \
- func (test06, char, 0, op, opname) \
- func (test07, char, 5, op, opname) \
- func (test08, char, 255, op, opname) \
- func (test09, unsigned int, 0, op, opname) \
- func (test10, unsigned int, 5, op, opname) \
- func (test11, unsigned int, 255, op, opname) \
- func (test12, unsigned short, 0, op, opname) \
- func (test13, unsigned short, 5, op, opname) \
- func (test14, unsigned short, 255, op, opname) \
- func (test15, unsigned char, 0, op, opname) \
- func (test16, unsigned char, 5, op, opname) \
- func (test17, unsigned char, 255, op, opname) \
+ func (test00, int, int, 0, op, opname) \
+ func (test01, int, int, 5, op, opname) \
+ func (test02, int, int, 255, op, opname) \
+ func (test03, int, short, 0, op, opname) \
+ func (test04, int, short, 5, op, opname) \
+ func (test05, int, short, 255, op, opname) \
+ func (test06, int, char, 0, op, opname) \
+ func (test07, int, char, 5, op, opname) \
+ func (test08, int, char, 255, op, opname) \
+ func (test09, int, unsigned int, 0, op, opname) \
+ func (test10, int, unsigned int, 5, op, opname) \
+ func (test11, int, unsigned int, 255, op, opname) \
+ func (test12, int, unsigned short, 0, op, opname) \
+ func (test13, int, unsigned short, 5, op, opname) \
+ func (test14, int, unsigned short, 255, op, opname) \
+ func (test15, int, unsigned char, 0, op, opname) \
+ func (test16, int, unsigned char, 5, op, opname) \
+ func (test17, int, unsigned char, 255, op, opname) \
+ func (test18, long long, long long, 0, op, opname) \
+ func (test19, long long, long long, 5, op, opname) \
+ func (test20, long long, long long, 127, op, opname) \
+ func (test21, long long, unsigned long long, 0, op, opname) \
+ func (test22, long long, unsigned long long, 5, op, opname) \
+ func (test23, long long, unsigned long long, 127, op, opname) \
funcs (+=, plus)
funcs (-=, minus)
diff --git a/gcc/testsuite/gcc.target/sh/pr54760-4.c b/gcc/testsuite/gcc.target/sh/pr54760-4.c
new file mode 100644
index 00000000000..3ee36a31389
--- /dev/null
+++ b/gcc/testsuite/gcc.target/sh/pr54760-4.c
@@ -0,0 +1,19 @@
+/* Check that the GBR address optimization does not combine a gbr store
+ and its use when a function call is inbetween, when GBR is a call used
+ register, i.e. it is invalidated by function calls. */
+/* { dg-do compile { target "sh*-*-*" } } */
+/* { dg-options "-O1 -fcall-used-gbr" } */
+/* { dg-skip-if "" { "sh*-*-*" } { "-m5*"} { "" } } */
+/* { dg-final { scan-assembler "stc\tgbr" } } */
+
+extern int test00 (void);
+int
+test01 (int x)
+{
+ /* We must see a stc gbr,rn before the function call, because
+ a function call could modify the gbr. In this case the user requests
+ the old gbr value, before the function call. */
+ int* p = (int*)__builtin_thread_pointer ();
+ p[5] = test00 ();
+ return 0;
+}
diff --git a/gcc/testsuite/gcc.target/sh/torture/pr34777.c b/gcc/testsuite/gcc.target/sh/torture/pr34777.c
new file mode 100644
index 00000000000..b2ec56adff7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/sh/torture/pr34777.c
@@ -0,0 +1,30 @@
+/* { dg-do compile { target "sh*-*-*" } } */
+/* { dg-additional-options "-fschedule-insns -fPIC -mprefergot" } */
+/* { dg-skip-if "" { "sh*-*-*" } { "-m5*" } { "" } } */
+
+static __inline __attribute__ ((__always_inline__)) void *
+_dl_mmap (void * start, int length, int prot, int flags, int fd,
+ int offset)
+{
+ register long __sc3 __asm__ ("r3") = 90;
+ register long __sc4 __asm__ ("r4") = (long) start;
+ register long __sc5 __asm__ ("r5") = (long) length;
+ register long __sc6 __asm__ ("r6") = (long) prot;
+ register long __sc7 __asm__ ("r7") = (long) flags;
+ register long __sc0 __asm__ ("r0") = (long) fd;
+ register long __sc1 __asm__ ("r1") = (long) offset;
+ __asm__ __volatile__ ("trapa %1"
+ : "=z" (__sc0)
+ : "i" (0x10 + 6), "0" (__sc0), "r" (__sc4),
+ "r" (__sc5), "r" (__sc6), "r" (__sc7),
+ "r" (__sc3), "r" (__sc1)
+ : "memory" );
+}
+
+extern int _dl_pagesize;
+void
+_dl_dprintf(int fd, const char *fmt, ...)
+{
+ static char *buf;
+ buf = _dl_mmap ((void *) 0, _dl_pagesize, 0x1 | 0x2, 0x02 | 0x20, -1, 0);
+}
diff --git a/gcc/testsuite/gcc.target/sh/torture/sh-torture.exp b/gcc/testsuite/gcc.target/sh/torture/sh-torture.exp
new file mode 100644
index 00000000000..f025aa3ef24
--- /dev/null
+++ b/gcc/testsuite/gcc.target/sh/torture/sh-torture.exp
@@ -0,0 +1,41 @@
+# Copyright (C) 2012 Free Software Foundation, Inc.
+
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with GCC; see the file COPYING3. If not see
+# <http://www.gnu.org/licenses/>.
+
+# GCC testsuite that uses the `gcc-dg.exp' driver, looping over
+# optimization options.
+
+# Exit immediately if this isn't a SH target.
+if { ![istarget sh*-*-*] } then {
+ return
+}
+
+# Load support procs.
+load_lib gcc-dg.exp
+
+# If a testcase doesn't have special options, use these.
+global DEFAULT_CFLAGS
+if ![info exists DEFAULT_CFLAGS] then {
+ set DEFAULT_CFLAGS " -ansi -pedantic-errors"
+}
+
+# Initialize `dg'.
+dg-init
+
+# Main loop.
+gcc-dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.\[cS\]]] $DEFAULT_CFLAGS
+
+# All done.
+dg-finish