diff options
Diffstat (limited to 'gcc/testsuite')
25 files changed, 978 insertions, 24 deletions
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 62d1625485b..a9df865c15f 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,32 @@ +2009-11-04 Harsha Jagasia <harsha.jagasia@amd.com> + Dwarakanath Rajagopal <dwarak.rajagopal@amd.com> + + * gcc.target/i386/xop-check.h: New file. + * gcc.target/i386/xop-hadduX.c: Ditto. + * gcc.target/i386/xop-haddX.c: Ditto. + * gcc.target/i386/xop-hsubX.c: Ditto. + * gcc.target/i386/xop-imul32widen-vector.c: Ditto. + * gcc.target/i386/xop-imul32widen-vector.c: Ditto. + * gcc.target/i386/xop-pcmov2.c: Ditto. + * gcc.target/i386/xop-pcmov.c: Ditto. + * gcc.target/i386/xop-rotate1-vector.c: Ditto. + * gcc.target/i386/xop-rotate2-vector.c: Ditto. + * gcc.target/i386/xop-rotate3-vector.c: Ditto. + * gcc.target/i386/xop-shift1-vector.c: Ditto. + * gcc.target/i386/xop-shift2-vector.c: Ditto. + * gcc.target/i386/xop-shift3-vector.c: Ditto. + * gcc.target/i386/i386.exp: Add check_effective_target_xop. + * gcc.target/i386/sse-12.c: Update with new compile options to + activate and check xopintrin.h intrinsic file. + * gcc.target/i386/sse-13.c: Ditto. + * gcc.target/i386/sse-14.c: Ditto. + * gcc.target/i386/sse-22.c: Ditto. + * gcc.target/i386/sse-23.c: Ditto. + * g++.dg/other/i386-2.C: Ditto. + * g++.dg/other/i386-3.C: Ditto. + * g++.dg/other/i386-5.C: Ditto. + * g++.dg/other/i386-6.C: Ditto. + 2009-11-04 Wei Guozhi <carrot@google.com> PR target/40835 diff --git a/gcc/testsuite/g++.dg/other/i386-2.C b/gcc/testsuite/g++.dg/other/i386-2.C index 4c9579d07cd..1ef6b2775d8 100644 --- a/gcc/testsuite/g++.dg/other/i386-2.C +++ b/gcc/testsuite/g++.dg/other/i386-2.C @@ -1,8 +1,9 @@ -/* Test that {,x,e,p,t,s,w,a,i}mmintrin.h, fma4intrin.h, mm3dnow.h and +/* Test that {,x,e,p,t,s,w,a,i}mmintrin.h, fma4intrin.h, xopintrin.h, mm3dnow.h and mm_malloc.h are usable with -O -pedantic-errors. */ /* { dg-do compile { target i?86-*-* x86_64-*-* } } */ -/* { dg-options "-O -pedantic-errors -march=k8 -m3dnow -mavx -msse4a -mfma4 -maes -mpclmul" } */ +/* { dg-options "-O -pedantic-errors -march=k8 -m3dnow -mavx -msse4a -mfma4 -mxop -maes -mpclmul" } */ #include <x86intrin.h> int dummy; + diff --git a/gcc/testsuite/g++.dg/other/i386-3.C b/gcc/testsuite/g++.dg/other/i386-3.C index b9e89169ccb..df33af8bbd9 100644 --- a/gcc/testsuite/g++.dg/other/i386-3.C +++ b/gcc/testsuite/g++.dg/other/i386-3.C @@ -1,6 +1,6 @@ -/* Test that {,x,e,p,t,s,w,a,i}mmintrin.h, fma4intrin.h, mm3dnow.h and +/* Test that {,x,e,p,t,s,w,a,i}mmintrin.h, fma4intrin.h, mm3dnow.h, xopintrin.h and mm_malloc.h are usable with -O -fkeep-inline-functions. */ /* { dg-do compile { target i?86-*-* x86_64-*-* } } */ -/* { dg-options "-O -fkeep-inline-functions -march=k8 -m3dnow -mavx -msse4a -mfma4 -maes -mpclmul" } */ +/* { dg-options "-O -fkeep-inline-functions -march=k8 -m3dnow -mavx -msse4a -mfma4 -mxop -maes -mpclmul" } */ #include <x86intrin.h> diff --git a/gcc/testsuite/g++.dg/other/i386-5.C b/gcc/testsuite/g++.dg/other/i386-5.C index 6dcb2d3b0d0..383aae365bb 100644 --- a/gcc/testsuite/g++.dg/other/i386-5.C +++ b/gcc/testsuite/g++.dg/other/i386-5.C @@ -1,6 +1,6 @@ -/* Test that {,x,e,p,t,s,w,a,i}mmintrin.h, fma4intrin.h, mm3dnow.h and +/* Test that {,x,e,p,t,s,w,a,i}mmintrin.h, fma4intrin.h, xopintrin.h, mm3dnow.h and mm_malloc.h are usable with -O -fkeep-inline-functions. */ /* { dg-do compile { target i?86-*-* x86_64-*-* } } */ -/* { dg-options "-O -fkeep-inline-functions -march=k8 -m3dnow -mavx -msse4a -mfma4 -maes -mpclmul" } */ +/* { dg-options "-O -fkeep-inline-functions -march=k8 -m3dnow -mavx -msse4a -mfma4 -mxop -maes -mpclmul" } */ #include <x86intrin.h> diff --git a/gcc/testsuite/g++.dg/other/i386-6.C b/gcc/testsuite/g++.dg/other/i386-6.C index 4c9579d07cd..2bd4609d671 100644 --- a/gcc/testsuite/g++.dg/other/i386-6.C +++ b/gcc/testsuite/g++.dg/other/i386-6.C @@ -1,7 +1,7 @@ -/* Test that {,x,e,p,t,s,w,a,i}mmintrin.h, fma4intrin.h, mm3dnow.h and +/* Test that {,x,e,p,t,s,w,a,i}mmintrin.h, fma4intrin.h, xopintrin.h, mm3dnow.h and mm_malloc.h are usable with -O -pedantic-errors. */ /* { dg-do compile { target i?86-*-* x86_64-*-* } } */ -/* { dg-options "-O -pedantic-errors -march=k8 -m3dnow -mavx -msse4a -mfma4 -maes -mpclmul" } */ +/* { dg-options "-O -pedantic-errors -march=k8 -m3dnow -mavx -msse4a -mfma4 -mxop -maes -mpclmul" } */ #include <x86intrin.h> diff --git a/gcc/testsuite/gcc.target/i386/i386.exp b/gcc/testsuite/gcc.target/i386/i386.exp index 3bfac8d6f71..2708b04d06e 100644 --- a/gcc/testsuite/gcc.target/i386/i386.exp +++ b/gcc/testsuite/gcc.target/i386/i386.exp @@ -146,6 +146,20 @@ proc check_effective_target_fma4 { } { } "-O2 -mfma4" ] } +# Return 1 if xop instructions can be compiled. +proc check_effective_target_xop { } { + return [check_no_compiler_messages xop object { + typedef long long __m128i __attribute__ ((__vector_size__ (16), __may_alias__)); + typedef short __v8hi __attribute__ ((__vector_size__ (16))); + __m128i _mm_maccs_epi16(__m128i __A, __m128i __B, __m128i __C) + { + return (__m128i) __builtin_ia32_pmacssww ((__v8hi)__A, + (__v8hi)__B, + (__v8hi)__C); + } + } "-O2 -mxop" ] +} + # If a testcase doesn't have special options, use these. global DEFAULT_CFLAGS if ![info exists DEFAULT_CFLAGS] then { diff --git a/gcc/testsuite/gcc.target/i386/sse-12.c b/gcc/testsuite/gcc.target/i386/sse-12.c index 85c36c8be31..d03c41bf10a 100644 --- a/gcc/testsuite/gcc.target/i386/sse-12.c +++ b/gcc/testsuite/gcc.target/i386/sse-12.c @@ -1,7 +1,7 @@ -/* Test that {,x,e,p,t,s,w,a,b,i}mmintrin.h, mm3dnow.h and mm_malloc.h are +/* Test that {,x,e,p,t,s,w,a,b,i}mmintrin.h, xopintrin.h, mm3dnow.h and mm_malloc.h are usable with -O -std=c89 -pedantic-errors. */ /* { dg-do compile } */ -/* { dg-options "-O -std=c89 -pedantic-errors -march=k8 -m3dnow -mavx -mfma4 -maes -mpclmul" } */ +/* { dg-options "-O -std=c89 -pedantic-errors -march=k8 -m3dnow -mavx -mfma4 -mxop -maes -mpclmul" } */ #include <x86intrin.h> diff --git a/gcc/testsuite/gcc.target/i386/sse-13.c b/gcc/testsuite/gcc.target/i386/sse-13.c index 1ce9d960884..2ef63d5fc68 100644 --- a/gcc/testsuite/gcc.target/i386/sse-13.c +++ b/gcc/testsuite/gcc.target/i386/sse-13.c @@ -1,10 +1,10 @@ /* { dg-do compile } */ -/* { dg-options "-O2 -Werror-implicit-function-declaration -march=k8 -m3dnow -mavx -maes -mpclmul" } */ +/* { dg-options "-O2 -Werror-implicit-function-declaration -march=k8 -m3dnow -mavx -mxop -maes -mpclmul" } */ #include <mm_malloc.h> /* Test that the intrinsics compile with optimization. All of them are - defined as inline functions in {,x,e,p,t,s,w,a,b,i}mmintrin.h and mm3dnow.h + defined as inline functions in {,x,e,p,t,s,w,a,b,i}mmintrin.h, xopintrin.h and mm3dnow.h that reference the proper builtin functions. Defining away "extern" and "__inline" results in all of them being compiled as proper functions. */ @@ -125,4 +125,10 @@ #define __builtin_ia32_vec_ext_v4hi(A, N) __builtin_ia32_vec_ext_v4hi(A, 0) #define __builtin_ia32_shufps(A, B, N) __builtin_ia32_shufps(A, B, 0) +/* xopintrin.h */ +#define __builtin_ia32_vprotbi(A, N) __builtin_ia32_vprotbi (A,1) +#define __builtin_ia32_vprotwi(A, N) __builtin_ia32_vprotwi (A,1) +#define __builtin_ia32_vprotdi(A, N) __builtin_ia32_vprotdi (A,1) +#define __builtin_ia32_vprotqi(A, N) __builtin_ia32_vprotqi (A,1) + #include <x86intrin.h> diff --git a/gcc/testsuite/gcc.target/i386/sse-14.c b/gcc/testsuite/gcc.target/i386/sse-14.c index c1ddb96e5c3..783cd0af106 100644 --- a/gcc/testsuite/gcc.target/i386/sse-14.c +++ b/gcc/testsuite/gcc.target/i386/sse-14.c @@ -1,10 +1,10 @@ /* { dg-do compile } */ -/* { dg-options "-O0 -Werror-implicit-function-declaration -march=k8 -m3dnow -mavx -msse4a -maes -mpclmul" } */ +/* { dg-options "-O0 -Werror-implicit-function-declaration -march=k8 -m3dnow -mavx -mxop -msse4a -maes -mpclmul" } */ #include <mm_malloc.h> /* Test that the intrinsics compile without optimization. All of them are - defined as inline functions in {,x,e,p,t,s,w,a}mmintrin.h and mm3dnow.h + defined as inline functions in {,x,e,p,t,s,w,a}mmintrin.h, xopintrin.h and mm3dnow.h that reference the proper builtin functions. Defining away "extern" and "__inline" results in all of them being compiled as proper functions. */ @@ -155,3 +155,10 @@ test_2 (_m_pinsrw, __m64, __m64, int, 1) test_1 (_mm_shuffle_pi16, __m64, __m64, 1) test_1 (_m_pshufw, __m64, __m64, 1) test_1 (_mm_prefetch, void, void *, _MM_HINT_NTA) + +/* xopintrin.h */ +test_1 ( _mm_roti_epi8, __m128i, __m128i, 1) +test_1 ( _mm_roti_epi16, __m128i, __m128i, 1) +test_1 ( _mm_roti_epi32, __m128i, __m128i, 1) +test_1 ( _mm_roti_epi64, __m128i, __m128i, 1) + diff --git a/gcc/testsuite/gcc.target/i386/sse-22.c b/gcc/testsuite/gcc.target/i386/sse-22.c index eeae0fcab75..541cad4d439 100644 --- a/gcc/testsuite/gcc.target/i386/sse-22.c +++ b/gcc/testsuite/gcc.target/i386/sse-22.c @@ -5,7 +5,7 @@ #include <mm_malloc.h> /* Test that the intrinsics compile without optimization. All of them are - defined as inline functions in {,x,e,p,t,s,w,a}mmintrin.h and mm3dnow.h + defined as inline functions in {,x,e,p,t,s,w,a}mmintrin.h, xopintrin.h and mm3dnow.h that reference the proper builtin functions. Defining away "extern" and "__inline" results in all of them being compiled as proper functions. */ @@ -37,7 +37,7 @@ #ifndef DIFFERENT_PRAGMAS -#pragma GCC target ("mmx,3dnow,sse,sse2,sse3,ssse3,sse4.1,sse4.2,sse4a,aes,pclmul") +#pragma GCC target ("mmx,3dnow,sse,sse2,sse3,ssse3,sse4.1,sse4.2,sse4a,aes,pclmul,xop") #endif /* Following intrinsics require immediate arguments. They @@ -159,3 +159,13 @@ test_1 (_mm_round_pd, __m128d, __m128d, 1) test_1 (_mm_round_ps, __m128, __m128, 1) test_2 (_mm_round_sd, __m128d, __m128d, __m128d, 1) test_2 (_mm_round_ss, __m128, __m128, __m128, 1) + +/* xopintrin.h (XOP). */ +#ifdef DIFFERENT_PRAGMAS +#pragma GCC target ("xop") +#endif +#include <x86intrin.h> +test_1 ( _mm_roti_epi8, __m128i, __m128i, 1) +test_1 ( _mm_roti_epi16, __m128i, __m128i, 1) +test_1 ( _mm_roti_epi32, __m128i, __m128i, 1) +test_1 ( _mm_roti_epi64, __m128i, __m128i, 1) diff --git a/gcc/testsuite/gcc.target/i386/sse-23.c b/gcc/testsuite/gcc.target/i386/sse-23.c index 63cb811d042..3e0fa1f5ca4 100644 --- a/gcc/testsuite/gcc.target/i386/sse-23.c +++ b/gcc/testsuite/gcc.target/i386/sse-23.c @@ -4,7 +4,7 @@ #include <mm_malloc.h> /* Test that the intrinsics compile with optimization. All of them are - defined as inline functions in {,x,e,p,t,s,w,a,b}mmintrin.h and mm3dnow.h + defined as inline functions in {,x,e,p,t,s,w,a}mmintrin.h, xopintrin.h and mm3dnow.h that reference the proper builtin functions. Defining away "extern" and "__inline" results in all of them being compiled as proper functions. */ @@ -93,14 +93,13 @@ #define __builtin_ia32_vec_ext_v4hi(A, N) __builtin_ia32_vec_ext_v4hi(A, 0) #define __builtin_ia32_shufps(A, B, N) __builtin_ia32_shufps(A, B, 0) -/* bmmintrin.h */ -#define __builtin_ia32_protbi(A, B) __builtin_ia32_protbi(A,1) -#define __builtin_ia32_protwi(A, B) __builtin_ia32_protwi(A,1) -#define __builtin_ia32_protdi(A, B) __builtin_ia32_protdi(A,1) -#define __builtin_ia32_protqi(A, B) __builtin_ia32_protqi(A,1) +/* xopintrin.h */ +#define __builtin_ia32_vprotbi(A, B) __builtin_ia32_vprotbi(A,1) +#define __builtin_ia32_vprotwi(A, B) __builtin_ia32_vprotwi(A,1) +#define __builtin_ia32_vprotdi(A, B) __builtin_ia32_vprotdi(A,1) +#define __builtin_ia32_vprotqi(A, B) __builtin_ia32_vprotqi(A,1) - -#pragma GCC target ("3dnow,sse4,sse4a,aes,pclmul") +#pragma GCC target ("3dnow,sse4,sse4a,aes,pclmul,xop") #include <wmmintrin.h> #include <smmintrin.h> #include <mm3dnow.h> diff --git a/gcc/testsuite/gcc.target/i386/xop-check.h b/gcc/testsuite/gcc.target/i386/xop-check.h new file mode 100644 index 00000000000..2dede33d851 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/xop-check.h @@ -0,0 +1,20 @@ +#include <stdlib.h> + +#include "cpuid.h" + +static void xop_test (void); + +int +main () +{ + unsigned int eax, ebx, ecx, edx; + + if (!__get_cpuid (0x80000001, &eax, &ebx, &ecx, &edx)) + return 0; + + /* Run XOP test only if host has XOP support. */ + if (ecx & bit_XOP) + xop_test (); + + exit (0); +} diff --git a/gcc/testsuite/gcc.target/i386/xop-haddX.c b/gcc/testsuite/gcc.target/i386/xop-haddX.c new file mode 100644 index 00000000000..7d3220baffe --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/xop-haddX.c @@ -0,0 +1,206 @@ +/* { dg-do run } */ +/* { dg-require-effective-target xop } */ +/* { dg-options "-O2 -mxop" } */ + +#include "xop-check.h" + +#include <x86intrin.h> +#include <string.h> + +#define NUM 10 + +union +{ + __m128i x[NUM]; + signed char ssi[NUM * 16]; + short si[NUM * 8]; + int li[NUM * 4]; + long long lli[NUM * 2]; +} dst, res, src1; + +static void +init_sbyte () +{ + int i; + for (i=0; i < NUM * 16; i++) + src1.ssi[i] = i; +} + +static void +init_sword () +{ + int i; + for (i=0; i < NUM * 8; i++) + src1.si[i] = i; +} + + +static void +init_sdword () +{ + int i; + for (i=0; i < NUM * 4; i++) + src1.li[i] = i; +} + +static int +check_sbyte2word () +{ + int i, j, s, t, check_fails = 0; + for (i = 0; i < NUM * 16; i = i + 16) + { + for (j = 0; j < 8; j++) + { + t = i + (2 * j); + s = (i / 2) + j; + res.si[s] = src1.ssi[t] + src1.ssi[t + 1] ; + if (res.si[s] != dst.si[s]) + check_fails++; + } + } +} + +static int +check_sbyte2dword () +{ + int i, j, s, t, check_fails = 0; + for (i = 0; i < NUM * 16; i = i + 16) + { + for (j = 0; j < 4; j++) + { + t = i + (4 * j); + s = (i / 4) + j; + res.li[s] = (src1.ssi[t] + src1.ssi[t + 1]) + (src1.ssi[t + 2] + + src1.ssi[t + 3]); + if (res.li[s] != dst.li[s]) + check_fails++; + } + } + return check_fails++; +} + +static int +check_sbyte2qword () +{ + int i, j, s, t, check_fails = 0; + for (i = 0; i < NUM * 16; i = i + 16) + { + for (j = 0; j < 2; j++) + { + t = i + (8 * j); + s = (i / 8) + j; + res.lli[s] = ((src1.ssi[t] + src1.ssi[t + 1]) + (src1.ssi[t + 2] + + src1.ssi[t + 3])) + ((src1.ssi[t + 4] + src1.ssi[t +5]) + + (src1.ssi[t + 6] + src1.ssi[t + 7])); + if (res.lli[s] != dst.lli[s]) + check_fails++; + } + } + return check_fails++; +} + +static int +check_sword2dword () +{ + int i, j, s, t, check_fails = 0; + for (i = 0; i < (NUM * 8); i = i + 8) + { + for (j = 0; j < 4; j++) + { + t = i + (2 * j); + s = (i / 2) + j; + res.li[s] = src1.si[t] + src1.si[t + 1] ; + if (res.li[s] != dst.li[s]) + check_fails++; + } + } +} + +static int +check_sword2qword () +{ + int i, j, s, t, check_fails = 0; + for (i = 0; i < NUM * 8; i = i + 8) + { + for (j = 0; j < 2; j++) + { + t = i + (4 * j); + s = (i / 4) + j; + res.lli[s] = (src1.si[t] + src1.si[t + 1]) + (src1.si[t + 2] + + src1.si[t + 3]); + if (res.lli[s] != dst.lli[s]) + check_fails++; + } + } + return check_fails++; +} + +static int +check_dword2qword () +{ + int i, j, s, t, check_fails = 0; + for (i = 0; i < (NUM * 4); i = i + 4) + { + for (j = 0; j < 2; j++) + { + t = i + (2 * j); + s = (i / 2) + j; + res.lli[s] = src1.li[t] + src1.li[t + 1] ; + if (res.lli[s] != dst.lli[s]) + check_fails++; + } + } +} + +static void +xop_test (void) +{ + int i; + + init_sbyte (); + + for (i = 0; i < NUM; i++) + dst.x[i] = _mm_haddw_epi8 (src1.x[i]); + + if (check_sbyte2word()) + abort (); + + + for (i = 0; i < (NUM ); i++) + dst.x[i] = _mm_haddd_epi8 (src1.x[i]); + + if (check_sbyte2dword()) + abort (); + + + for (i = 0; i < NUM; i++) + dst.x[i] = _mm_haddq_epi8 (src1.x[i]); + + if (check_sbyte2qword()) + abort (); + + + init_sword (); + + for (i = 0; i < (NUM ); i++) + dst.x[i] = _mm_haddd_epi16 (src1.x[i]); + + if (check_sword2dword()) + abort (); + + for (i = 0; i < NUM; i++) + dst.x[i] = _mm_haddq_epi16 (src1.x[i]); + + if (check_sword2qword()) + abort (); + + + init_sdword (); + + for (i = 0; i < NUM; i++) + dst.x[i] = _mm_haddq_epi32 (src1.x[i]); + + if (check_dword2qword()) + abort (); + +} diff --git a/gcc/testsuite/gcc.target/i386/xop-hadduX.c b/gcc/testsuite/gcc.target/i386/xop-hadduX.c new file mode 100644 index 00000000000..9c7ea9a2a60 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/xop-hadduX.c @@ -0,0 +1,207 @@ +/* { dg-do run } */ +/* { dg-require-effective-target xop } */ +/* { dg-options "-O2 -mxop" } */ + +#include "xop-check.h" + +#include <x86intrin.h> +#include <string.h> + +#define NUM 10 + +union +{ + __m128i x[NUM]; + unsigned char ssi[NUM * 16]; + unsigned short si[NUM * 8]; + unsigned int li[NUM * 4]; + unsigned long long lli[NUM * 2]; +} dst, res, src1; + +static void +init_byte () +{ + int i; + for (i=0; i < NUM * 16; i++) + src1.ssi[i] = i; +} + +static void +init_word () +{ + int i; + for (i=0; i < NUM * 8; i++) + src1.si[i] = i; +} + + +static void +init_dword () +{ + int i; + for (i=0; i < NUM * 4; i++) + src1.li[i] = i; +} + +static int +check_byte2word () +{ + int i, j, s, t, check_fails = 0; + for (i = 0; i < NUM * 16; i = i + 16) + { + for (j = 0; j < 8; j++) + { + t = i + (2 * j); + s = (i / 2) + j; + res.si[s] = src1.ssi[t] + src1.ssi[t + 1] ; + if (res.si[s] != dst.si[s]) + check_fails++; + } + } +} + +static int +check_byte2dword () +{ + int i, j, s, t, check_fails = 0; + for (i = 0; i < NUM * 16; i = i + 16) + { + for (j = 0; j < 4; j++) + { + t = i + (4 * j); + s = (i / 4) + j; + res.li[s] = (src1.ssi[t] + src1.ssi[t + 1]) + (src1.ssi[t + 2] + + src1.ssi[t + 3]); + if (res.li[s] != dst.li[s]) + check_fails++; + } + } + return check_fails++; +} + +static int +check_byte2qword () +{ + int i, j, s, t, check_fails = 0; + for (i = 0; i < NUM * 16; i = i + 16) + { + for (j = 0; j < 2; j++) + { + t = i + (8 * j); + s = (i / 8) + j; + res.lli[s] = ((src1.ssi[t] + src1.ssi[t + 1]) + (src1.ssi[t + 2] + + src1.ssi[t + 3])) + ((src1.ssi[t + 4] + src1.ssi[t +5]) + + (src1.ssi[t + 6] + src1.ssi[t + 7])); + if (res.lli[s] != dst.lli[s]) + check_fails++; + } + } + return check_fails++; +} + +static int +check_word2dword () +{ + int i, j, s, t, check_fails = 0; + for (i = 0; i < (NUM * 8); i = i + 8) + { + for (j = 0; j < 4; j++) + { + t = i + (2 * j); + s = (i / 2) + j; + res.li[s] = src1.si[t] + src1.si[t + 1] ; + if (res.li[s] != dst.li[s]) + check_fails++; + } + } +} + +static int +check_word2qword () +{ + int i, j, s, t, check_fails = 0; + for (i = 0; i < NUM * 8; i = i + 8) + { + for (j = 0; j < 2; j++) + { + t = i + (4 * j); + s = (i / 4) + j; + res.lli[s] = (src1.si[t] + src1.si[t + 1]) + (src1.si[t + 2] + + src1.si[t + 3]); + if (res.lli[s] != dst.lli[s]) + check_fails++; + } + } + return check_fails++; +} + +static int +check_dword2qword () +{ + int i, j, s, t, check_fails = 0; + for (i = 0; i < (NUM * 4); i = i + 4) + { + for (j = 0; j < 2; j++) + { + t = i + (2 * j); + s = (i / 2) + j; + res.lli[s] = src1.li[t] + src1.li[t + 1] ; + if (res.lli[s] != dst.lli[s]) + check_fails++; + } + } +} + +static void +xop_test (void) +{ + int i; + + /* Check haddubw */ + init_byte (); + + for (i = 0; i < NUM; i++) + dst.x[i] = _mm_haddw_epu8 (src1.x[i]); + + if (check_byte2word()) + abort (); + + /* Check haddubd */ + for (i = 0; i < (NUM ); i++) + dst.x[i] = _mm_haddd_epu8 (src1.x[i]); + + if (check_byte2dword()) + abort (); + + /* Check haddubq */ + for (i = 0; i < NUM; i++) + dst.x[i] = _mm_haddq_epu8 (src1.x[i]); + + if (check_byte2qword()) + abort (); + + /* Check hadduwd */ + init_word (); + + for (i = 0; i < (NUM ); i++) + dst.x[i] = _mm_haddd_epu16 (src1.x[i]); + + if (check_word2dword()) + abort (); + + /* Check haddbuwq */ + + for (i = 0; i < NUM; i++) + dst.x[i] = _mm_haddq_epu16 (src1.x[i]); + + if (check_word2qword()) + abort (); + + /* Check hadudq */ + init_dword (); + for (i = 0; i < NUM; i++) + dst.x[i] = _mm_haddq_epu32 (src1.x[i]); + + if (check_dword2qword()) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/xop-hsubX.c b/gcc/testsuite/gcc.target/i386/xop-hsubX.c new file mode 100644 index 00000000000..f0fa9b312f2 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/xop-hsubX.c @@ -0,0 +1,128 @@ +/* { dg-do run } */ +/* { dg-require-effective-target xop } */ +/* { dg-options "-O2 -mxop" } */ + +#include "xop-check.h" + +#include <x86intrin.h> +#include <string.h> + +#define NUM 10 + +union +{ + __m128i x[NUM]; + signed char ssi[NUM * 16]; + short si[NUM * 8]; + int li[NUM * 4]; + long long lli[NUM * 2]; +} dst, res, src1; + +static void +init_sbyte () +{ + int i; + for (i=0; i < NUM * 16; i++) + src1.ssi[i] = i; +} + +static void +init_sword () +{ + int i; + for (i=0; i < NUM * 8; i++) + src1.si[i] = i; +} + + +static void +init_sdword () +{ + int i; + for (i=0; i < NUM * 4; i++) + src1.li[i] = i; +} + +static int +check_sbyte2word () +{ + int i, j, s, t, check_fails = 0; + for (i = 0; i < NUM * 16; i = i + 16) + { + for (j = 0; j < 8; j++) + { + t = i + (2 * j); + s = (i / 2) + j; + res.si[s] = src1.ssi[t] - src1.ssi[t + 1] ; + if (res.si[s] != dst.si[s]) + check_fails++; + } + } +} + +static int +check_sword2dword () +{ + int i, j, s, t, check_fails = 0; + for (i = 0; i < (NUM * 8); i = i + 8) + { + for (j = 0; j < 4; j++) + { + t = i + (2 * j); + s = (i / 2) + j; + res.li[s] = src1.si[t] - src1.si[t + 1] ; + if (res.li[s] != dst.li[s]) + check_fails++; + } + } +} + +static int +check_dword2qword () +{ + int i, j, s, t, check_fails = 0; + for (i = 0; i < (NUM * 4); i = i + 4) + { + for (j = 0; j < 2; j++) + { + t = i + (2 * j); + s = (i / 2) + j; + res.lli[s] = src1.li[t] - src1.li[t + 1] ; + if (res.lli[s] != dst.lli[s]) + check_fails++; + } + } +} + +static void +xop_test (void) +{ + int i; + + /* Check hsubbw */ + init_sbyte (); + + for (i = 0; i < NUM; i++) + dst.x[i] = _mm_hsubw_epi8 (src1.x[i]); + + if (check_sbyte2word()) + abort (); + + + /* Check hsubwd */ + init_sword (); + + for (i = 0; i < (NUM ); i++) + dst.x[i] = _mm_hsubd_epi16 (src1.x[i]); + + if (check_sword2dword()) + abort (); + + /* Check hsubdq */ + init_sdword (); + for (i = 0; i < NUM; i++) + dst.x[i] = _mm_hsubq_epi32 (src1.x[i]); + + if (check_dword2qword()) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/xop-imul32widen-vector.c b/gcc/testsuite/gcc.target/i386/xop-imul32widen-vector.c new file mode 100644 index 00000000000..0406d023df5 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/xop-imul32widen-vector.c @@ -0,0 +1,36 @@ +/* Test that the compiler properly optimizes floating point multiply and add + instructions vector into pmacsdd/etc. on XOP systems. */ + +/* { dg-do compile } */ +/* { dg-require-effective-target lp64 } */ +/* { dg-options "-O2 -mxop -ftree-vectorize" } */ + +extern void exit (int); + +typedef long __m128i __attribute__ ((__vector_size__ (16), __may_alias__)); + +#define SIZE 10240 + +union { + __m128i i_align; + int i32[SIZE]; + long i64[SIZE]; +} a, b, c, d; + +void +imul32_to_64 (void) +{ + int i; + + for (i = 0; i < SIZE; i++) + a.i64[i] = ((long)b.i32[i]) * ((long)c.i32[i]); +} + +int main () +{ + imul32_to_64 (); + exit (0); +} + +/* { dg-final { scan-assembler "vpmacsdql" } } */ +/* { dg-final { scan-assembler "vpmacsdqh" } } */ diff --git a/gcc/testsuite/gcc.target/i386/xop-imul64-vector.c b/gcc/testsuite/gcc.target/i386/xop-imul64-vector.c new file mode 100644 index 00000000000..738cac04105 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/xop-imul64-vector.c @@ -0,0 +1,36 @@ +/* Test that the compiler properly optimizes floating point multiply and add + instructions vector into pmacsdd/etc. on XOP systems. */ + +/* { dg-do compile } */ +/* { dg-require-effective-target lp64 } */ +/* { dg-options "-O2 -mxop -ftree-vectorize" } */ + +extern void exit (int); + +typedef long __m128i __attribute__ ((__vector_size__ (16), __may_alias__)); + +#define SIZE 10240 + +union { + __m128i i_align; + long i64[SIZE]; +} a, b, c, d; + +void +imul64 (void) +{ + int i; + + for (i = 0; i < SIZE; i++) + a.i64[i] = b.i64[i] * c.i64[i]; +} + +int main () +{ + imul64 (); + exit (0); +} + +/* { dg-final { scan-assembler "vpmacsdd" } } */ +/* { dg-final { scan-assembler "vphadddq" } } */ +/* { dg-final { scan-assembler "vpmacsdql" } } */ diff --git a/gcc/testsuite/gcc.target/i386/xop-pcmov.c b/gcc/testsuite/gcc.target/i386/xop-pcmov.c new file mode 100644 index 00000000000..d6375b1fd50 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/xop-pcmov.c @@ -0,0 +1,23 @@ +/* Test that the compiler properly optimizes conditional floating point moves + into the pcmov instruction on XOP systems. */ + +/* { dg-do compile } */ +/* { dg-require-effective-target lp64 } */ +/* { dg-options "-O2 -mxop" } */ + +extern void exit (int); + +double dbl_test (double a, double b, double c, double d) +{ + return (a > b) ? c : d; +} + +double dbl_a = 1, dbl_b = 2, dbl_c = 3, dbl_d = 4, dbl_e; + +int main() +{ + dbl_e = dbl_test (dbl_a, dbl_b, dbl_c, dbl_d); + exit (0); +} + +/* { dg-final { scan-assembler "vpcmov" } } */ diff --git a/gcc/testsuite/gcc.target/i386/xop-pcmov2.c b/gcc/testsuite/gcc.target/i386/xop-pcmov2.c new file mode 100644 index 00000000000..617da39da98 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/xop-pcmov2.c @@ -0,0 +1,23 @@ +/* Test that the compiler properly optimizes conditional floating point moves + into the pcmov instruction on XOP systems. */ + +/* { dg-do compile } */ +/* { dg-require-effective-target lp64 } */ +/* { dg-options "-O2 -mxop" } */ + +extern void exit (int); + +float flt_test (float a, float b, float c, float d) +{ + return (a > b) ? c : d; +} + +float flt_a = 1, flt_b = 2, flt_c = 3, flt_d = 4, flt_e; + +int main() +{ + flt_e = flt_test (flt_a, flt_b, flt_c, flt_d); + exit (0); +} + +/* { dg-final { scan-assembler "vpcmov" } } */ diff --git a/gcc/testsuite/gcc.target/i386/xop-rotate1-vector.c b/gcc/testsuite/gcc.target/i386/xop-rotate1-vector.c new file mode 100644 index 00000000000..e3ae644d0b5 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/xop-rotate1-vector.c @@ -0,0 +1,35 @@ +/* Test that the compiler properly optimizes vector rotate instructions vector + into prot on XOP systems. */ + +/* { dg-do compile } */ +/* { dg-require-effective-target lp64 } */ +/* { dg-options "-O2 -mxop -ftree-vectorize" } */ + +extern void exit (int); + +typedef long __m128i __attribute__ ((__vector_size__ (16), __may_alias__)); + +#define SIZE 10240 + +union { + __m128i i_align; + unsigned u32[SIZE]; +} a, b, c; + +void +left_rotate32 (void) +{ + int i; + + for (i = 0; i < SIZE; i++) + a.u32[i] = (b.u32[i] << ((sizeof (int) * 8) - 4)) | (b.u32[i] >> 4); +} + +int +main () +{ + left_rotate32 (); + exit (0); +} + +/* { dg-final { scan-assembler "vprotd" } } */ diff --git a/gcc/testsuite/gcc.target/i386/xop-rotate2-vector.c b/gcc/testsuite/gcc.target/i386/xop-rotate2-vector.c new file mode 100644 index 00000000000..9996279bc0f --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/xop-rotate2-vector.c @@ -0,0 +1,35 @@ +/* Test that the compiler properly optimizes vector rotate instructions vector + into prot on XOP systems. */ + +/* { dg-do compile } */ +/* { dg-require-effective-target lp64 } */ +/* { dg-options "-O2 -mxop -ftree-vectorize" } */ + +extern void exit (int); + +typedef long __m128i __attribute__ ((__vector_size__ (16), __may_alias__)); + +#define SIZE 10240 + +union { + __m128i i_align; + unsigned u32[SIZE]; +} a, b, c; + +void +right_rotate32_b (void) +{ + int i; + + for (i = 0; i < SIZE; i++) + a.u32[i] = (b.u32[i] >> ((sizeof (int) * 8) - 4)) | (b.u32[i] << 4); +} + +int +main () +{ + right_rotate (); + exit (0); +} + +/* { dg-final { scan-assembler "vprot" } } */ diff --git a/gcc/testsuite/gcc.target/i386/xop-rotate3-vector.c b/gcc/testsuite/gcc.target/i386/xop-rotate3-vector.c new file mode 100644 index 00000000000..73d52f5f3f0 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/xop-rotate3-vector.c @@ -0,0 +1,34 @@ +/* Test that the compiler properly optimizes vector rotate instructions vector + into prot on XOP systems. */ + +/* { dg-do compile } */ +/* { dg-require-effective-target lp64 } */ +/* { dg-options "-O2 -mxop -ftree-vectorize" } */ + +extern void exit (int); + +typedef long __m128i __attribute__ ((__vector_size__ (16), __may_alias__)); + +#define SIZE 10240 + +union { + __m128i i_align; + unsigned u32[SIZE]; +} a, b, c; + +void +vector_rotate32 (void) +{ + int i; + + for (i = 0; i < SIZE; i++) + a.u32[i] = (b.u32[i] >> ((sizeof (int) * 8) - c.u32[i])) | (b.u32[i] << c.u32[i]); +} + +int main () +{ + vector_rotate32 (); + exit (0); +} + +/* { dg-final { scan-assembler "vprotd" } } */ diff --git a/gcc/testsuite/gcc.target/i386/xop-shift1-vector.c b/gcc/testsuite/gcc.target/i386/xop-shift1-vector.c new file mode 100644 index 00000000000..eb84439c496 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/xop-shift1-vector.c @@ -0,0 +1,35 @@ +/* Test that the compiler properly optimizes vector shift instructions into + psha/pshl on XOP systems. */ + +/* { dg-do compile } */ +/* { dg-require-effective-target lp64 } */ +/* { dg-options "-O2 -mxop -ftree-vectorize" } */ + +extern void exit (int); + +typedef long __m128i __attribute__ ((__vector_size__ (16), __may_alias__)); + +#define SIZE 10240 + +union { + __m128i i_align; + int i32[SIZE]; + unsigned u32[SIZE]; +} a, b, c; + +void +left_shift32 (void) +{ + int i; + + for (i = 0; i < SIZE; i++) + a.i32[i] = b.i32[i] << c.i32[i]; +} + +int main () +{ + left_shfit32 (); + exit (0); +} + +/* { dg-final { scan-assembler "vpshad" } } */ diff --git a/gcc/testsuite/gcc.target/i386/xop-shift2-vector.c b/gcc/testsuite/gcc.target/i386/xop-shift2-vector.c new file mode 100644 index 00000000000..e59c30d021b --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/xop-shift2-vector.c @@ -0,0 +1,35 @@ +/* Test that the compiler properly optimizes vector shift instructions into + psha/pshl on XOP systems. */ + +/* { dg-do compile } */ +/* { dg-require-effective-target lp64 } */ +/* { dg-options "-O2 -mxop -ftree-vectorize" } */ + +extern void exit (int); + +typedef long __m128i __attribute__ ((__vector_size__ (16), __may_alias__)); + +#define SIZE 10240 + +union { + __m128i i_align; + int i32[SIZE]; + unsigned u32[SIZE]; +} a, b, c; + +void +right_sign_shift32 (void) +{ + int i; + + for (i = 0; i < SIZE; i++) + a.i32[i] = b.i32[i] >> c.i32[i]; +} + +int main () +{ + right_sign_shfit32 (); + exit (0); +} + +/* { dg-final { scan-assembler "vpshad" } } */ diff --git a/gcc/testsuite/gcc.target/i386/xop-shift3-vector.c b/gcc/testsuite/gcc.target/i386/xop-shift3-vector.c new file mode 100644 index 00000000000..2b9302db52d --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/xop-shift3-vector.c @@ -0,0 +1,35 @@ +/* Test that the compiler properly optimizes vector shift instructions into + psha/pshl on XOP systems. */ + +/* { dg-do compile } */ +/* { dg-require-effective-target lp64 } */ +/* { dg-options "-O2 -mxop -ftree-vectorize" } */ + +extern void exit (int); + +typedef long __m128i __attribute__ ((__vector_size__ (16), __may_alias__)); + +#define SIZE 10240 + +union { + __m128i i_align; + int i32[SIZE]; + unsigned u32[SIZE]; +} a, b, c; + +void +right_uns_shift32 (void) +{ + int i; + + for (i = 0; i < SIZE; i++) + a.u32[i] = b.u32[i] >> c.i32[i]; +} + +int main () +{ + right_uns_shfit32 (); + exit (0); +} + +/* { dg-final { scan-assembler "vpshld" } } */ |