diff options
Diffstat (limited to 'gcc/testsuite')
112 files changed, 2135 insertions, 6 deletions
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 261bb98a3a4..00ae0d12f54 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,166 @@ +2014-04-30 Alan Lawrence <alan.lawrence@arm.com> + + * gcc.target/aarch64/vuzps32_1.c: Expect zip1/2 insn rather than uzp1/2. + * gcc.target/aarch64/vuzpu32_1.c: Likewise. + * gcc.target/aarch64/vuzpf32_1.c: Likewise. + +2014-04-30 Alan Lawrence <alan.lawrence@arm.com> + + * gcc.target/aarch64/simd/vuzpf32_1.c: New file. + * gcc.target/aarch64/simd/vuzpf32.x: New file. + * gcc.target/aarch64/simd/vuzpp16_1.c: New file. + * gcc.target/aarch64/simd/vuzpp16.x: New file. + * gcc.target/aarch64/simd/vuzpp8_1.c: New file. + * gcc.target/aarch64/simd/vuzpp8.x: New file. + * gcc.target/aarch64/simd/vuzpqf32_1.c: New file. + * gcc.target/aarch64/simd/vuzpqf32.x: New file. + * gcc.target/aarch64/simd/vuzpqp16_1.c: New file. + * gcc.target/aarch64/simd/vuzpqp16.x: New file. + * gcc.target/aarch64/simd/vuzpqp8_1.c: New file. + * gcc.target/aarch64/simd/vuzpqp8.x: New file. + * gcc.target/aarch64/simd/vuzpqs16_1.c: New file. + * gcc.target/aarch64/simd/vuzpqs16.x: New file. + * gcc.target/aarch64/simd/vuzpqs32_1.c: New file. + * gcc.target/aarch64/simd/vuzpqs32.x: New file. + * gcc.target/aarch64/simd/vuzpqs8_1.c: New file. + * gcc.target/aarch64/simd/vuzpqs8.x: New file. + * gcc.target/aarch64/simd/vuzpqu16_1.c: New file. + * gcc.target/aarch64/simd/vuzpqu16.x: New file. + * gcc.target/aarch64/simd/vuzpqu32_1.c: New file. + * gcc.target/aarch64/simd/vuzpqu32.x: New file. + * gcc.target/aarch64/simd/vuzpqu8_1.c: New file. + * gcc.target/aarch64/simd/vuzpqu8.x: New file. + * gcc.target/aarch64/simd/vuzps16_1.c: New file. + * gcc.target/aarch64/simd/vuzps16.x: New file. + * gcc.target/aarch64/simd/vuzps32_1.c: New file. + * gcc.target/aarch64/simd/vuzps32.x: New file. + * gcc.target/aarch64/simd/vuzps8_1.c: New file. + * gcc.target/aarch64/simd/vuzps8.x: New file. + * gcc.target/aarch64/simd/vuzpu16_1.c: New file. + * gcc.target/aarch64/simd/vuzpu16.x: New file. + * gcc.target/aarch64/simd/vuzpu32_1.c: New file. + * gcc.target/aarch64/simd/vuzpu32.x: New file. + * gcc.target/aarch64/simd/vuzpu8_1.c: New file. + * gcc.target/aarch64/simd/vuzpu8.x: New file. + +2014-04-30 Richard Biener <rguenther@suse.de> + + PR tree-optimization/48329 + * gfortran.dg/vect/pr48329.f90: New testcase. + +2014-04-30 Marek Polacek <polacek@redhat.com> + + * c-c++-common/ubsan/div-by-zero-5.c: Fix formatting. + * c-c++-common/ubsan/float-div-by-zero-1.c: New test. + +2014-04-30 Marek Polacek <polacek@redhat.com> + + PR c/60139 + * gcc.dg/pr60139.c: New test. + +2014-04-30 Marek Polacek <polacek@redhat.com> + + PR c/60351 + * gcc.dg/pr60351.c: New test. + +2013-04-29 Alan Lawrence <alan.lawrence@arm.com> + + * gcc.target/arm/simd/simd.exp: New file. + * gcc.target/arm/simd/vzipqf32_1.c: New file. + * gcc.target/arm/simd/vzipqp16_1.c: New file. + * gcc.target/arm/simd/vzipqp8_1.c: New file. + * gcc.target/arm/simd/vzipqs16_1.c: New file. + * gcc.target/arm/simd/vzipqs32_1.c: New file. + * gcc.target/arm/simd/vzipqs8_1.c: New file. + * gcc.target/arm/simd/vzipqu16_1.c: New file. + * gcc.target/arm/simd/vzipqu32_1.c: New file. + * gcc.target/arm/simd/vzipqu8_1.c: New file. + * gcc.target/arm/simd/vzipf32_1.c: New file. + * gcc.target/arm/simd/vzipp16_1.c: New file. + * gcc.target/arm/simd/vzipp8_1.c: New file. + * gcc.target/arm/simd/vzips16_1.c: New file. + * gcc.target/arm/simd/vzips32_1.c: New file. + * gcc.target/arm/simd/vzips8_1.c: New file. + * gcc.target/arm/simd/vzipu16_1.c: New file. + * gcc.target/arm/simd/vzipu32_1.c: New file. + * gcc.target/arm/simd/vzipu8_1.c: New file. + +2014-04-29 Paolo Carlini <paolo.carlini@oracle.com> + + PR c++/51707 + * g++.dg/cpp0x/constexpr-51707.C: New. + +2014-04-29 David Malcolm <dmalcolm@redhat.com> + + * gcc.dg/tree-ssa/pr23401.c: Update the expected number of + occurrences of "int" in the gimple dump to reflect that the return + types of functions now show up in such dumps. + * gcc.dg/tree-ssa/pr27810.c: Likewise. + +2014-04-29 Jakub Jelinek <jakub@redhat.com> + + PR tree-optimization/60971 + * c-c++-common/turtore/pr60971.c: New test. + +2014-04-29 Alan Lawrence <alan.lawrence@arm.com> + + * gcc.target/aarch64/simd/simd.exp: New file. + * gcc.target/aarch64/simd/vzipf32_1.c: New file. + * gcc.target/aarch64/simd/vzipf32.x: New file. + * gcc.target/aarch64/simd/vzipp16_1.c: New file. + * gcc.target/aarch64/simd/vzipp16.x: New file. + * gcc.target/aarch64/simd/vzipp8_1.c: New file. + * gcc.target/aarch64/simd/vzipp8.x: New file. + * gcc.target/aarch64/simd/vzipqf32_1.c: New file. + * gcc.target/aarch64/simd/vzipqf32.x: New file. + * gcc.target/aarch64/simd/vzipqp16_1.c: New file. + * gcc.target/aarch64/simd/vzipqp16.x: New file. + * gcc.target/aarch64/simd/vzipqp8_1.c: New file. + * gcc.target/aarch64/simd/vzipqp8.x: New file. + * gcc.target/aarch64/simd/vzipqs16_1.c: New file. + * gcc.target/aarch64/simd/vzipqs16.x: New file. + * gcc.target/aarch64/simd/vzipqs32_1.c: New file. + * gcc.target/aarch64/simd/vzipqs32.x: New file. + * gcc.target/aarch64/simd/vzipqs8_1.c: New file. + * gcc.target/aarch64/simd/vzipqs8.x: New file. + * gcc.target/aarch64/simd/vzipqu16_1.c: New file. + * gcc.target/aarch64/simd/vzipqu16.x: New file. + * gcc.target/aarch64/simd/vzipqu32_1.c: New file. + * gcc.target/aarch64/simd/vzipqu32.x: New file. + * gcc.target/aarch64/simd/vzipqu8_1.c: New file. + * gcc.target/aarch64/simd/vzipqu8.x: New file. + * gcc.target/aarch64/simd/vzips16_1.c: New file. + * gcc.target/aarch64/simd/vzips16.x: New file. + * gcc.target/aarch64/simd/vzips32_1.c: New file. + * gcc.target/aarch64/simd/vzips32.x: New file. + * gcc.target/aarch64/simd/vzips8_1.c: New file. + * gcc.target/aarch64/simd/vzips8.x: New file. + * gcc.target/aarch64/simd/vzipu16_1.c: New file. + * gcc.target/aarch64/simd/vzipu16.x: New file. + * gcc.target/aarch64/simd/vzipu32_1.c: New file. + * gcc.target/aarch64/simd/vzipu32.x: New file. + * gcc.target/aarch64/simd/vzipu8_1.c: New file. + * gcc.target/aarch64/simd/vzipu8.x: New file. + +2014-04-29 Zhenqiang Chen <zhenqiang.chen@linaro.org> + + * gcc.target/aarch64/fcsel_1.c: New test case. + +2014-04-28 Jerry DeLisle <jvdelisle@gcc.gnu> + + PR libfortran/60810 + * gfortran.dg/arrayio_13.f90: New test. + +2014-04-28 Martin Jambor <mjambor@suse.cz> + + * gcc.dg/tree-ssa/sra-14.c: New test. + +2014-04-28 Richard Biener <rguenther@suse.de> + + PR middle-end/60092 + * gcc.dg/tree-ssa/alias-32.c: New testcase. + * gcc.dg/vect/pr60092.c: Likewise. + 2014-04-28 Richard Biener <rguenther@suse.de> * gcc.dg/tree-ssa/vrp91.c: New testcase. diff --git a/gcc/testsuite/c-c++-common/torture/pr60971.c b/gcc/testsuite/c-c++-common/torture/pr60971.c new file mode 100644 index 00000000000..b7a967dabb4 --- /dev/null +++ b/gcc/testsuite/c-c++-common/torture/pr60971.c @@ -0,0 +1,34 @@ +/* PR tree-optimization/60971 */ +/* { dg-do run } */ + +#ifndef __cplusplus +#define bool _Bool +#endif + +volatile unsigned char c; + +__attribute__((noinline)) unsigned char +foo (void) +{ + return c; +} + +__attribute__((noinline)) bool +bar (void) +{ + return foo () & 1; +} + +int +main () +{ + c = 0x41; + c = bar (); + if (c != 1) + __builtin_abort (); + c = 0x20; + c = bar (); + if (c != 0) + __builtin_abort (); + return 0; +} diff --git a/gcc/testsuite/c-c++-common/ubsan/div-by-zero-5.c b/gcc/testsuite/c-c++-common/ubsan/div-by-zero-5.c index 7a28bacd14b..bb391c5b36d 100644 --- a/gcc/testsuite/c-c++-common/ubsan/div-by-zero-5.c +++ b/gcc/testsuite/c-c++-common/ubsan/div-by-zero-5.c @@ -1,4 +1,4 @@ -/* { dg-do compile} */ +/* { dg-do compile } */ /* { dg-options "-fsanitize=integer-divide-by-zero" } */ void diff --git a/gcc/testsuite/c-c++-common/ubsan/float-div-by-zero-1.c b/gcc/testsuite/c-c++-common/ubsan/float-div-by-zero-1.c new file mode 100644 index 00000000000..2271ea9b776 --- /dev/null +++ b/gcc/testsuite/c-c++-common/ubsan/float-div-by-zero-1.c @@ -0,0 +1,26 @@ +/* { dg-do run } */ +/* { dg-options "-fsanitize=float-divide-by-zero" } */ + +int +main (void) +{ + volatile float a = 1.3f; + volatile double b = 0.0; + volatile int c = 4; + volatile float res; + + res = a / b; + res = a / 0.0; + res = 2.7f / b; + res = 3.6 / (b = 0.0, b); + res = c / b; + res = b / c; + + return 0; +} + +/* { dg-output "division by zero\[^\n\r]*(\n|\r\n|\r)" } */ +/* { dg-output "\[^\n\r]*division by zero\[^\n\r]*(\n|\r\n|\r)" } */ +/* { dg-output "\[^\n\r]*division by zero\[^\n\r]*(\n|\r\n|\r)" } */ +/* { dg-output "\[^\n\r]*division by zero\[^\n\r]*(\n|\r\n|\r)" } */ +/* { dg-output "\[^\n\r]*division by zero\[^\n\r]*" } */ diff --git a/gcc/testsuite/g++.dg/cpp0x/constexpr-51707.C b/gcc/testsuite/g++.dg/cpp0x/constexpr-51707.C new file mode 100644 index 00000000000..ae02a31c540 --- /dev/null +++ b/gcc/testsuite/g++.dg/cpp0x/constexpr-51707.C @@ -0,0 +1,14 @@ +// PR c++/51707 +// { dg-do compile { target c++11 } } + +struct S { + constexpr S() {} +}; + +struct T { + constexpr T(S const& s) : s{s} {} + S const& s; +}; + +constexpr S s {}; +constexpr T t { s }; diff --git a/gcc/testsuite/g++.dg/cpp0x/constexpr-aggr1.C b/gcc/testsuite/g++.dg/cpp0x/constexpr-aggr1.C new file mode 100644 index 00000000000..7e4da11a2df --- /dev/null +++ b/gcc/testsuite/g++.dg/cpp0x/constexpr-aggr1.C @@ -0,0 +1,17 @@ +// PR c++/60951 +// { dg-do compile { target c++11 } } + +struct Foo { + constexpr Foo(int x = 0) : memb(x) {} + int memb; +}; + +struct FooContainer { + Foo foo[2]; +}; + +void fubar() { + int nonConst = 0; + FooContainer fooContainer; + fooContainer = { { 0, nonConst } }; +} diff --git a/gcc/testsuite/g++.dg/cpp0x/defaulted49.C b/gcc/testsuite/g++.dg/cpp0x/defaulted49.C new file mode 100644 index 00000000000..357be419db7 --- /dev/null +++ b/gcc/testsuite/g++.dg/cpp0x/defaulted49.C @@ -0,0 +1,15 @@ +// PR c++/60980 +// { dg-do compile { target c++11 } } + +struct x0 +{ + x0 () = default; +}; +struct x1 +{ + x0 x2[2]; + void x3 () + { + x1 (); + } +}; diff --git a/gcc/testsuite/g++.dg/cpp0x/nsdmi-defer6.C b/gcc/testsuite/g++.dg/cpp0x/nsdmi-defer6.C index 033c14264dd..0f06343958b 100644 --- a/gcc/testsuite/g++.dg/cpp0x/nsdmi-defer6.C +++ b/gcc/testsuite/g++.dg/cpp0x/nsdmi-defer6.C @@ -1,8 +1,8 @@ // { dg-do compile { target c++11 } } -struct A // { dg-error "non-static data member" } +struct A { - int i = (A(), 42); // { dg-message "required here" } + int i = (A(), 42); // { dg-error "constructor required" } }; A a; diff --git a/gcc/testsuite/g++.dg/cpp0x/nsdmi-dr1397.C b/gcc/testsuite/g++.dg/cpp0x/nsdmi-dr1397.C new file mode 100644 index 00000000000..061af8b8c29 --- /dev/null +++ b/gcc/testsuite/g++.dg/cpp0x/nsdmi-dr1397.C @@ -0,0 +1,7 @@ +// DR 1397 +// { dg-require-effective-target c++11 } + +struct A +{ + int i = sizeof(A{}); // { dg-error "" } +}; diff --git a/gcc/testsuite/g++.dg/cpp0x/nsdmi-eh1.C b/gcc/testsuite/g++.dg/cpp0x/nsdmi-eh1.C index edcf5887db1..9bc632c4bc7 100644 --- a/gcc/testsuite/g++.dg/cpp0x/nsdmi-eh1.C +++ b/gcc/testsuite/g++.dg/cpp0x/nsdmi-eh1.C @@ -1,5 +1,5 @@ // Core issue 1351 -// { dg-do run { xfail *-*-* } } +// { dg-do run } // { dg-require-effective-target c++11 } bool fail; diff --git a/gcc/testsuite/gcc.dg/pr60139.c b/gcc/testsuite/gcc.dg/pr60139.c new file mode 100644 index 00000000000..a63d8b5b9bd --- /dev/null +++ b/gcc/testsuite/gcc.dg/pr60139.c @@ -0,0 +1,14 @@ +/* PR c/60139 */ +/* { dg-do compile } */ +/* { dg-options "-Wpedantic" } */ +/* { dg-prune-output ".*near initialization for.*" } */ + +double sin (double); +void +fn (int *p) +{ + int **a[] = { &p, /* { dg-warning "17:initializer element is not computable at load time" } */ + (void *) 0, &p }; /* { dg-warning "28:initializer element is not computable at load time" } */ + double d[] = { sin (1.0), /* { dg-warning "18:initializer element is not a constant expression" } */ + 8.8, sin (1.0), 2.6 }; /* { dg-warning "23:initializer element is not a constant expression" } */ +} diff --git a/gcc/testsuite/gcc.dg/pr60351.c b/gcc/testsuite/gcc.dg/pr60351.c new file mode 100644 index 00000000000..29184d94872 --- /dev/null +++ b/gcc/testsuite/gcc.dg/pr60351.c @@ -0,0 +1,11 @@ +/* PR c/60351 */ +/* { dg-do compile } */ + +void +f (int i) +{ + i >> -1; /* { dg-warning "5:right shift count is negative" } */ + i >> 250; /* { dg-warning "5:right shift count >= width of type" } */ + i << -1; /* { dg-warning "5:left shift count is negative" } */ + i << 250; /* { dg-warning "5:left shift count >= width of type" } */ +} diff --git a/gcc/testsuite/gcc.dg/tree-ssa/alias-32.c b/gcc/testsuite/gcc.dg/tree-ssa/alias-32.c new file mode 100644 index 00000000000..5d0dcc2937e --- /dev/null +++ b/gcc/testsuite/gcc.dg/tree-ssa/alias-32.c @@ -0,0 +1,20 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -fdump-tree-cddce1" } */ + +int bar (short *p) +{ + int res = *p; + struct { int *q1; int *q2; } q; + q.q1 = __builtin_aligned_alloc (128, 128 * sizeof (int)); + q.q2 = __builtin_aligned_alloc (128, 128 * sizeof (int)); + *q.q1 = 1; + *q.q2 = 2; + return res + *p + *q.q1 + *q.q2; +} + +/* There should be only one load from *p left. All stores and all + other loads should be removed. Likewise the calls to aligned_alloc. */ + +/* { dg-final { scan-tree-dump-times "\\\*\[^ \]" 1 "cddce1" } } */ +/* { dg-final { scan-tree-dump-not "aligned_alloc" "cddce1" } } */ +/* { dg-final { cleanup-tree-dump "cddce1" } } */ diff --git a/gcc/testsuite/gcc.dg/tree-ssa/pr23401.c b/gcc/testsuite/gcc.dg/tree-ssa/pr23401.c index 1d30ac7519f..3940692cd6c 100644 --- a/gcc/testsuite/gcc.dg/tree-ssa/pr23401.c +++ b/gcc/testsuite/gcc.dg/tree-ssa/pr23401.c @@ -19,6 +19,6 @@ int ffff(int i) /* We should not use extra temporaries apart from for i1 + i2. */ -/* { dg-final { scan-tree-dump-times "int" 5 "gimple" } } */ +/* { dg-final { scan-tree-dump-times "int" 6 "gimple" } } */ /* { dg-final { scan-tree-dump-times "int D\\\." 1 "gimple" } } */ /* { dg-final { cleanup-tree-dump "gimple" } } */ diff --git a/gcc/testsuite/gcc.dg/tree-ssa/pr27810.c b/gcc/testsuite/gcc.dg/tree-ssa/pr27810.c index c7da3bd5d06..6d0904bb06b 100644 --- a/gcc/testsuite/gcc.dg/tree-ssa/pr27810.c +++ b/gcc/testsuite/gcc.dg/tree-ssa/pr27810.c @@ -13,6 +13,6 @@ int qqq (int a) /* We should not use an extra temporary for the result of the function call. */ -/* { dg-final { scan-tree-dump-times "int" 3 "gimple" } } */ +/* { dg-final { scan-tree-dump-times "int" 4 "gimple" } } */ /* { dg-final { scan-tree-dump-times "int D\\\." 1 "gimple" } } */ /* { dg-final { cleanup-tree-dump "gimple" } } */ diff --git a/gcc/testsuite/gcc.dg/tree-ssa/sra-14.c b/gcc/testsuite/gcc.dg/tree-ssa/sra-14.c new file mode 100644 index 00000000000..6cbc0b43d58 --- /dev/null +++ b/gcc/testsuite/gcc.dg/tree-ssa/sra-14.c @@ -0,0 +1,70 @@ +/* { dg-do run } */ +/* { dg-options "-O1" } */ + +struct S +{ + int i, j; +}; + +struct Z +{ + struct S d, s; +}; + +struct S __attribute__ ((noinline, noclone)) +get_s (void) +{ + struct S s; + s.i = 5; + s.j = 6; + + return s; +} + +struct S __attribute__ ((noinline, noclone)) +get_d (void) +{ + struct S d; + d.i = 0; + d.j = 0; + + return d; +} + +int __attribute__ ((noinline, noclone)) +get_c (void) +{ + return 1; +} + +int __attribute__ ((noinline, noclone)) +my_nop (int i) +{ + return i; +} + +int __attribute__ ((noinline, noclone)) +foo (void) +{ + struct Z z; + int i, c = get_c (); + + z.d = get_d (); + z.s = get_s (); + + for (i = 0; i < c; i++) + { + z.s.i = my_nop (z.s.i); + z.s.j = my_nop (z.s.j); + } + + return z.s.i + z.s.j; +} + +int main (int argc, char *argv[]) +{ + if (foo () != 11) + __builtin_abort (); + return 0; +} + diff --git a/gcc/testsuite/gcc.dg/vect/pr60092.c b/gcc/testsuite/gcc.dg/vect/pr60092.c new file mode 100644 index 00000000000..e03c625b489 --- /dev/null +++ b/gcc/testsuite/gcc.dg/vect/pr60092.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target vect_int } */ + +int *foo (int n) +{ + int *p = __builtin_aligned_alloc (256, n * sizeof (int)); + int *q = __builtin_aligned_alloc (256, n * sizeof (int)); + bar (q); + int i; + for (i = 0; i < n; ++i) + p[i] = q[i] + q[i]; + return p; +} + +/* { dg-final { scan-tree-dump "LOOP VECTORIZED" "vect" } } */ +/* { dg-final { scan-tree-dump-not "Peeling for alignment will be applied" "vect" } } */ +/* { dg-final { scan-tree-dump-not "Vectorizing an unaligned access" "vect" } } */ +/* { dg-final { cleanup-tree-dump "vect" } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/fcsel_1.c b/gcc/testsuite/gcc.target/aarch64/fcsel_1.c new file mode 100644 index 00000000000..2704ee0ede7 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/fcsel_1.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-options " -O2 " } */ + +float +f_1 (float a, float b, float c, float d) +{ + if (a > 0.0) + return c; + else + return 2.0; +} + +double +f_2 (double a, double b, double c, double d) +{ + if (a > b) + return c; + else + return d; +} + +/* { dg-final { scan-assembler-times "\tfcsel" 2 } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/simd/simd.exp b/gcc/testsuite/gcc.target/aarch64/simd/simd.exp new file mode 100644 index 00000000000..097d29a9e13 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/simd/simd.exp @@ -0,0 +1,45 @@ +# Specific regression driver for AArch64 SIMD instructions. +# Copyright (C) 2014 Free Software Foundation, Inc. +# Contributed by ARM Ltd. +# +# This file is part of GCC. +# +# GCC is free software; you can redistribute it and/or modify it +# under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 3, or (at your option) +# any later version. +# +# GCC is distributed in the hope that it will be useful, but +# WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +# General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with GCC; see the file COPYING3. If not see +# <http://www.gnu.org/licenses/>. */ + +# GCC testsuite that uses the `dg.exp' driver. + +# Exit immediately if this isn't an AArch64 target. +if {![istarget aarch64*-*-*] } then { + return +} + +# Load support procs. +load_lib gcc-dg.exp + +# If a testcase doesn't have special options, use these. +global DEFAULT_CFLAGS +if ![info exists DEFAULT_CFLAGS] then { + set DEFAULT_CFLAGS " -ansi -pedantic-errors" +} + +# Initialize `dg'. +dg-init + +# Main loop. +dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.\[cCS\]]] \ + "" $DEFAULT_CFLAGS + +# All done. +dg-finish diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vuzpf32.x b/gcc/testsuite/gcc.target/aarch64/simd/vuzpf32.x new file mode 100644 index 00000000000..86c3700e522 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/simd/vuzpf32.x @@ -0,0 +1,26 @@ +extern void abort (void); + +float32x2x2_t +test_vuzpf32 (float32x2_t _a, float32x2_t _b) +{ + return vuzp_f32 (_a, _b); +} + +int +main (int argc, char **argv) +{ + int i; + float32_t first[] = {1, 2}; + float32_t second[] = {3, 4}; + float32x2x2_t result = test_vuzpf32 (vld1_f32 (first), vld1_f32 (second)); + float32_t exp1[] = {1, 3}; + float32_t exp2[] = {2, 4}; + float32x2_t expect1 = vld1_f32 (exp1); + float32x2_t expect2 = vld1_f32 (exp2); + + for (i = 0; i < 2; i++) + if ((result.val[0][i] != expect1[i]) || (result.val[1][i] != expect2[i])) + abort (); + + return 0; +} diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vuzpf32_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vuzpf32_1.c new file mode 100644 index 00000000000..0daba1c7f93 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/simd/vuzpf32_1.c @@ -0,0 +1,11 @@ +/* Test the `vuzp_f32' AArch64 SIMD intrinsic. */ + +/* { dg-do run } */ +/* { dg-options "-save-temps -fno-inline" } */ + +#include <arm_neon.h> +#include "vuzpf32.x" + +/* { dg-final { scan-assembler-times "zip1\[ \t\]+v\[0-9\]+\.2s, ?v\[0-9\]+\.2s, ?v\[0-9\]+\.2s!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */ +/* { dg-final { scan-assembler-times "zip2\[ \t\]+v\[0-9\]+\.2s, ?v\[0-9\]+\.2s, ?v\[0-9\]+\.2s!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vuzpp16.x b/gcc/testsuite/gcc.target/aarch64/simd/vuzpp16.x new file mode 100644 index 00000000000..bc45efcd965 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/simd/vuzpp16.x @@ -0,0 +1,26 @@ +extern void abort (void); + +poly16x4x2_t +test_vuzpp16 (poly16x4_t _a, poly16x4_t _b) +{ + return vuzp_p16 (_a, _b); +} + +int +main (int argc, char **argv) +{ + int i; + poly16_t first[] = {1, 2, 3, 4}; + poly16_t second[] = {5, 6, 7, 8}; + poly16x4x2_t result = test_vuzpp16 (vld1_p16 (first), vld1_p16 (second)); + poly16_t exp1[] = {1, 3, 5, 7}; + poly16_t exp2[] = {2, 4, 6, 8}; + poly16x4_t expect1 = vld1_p16 (exp1); + poly16x4_t expect2 = vld1_p16 (exp2); + + for (i = 0; i < 4; i++) + if ((result.val[0][i] != expect1[i]) || (result.val[1][i] != expect2[i])) + abort (); + + return 0; +} diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vuzpp16_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vuzpp16_1.c new file mode 100644 index 00000000000..03b07220640 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/simd/vuzpp16_1.c @@ -0,0 +1,11 @@ +/* Test the `vuzp_p16' AArch64 SIMD intrinsic. */ + +/* { dg-do run } */ +/* { dg-options "-save-temps -fno-inline" } */ + +#include <arm_neon.h> +#include "vuzpp16.x" + +/* { dg-final { scan-assembler-times "uzp1\[ \t\]+v\[0-9\]+\.4h, ?v\[0-9\]+\.4h, ?v\[0-9\]+\.4h!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */ +/* { dg-final { scan-assembler-times "uzp2\[ \t\]+v\[0-9\]+\.4h, ?v\[0-9\]+\.4h, ?v\[0-9\]+\.4h!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vuzpp8.x b/gcc/testsuite/gcc.target/aarch64/simd/vuzpp8.x new file mode 100644 index 00000000000..b4ef51cae74 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/simd/vuzpp8.x @@ -0,0 +1,26 @@ +extern void abort (void); + +poly8x8x2_t +test_vuzpp8 (poly8x8_t _a, poly8x8_t _b) +{ + return vuzp_p8 (_a, _b); +} + +int +main (int argc, char **argv) +{ + int i; + poly8_t first[] = {1, 2, 3, 4, 5, 6, 7, 8}; + poly8_t second[] = {9, 10, 11, 12, 13, 14, 15, 16}; + poly8x8x2_t result = test_vuzpp8 (vld1_p8 (first), vld1_p8 (second)); + poly8_t exp1[] = {1, 3, 5, 7, 9, 11, 13, 15}; + poly8_t exp2[] = {2, 4, 6, 8, 10, 12, 14, 16}; + poly8x8_t expect1 = vld1_p8 (exp1); + poly8x8_t expect2 = vld1_p8 (exp2); + + for (i = 0; i < 8; i++) + if ((result.val[0][i] != expect1[i]) || (result.val[1][i] != expect2[i])) + abort (); + + return 0; +} diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vuzpp8_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vuzpp8_1.c new file mode 100644 index 00000000000..5186b1f9166 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/simd/vuzpp8_1.c @@ -0,0 +1,11 @@ +/* Test the `vuzp_p8' AArch64 SIMD intrinsic. */ + +/* { dg-do run } */ +/* { dg-options "-save-temps -fno-inline" } */ + +#include <arm_neon.h> +#include "vuzpp8.x" + +/* { dg-final { scan-assembler-times "uzp1\[ \t\]+v\[0-9\]+\.8b, ?v\[0-9\]+\.8b, ?v\[0-9\]+\.8b!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */ +/* { dg-final { scan-assembler-times "uzp2\[ \t\]+v\[0-9\]+\.8b, ?v\[0-9\]+\.8b, ?v\[0-9\]+\.8b!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vuzpqf32.x b/gcc/testsuite/gcc.target/aarch64/simd/vuzpqf32.x new file mode 100644 index 00000000000..f1b48da315f --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/simd/vuzpqf32.x @@ -0,0 +1,26 @@ +extern void abort (void); + +float32x4x2_t +test_vuzpqf32 (float32x4_t _a, float32x4_t _b) +{ + return vuzpq_f32 (_a, _b); +} + +int +main (int argc, char **argv) +{ + int i; + float32_t first[] = {1, 2, 3, 4}; + float32_t second[] = {5, 6, 7, 8}; + float32x4x2_t result = test_vuzpqf32 (vld1q_f32 (first), vld1q_f32 (second)); + float32_t exp1[] = {1, 3, 5, 7}; + float32_t exp2[] = {2, 4, 6, 8}; + float32x4_t expect1 = vld1q_f32 (exp1); + float32x4_t expect2 = vld1q_f32 (exp2); + + for (i = 0; i < 4; i++) + if ((result.val[0][i] != expect1[i]) || (result.val[1][i] != expect2[i])) + abort (); + + return 0; +} diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vuzpqf32_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vuzpqf32_1.c new file mode 100644 index 00000000000..1167f7bbe00 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/simd/vuzpqf32_1.c @@ -0,0 +1,11 @@ +/* Test the `vuzpq_f32' AArch64 SIMD intrinsic. */ + +/* { dg-do run } */ +/* { dg-options "-save-temps -fno-inline" } */ + +#include <arm_neon.h> +#include "vuzpqf32.x" + +/* { dg-final { scan-assembler-times "uzp1\[ \t\]+v\[0-9\]+\.4s, ?v\[0-9\]+\.4s, ?v\[0-9\]+\.4s!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */ +/* { dg-final { scan-assembler-times "uzp2\[ \t\]+v\[0-9\]+\.4s, ?v\[0-9\]+\.4s, ?v\[0-9\]+\.4s!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vuzpqp16.x b/gcc/testsuite/gcc.target/aarch64/simd/vuzpqp16.x new file mode 100644 index 00000000000..d4e08f74631 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/simd/vuzpqp16.x @@ -0,0 +1,26 @@ +extern void abort (void); + +poly16x8x2_t +test_vuzpqp16 (poly16x8_t _a, poly16x8_t _b) +{ + return vuzpq_p16 (_a, _b); +} + +int +main (int argc, char **argv) +{ + int i; + poly16_t first[] = {1, 2, 3, 4, 5, 6, 7, 8}; + poly16_t second[] = {9, 10, 11, 12, 13, 14, 15, 16}; + poly16x8x2_t result = test_vuzpqp16 (vld1q_p16 (first), vld1q_p16 (second)); + poly16_t exp1[] = {1, 3, 5, 7, 9, 11, 13, 15}; + poly16_t exp2[] = {2, 4, 6, 8, 10, 12, 14, 16}; + poly16x8_t expect1 = vld1q_p16 (exp1); + poly16x8_t expect2 = vld1q_p16 (exp2); + + for (i = 0; i < 8; i++) + if ((result.val[0][i] != expect1[i]) || (result.val[1][i] != expect2[i])) + abort (); + + return 0; +} diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vuzpqp16_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vuzpqp16_1.c new file mode 100644 index 00000000000..c6648045cf3 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/simd/vuzpqp16_1.c @@ -0,0 +1,11 @@ +/* Test the `vuzpq_p16' AArch64 SIMD intrinsic. */ + +/* { dg-do run } */ +/* { dg-options "-save-temps -fno-inline" } */ + +#include <arm_neon.h> +#include "vuzpqp16.x" + +/* { dg-final { scan-assembler-times "uzp1\[ \t\]+v\[0-9\]+\.8h, ?v\[0-9\]+\.8h, ?v\[0-9\]+\.8h!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */ +/* { dg-final { scan-assembler-times "uzp2\[ \t\]+v\[0-9\]+\.8h, ?v\[0-9\]+\.8h, ?v\[0-9\]+\.8h!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vuzpqp8.x b/gcc/testsuite/gcc.target/aarch64/simd/vuzpqp8.x new file mode 100644 index 00000000000..31541de7e14 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/simd/vuzpqp8.x @@ -0,0 +1,27 @@ +extern void abort (void); + +poly8x16x2_t +test_vuzpqp8 (poly8x16_t _a, poly8x16_t _b) +{ + return vuzpq_p8 (_a, _b); +} + +int +main (int argc, char **argv) +{ + int i; + poly8_t first[] = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16}; + poly8_t second[] = + {17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32}; + poly8x16x2_t result = test_vuzpqp8 (vld1q_p8 (first), vld1q_p8 (second)); + poly8_t exp1[] = {1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31}; + poly8_t exp2[] = {2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30, 32}; + poly8x16_t expect1 = vld1q_p8 (exp1); + poly8x16_t expect2 = vld1q_p8 (exp2); + + for (i = 0; i < 16; i++) + if ((result.val[0][i] != expect1[i]) || (result.val[1][i] != expect2[i])) + abort (); + + return 0; +} diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vuzpqp8_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vuzpqp8_1.c new file mode 100644 index 00000000000..a9e6ce222e7 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/simd/vuzpqp8_1.c @@ -0,0 +1,11 @@ +/* Test the `vuzpq_p8' AArch64 SIMD intrinsic. */ + +/* { dg-do run } */ +/* { dg-options "-save-temps -fno-inline" } */ + +#include <arm_neon.h> +#include "vuzpqp8.x" + +/* { dg-final { scan-assembler-times "uzp1\[ \t\]+v\[0-9\]+\.16b, ?v\[0-9\]+\.16b, ?v\[0-9\]+\.16b!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */ +/* { dg-final { scan-assembler-times "uzp2\[ \t\]+v\[0-9\]+\.16b, ?v\[0-9\]+\.16b, ?v\[0-9\]+\.16b!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vuzpqs16.x b/gcc/testsuite/gcc.target/aarch64/simd/vuzpqs16.x new file mode 100644 index 00000000000..439107b2ec5 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/simd/vuzpqs16.x @@ -0,0 +1,26 @@ +extern void abort (void); + +int16x8x2_t +test_vuzpqs16 (int16x8_t _a, int16x8_t _b) +{ + return vuzpq_s16 (_a, _b); +} + +int +main (int argc, char **argv) +{ + int i; + int16_t first[] = {1, 2, 3, 4, 5, 6, 7, 8}; + int16_t second[] = {9, 10, 11, 12, 13, 14, 15, 16}; + int16x8x2_t result = test_vuzpqs16 (vld1q_s16 (first), vld1q_s16 (second)); + int16_t exp1[] = {1, 3, 5, 7, 9, 11, 13, 15}; + int16_t exp2[] = {2, 4, 6, 8, 10, 12, 14, 16}; + int16x8_t expect1 = vld1q_s16 (exp1); + int16x8_t expect2 = vld1q_s16 (exp2); + + for (i = 0; i < 8; i++) + if ((result.val[0][i] != expect1[i]) || (result.val[1][i] != expect2[i])) + abort (); + + return 0; +} diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vuzpqs16_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vuzpqs16_1.c new file mode 100644 index 00000000000..af1e28b7669 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/simd/vuzpqs16_1.c @@ -0,0 +1,11 @@ +/* Test the `vuzpq_s16' AArch64 SIMD intrinsic. */ + +/* { dg-do run } */ +/* { dg-options "-save-temps -fno-inline" } */ + +#include <arm_neon.h> +#include "vuzpqs16.x" + +/* { dg-final { scan-assembler-times "uzp1\[ \t\]+v\[0-9\]+\.8h, ?v\[0-9\]+\.8h, ?v\[0-9\]+\.8h!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */ +/* { dg-final { scan-assembler-times "uzp2\[ \t\]+v\[0-9\]+\.8h, ?v\[0-9\]+\.8h, ?v\[0-9\]+\.8h!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vuzpqs32.x b/gcc/testsuite/gcc.target/aarch64/simd/vuzpqs32.x new file mode 100644 index 00000000000..84463f038e5 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/simd/vuzpqs32.x @@ -0,0 +1,26 @@ +extern void abort (void); + +int32x4x2_t +test_vuzpqs32 (int32x4_t _a, int32x4_t _b) +{ + return vuzpq_s32 (_a, _b); +} + +int +main (int argc, char **argv) +{ + int i; + int32_t first[] = {1, 2, 3, 4}; + int32_t second[] = {5, 6, 7, 8}; + int32x4x2_t result = test_vuzpqs32 (vld1q_s32 (first), vld1q_s32 (second)); + int32_t exp1[] = {1, 3, 5, 7}; + int32_t exp2[] = {2, 4, 6, 8}; + int32x4_t expect1 = vld1q_s32 (exp1); + int32x4_t expect2 = vld1q_s32 (exp2); + + for (i = 0; i < 4; i++) + if ((result.val[0][i] != expect1[i]) || (result.val[1][i] != expect2[i])) + abort (); + + return 0; +} diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vuzpqs32_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vuzpqs32_1.c new file mode 100644 index 00000000000..a4bf7ac7e59 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/simd/vuzpqs32_1.c @@ -0,0 +1,11 @@ +/* Test the `vuzpq_s32' AArch64 SIMD intrinsic. */ + +/* { dg-do run } */ +/* { dg-options "-save-temps -fno-inline" } */ + +#include <arm_neon.h> +#include "vuzpqs32.x" + +/* { dg-final { scan-assembler-times "uzp1\[ \t\]+v\[0-9\]+\.4s, ?v\[0-9\]+\.4s, ?v\[0-9\]+\.4s!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */ +/* { dg-final { scan-assembler-times "uzp2\[ \t\]+v\[0-9\]+\.4s, ?v\[0-9\]+\.4s, ?v\[0-9\]+\.4s!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vuzpqs8.x b/gcc/testsuite/gcc.target/aarch64/simd/vuzpqs8.x new file mode 100644 index 00000000000..c8b916780d7 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/simd/vuzpqs8.x @@ -0,0 +1,27 @@ +extern void abort (void); + +int8x16x2_t +test_vuzpqs8 (int8x16_t _a, int8x16_t _b) +{ + return vuzpq_s8 (_a, _b); +} + +int +main (int argc, char **argv) +{ + int i; + int8_t first[] = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16}; + int8_t second[] = + {17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32}; + int8x16x2_t result = test_vuzpqs8 (vld1q_s8 (first), vld1q_s8 (second)); + int8_t exp1[] = {1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31}; + int8_t exp2[] = {2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30, 32}; + int8x16_t expect1 = vld1q_s8 (exp1); + int8x16_t expect2 = vld1q_s8 (exp2); + + for (i = 0; i < 16; i++) + if ((result.val[0][i] != expect1[i]) || (result.val[1][i] != expect2[i])) + abort (); + + return 0; +} diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vuzpqs8_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vuzpqs8_1.c new file mode 100644 index 00000000000..234a3292823 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/simd/vuzpqs8_1.c @@ -0,0 +1,11 @@ +/* Test the `vuzpq_s8' AArch64 SIMD intrinsic. */ + +/* { dg-do run } */ +/* { dg-options "-save-temps -fno-inline" } */ + +#include <arm_neon.h> +#include "vuzpqs8.x" + +/* { dg-final { scan-assembler-times "uzp1\[ \t\]+v\[0-9\]+\.16b, ?v\[0-9\]+\.16b, ?v\[0-9\]+\.16b!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */ +/* { dg-final { scan-assembler-times "uzp2\[ \t\]+v\[0-9\]+\.16b, ?v\[0-9\]+\.16b, ?v\[0-9\]+\.16b!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vuzpqu16.x b/gcc/testsuite/gcc.target/aarch64/simd/vuzpqu16.x new file mode 100644 index 00000000000..1757467b467 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/simd/vuzpqu16.x @@ -0,0 +1,26 @@ +extern void abort (void); + +uint16x8x2_t +test_vuzpqu16 (uint16x8_t _a, uint16x8_t _b) +{ + return vuzpq_u16 (_a, _b); +} + +int +main (int argc, char **argv) +{ + int i; + uint16_t first[] = {1, 2, 3, 4, 5, 6, 7, 8}; + uint16_t second[] = {9, 10, 11, 12, 13, 14, 15, 16}; + uint16x8x2_t result = test_vuzpqu16 (vld1q_u16 (first), vld1q_u16 (second)); + uint16_t exp1[] = {1, 3, 5, 7, 9, 11, 13, 15}; + uint16_t exp2[] = {2, 4, 6, 8, 10, 12, 14, 16}; + uint16x8_t expect1 = vld1q_u16 (exp1); + uint16x8_t expect2 = vld1q_u16 (exp2); + + for (i = 0; i < 8; i++) + if ((result.val[0][i] != expect1[i]) || (result.val[1][i] != expect2[i])) + abort (); + + return 0; +} diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vuzpqu16_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vuzpqu16_1.c new file mode 100644 index 00000000000..3f029ed5439 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/simd/vuzpqu16_1.c @@ -0,0 +1,11 @@ +/* Test the `vuzpq_u16' AArch64 SIMD intrinsic. */ + +/* { dg-do run } */ +/* { dg-options "-save-temps -fno-inline" } */ + +#include <arm_neon.h> +#include "vuzpqu16.x" + +/* { dg-final { scan-assembler-times "uzp1\[ \t\]+v\[0-9\]+\.8h, ?v\[0-9\]+\.8h, ?v\[0-9\]+\.8h!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */ +/* { dg-final { scan-assembler-times "uzp2\[ \t\]+v\[0-9\]+\.8h, ?v\[0-9\]+\.8h, ?v\[0-9\]+\.8h!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vuzpqu32.x b/gcc/testsuite/gcc.target/aarch64/simd/vuzpqu32.x new file mode 100644 index 00000000000..9ff23694c29 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/simd/vuzpqu32.x @@ -0,0 +1,26 @@ +extern void abort (void); + +uint32x4x2_t +test_vuzpqu32 (uint32x4_t _a, uint32x4_t _b) +{ + return vuzpq_u32 (_a, _b); +} + +int +main (int argc, char **argv) +{ + int i; + uint32_t first[] = {1, 2, 3, 4}; + uint32_t second[] = {5, 6, 7, 8}; + uint32x4x2_t result = test_vuzpqu32 (vld1q_u32 (first), vld1q_u32 (second)); + uint32_t exp1[] = {1, 3, 5, 7}; + uint32_t exp2[] = {2, 4, 6, 8}; + uint32x4_t expect1 = vld1q_u32 (exp1); + uint32x4_t expect2 = vld1q_u32 (exp2); + + for (i = 0; i < 4; i++) + if ((result.val[0][i] != expect1[i]) || (result.val[1][i] != expect2[i])) + abort (); + + return 0; +} diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vuzpqu32_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vuzpqu32_1.c new file mode 100644 index 00000000000..16090eed712 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/simd/vuzpqu32_1.c @@ -0,0 +1,11 @@ +/* Test the `vuzpq_u32' AArch64 SIMD intrinsic. */ + +/* { dg-do run } */ +/* { dg-options "-save-temps -fno-inline" } */ + +#include <arm_neon.h> +#include "vuzpqu32.x" + +/* { dg-final { scan-assembler-times "uzp1\[ \t\]+v\[0-9\]+\.4s, ?v\[0-9\]+\.4s, ?v\[0-9\]+\.4s!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */ +/* { dg-final { scan-assembler-times "uzp2\[ \t\]+v\[0-9\]+\.4s, ?v\[0-9\]+\.4s, ?v\[0-9\]+\.4s!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vuzpqu8.x b/gcc/testsuite/gcc.target/aarch64/simd/vuzpqu8.x new file mode 100644 index 00000000000..1f5288d0ce3 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/simd/vuzpqu8.x @@ -0,0 +1,27 @@ +extern void abort (void); + +uint8x16x2_t +test_vuzpqu8 (uint8x16_t _a, uint8x16_t _b) +{ + return vuzpq_u8 (_a, _b); +} + +int +main (int argc, char **argv) +{ + int i; + uint8_t first[] = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16}; + uint8_t second[] = + {17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32}; + uint8x16x2_t result = test_vuzpqu8 (vld1q_u8 (first), vld1q_u8 (second)); + uint8_t exp1[] = {1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31}; + uint8_t exp2[] = {2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30, 32}; + uint8x16_t expect1 = vld1q_u8 (exp1); + uint8x16_t expect2 = vld1q_u8 (exp2); + + for (i = 0; i < 16; i++) + if ((result.val[0][i] != expect1[i]) || (result.val[1][i] != expect2[i])) + abort (); + + return 0; +} diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vuzpqu8_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vuzpqu8_1.c new file mode 100644 index 00000000000..6313e4c9b5d --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/simd/vuzpqu8_1.c @@ -0,0 +1,11 @@ +/* Test the `vuzpq_u8' AArch64 SIMD intrinsic. */ + +/* { dg-do run } */ +/* { dg-options "-save-temps -fno-inline" } */ + +#include <arm_neon.h> +#include "vuzpqu8.x" + +/* { dg-final { scan-assembler-times "uzp1\[ \t\]+v\[0-9\]+\.16b, ?v\[0-9\]+\.16b, ?v\[0-9\]+\.16b!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */ +/* { dg-final { scan-assembler-times "uzp2\[ \t\]+v\[0-9\]+\.16b, ?v\[0-9\]+\.16b, ?v\[0-9\]+\.16b!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vuzps16.x b/gcc/testsuite/gcc.target/aarch64/simd/vuzps16.x new file mode 100644 index 00000000000..4775135d842 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/simd/vuzps16.x @@ -0,0 +1,26 @@ +extern void abort (void); + +int16x4x2_t +test_vuzps16 (int16x4_t _a, int16x4_t _b) +{ + return vuzp_s16 (_a, _b); +} + +int +main (int argc, char **argv) +{ + int i; + int16_t first[] = {1, 2, 3, 4}; + int16_t second[] = {5, 6, 7, 8}; + int16x4x2_t result = test_vuzps16 (vld1_s16 (first), vld1_s16 (second)); + int16_t exp1[] = {1, 3, 5, 7}; + int16_t exp2[] = {2, 4, 6, 8}; + int16x4_t expect1 = vld1_s16 (exp1); + int16x4_t expect2 = vld1_s16 (exp2); + + for (i = 0; i < 4; i++) + if ((result.val[0][i] != expect1[i]) || (result.val[1][i] != expect2[i])) + abort (); + + return 0; +} diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vuzps16_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vuzps16_1.c new file mode 100644 index 00000000000..f31bd31d0bf --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/simd/vuzps16_1.c @@ -0,0 +1,11 @@ +/* Test the `vuzp_s16' AArch64 SIMD intrinsic. */ + +/* { dg-do run } */ +/* { dg-options "-save-temps -fno-inline" } */ + +#include <arm_neon.h> +#include "vuzps16.x" + +/* { dg-final { scan-assembler-times "uzp1\[ \t\]+v\[0-9\]+\.4h, ?v\[0-9\]+\.4h, ?v\[0-9\]+\.4h!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */ +/* { dg-final { scan-assembler-times "uzp2\[ \t\]+v\[0-9\]+\.4h, ?v\[0-9\]+\.4h, ?v\[0-9\]+\.4h!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vuzps32.x b/gcc/testsuite/gcc.target/aarch64/simd/vuzps32.x new file mode 100644 index 00000000000..6f885ce083b --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/simd/vuzps32.x @@ -0,0 +1,26 @@ +extern void abort (void); + +int32x2x2_t +test_vuzps32 (int32x2_t _a, int32x2_t _b) +{ + return vuzp_s32 (_a, _b); +} + +int +main (int argc, char **argv) +{ + int i; + int32_t first[] = {1, 2}; + int32_t second[] = {3, 4}; + int32x2x2_t result = test_vuzps32 (vld1_s32 (first), vld1_s32 (second)); + int32_t exp1[] = {1, 3}; + int32_t exp2[] = {2, 4}; + int32x2_t expect1 = vld1_s32 (exp1); + int32x2_t expect2 = vld1_s32 (exp2); + + for (i = 0; i < 2; i++) + if ((result.val[0][i] != expect1[i]) || (result.val[1][i] != expect2[i])) + abort (); + + return 0; +} diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vuzps32_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vuzps32_1.c new file mode 100644 index 00000000000..af48d63a67e --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/simd/vuzps32_1.c @@ -0,0 +1,11 @@ +/* Test the `vuzp_s32' AArch64 SIMD intrinsic. */ + +/* { dg-do run } */ +/* { dg-options "-save-temps -fno-inline" } */ + +#include <arm_neon.h> +#include "vuzps32.x" + +/* { dg-final { scan-assembler-times "zip1\[ \t\]+v\[0-9\]+\.2s, ?v\[0-9\]+\.2s, ?v\[0-9\]+\.2s!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */ +/* { dg-final { scan-assembler-times "zip2\[ \t\]+v\[0-9\]+\.2s, ?v\[0-9\]+\.2s, ?v\[0-9\]+\.2s!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vuzps8.x b/gcc/testsuite/gcc.target/aarch64/simd/vuzps8.x new file mode 100644 index 00000000000..62ccad45779 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/simd/vuzps8.x @@ -0,0 +1,26 @@ +extern void abort (void); + +int8x8x2_t +test_vuzps8 (int8x8_t _a, int8x8_t _b) +{ + return vuzp_s8 (_a, _b); +} + +int +main (int argc, char **argv) +{ + int i; + int8_t first[] = {1, 2, 3, 4, 5, 6, 7, 8}; + int8_t second[] = {9, 10, 11, 12, 13, 14, 15, 16}; + int8x8x2_t result = test_vuzps8 (vld1_s8 (first), vld1_s8 (second)); + int8_t exp1[] = {1, 3, 5, 7, 9, 11, 13, 15}; + int8_t exp2[] = {2, 4, 6, 8, 10, 12, 14, 16}; + int8x8_t expect1 = vld1_s8 (exp1); + int8x8_t expect2 = vld1_s8 (exp2); + + for (i = 0; i < 8; i++) + if ((result.val[0][i] != expect1[i]) || (result.val[1][i] != expect2[i])) + abort (); + + return 0; +} diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vuzps8_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vuzps8_1.c new file mode 100644 index 00000000000..5962604ae42 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/simd/vuzps8_1.c @@ -0,0 +1,11 @@ +/* Test the `vuzp_s8' AArch64 SIMD intrinsic. */ + +/* { dg-do run } */ +/* { dg-options "-save-temps -fno-inline" } */ + +#include <arm_neon.h> +#include "vuzps8.x" + +/* { dg-final { scan-assembler-times "uzp1\[ \t\]+v\[0-9\]+\.8b, ?v\[0-9\]+\.8b, ?v\[0-9\]+\.8b!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */ +/* { dg-final { scan-assembler-times "uzp2\[ \t\]+v\[0-9\]+\.8b, ?v\[0-9\]+\.8b, ?v\[0-9\]+\.8b!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vuzpu16.x b/gcc/testsuite/gcc.target/aarch64/simd/vuzpu16.x new file mode 100644 index 00000000000..a5983f6f0b2 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/simd/vuzpu16.x @@ -0,0 +1,26 @@ +extern void abort (void); + +uint16x4x2_t +test_vuzpu16 (uint16x4_t _a, uint16x4_t _b) +{ + return vuzp_u16 (_a, _b); +} + +int +main (int argc, char **argv) +{ + int i; + uint16_t first[] = {1, 2, 3, 4}; + uint16_t second[] = {5, 6, 7, 8}; + uint16x4x2_t result = test_vuzpu16 (vld1_u16 (first), vld1_u16 (second)); + uint16_t exp1[] = {1, 3, 5, 7}; + uint16_t exp2[] = {2, 4, 6, 8}; + uint16x4_t expect1 = vld1_u16 (exp1); + uint16x4_t expect2 = vld1_u16 (exp2); + + for (i = 0; i < 4; i++) + if ((result.val[0][i] != expect1[i]) || (result.val[1][i] != expect2[i])) + abort (); + + return 0; +} diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vuzpu16_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vuzpu16_1.c new file mode 100644 index 00000000000..5025c5ff43e --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/simd/vuzpu16_1.c @@ -0,0 +1,11 @@ +/* Test the `vuzp_u16' AArch64 SIMD intrinsic. */ + +/* { dg-do run } */ +/* { dg-options "-save-temps -fno-inline" } */ + +#include <arm_neon.h> +#include "vuzpu16.x" + +/* { dg-final { scan-assembler-times "uzp1\[ \t\]+v\[0-9\]+\.4h, ?v\[0-9\]+\.4h, ?v\[0-9\]+\.4h!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */ +/* { dg-final { scan-assembler-times "uzp2\[ \t\]+v\[0-9\]+\.4h, ?v\[0-9\]+\.4h, ?v\[0-9\]+\.4h!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vuzpu32.x b/gcc/testsuite/gcc.target/aarch64/simd/vuzpu32.x new file mode 100644 index 00000000000..6bf673130d9 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/simd/vuzpu32.x @@ -0,0 +1,26 @@ +extern void abort (void); + +uint32x2x2_t +test_vuzpu32 (uint32x2_t _a, uint32x2_t _b) +{ + return vuzp_u32 (_a, _b); +} + +int +main (int argc, char **argv) +{ + int i; + uint32_t first[] = {1, 2}; + uint32_t second[] = {3, 4}; + uint32x2x2_t result = test_vuzpu32 (vld1_u32 (first), vld1_u32 (second)); + uint32_t exp1[] = {1, 3}; + uint32_t exp2[] = {2, 4}; + uint32x2_t expect1 = vld1_u32 (exp1); + uint32x2_t expect2 = vld1_u32 (exp2); + + for (i = 0; i < 2; i++) + if ((result.val[0][i] != expect1[i]) || (result.val[1][i] != expect2[i])) + abort (); + + return 0; +} diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vuzpu32_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vuzpu32_1.c new file mode 100644 index 00000000000..05e1c95d42d --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/simd/vuzpu32_1.c @@ -0,0 +1,11 @@ +/* Test the `vuzp_u32' AArch64 SIMD intrinsic. */ + +/* { dg-do run } */ +/* { dg-options "-save-temps -fno-inline" } */ + +#include <arm_neon.h> +#include "vuzpu32.x" + +/* { dg-final { scan-assembler-times "zip1\[ \t\]+v\[0-9\]+\.2s, ?v\[0-9\]+\.2s, ?v\[0-9\]+\.2s!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */ +/* { dg-final { scan-assembler-times "zip2\[ \t\]+v\[0-9\]+\.2s, ?v\[0-9\]+\.2s, ?v\[0-9\]+\.2s!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vuzpu8.x b/gcc/testsuite/gcc.target/aarch64/simd/vuzpu8.x new file mode 100644 index 00000000000..c3e67e8418f --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/simd/vuzpu8.x @@ -0,0 +1,26 @@ +extern void abort (void); + +uint8x8x2_t +test_vuzpu8 (uint8x8_t _a, uint8x8_t _b) +{ + return vuzp_u8 (_a, _b); +} + +int +main (int argc, char **argv) +{ + int i; + uint8_t first[] = {1, 2, 3, 4, 5, 6, 7, 8}; + uint8_t second[] = {9, 10, 11, 12, 13, 14, 15, 16}; + uint8x8x2_t result = test_vuzpu8 (vld1_u8 (first), vld1_u8 (second)); + uint8_t exp1[] = {1, 3, 5, 7, 9, 11, 13, 15}; + uint8_t exp2[] = {2, 4, 6, 8, 10, 12, 14, 16}; + uint8x8_t expect1 = vld1_u8 (exp1); + uint8x8_t expect2 = vld1_u8 (exp2); + + for (i = 0; i < 8; i++) + if ((result.val[0][i] != expect1[i]) || (result.val[1][i] != expect2[i])) + abort (); + + return 0; +} diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vuzpu8_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vuzpu8_1.c new file mode 100644 index 00000000000..57aa49c9330 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/simd/vuzpu8_1.c @@ -0,0 +1,11 @@ +/* Test the `vuzp_u8' AArch64 SIMD intrinsic. */ + +/* { dg-do run } */ +/* { dg-options "-save-temps -fno-inline" } */ + +#include <arm_neon.h> +#include "vuzpu8.x" + +/* { dg-final { scan-assembler-times "uzp1\[ \t\]+v\[0-9\]+\.8b, ?v\[0-9\]+\.8b, ?v\[0-9\]+\.8b!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */ +/* { dg-final { scan-assembler-times "uzp2\[ \t\]+v\[0-9\]+\.8b, ?v\[0-9\]+\.8b, ?v\[0-9\]+\.8b!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vzipf32.x b/gcc/testsuite/gcc.target/aarch64/simd/vzipf32.x new file mode 100644 index 00000000000..cc69b892a02 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/simd/vzipf32.x @@ -0,0 +1,27 @@ +extern void abort (void); + +float32x2x2_t +test_vzipf32 (float32x2_t _a, float32x2_t _b) +{ + return vzip_f32 (_a, _b); +} + +int +main (int argc, char **argv) +{ + int i; + float32_t first[] = {1, 2}; + float32_t second[] = {3, 4}; + float32x2x2_t result = test_vzipf32 (vld1_f32 (first), vld1_f32 (second)); + float32x2_t res1 = result.val[0], res2 = result.val[1]; + float32_t exp1[] = {1, 3}; + float32_t exp2[] = {2, 4}; + float32x2_t expected1 = vld1_f32 (exp1); + float32x2_t expected2 = vld1_f32 (exp2); + + for (i = 0; i < 2; i++) + if ((res1[i] != expected1[i]) || (res2[i] != expected2[i])) + abort (); + + return 0; +} diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vzipf32_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vzipf32_1.c new file mode 100644 index 00000000000..df3395a034e --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/simd/vzipf32_1.c @@ -0,0 +1,11 @@ +/* Test the `vzip_f32' AArch64 SIMD intrinsic. */ + +/* { dg-do run } */ +/* { dg-options "-save-temps -fno-inline" } */ + +#include <arm_neon.h> +#include "vzipf32.x" + +/* { dg-final { scan-assembler-times "zip1\[ \t\]+v\[0-9\]+\.2s, ?v\[0-9\]+\.2s, ?v\[0-9\]+\.2s!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */ +/* { dg-final { scan-assembler-times "zip2\[ \t\]+v\[0-9\]+\.2s, ?v\[0-9\]+\.2s, ?v\[0-9\]+\.2s!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vzipp16.x b/gcc/testsuite/gcc.target/aarch64/simd/vzipp16.x new file mode 100644 index 00000000000..6bdb3e66ac6 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/simd/vzipp16.x @@ -0,0 +1,27 @@ +extern void abort (void); + +poly16x4x2_t +test_vzipp16 (poly16x4_t _a, poly16x4_t _b) +{ + return vzip_p16 (_a, _b); +} + +int +main (int argc, char **argv) +{ + int i; + poly16_t first[] = {1, 2, 3, 4}; + poly16_t second[] = {5, 6, 7, 8}; + poly16x4x2_t result = test_vzipp16 (vld1_p16 (first), vld1_p16 (second)); + poly16x4_t res1 = result.val[0], res2 = result.val[1]; + poly16_t exp1[] = {1, 5, 2, 6}; + poly16_t exp2[] = {3, 7, 4, 8}; + poly16x4_t expected1 = vld1_p16 (exp1); + poly16x4_t expected2 = vld1_p16 (exp2); + + for (i = 0; i < 4; i++) + if ((res1[i] != expected1[i]) || (res2[i] != expected2[i])) + abort (); + + return 0; +} diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vzipp16_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vzipp16_1.c new file mode 100644 index 00000000000..e626a7877b3 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/simd/vzipp16_1.c @@ -0,0 +1,11 @@ +/* Test the `vzip_p16' AArch64 SIMD intrinsic. */ + +/* { dg-do run } */ +/* { dg-options "-save-temps -fno-inline" } */ + +#include <arm_neon.h> +#include "vzipp16.x" + +/* { dg-final { scan-assembler-times "zip1\[ \t\]+v\[0-9\]+\.4h, ?v\[0-9\]+\.4h, ?v\[0-9\]+\.4h!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */ +/* { dg-final { scan-assembler-times "zip2\[ \t\]+v\[0-9\]+\.4h, ?v\[0-9\]+\.4h, ?v\[0-9\]+\.4h!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vzipp8.x b/gcc/testsuite/gcc.target/aarch64/simd/vzipp8.x new file mode 100644 index 00000000000..5e8297eee4b --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/simd/vzipp8.x @@ -0,0 +1,27 @@ +extern void abort (void); + +poly8x8x2_t +test_vzipp8 (poly8x8_t _a, poly8x8_t _b) +{ + return vzip_p8 (_a, _b); +} + +int +main (int argc, char **argv) +{ + int i; + poly8_t first[] = {1, 2, 3, 4, 5, 6, 7, 8}; + poly8_t second[] = {9, 10, 11, 12, 13, 14, 15, 16}; + poly8x8x2_t result = test_vzipp8 (vld1_p8 (first), vld1_p8 (second)); + poly8x8_t res1 = result.val[0], res2 = result.val[1]; + poly8_t exp1[] = {1, 9, 2, 10, 3, 11, 4, 12}; + poly8_t exp2[] = {5, 13, 6, 14, 7, 15, 8, 16}; + poly8x8_t expected1 = vld1_p8 (exp1); + poly8x8_t expected2 = vld1_p8 (exp2); + + for (i = 0; i < 8; i++) + if ((res1[i] != expected1[i]) || (res2[i] != expected2[i])) + abort (); + + return 0; +} diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vzipp8_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vzipp8_1.c new file mode 100644 index 00000000000..f99cb70211b --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/simd/vzipp8_1.c @@ -0,0 +1,11 @@ +/* Test the `vzip_p8' AArch64 SIMD intrinsic. */ + +/* { dg-do run } */ +/* { dg-options "-save-temps -fno-inline" } */ + +#include <arm_neon.h> +#include "vzipp8.x" + +/* { dg-final { scan-assembler-times "zip1\[ \t\]+v\[0-9\]+\.8b, ?v\[0-9\]+\.8b, ?v\[0-9\]+\.8b!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */ +/* { dg-final { scan-assembler-times "zip2\[ \t\]+v\[0-9\]+\.8b, ?v\[0-9\]+\.8b, ?v\[0-9\]+\.8b!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vzipqf32.x b/gcc/testsuite/gcc.target/aarch64/simd/vzipqf32.x new file mode 100644 index 00000000000..e220aeaeb14 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/simd/vzipqf32.x @@ -0,0 +1,27 @@ +extern void abort (void); + +float32x4x2_t +test_vzipqf32 (float32x4_t _a, float32x4_t _b) +{ + return vzipq_f32 (_a, _b); +} + +int +main (int argc, char **argv) +{ + int i; + float32_t first[] = {1, 2, 3, 4}; + float32_t second[] = {5, 6, 7, 8}; + float32x4x2_t result = test_vzipqf32 (vld1q_f32 (first), vld1q_f32 (second)); + float32x4_t res1 = result.val[0], res2 = result.val[1]; + float32_t exp1[] = {1, 5, 2, 6}; + float32_t exp2[] = {3, 7, 4, 8}; + float32x4_t expected1 = vld1q_f32 (exp1); + float32x4_t expected2 = vld1q_f32 (exp2); + + for (i = 0; i < 4; i++) + if ((res1[i] != expected1[i]) || (res2[i] != expected2[i])) + abort (); + + return 0; +} diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vzipqf32_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vzipqf32_1.c new file mode 100644 index 00000000000..74dae27dda0 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/simd/vzipqf32_1.c @@ -0,0 +1,11 @@ +/* Test the `vzipq_f32' AArch64 SIMD intrinsic. */ + +/* { dg-do run } */ +/* { dg-options "-save-temps -fno-inline" } */ + +#include <arm_neon.h> +#include "vzipqf32.x" + +/* { dg-final { scan-assembler-times "zip1\[ \t\]+v\[0-9\]+\.4s, ?v\[0-9\]+\.4s, ?v\[0-9\]+\.4s!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */ +/* { dg-final { scan-assembler-times "zip2\[ \t\]+v\[0-9\]+\.4s, ?v\[0-9\]+\.4s, ?v\[0-9\]+\.4s!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vzipqp16.x b/gcc/testsuite/gcc.target/aarch64/simd/vzipqp16.x new file mode 100644 index 00000000000..640d7a2513f --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/simd/vzipqp16.x @@ -0,0 +1,27 @@ +extern void abort (void); + +poly16x8x2_t +test_vzipqp16 (poly16x8_t _a, poly16x8_t _b) +{ + return vzipq_p16 (_a, _b); +} + +int +main (int argc, char **argv) +{ + int i; + poly16_t first[] = {1, 2, 3, 4, 5, 6, 7, 8}; + poly16_t second[] = {9, 10, 11, 12, 13, 14, 15, 16}; + poly16x8x2_t result = test_vzipqp16 (vld1q_p16 (first), vld1q_p16 (second)); + poly16x8_t res1 = result.val[0], res2 = result.val[1]; + poly16_t exp1[] = {1, 9, 2, 10, 3, 11, 4, 12}; + poly16_t exp2[] = {5, 13, 6, 14, 7, 15, 8, 16}; + poly16x8_t expected1 = vld1q_p16 (exp1); + poly16x8_t expected2 = vld1q_p16 (exp2); + + for (i = 0; i < 8; i++) + if ((res1[i] != expected1[i]) || (res2[i] != expected2[i])) + abort (); + + return 0; +} diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vzipqp16_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vzipqp16_1.c new file mode 100644 index 00000000000..0bfd4f1a53b --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/simd/vzipqp16_1.c @@ -0,0 +1,11 @@ +/* Test the `vzipq_p16' AArch64 SIMD intrinsic. */ + +/* { dg-do run } */ +/* { dg-options "-save-temps -fno-inline" } */ + +#include <arm_neon.h> +#include "vzipqp16.x" + +/* { dg-final { scan-assembler-times "zip1\[ \t\]+v\[0-9\]+\.8h, ?v\[0-9\]+\.8h, ?v\[0-9\]+\.8h!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */ +/* { dg-final { scan-assembler-times "zip2\[ \t\]+v\[0-9\]+\.8h, ?v\[0-9\]+\.8h, ?v\[0-9\]+\.8h!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vzipqp8.x b/gcc/testsuite/gcc.target/aarch64/simd/vzipqp8.x new file mode 100644 index 00000000000..b211b4e532f --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/simd/vzipqp8.x @@ -0,0 +1,29 @@ +extern void abort (void); + +poly8x16x2_t +test_vzipqp8 (poly8x16_t _a, poly8x16_t _b) +{ + return vzipq_p8 (_a, _b); +} + +int +main (int argc, char **argv) +{ + int i; + poly8_t first[] = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16}; + poly8_t second[] = + {17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32}; + poly8x16x2_t result = test_vzipqp8 (vld1q_p8 (first), vld1q_p8 (second)); + poly8x16_t res1 = result.val[0], res2 = result.val[1]; + poly8_t exp1[] = {1, 17, 2, 18, 3, 19, 4, 20, 5, 21, 6, 22, 7, 23, 8, 24}; + poly8_t exp2[] = + {9, 25, 10, 26, 11, 27, 12, 28, 13, 29, 14, 30, 15, 31, 16, 32}; + poly8x16_t expected1 = vld1q_p8 (exp1); + poly8x16_t expected2 = vld1q_p8 (exp2); + + for (i = 0; i < 16; i++) + if ((res1[i] != expected1[i]) || (res2[i] != expected2[i])) + abort (); + + return 0; +} diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vzipqp8_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vzipqp8_1.c new file mode 100644 index 00000000000..fb245063491 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/simd/vzipqp8_1.c @@ -0,0 +1,11 @@ +/* Test the `vzipq_p8' AArch64 SIMD intrinsic. */ + +/* { dg-do run } */ +/* { dg-options "-save-temps -fno-inline" } */ + +#include <arm_neon.h> +#include "vzipqp8.x" + +/* { dg-final { scan-assembler-times "zip1\[ \t\]+v\[0-9\]+\.16b, ?v\[0-9\]+\.16b, ?v\[0-9\]+\.16b!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */ +/* { dg-final { scan-assembler-times "zip2\[ \t\]+v\[0-9\]+\.16b, ?v\[0-9\]+\.16b, ?v\[0-9\]+\.16b!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vzipqs16.x b/gcc/testsuite/gcc.target/aarch64/simd/vzipqs16.x new file mode 100644 index 00000000000..97ee6b5bde6 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/simd/vzipqs16.x @@ -0,0 +1,27 @@ +extern void abort (void); + +int16x8x2_t +test_vzipqs16 (int16x8_t _a, int16x8_t _b) +{ + return vzipq_s16 (_a, _b); +} + +int +main (int argc, char **argv) +{ + int i; + int16_t first[] = {1, 2, 3, 4, 5, 6, 7, 8}; + int16_t second[] = {9, 10, 11, 12, 13, 14, 15, 16}; + int16x8x2_t result = test_vzipqs16 (vld1q_s16 (first), vld1q_s16 (second)); + int16x8_t res1 = result.val[0], res2 = result.val[1]; + int16_t exp1[] = {1, 9, 2, 10, 3, 11, 4, 12}; + int16_t exp2[] = {5, 13, 6, 14, 7, 15, 8, 16}; + int16x8_t expected1 = vld1q_s16 (exp1); + int16x8_t expected2 = vld1q_s16 (exp2); + + for (i = 0; i < 8; i++) + if ((res1[i] != expected1[i]) || (res2[i] != expected2[i])) + abort (); + + return 0; +} diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vzipqs16_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vzipqs16_1.c new file mode 100644 index 00000000000..3ff551cceb2 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/simd/vzipqs16_1.c @@ -0,0 +1,11 @@ +/* Test the `vzipq_s16' AArch64 SIMD intrinsic. */ + +/* { dg-do run } */ +/* { dg-options "-save-temps -fno-inline" } */ + +#include <arm_neon.h> +#include "vzipqs16.x" + +/* { dg-final { scan-assembler-times "zip1\[ \t\]+v\[0-9\]+\.8h, ?v\[0-9\]+\.8h, ?v\[0-9\]+\.8h!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */ +/* { dg-final { scan-assembler-times "zip2\[ \t\]+v\[0-9\]+\.8h, ?v\[0-9\]+\.8h, ?v\[0-9\]+\.8h!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vzipqs32.x b/gcc/testsuite/gcc.target/aarch64/simd/vzipqs32.x new file mode 100644 index 00000000000..45f490d7350 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/simd/vzipqs32.x @@ -0,0 +1,27 @@ +extern void abort (void); + +int32x4x2_t +test_vzipqs32 (int32x4_t _a, int32x4_t _b) +{ + return vzipq_s32 (_a, _b); +} + +int +main (int argc, char **argv) +{ + int i; + int32_t first[] = {1, 2, 3, 4}; + int32_t second[] = {5, 6, 7, 8}; + int32x4x2_t result = test_vzipqs32 (vld1q_s32 (first), vld1q_s32 (second)); + int32x4_t res1 = result.val[0], res2 = result.val[1]; + int32_t exp1[] = {1, 5, 2, 6}; + int32_t exp2[] = {3, 7, 4, 8}; + int32x4_t expected1 = vld1q_s32 (exp1); + int32x4_t expected2 = vld1q_s32 (exp2); + + for (i = 0; i < 4; i++) + if ((res1[i] != expected1[i]) || (res2[i] != expected2[i])) + abort (); + + return 0; +} diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vzipqs32_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vzipqs32_1.c new file mode 100644 index 00000000000..51681581bc9 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/simd/vzipqs32_1.c @@ -0,0 +1,11 @@ +/* Test the `vzipq_s32' AArch64 SIMD intrinsic. */ + +/* { dg-do run } */ +/* { dg-options "-save-temps -fno-inline" } */ + +#include <arm_neon.h> +#include "vzipqs32.x" + +/* { dg-final { scan-assembler-times "zip1\[ \t\]+v\[0-9\]+\.4s, ?v\[0-9\]+\.4s, ?v\[0-9\]+\.4s!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */ +/* { dg-final { scan-assembler-times "zip2\[ \t\]+v\[0-9\]+\.4s, ?v\[0-9\]+\.4s, ?v\[0-9\]+\.4s!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vzipqs8.x b/gcc/testsuite/gcc.target/aarch64/simd/vzipqs8.x new file mode 100644 index 00000000000..68cc84b7e86 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/simd/vzipqs8.x @@ -0,0 +1,29 @@ +extern void abort (void); + +int8x16x2_t +test_vzipqs8 (int8x16_t _a, int8x16_t _b) +{ + return vzipq_s8 (_a, _b); +} + +int +main (int argc, char **argv) +{ + int i; + int8_t first[] = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16}; + int8_t second[] = + {17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32}; + int8x16x2_t result = test_vzipqs8 (vld1q_s8 (first), vld1q_s8 (second)); + int8x16_t res1 = result.val[0], res2 = result.val[1]; + int8_t exp1[] = {1, 17, 2, 18, 3, 19, 4, 20, 5, 21, 6, 22, 7, 23, 8, 24}; + int8_t exp2[] = + {9, 25, 10, 26, 11, 27, 12, 28, 13, 29, 14, 30, 15, 31, 16, 32}; + int8x16_t expected1 = vld1q_s8 (exp1); + int8x16_t expected2 = vld1q_s8 (exp2); + + for (i = 0; i < 16; i++) + if ((res1[i] != expected1[i]) || (res2[i] != expected2[i])) + abort (); + + return 0; +} diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vzipqs8_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vzipqs8_1.c new file mode 100644 index 00000000000..ec035f3247d --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/simd/vzipqs8_1.c @@ -0,0 +1,11 @@ +/* Test the `vzipq_s8' AArch64 SIMD intrinsic. */ + +/* { dg-do run } */ +/* { dg-options "-save-temps -fno-inline" } */ + +#include <arm_neon.h> +#include "vzipqs8.x" + +/* { dg-final { scan-assembler-times "zip1\[ \t\]+v\[0-9\]+\.16b, ?v\[0-9\]+\.16b, ?v\[0-9\]+\.16b!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */ +/* { dg-final { scan-assembler-times "zip2\[ \t\]+v\[0-9\]+\.16b, ?v\[0-9\]+\.16b, ?v\[0-9\]+\.16b!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vzipqu16.x b/gcc/testsuite/gcc.target/aarch64/simd/vzipqu16.x new file mode 100644 index 00000000000..dc4e1462d79 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/simd/vzipqu16.x @@ -0,0 +1,27 @@ +extern void abort (void); + +uint16x8x2_t +test_vzipqu16 (uint16x8_t _a, uint16x8_t _b) +{ + return vzipq_u16 (_a, _b); +} + +int +main (int argc, char **argv) +{ + int i; + uint16_t first[] = {1, 2, 3, 4, 5, 6, 7, 8}; + uint16_t second[] = {9, 10, 11, 12, 13, 14, 15, 16}; + uint16x8x2_t result = test_vzipqu16 (vld1q_u16 (first), vld1q_u16 (second)); + uint16x8_t res1 = result.val[0], res2 = result.val[1]; + uint16_t exp1[] = {1, 9, 2, 10, 3, 11, 4, 12}; + uint16_t exp2[] = {5, 13, 6, 14, 7, 15, 8, 16}; + uint16x8_t expected1 = vld1q_u16 (exp1); + uint16x8_t expected2 = vld1q_u16 (exp2); + + for (i = 0; i < 8; i++) + if ((res1[i] != expected1[i]) || (res2[i] != expected2[i])) + abort (); + + return 0; +} diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vzipqu16_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vzipqu16_1.c new file mode 100644 index 00000000000..b540c8236a6 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/simd/vzipqu16_1.c @@ -0,0 +1,11 @@ +/* Test the `vzipq_u16' AArch64 SIMD intrinsic. */ + +/* { dg-do run } */ +/* { dg-options "-save-temps -fno-inline" } */ + +#include <arm_neon.h> +#include "vzipqu16.x" + +/* { dg-final { scan-assembler-times "zip1\[ \t\]+v\[0-9\]+\.8h, ?v\[0-9\]+\.8h, ?v\[0-9\]+\.8h!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */ +/* { dg-final { scan-assembler-times "zip2\[ \t\]+v\[0-9\]+\.8h, ?v\[0-9\]+\.8h, ?v\[0-9\]+\.8h!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vzipqu32.x b/gcc/testsuite/gcc.target/aarch64/simd/vzipqu32.x new file mode 100644 index 00000000000..8dde7e9bd62 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/simd/vzipqu32.x @@ -0,0 +1,27 @@ +extern void abort (void); + +uint32x4x2_t +test_vzipqu32 (uint32x4_t _a, uint32x4_t _b) +{ + return vzipq_u32 (_a, _b); +} + +int +main (int argc, char **argv) +{ + int i; + uint32_t first[] = {1, 2, 3, 4}; + uint32_t second[] = {5, 6, 7, 8}; + uint32x4x2_t result = test_vzipqu32 (vld1q_u32 (first), vld1q_u32 (second)); + uint32x4_t res1 = result.val[0], res2 = result.val[1]; + uint32_t exp1[] = {1, 5, 2, 6}; + uint32_t exp2[] = {3, 7, 4, 8}; + uint32x4_t expected1 = vld1q_u32 (exp1); + uint32x4_t expected2 = vld1q_u32 (exp2); + + for (i = 0; i < 4; i++) + if ((res1[i] != expected1[i]) || (res2[i] != expected2[i])) + abort (); + + return 0; +} diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vzipqu32_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vzipqu32_1.c new file mode 100644 index 00000000000..ca907b34523 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/simd/vzipqu32_1.c @@ -0,0 +1,11 @@ +/* Test the `vzipq_u32' AArch64 SIMD intrinsic. */ + +/* { dg-do run } */ +/* { dg-options "-save-temps -fno-inline" } */ + +#include <arm_neon.h> +#include "vzipqu32.x" + +/* { dg-final { scan-assembler-times "zip1\[ \t\]+v\[0-9\]+\.4s, ?v\[0-9\]+\.4s, ?v\[0-9\]+\.4s!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */ +/* { dg-final { scan-assembler-times "zip2\[ \t\]+v\[0-9\]+\.4s, ?v\[0-9\]+\.4s, ?v\[0-9\]+\.4s!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vzipqu8.x b/gcc/testsuite/gcc.target/aarch64/simd/vzipqu8.x new file mode 100644 index 00000000000..8f2603bfebe --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/simd/vzipqu8.x @@ -0,0 +1,29 @@ +extern void abort (void); + +uint8x16x2_t +test_vzipqu8 (uint8x16_t _a, uint8x16_t _b) +{ + return vzipq_u8 (_a, _b); +} + +int +main (int argc, char **argv) +{ + int i; + uint8_t first[] = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16}; + uint8_t second[] = + {17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32}; + uint8x16x2_t result = test_vzipqu8 (vld1q_u8 (first), vld1q_u8 (second)); + uint8x16_t res1 = result.val[0], res2 = result.val[1]; + uint8_t exp1[] = {1, 17, 2, 18, 3, 19, 4, 20, 5, 21, 6, 22, 7, 23, 8, 24}; + uint8_t exp2[] = + {9, 25, 10, 26, 11, 27, 12, 28, 13, 29, 14, 30, 15, 31, 16, 32}; + uint8x16_t expected1 = vld1q_u8 (exp1); + uint8x16_t expected2 = vld1q_u8 (exp2); + + for (i = 0; i < 16; i++) + if ((res1[i] != expected1[i]) || (res2[i] != expected2[i])) + abort (); + + return 0; +} diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vzipqu8_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vzipqu8_1.c new file mode 100644 index 00000000000..16ada581746 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/simd/vzipqu8_1.c @@ -0,0 +1,11 @@ +/* Test the `vzipq_u8' AArch64 SIMD intrinsic. */ + +/* { dg-do run } */ +/* { dg-options "-save-temps -fno-inline" } */ + +#include <arm_neon.h> +#include "vzipqu8.x" + +/* { dg-final { scan-assembler-times "zip1\[ \t\]+v\[0-9\]+\.16b, ?v\[0-9\]+\.16b, ?v\[0-9\]+\.16b!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */ +/* { dg-final { scan-assembler-times "zip2\[ \t\]+v\[0-9\]+\.16b, ?v\[0-9\]+\.16b, ?v\[0-9\]+\.16b!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vzips16.x b/gcc/testsuite/gcc.target/aarch64/simd/vzips16.x new file mode 100644 index 00000000000..71ee4687f3d --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/simd/vzips16.x @@ -0,0 +1,27 @@ +extern void abort (void); + +int16x4x2_t +test_vzips16 (int16x4_t _a, int16x4_t _b) +{ + return vzip_s16 (_a, _b); +} + +int +main (int argc, char **argv) +{ + int i; + int16_t first[] = {1, 2, 3, 4}; + int16_t second[] = {5, 6, 7, 8}; + int16x4x2_t result = test_vzips16 (vld1_s16 (first), vld1_s16 (second)); + int16x4_t res1 = result.val[0], res2 = result.val[1]; + int16_t exp1[] = {1, 5, 2, 6}; + int16_t exp2[] = {3, 7, 4, 8}; + int16x4_t expected1 = vld1_s16 (exp1); + int16x4_t expected2 = vld1_s16 (exp2); + + for (i = 0; i < 4; i++) + if ((res1[i] != expected1[i]) || (res2[i] != expected2[i])) + abort (); + + return 0; +} diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vzips16_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vzips16_1.c new file mode 100644 index 00000000000..04a97546922 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/simd/vzips16_1.c @@ -0,0 +1,11 @@ +/* Test the `vzip_s16' AArch64 SIMD intrinsic. */ + +/* { dg-do run } */ +/* { dg-options "-save-temps -fno-inline" } */ + +#include <arm_neon.h> +#include "vzips16.x" + +/* { dg-final { scan-assembler-times "zip1\[ \t\]+v\[0-9\]+\.4h, ?v\[0-9\]+\.4h, ?v\[0-9\]+\.4h!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */ +/* { dg-final { scan-assembler-times "zip2\[ \t\]+v\[0-9\]+\.4h, ?v\[0-9\]+\.4h, ?v\[0-9\]+\.4h!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vzips32.x b/gcc/testsuite/gcc.target/aarch64/simd/vzips32.x new file mode 100644 index 00000000000..25bee1c2846 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/simd/vzips32.x @@ -0,0 +1,27 @@ +extern void abort (void); + +int32x2x2_t +test_vzips32 (int32x2_t _a, int32x2_t _b) +{ + return vzip_s32 (_a, _b); +} + +int +main (int argc, char **argv) +{ + int i; + int32_t first[] = {1, 2}; + int32_t second[] = {3, 4}; + int32x2x2_t result = test_vzips32 (vld1_s32 (first), vld1_s32 (second)); + int32x2_t res1 = result.val[0], res2 = result.val[1]; + int32_t exp1[] = {1, 3}; + int32_t exp2[] = {2, 4}; + int32x2_t expected1 = vld1_s32 (exp1); + int32x2_t expected2 = vld1_s32 (exp2); + + for (i = 0; i < 2; i++) + if ((res1[i] != expected1[i]) || (res2[i] != expected2[i])) + abort (); + + return 0; +} diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vzips32_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vzips32_1.c new file mode 100644 index 00000000000..1c44f64453e --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/simd/vzips32_1.c @@ -0,0 +1,11 @@ +/* Test the `vzip_s32' AArch64 SIMD intrinsic. */ + +/* { dg-do run } */ +/* { dg-options "-save-temps -fno-inline" } */ + +#include <arm_neon.h> +#include "vzips32.x" + +/* { dg-final { scan-assembler-times "zip1\[ \t\]+v\[0-9\]+\.2s, ?v\[0-9\]+\.2s, ?v\[0-9\]+\.2s!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */ +/* { dg-final { scan-assembler-times "zip2\[ \t\]+v\[0-9\]+\.2s, ?v\[0-9\]+\.2s, ?v\[0-9\]+\.2s!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vzips8.x b/gcc/testsuite/gcc.target/aarch64/simd/vzips8.x new file mode 100644 index 00000000000..4f04d731abe --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/simd/vzips8.x @@ -0,0 +1,27 @@ +extern void abort (void); + +int8x8x2_t +test_vzips8 (int8x8_t _a, int8x8_t _b) +{ + return vzip_s8 (_a, _b); +} + +int +main (int argc, char **argv) +{ + int i; + int8_t first[] = {1, 2, 3, 4, 5, 6, 7, 8}; + int8_t second[] = {9, 10, 11, 12, 13, 14, 15, 16}; + int8x8x2_t result = test_vzips8 (vld1_s8 (first), vld1_s8 (second)); + int8x8_t res1 = result.val[0], res2 = result.val[1]; + int8_t exp1[] = {1, 9, 2, 10, 3, 11, 4, 12}; + int8_t exp2[] = {5, 13, 6, 14, 7, 15, 8, 16}; + int8x8_t expected1 = vld1_s8 (exp1); + int8x8_t expected2 = vld1_s8 (exp2); + + for (i = 0; i < 8; i++) + if ((res1[i] != expected1[i]) || (res2[i] != expected2[i])) + abort (); + + return 0; +} diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vzips8_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vzips8_1.c new file mode 100644 index 00000000000..5ab7230aa04 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/simd/vzips8_1.c @@ -0,0 +1,11 @@ +/* Test the `vzip_s8' AArch64 SIMD intrinsic. */ + +/* { dg-do run } */ +/* { dg-options "-save-temps -fno-inline" } */ + +#include <arm_neon.h> +#include "vzips8.x" + +/* { dg-final { scan-assembler-times "zip1\[ \t\]+v\[0-9\]+\.8b, ?v\[0-9\]+\.8b, ?v\[0-9\]+\.8b!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */ +/* { dg-final { scan-assembler-times "zip2\[ \t\]+v\[0-9\]+\.8b, ?v\[0-9\]+\.8b, ?v\[0-9\]+\.8b!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vzipu16.x b/gcc/testsuite/gcc.target/aarch64/simd/vzipu16.x new file mode 100644 index 00000000000..f8dd2ceea98 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/simd/vzipu16.x @@ -0,0 +1,27 @@ +extern void abort (void); + +uint16x4x2_t +test_vzipu16 (uint16x4_t _a, uint16x4_t _b) +{ + return vzip_u16 (_a, _b); +} + +int +main (int argc, char **argv) +{ + int i; + uint16_t first[] = {1, 2, 3, 4}; + uint16_t second[] = {5, 6, 7, 8}; + uint16x4x2_t result = test_vzipu16 (vld1_u16 (first), vld1_u16 (second)); + uint16x4_t res1 = result.val[0], res2 = result.val[1]; + uint16_t exp1[] = {1, 5, 2, 6}; + uint16_t exp2[] = {3, 7, 4, 8}; + uint16x4_t expected1 = vld1_u16 (exp1); + uint16x4_t expected2 = vld1_u16 (exp2); + + for (i = 0; i < 4; i++) + if ((res1[i] != expected1[i]) || (res2[i] != expected2[i])) + abort (); + + return 0; +} diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vzipu16_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vzipu16_1.c new file mode 100644 index 00000000000..abf7365a733 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/simd/vzipu16_1.c @@ -0,0 +1,11 @@ +/* Test the `vzip_u16' AArch64 SIMD intrinsic. */ + +/* { dg-do run } */ +/* { dg-options "-save-temps -fno-inline" } */ + +#include <arm_neon.h> +#include "vzipu16.x" + +/* { dg-final { scan-assembler-times "zip1\[ \t\]+v\[0-9\]+\.4h, ?v\[0-9\]+\.4h, ?v\[0-9\]+\.4h!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */ +/* { dg-final { scan-assembler-times "zip2\[ \t\]+v\[0-9\]+\.4h, ?v\[0-9\]+\.4h, ?v\[0-9\]+\.4h!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vzipu32.x b/gcc/testsuite/gcc.target/aarch64/simd/vzipu32.x new file mode 100644 index 00000000000..0579fc4a8be --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/simd/vzipu32.x @@ -0,0 +1,27 @@ +extern void abort (void); + +uint32x2x2_t +test_vzipu32 (uint32x2_t _a, uint32x2_t _b) +{ + return vzip_u32 (_a, _b); +} + +int +main (int argc, char **argv) +{ + int i; + uint32_t first[] = {1, 2}; + uint32_t second[] = {3, 4}; + uint32x2x2_t result = test_vzipu32 (vld1_u32 (first), vld1_u32 (second)); + uint32x2_t res1 = result.val[0], res2 = result.val[1]; + uint32_t exp1[] = {1, 3}; + uint32_t exp2[] = {2, 4}; + uint32x2_t expected1 = vld1_u32 (exp1); + uint32x2_t expected2 = vld1_u32 (exp2); + + for (i = 0; i < 2; i++) + if ((res1[i] != expected1[i]) || (res2[i] != expected2[i])) + abort (); + + return 0; +} diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vzipu32_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vzipu32_1.c new file mode 100644 index 00000000000..d994cb29c4f --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/simd/vzipu32_1.c @@ -0,0 +1,11 @@ +/* Test the `vzip_u32' AArch64 SIMD intrinsic. */ + +/* { dg-do run } */ +/* { dg-options "-save-temps -fno-inline" } */ + +#include <arm_neon.h> +#include "vzipu32.x" + +/* { dg-final { scan-assembler-times "zip1\[ \t\]+v\[0-9\]+\.2s, ?v\[0-9\]+\.2s, ?v\[0-9\]+\.2s!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */ +/* { dg-final { scan-assembler-times "zip2\[ \t\]+v\[0-9\]+\.2s, ?v\[0-9\]+\.2s, ?v\[0-9\]+\.2s!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vzipu8.x b/gcc/testsuite/gcc.target/aarch64/simd/vzipu8.x new file mode 100644 index 00000000000..28d9205c4f5 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/simd/vzipu8.x @@ -0,0 +1,27 @@ +extern void abort (void); + +uint8x8x2_t +test_vzipu8 (uint8x8_t _a, uint8x8_t _b) +{ + return vzip_u8 (_a, _b); +} + +int +main (int argc, char **argv) +{ + int i; + uint8_t first[] = {1, 2, 3, 4, 5, 6, 7, 8}; + uint8_t second[] = {9, 10, 11, 12, 13, 14, 15, 16}; + uint8x8x2_t result = test_vzipu8 (vld1_u8 (first), vld1_u8 (second)); + uint8x8_t res1 = result.val[0], res2 = result.val[1]; + uint8_t exp1[] = {1, 9, 2, 10, 3, 11, 4, 12}; + uint8_t exp2[] = {5, 13, 6, 14, 7, 15, 8, 16}; + uint8x8_t expected1 = vld1_u8 (exp1); + uint8x8_t expected2 = vld1_u8 (exp2); + + for (i = 0; i < 8; i++) + if ((res1[i] != expected1[i]) || (res2[i] != expected2[i])) + abort (); + + return 0; +} diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vzipu8_1.c b/gcc/testsuite/gcc.target/aarch64/simd/vzipu8_1.c new file mode 100644 index 00000000000..990186a33f1 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/simd/vzipu8_1.c @@ -0,0 +1,11 @@ +/* Test the `vzip_u8' AArch64 SIMD intrinsic. */ + +/* { dg-do run } */ +/* { dg-options "-save-temps -fno-inline" } */ + +#include <arm_neon.h> +#include "vzipu8.x" + +/* { dg-final { scan-assembler-times "zip1\[ \t\]+v\[0-9\]+\.8b, ?v\[0-9\]+\.8b, ?v\[0-9\]+\.8b!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */ +/* { dg-final { scan-assembler-times "zip2\[ \t\]+v\[0-9\]+\.8b, ?v\[0-9\]+\.8b, ?v\[0-9\]+\.8b!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/simd.exp b/gcc/testsuite/gcc.target/arm/simd/simd.exp new file mode 100644 index 00000000000..746429dadf6 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/simd.exp @@ -0,0 +1,35 @@ +# Copyright (C) 1997-2014 Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with GCC; see the file COPYING3. If not see +# <http://www.gnu.org/licenses/>. + +# GCC testsuite that uses the `dg.exp' driver. + +# Exit immediately if this isn't an ARM target. +if ![istarget arm*-*-*] then { + return +} + +# Load support procs. +load_lib gcc-dg.exp + +# Initialize `dg'. +dg-init + +# Main loop. +dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.\[cCS\]]] \ + "" "" + +# All done. +dg-finish diff --git a/gcc/testsuite/gcc.target/arm/simd/vzipf32_1.c b/gcc/testsuite/gcc.target/arm/simd/vzipf32_1.c new file mode 100644 index 00000000000..efaa96ea955 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/vzipf32_1.c @@ -0,0 +1,12 @@ +/* Test the `vzipf32' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O1 -fno-inline" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include "../../aarch64/simd/vzipf32.x" + +/* { dg-final { scan-assembler-times "vuzp\.32\[ \t\]+\[dD\]\[0-9\]+, ?\[dD\]\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vzipp16_1.c b/gcc/testsuite/gcc.target/arm/simd/vzipp16_1.c new file mode 100644 index 00000000000..4154333a7f7 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/vzipp16_1.c @@ -0,0 +1,12 @@ +/* Test the `vzipp16' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O1 -fno-inline" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include "../../aarch64/simd/vzipp16.x" + +/* { dg-final { scan-assembler-times "vzip\.16\[ \t\]+\[dD\]\[0-9\]+, ?\[dD\]\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vzipp8_1.c b/gcc/testsuite/gcc.target/arm/simd/vzipp8_1.c new file mode 100644 index 00000000000..9fe2384c9f9 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/vzipp8_1.c @@ -0,0 +1,12 @@ +/* Test the `vzipp8' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O1 -fno-inline" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include "../../aarch64/simd/vzipp8.x" + +/* { dg-final { scan-assembler-times "vzip\.8\[ \t\]+\[dD\]\[0-9\]+, ?\[dD\]\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vzipqf32_1.c b/gcc/testsuite/gcc.target/arm/simd/vzipqf32_1.c new file mode 100644 index 00000000000..8c547a79f5b --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/vzipqf32_1.c @@ -0,0 +1,12 @@ +/* Test the `vzipQf32' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O1 -fno-inline" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include "../../aarch64/simd/vzipqf32.x" + +/* { dg-final { scan-assembler-times "vzip\.32\[ \t\]+\[qQ\]\[0-9\]+, ?\[qQ\]\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vzipqp16_1.c b/gcc/testsuite/gcc.target/arm/simd/vzipqp16_1.c new file mode 100644 index 00000000000..e2af10b2af1 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/vzipqp16_1.c @@ -0,0 +1,12 @@ +/* Test the `vzipQp16' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O1 -fno-inline" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include "../../aarch64/simd/vzipqp16.x" + +/* { dg-final { scan-assembler-times "vzip\.16\[ \t\]+\[qQ\]\[0-9\]+, ?\[qQ\]\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vzipqp8_1.c b/gcc/testsuite/gcc.target/arm/simd/vzipqp8_1.c new file mode 100644 index 00000000000..11a13298563 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/vzipqp8_1.c @@ -0,0 +1,12 @@ +/* Test the `vzipQp8' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O1 -fno-inline" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include "../../aarch64/simd/vzipqp8.x" + +/* { dg-final { scan-assembler-times "vzip\.8\[ \t\]+\[qQ\]\[0-9\]+, ?\[qQ\]\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vzipqs16_1.c b/gcc/testsuite/gcc.target/arm/simd/vzipqs16_1.c new file mode 100644 index 00000000000..0576c0033e6 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/vzipqs16_1.c @@ -0,0 +1,12 @@ +/* Test the `vzipQs16' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O1 -fno-inline" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include "../../aarch64/simd/vzipqs16.x" + +/* { dg-final { scan-assembler-times "vzip\.16\[ \t\]+\[qQ\]\[0-9\]+, ?\[qQ\]\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vzipqs32_1.c b/gcc/testsuite/gcc.target/arm/simd/vzipqs32_1.c new file mode 100644 index 00000000000..6cf24396d20 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/vzipqs32_1.c @@ -0,0 +1,12 @@ +/* Test the `vzipQs32' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O1 -fno-inline" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include "../../aarch64/simd/vzipqs32.x" + +/* { dg-final { scan-assembler-times "vzip\.32\[ \t\]+\[qQ\]\[0-9\]+, ?\[qQ\]\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vzipqs8_1.c b/gcc/testsuite/gcc.target/arm/simd/vzipqs8_1.c new file mode 100644 index 00000000000..0244374e001 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/vzipqs8_1.c @@ -0,0 +1,12 @@ +/* Test the `vzipQs8' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O1 -fno-inline" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include "../../aarch64/simd/vzipqs8.x" + +/* { dg-final { scan-assembler-times "vzip\.8\[ \t\]+\[qQ\]\[0-9\]+, ?\[qQ\]\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vzipqu16_1.c b/gcc/testsuite/gcc.target/arm/simd/vzipqu16_1.c new file mode 100644 index 00000000000..3c406f514d2 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/vzipqu16_1.c @@ -0,0 +1,12 @@ +/* Test the `vzipQu16' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O1 -fno-inline" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include "../../aarch64/simd/vzipqu16.x" + +/* { dg-final { scan-assembler-times "vzip\.16\[ \t\]+\[qQ\]\[0-9\]+, ?\[qQ\]\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vzipqu32_1.c b/gcc/testsuite/gcc.target/arm/simd/vzipqu32_1.c new file mode 100644 index 00000000000..ba1393c6c92 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/vzipqu32_1.c @@ -0,0 +1,12 @@ +/* Test the `vzipQu32' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O1 -fno-inline" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include "../../aarch64/simd/vzipqu32.x" + +/* { dg-final { scan-assembler-times "vzip\.32\[ \t\]+\[qQ\]\[0-9\]+, ?\[qQ\]\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vzipqu8_1.c b/gcc/testsuite/gcc.target/arm/simd/vzipqu8_1.c new file mode 100644 index 00000000000..023ecac3a52 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/vzipqu8_1.c @@ -0,0 +1,12 @@ +/* Test the `vzipQu8' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O1 -fno-inline" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include "../../aarch64/simd/vzipqu8.x" + +/* { dg-final { scan-assembler-times "vzip\.8\[ \t\]+\[qQ\]\[0-9\]+, ?\[qQ\]\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vzips16_1.c b/gcc/testsuite/gcc.target/arm/simd/vzips16_1.c new file mode 100644 index 00000000000..b6c3c2fe897 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/vzips16_1.c @@ -0,0 +1,12 @@ +/* Test the `vzips16' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O1 -fno-inline" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include "../../aarch64/simd/vzips16.x" + +/* { dg-final { scan-assembler-times "vzip\.16\[ \t\]+\[dD\]\[0-9\]+, ?\[dD\]\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vzips32_1.c b/gcc/testsuite/gcc.target/arm/simd/vzips32_1.c new file mode 100644 index 00000000000..1a6f1709342 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/vzips32_1.c @@ -0,0 +1,12 @@ +/* Test the `vzips32' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O1 -fno-inline" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include "../../aarch64/simd/vzips32.x" + +/* { dg-final { scan-assembler-times "vuzp\.32\[ \t\]+\[dD\]\[0-9\]+, ?\[dD\]\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vzips8_1.c b/gcc/testsuite/gcc.target/arm/simd/vzips8_1.c new file mode 100644 index 00000000000..8569357817b --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/vzips8_1.c @@ -0,0 +1,12 @@ +/* Test the `vzips8' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O1 -fno-inline" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include "../../aarch64/simd/vzips8.x" + +/* { dg-final { scan-assembler-times "vzip\.8\[ \t\]+\[dD\]\[0-9\]+, ?\[dD\]\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vzipu16_1.c b/gcc/testsuite/gcc.target/arm/simd/vzipu16_1.c new file mode 100644 index 00000000000..23bfcc4d962 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/vzipu16_1.c @@ -0,0 +1,12 @@ +/* Test the `vzipu16' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O1 -fno-inline" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include "../../aarch64/simd/vzipu16.x" + +/* { dg-final { scan-assembler-times "vzip\.16\[ \t\]+\[dD\]\[0-9\]+, ?\[dD\]\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vzipu32_1.c b/gcc/testsuite/gcc.target/arm/simd/vzipu32_1.c new file mode 100644 index 00000000000..6a753f25a9c --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/vzipu32_1.c @@ -0,0 +1,12 @@ +/* Test the `vzipu32' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O1 -fno-inline" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include "../../aarch64/simd/vzipu32.x" + +/* { dg-final { scan-assembler-times "vuzp\.32\[ \t\]+\[dD\]\[0-9\]+, ?\[dD\]\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vzipu8_1.c b/gcc/testsuite/gcc.target/arm/simd/vzipu8_1.c new file mode 100644 index 00000000000..972af74237f --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/vzipu8_1.c @@ -0,0 +1,12 @@ +/* Test the `vzipu8' ARM Neon intrinsic. */ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O1 -fno-inline" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include "../../aarch64/simd/vzipu8.x" + +/* { dg-final { scan-assembler-times "vzip\.8\[ \t\]+\[dD\]\[0-9\]+, ?\[dD\]\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gfortran.dg/arrayio_13.f90 b/gcc/testsuite/gfortran.dg/arrayio_13.f90 new file mode 100644 index 00000000000..92a856bc869 --- /dev/null +++ b/gcc/testsuite/gfortran.dg/arrayio_13.f90 @@ -0,0 +1,14 @@ +! { dg-do run } +! PR60810 Bogus end-of-file +program readstrlist + character(len=80), dimension(2) :: ver + integer :: a, b, c + a = 1 + b = 2 + c = 3 + ver(1) = '285 383' + ver(2) = '985' + read( ver, *) a, b, c + if (a /= 285 .or. b /= 383 .or. c /= 985) call abort + !write ( *, *) a, b, c +end diff --git a/gcc/testsuite/gfortran.dg/vect/pr48329.f90 b/gcc/testsuite/gfortran.dg/vect/pr48329.f90 new file mode 100644 index 00000000000..6ad03d4bd33 --- /dev/null +++ b/gcc/testsuite/gfortran.dg/vect/pr48329.f90 @@ -0,0 +1,29 @@ +! { dg-do compile } +! { dg-require-effective-target vect_float } +! { dg-require-effective-target vect_intfloat_cvt } +! { dg-additional-options "-ffast-math" } + +program calcpi + + implicit none + real(kind=4):: h,x,sum,pi + integer:: n,i + real(kind=4):: f + + f(x) = 4.0/(1.0+x**2) + + n = 2100000000 + + h= 1.0 / n + sum = 0.0 + DO i=1, n + x = h * (i-0.5) + sum = sum + f(x) + END DO + pi = h * sum + write(*,*) 'Pi=',pi + +end program calcpi + +! { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" } } +! { dg-final { cleanup-tree-dump "vect" } } |