| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| * | arm: Fix ICE with -fstack-protector -mpure-code [PR98998] | Jakub Jelinek | 2021-02-19 | 1 | -0/+10 |
| * | Update copyright years. | Jakub Jelinek | 2021-01-04 | 1 | -1/+1 |
| * | arm&aarch64: subdivide the type attribute "alu_shfit_imm" | Qian Jianhua | 2020-12-22 | 1 | -13/+18 |
| * | arm: Fix ICEs in no-literal-pool.c on MVE [PR97251] | Alex Coplan | 2020-09-30 | 1 | -2/+2 |
| * | arm: Fix fp16 move patterns for base MVE | Richard Sandiford | 2020-09-25 | 1 | -1/+3 |
| * | arm: Fix canary address calculation for non-PIC | Richard Sandiford | 2020-09-24 | 1 | -2/+2 |
| * | [PATCH 4/5][Arm] New pattern for CSNEG instructions | Sudi Das | 2020-09-18 | 1 | -1/+1 |
| * | arm: Clear canary value after stack_protect_test [PR96191] | Richard Sandiford | 2020-08-06 | 1 | -2/+4 |
| * | [Arm] Disallow arm_movdi when targetting MVE | Matthew Malcomson | 2020-04-15 | 1 | -0/+1 |
| * | [Arm] Implement scalar Custom Datapath Extension intrinsics | Matthew Malcomson | 2020-04-08 | 1 | -0/+70 |
| * | arm: MVE Don't use lsll for 32-bit shifts scalar | Andre Simoes Dias Vieira | 2020-04-07 | 1 | -1/+2 |
| * | arm: Fix arm {,u}subvdi4 and usubvsi4 expanders [PR94286] | Jakub Jelinek | 2020-03-24 | 1 | -3/+4 |
| * | gcc, Arm: Fix no_cond issue introduced by MVE | Andre Simoes Dias Vieira | 2020-03-20 | 1 | -4/+4 |
| * | [ARM][GCC][2/x]: MVE ACLE intrinsics framework patch. | Srinath Parvathaneni | 2020-03-16 | 1 | -2/+6 |
| * | [ARM][GCC][1/x]: MVE ACLE intrinsics framework patch. | Srinath Parvathaneni | 2020-03-16 | 1 | -8/+13 |
| * | [ARM] Fix -mpure-code for v6m | Christophe Lyon | 2020-02-25 | 1 | -0/+9 |
| * | [PATCH, GCC/ARM] Fix MVE scalar shift tests | Mihail Ionescu | 2020-02-21 | 1 | -3/+3 |
| * | arm: correct constraints on movsi_compare0 [PR91913] | Richard Earnshaw | 2020-02-10 | 1 | -3/+8 |
| * | This patch is for PR target/91816 | Stam Markianos-Wright | 2020-02-03 | 1 | -22/+82 |
| * | arm: Fix uaddvdi4 expander [PR93494] | Jakub Jelinek | 2020-01-30 | 1 | -1/+1 |
| * | [GCC/ARM, 2/2] Add support for ASRL(imm), LSLL(imm) and LSRL(imm) instruction... | Mihail Ionescu | 2020-01-17 | 1 | -3/+15 |
| * | [GCC/ARM, 1/2] Add support for ASRL(reg) and LSLL(reg) instructions for Armv8... | Mihail Ionescu | 2020-01-17 | 1 | -0/+26 |
| * | [GCC][PATCH][ARM] Add Bfloat16_t scalar type, vector types and machine modes ... | Stam Markianos-Wright | 2020-01-16 | 1 | -19/+19 |
| * | [PATCH, GCC/ARM, 9/10] Call nscall function with blxns | Mihail Ionescu | 2020-01-16 | 1 | -6/+12 |
| * | Update copyright years. | Jakub Jelinek | 2020-01-01 | 1 | -1/+1 |
| * | arm: Rename CC_NOOVmode to CC_NZmode | Richard Henderson | 2019-11-14 | 1 | -93/+93 |
| * | [arm][6/X] Add support for __[us]sat16 intrinsics | Kyrylo Tkachov | 2019-11-07 | 1 | -0/+27 |
| * | [arm][5/X] Implement Q-bit-setting SIMD32 intrinsics | Kyrylo Tkachov | 2019-11-07 | 1 | -0/+56 |
| * | [arm][4/X] Add initial support for GE-setting SIMD32 intrinsics | Kyrylo Tkachov | 2019-11-07 | 1 | -2/+26 |
| * | [arm][3/X] Implement __smla* intrinsics (Q-setting) | Kyrylo Tkachov | 2019-11-07 | 1 | -2/+134 |
| * | [arm][2/X] Implement __qadd, __qsub, __qdbl intrinsics | Kyrylo Tkachov | 2019-11-07 | 1 | -0/+26 |
| * | [arm][1/X] Add initial support for saturation intrinsics | Kyrylo Tkachov | 2019-11-07 | 1 | -7/+145 |
| * | [arm] Pattern match insns for a + ~b + Carry | Richard Earnshaw | 2019-10-31 | 1 | -0/+35 |
| * | [arm] Match subtraction from carry_operation | Richard Earnshaw | 2019-10-22 | 1 | -0/+13 |
| * | [arm] clean up alu+shift patterns | Richard Earnshaw | 2019-10-21 | 1 | -87/+79 |
| * | [arm] Improvements to negvsi4 and negvdi4. | Richard Earnshaw | 2019-10-18 | 1 | -36/+5 |
| * | [arm] Early expansion of subvdi4 | Richard Earnshaw | 2019-10-18 | 1 | -17/+114 |
| * | [arm] Improve constant handling for subvsi4. | Richard Earnshaw | 2019-10-18 | 1 | -5/+91 |
| * | [arm] Early expansion of usubvdi4. | Richard Earnshaw | 2019-10-18 | 1 | -4/+109 |
| * | [arm] Improve constant handling for usubvsi4. | Richard Earnshaw | 2019-10-18 | 1 | -5/+41 |
| * | [arm] Early split addvdi4 | Richard Earnshaw | 2019-10-18 | 1 | -21/+160 |
| * | [arm] Allow the summation result of signed add-with-overflow to be discarded. | Richard Earnshaw | 2019-10-18 | 1 | -0/+78 |
| * | [arm] Improve code generation for addvsi4. | Richard Earnshaw | 2019-10-18 | 1 | -10/+53 |
| * | [arm] Early expansion of uaddvdi4. | Richard Earnshaw | 2019-10-18 | 1 | -19/+152 |
| * | [arm] Handle immediate values in uaddvsi4 | Richard Earnshaw | 2019-10-18 | 1 | -56/+62 |
| * | [arm] Cleanup dead code - old support for DImode comparisons | Richard Earnshaw | 2019-10-18 | 1 | -45/+0 |
| * | [arm] Handle some constant comparisons using rsbs+rscs | Richard Earnshaw | 2019-10-18 | 1 | -0/+27 |
| * | [arm] early split most DImode comparison operations. | Richard Earnshaw | 2019-10-18 | 1 | -0/+45 |
| * | [arm] Improve handling of DImode comparisions against constants. | Richard Earnshaw | 2019-10-18 | 1 | -2/+2 |
| * | [arm] Early split simple DImode equality comparisons | Richard Earnshaw | 2019-10-18 | 1 | -11/+0 |
