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* [ARM][GCC][8/5x]: Remaining MVE store intrinsics which stores an half word, w...Srinath Parvathaneni2020-03-185-3/+994
* [ARM][GCC][7/5x]: MVE store intrinsics which stores byte,half word or word to...Srinath Parvathaneni2020-03-183-2/+794
* [ARM][GCC][6/5x]: Remaining MVE load intrinsics which loads half word and wor...Srinath Parvathaneni2020-03-183-2/+819
* [ARM][GCC][5/5x]: MVE ACLE load intrinsics which load a byte, halfword, or wo...Srinath Parvathaneni2020-03-183-5/+694
* [ARM][GCC][4/5x]: MVE load intrinsics with zero(_z) suffix.Srinath Parvathaneni2020-03-184-2/+222
* [ARM][GCC][3/5x]: MVE store intrinsics with predicated suffix.Srinath Parvathaneni2020-03-184-0/+217
* [ARM][GCC][2/5x]: MVE load intrinsics.Srinath Parvathaneni2020-03-184-2/+281
* [ARM][GCC][1/5x]: MVE store intrinsics.Srinath Parvathaneni2020-03-184-2/+250
* [ARM][GCC][4/4x]: MVE intrinsics with quaternary operands.Srinath Parvathaneni2020-03-183-293/+1617
* [ARM][GCC][3/4x]: MVE intrinsics with quaternary operands.Srinath Parvathaneni2020-03-185-4/+1422
* [ARM][GCC][2/4x]: MVE intrinsics with quaternary operands.Srinath Parvathaneni2020-03-183-2/+4235
* [ARM][GCC][1/4x]: MVE intrinsics with quaternary operands.Srinath Parvathaneni2020-03-184-21/+498
* [ARM][GCC][3/3x]: MVE intrinsics with ternary operands.Srinath Parvathaneni2020-03-183-54/+4066
* [ARM][GCC][2/3x]: MVE intrinsics with ternary operands.Srinath Parvathaneni2020-03-185-3/+4008
* amdgcn: Fix vector compare modesAndrew Stubbs2020-03-182-2/+6
* amdgcn: Add cond_add/sub/and/ior/xor for all vector modesAndrew Stubbs2020-03-181-15/+12
* Fix up duplicated duplicated words in commentsJakub Jelinek2020-03-181-1/+1
* aarch64: Fix SYMBOL_TINY_GOT handling for ILP32 [PR94201]Duan bo2020-03-182-8/+31
* aarch64: Treat p12-p15 as call-preserved in SVE PCS functionsRichard Sandiford2020-03-181-7/+24
* aarch64: Fix bf16_v(ld|st)n.c failures for big-endianRichard Sandiford2020-03-171-1/+2
* [ARM][GCC][1/3x]: MVE intrinsics with ternary operands.Srinath Parvathaneni2020-03-174-295/+995
* [ARM][GCC][5/2x]: MVE intrinsics with binary operands.Srinath Parvathaneni2020-03-173-328/+3413
* [ARM][GCC][4/2x]: MVE intrinsics with binary operands.Srinath Parvathaneni2020-03-175-4/+5000
* [ARM][GCC][3/2x]: MVE intrinsics with binary operands.Srinath Parvathaneni2020-03-174-4/+238
* [ARM][GCC][2/2x]: MVE intrinsics with binary operands.Srinath Parvathaneni2020-03-176-4/+256
* [ARM][GCC][1/2x]: MVE intrinsics with binary operands.Srinath Parvathaneni2020-03-176-4/+206
* [ARM][GCC][4/1x]: MVE intrinsics with unary operand.Srinath Parvathaneni2020-03-174-1/+79
* [ARM][GCC][3/1x]: MVE intrinsics with unary operand.Srinath Parvathaneni2020-03-175-6/+1063
* Fix up duplicated duplicated words mostly in commentsJakub Jelinek2020-03-1716-21/+21
* [GCC][PATCH][ARM] Add multilib mapping for Armv8.1-M+MVE with -mfloat-abi=hardMihail Ionescu2020-03-171-6/+7
* [ARM][GCC][2/1x]: MVE intrinsics with unary operand.Srinath Parvathaneni2020-03-174-2/+217
* [ARM][GCC][1/1x]: Patch to support MVE ACLE intrinsics with unary operand.Srinath Parvathaneni2020-03-174-1/+536
* [ARM][GCC][4/x]: MVE ACLE vector interleaving store intrinsics.Srinath Parvathaneni2020-03-177-10/+463
* [ARM][GCC][3/x]: MVE ACLE intrinsics framework patch.Srinath Parvathaneni2020-03-161-3/+19
* [ARM][GCC][2/x]: MVE ACLE intrinsics framework patch.Srinath Parvathaneni2020-03-168-71/+131
* [ARM][GCC][1/x]: MVE ACLE intrinsics framework patch.Srinath Parvathaneni2020-03-1617-150/+611
* i386: Use ix86_output_ssemov for SImode TYPE_SSEMOVH.J. Lu2020-03-162-28/+2
* i386: Use ix86_output_ssemov for SFmode TYPE_SSEMOVH.J. Lu2020-03-152-24/+11
* driver: Fix redundant descriptions in optionsLewis Hyatt2020-03-152-3/+3
* i386: Use ix86_output_ssemov for DImode TYPE_SSEMOVH.J. Lu2020-03-141-29/+2
* Fix doubled indefinite articles, mostly in comments.Jakub Jelinek2020-03-142-2/+2
* Fix UBSAN error, shifting 64 bit value by 64.Aaron Sawdey2020-03-131-1/+4
* aarch64: Fix another bug in aarch64_add_offset_1 [PR94121]Jakub Jelinek2020-03-131-1/+2
* i386: Use ix86_output_ssemov for DFmode TYPE_SSEMOVH.J. Lu2020-03-132-41/+9
* aarch64: Add --params to control the number of recip steps [PR94154]Bu Le2020-03-132-3/+14
* Support for the CPEN control register was removed in rev .50 of the RXv1 Inst...Jeff Law2020-03-122-2/+0
* i386: Use ix86_output_ssemov for MMX TYPE_SSEMOVH.J. Lu2020-03-122-27/+21
* [rs6000] Fix a wrong GC issueBin Bin Lv2020-03-113-4/+5
* Bug fix: cannot convert 'const short int*' to 'const __bf16*'Delia Burduv2020-03-112-13/+15
* pdp11: Fix handling of common (local and global) vars [PR94134]Jakub Jelinek2020-03-111-1/+2
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