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authorJoel Brobecker <brobecker@gnat.com>2010-09-28 21:46:09 +0000
committerJoel Brobecker <brobecker@gnat.com>2010-09-28 21:46:09 +0000
commit27a709284e8419d78ee042ec78fda19e11a94017 (patch)
tree4a9d4f5bd6b498c9a275504294c611b12408a163 /gdb/configure.tgt
parent9e580aa51107b206d0e1306f126996dd8db71dcf (diff)
downloadgdb-27a709284e8419d78ee042ec78fda19e11a94017.tar.gz
Add a sparc simulator with the sparc bareboard target.
gdb/ChangeLog: * configure.tgt (sparc-*-*): Set gdb_sim to ../sim/erc32/libsim.a. (sparc-*-rtems*): Delete, now redundant with the sparc-*-* case.
Diffstat (limited to 'gdb/configure.tgt')
-rw-r--r--gdb/configure.tgt6
1 files changed, 1 insertions, 5 deletions
diff --git a/gdb/configure.tgt b/gdb/configure.tgt
index 80cfb490272..24a6bf91c12 100644
--- a/gdb/configure.tgt
+++ b/gdb/configure.tgt
@@ -514,15 +514,11 @@ sparc-*-solaris2* | sparcv9-*-solaris2* | sparc64-*-solaris2*)
gdb_target_obs="sparc64-tdep.o sparc64-sol2-tdep.o sparc-tdep.o \
sparc-sol2-tdep.o sol2-tdep.o solib.o solib-svr4.o"
;;
-sparc-*-rtems*)
- # Target: SPARC embedded with simulator
- gdb_target_obs="sparc-tdep.o"
- gdb_sim=../sim/erc32/libsim.a
- ;;
sparc-*-*)
# Target: SPARC
gdb_target_obs="sparc-tdep.o ravenscar-thread.o \
ravenscar-sparc-thread.o"
+ gdb_sim=../sim/erc32/libsim.a
;;
sparc64-*-*)
# Target: UltraSPARC