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| author | Maciej W. Rozycki <macro@linux-mips.org> | 2012-04-10 22:54:23 +0000 |
|---|---|---|
| committer | Maciej W. Rozycki <macro@linux-mips.org> | 2012-04-10 22:54:23 +0000 |
| commit | 62383a0b28edf21925d503b780515f2f7461efba (patch) | |
| tree | e45cafa765e868d70e04ff76a4ac152584e9c567 /gdb/mips-tdep.c | |
| parent | 904b1e91792c8c460f8c0c29509a04cb8e955225 (diff) | |
| download | gdb-62383a0b28edf21925d503b780515f2f7461efba.tar.gz | |
* mips-tdep.c (mips32_next_pc): Handle JALX.
Diffstat (limited to 'gdb/mips-tdep.c')
| -rw-r--r-- | gdb/mips-tdep.c | 18 |
1 files changed, 10 insertions, 8 deletions
diff --git a/gdb/mips-tdep.c b/gdb/mips-tdep.c index 013b07c8803..7ec358387b3 100644 --- a/gdb/mips-tdep.c +++ b/gdb/mips-tdep.c @@ -1203,6 +1203,16 @@ mips32_next_pc (struct frame_info *frame, CORE_ADDR pc) && (itype_rt (inst) & 2) == 0) /* BC1ANY4F, BC1ANY4T: 010001 01010 xxx0x */ pc = mips32_bc1_pc (gdbarch, frame, inst, pc + 4, 4); + else if (itype_op (inst) == 29) + /* JALX: 011101 */ + /* The new PC will be alternate mode. */ + { + unsigned long reg; + + reg = jtype_target (inst) << 2; + /* Add 1 to indicate 16-bit mode -- invert ISA mode. */ + pc = ((pc + 4) & ~(CORE_ADDR) 0x0fffffff) + reg + 1; + } else pc += 4; /* Not a branch, next instruction is easy. */ } @@ -1295,14 +1305,6 @@ mips32_next_pc (struct frame_info *frame, CORE_ADDR pc) pc = reg + ((pc + 4) & ~(CORE_ADDR) 0x0fffffff); } break; - /* FIXME case JALX : */ - { - unsigned long reg; - reg = jtype_target (inst) << 2; - pc = reg + ((pc + 4) & ~(CORE_ADDR) 0x0fffffff) + 1; /* yes, +1 */ - /* Add 1 to indicate 16 bit mode - Invert ISA mode */ - } - break; /* The new PC will be alternate mode */ case 4: /* BEQ, BEQL */ equal_branch: if (get_frame_register_signed (frame, itype_rs (inst)) == |