* NEWS: Document target described register support for PowerPC.

	* ppc-tdep.h: Remove ppc_spr constants.
	(struct gdbarch_tdep): Remove regs, ppc_sr0_regnum, and
	ppc_builtin_type_vec128 members.
	(PPC_R0_REGNUM, PPC_F0_REGNUM, PPC_PC_REGNUM, PPC_MSR_REGNUM)
	(PPC_CR_REGNUM, PPC_LR_REGNUM, PPC_CTR_REGNUM, PPC_XER_REGNUM)
	(PPC_FPSCR_REGNUM, PPC_MQ_REGNUM, PPC_SPE_UPPER_GP0_REGNUM)
	(PPC_SPE_ACC_REGNUM, PPC_SPE_FSCR_REGNUM, PPC_VR0_REGNUM)
	(PPC_VSCR_REGNUM, PPC_VRSAVE_REGNUM, PPC_NUM_REGS): New constants.
	* rs6000-tdep.c: Include preparsed descriptions.
	(init_sim_regno_table): Do not iterate over pseudo registers.
	Look up segment registers by name.  Use sim_spr_register_name
	for SPRs.
	(rs6000_register_sim_regno): Call init_sim_regno_table here.
	(rs6000_builtin_type_vec128): Delete.
	(rs6000_register_name): Only handle SPE pseudo registers and upper
	halves.  Call tdesc_register_name for everything else.
	(rs6000_register_type): Delete.  Replace with...
	(rs6000_pseudo_register_type): ...this new function.  Only handle
	SPE pseudo registers.
	(rs6000_register_reggroup_p): Delete.  Replace with...
	(rs6000_pseudo_register_reggroup_p): ...this new function.  Only
	handle SPE pseudo registers.
	(rs6000_convert_register_p): Use ppc_fp0_regnum instead of
	"struct reg".
	(rs6000_register_to_value, rs6000_value_to_register): Remove check
	of reg->fpr.
	(e500_register_reggroup_p): Delete.
	(STR, R, R4, R8, R16, F, P8, R32, R64, R0, A4, S, S4, SN4, S64)
	(COMMON_UISA_REGS, PPC_UISA_SPRS, PPC_UISA_NOFP_SPRS)
	(PPC_SEGMENT_REGS, PPC_OEA_SPRS, PPC_ALTIVEC_REGS, PPC_SPE_GP_REGS)
	(PPC_SPE_UPPER_GP_REGS, PPC_EV_PSEUDO_REGS): Delete macros.
	(registers_powerpc, registers_403, registers_403GC, registers_505)
	(registers_860, registers_601, registers_602, registers_603)
	(registers_604, registers_750, registers_7400, registers_e500): Delete
	variables.
	(struct variant): Delete nregs, npregs, num_tot_regs, and regs.  Add
	tdesc.
	(tot_num_registers, num_registers, num_pseudo_registers): Delete.
	(variants): Delete outdated comment.  Use standard target descriptions
	instead of "struct reg" arrays.
	(init_variants): Delete.
	(rs6000_gdbarch_init): Do not guess word size from the BFD
	architecture if we have a target description.  Select a variant
	before creating a new architecture.  Use the variant's target
	description if the target did not define a register layout.
	Validate target-supplied registers.  Reject mismatches.  Use
	fixed register numbers and new constants instead of magic
	numbers.  Call set_gdbarch_ps_regnum.  Call tdesc_use_registers.
	(_initialize_rs6000_tdep): Initialize the preparsed target
	descriptions.
	* target-descriptions.c (tdesc_predefined_types): Add int128 and
	uint128.
	(tdesc_find_register_early): New function.
	(tdesc_numbered_register): Use it.
	(tdesc_register_size): New function.
	(tdesc_use_registers): Take a target_desc argument.  Do not use
	gdbarch_target_desc.
	* target-descriptions.h (tdesc_use_registers): Update prototype
	and comment.
	(tdesc_register_size): New prototype.
	* Makefile.in (powerpc_32_c, powerpc_403_c, powerpc_403gc_c)
	(powerpc_505_c, powerpc_601_c, powerpc_602_c, powerpc_603_c)
	(powerpc_604_c, powerpc_64_c, powerpc_7400_c, powerpc_750_c)
	(powerpc_860_c, powerpc_e500_c, rs6000_c): New macros.
	(rs6000-tdep.o): Update.
	* arm-tdep.c (arm_gdbarch_init): Update call to tdesc_use_registers.
	* m68k-tdep.c (m68k_gdbarch_init): Likewise.
	* mips-tdep.c (mips_gdbarch_init): Likewise.

	* gdb.texinfo (Predefined Target Types): Add int128
	and uint128.
	(Standard Target Features): Add PowerPC features.

	* gdb.xml/tdesc-regs.exp: Add PowerPC support.

	* sim-ppc.h (sim_spr_register_name): New prototype.

	* gdb-sim.c (regnum2spr): Rename to...
	(sim_spr_register_name): ... this.  Make global.

1 files changed, 24 insertions, 187 deletions

diff --git a/gdb/ppc-tdep.h b/gdb/ppc-tdep.h
index 3c169734bc4..76fcf9e76ab 100644
--- a/gdb/ppc-tdep.h
+++ b/gdb/ppc-tdep.h
@@ -139,7 +139,6 @@ extern void ppc_collect_fpregset (const struct regset *regset,
 struct gdbarch_tdep
   {
     int wordsize;              /* size in bytes of fixed-point word */
-    const struct reg *regs;    /* from current variant */
     int ppc_gp0_regnum;		/* GPR register 0 */
     int ppc_toc_regnum;		/* TOC register */
     int ppc_ps_regnum;	        /* Processor (or machine) status (%msr) */
@@ -156,9 +155,6 @@ struct gdbarch_tdep
     int ppc_fp0_regnum;         /* floating-point register 0 */
     int ppc_fpscr_regnum;	/* fp status and condition register */
 
-    /* Segment registers.  */
-    int ppc_sr0_regnum;         /* segment register 0 */
-
     /* Multiplier-Quotient Register (older POWER architectures only).  */
     int ppc_mq_regnum;
 
@@ -186,7 +182,6 @@ struct gdbarch_tdep
 
     /* ISA-specific types.  */
     struct type *ppc_builtin_type_vec64;
-    struct type *ppc_builtin_type_vec128;
 };
 
 
@@ -200,189 +195,31 @@ enum
   };
 
 
-/* Constants for SPR register numbers.  These are *not* GDB register
-   numbers: they are the numbers used in the PowerPC ISA itself to
-   refer to these registers.
-
-   This table includes all the SPRs from all the variants I could find
-   documentation for.
-
-   There may be registers from different PowerPC variants assigned the
-   same number, but that's fine: GDB and the SIM always use the
-   numbers in the context of a particular variant, so it's not
-   ambiguous.
-
-   We need to deviate from the naming pattern when variants have
-   special-purpose registers of the same name, but with different
-   numbers.  Fortunately, this is rare: look below to see how we
-   handle the 'tcr' registers on the 403/403GX and 602.  */
+/* Register number constants.  These are GDB internal register
+   numbers; they are not used for the simulator or remote targets.
+   Extra SPRs (those other than MQ, CTR, LR, XER, SPEFSCR) are given
+   numbers above PPC_NUM_REGS.  So are segment registers and other
+   target-defined registers.  */
+enum {
+  PPC_R0_REGNUM = 0,
+  PPC_F0_REGNUM = 32,
+  PPC_PC_REGNUM = 64,
+  PPC_MSR_REGNUM = 65,
+  PPC_CR_REGNUM = 66,
+  PPC_LR_REGNUM = 67,
+  PPC_CTR_REGNUM = 68,
+  PPC_XER_REGNUM = 69,
+  PPC_FPSCR_REGNUM = 70,
+  PPC_MQ_REGNUM = 71,
+  PPC_SPE_UPPER_GP0_REGNUM = 72,
+  PPC_SPE_ACC_REGNUM = 104,
+  PPC_SPE_FSCR_REGNUM = 105,
+  PPC_VR0_REGNUM = 106,
+  PPC_VSCR_REGNUM = 138,
+  PPC_VRSAVE_REGNUM = 139,
+  PPC_NUM_REGS
+};
 
-enum
-  {
-    ppc_spr_mq        =    0,
-    ppc_spr_xer       =    1,
-    ppc_spr_rtcu      =    4,
-    ppc_spr_rtcl      =    5,
-    ppc_spr_lr        =    8,
-    ppc_spr_ctr       =    9,
-    ppc_spr_cnt       =    9,
-    ppc_spr_dsisr     =   18,
-    ppc_spr_dar       =   19,
-    ppc_spr_dec       =   22,
-    ppc_spr_sdr1      =   25,
-    ppc_spr_srr0      =   26,
-    ppc_spr_srr1      =   27,
-    ppc_spr_eie       =   80,
-    ppc_spr_eid       =   81,
-    ppc_spr_nri       =   82,
-    ppc_spr_sp        =  102,
-    ppc_spr_cmpa      =  144,
-    ppc_spr_cmpb      =  145,
-    ppc_spr_cmpc      =  146,
-    ppc_spr_cmpd      =  147,
-    ppc_spr_icr       =  148,
-    ppc_spr_der       =  149,
-    ppc_spr_counta    =  150,
-    ppc_spr_countb    =  151,
-    ppc_spr_cmpe      =  152,
-    ppc_spr_cmpf      =  153,
-    ppc_spr_cmpg      =  154,
-    ppc_spr_cmph      =  155,
-    ppc_spr_lctrl1    =  156,
-    ppc_spr_lctrl2    =  157,
-    ppc_spr_ictrl     =  158,
-    ppc_spr_bar       =  159,
-    ppc_spr_vrsave    =  256,
-    ppc_spr_sprg0     =  272,
-    ppc_spr_sprg1     =  273,
-    ppc_spr_sprg2     =  274,
-    ppc_spr_sprg3     =  275,
-    ppc_spr_asr       =  280,
-    ppc_spr_ear       =  282,
-    ppc_spr_tbl       =  284,
-    ppc_spr_tbu       =  285,
-    ppc_spr_pvr       =  287,
-    ppc_spr_spefscr   =  512,
-    ppc_spr_ibat0u    =  528,
-    ppc_spr_ibat0l    =  529,
-    ppc_spr_ibat1u    =  530,
-    ppc_spr_ibat1l    =  531,
-    ppc_spr_ibat2u    =  532,
-    ppc_spr_ibat2l    =  533,
-    ppc_spr_ibat3u    =  534,
-    ppc_spr_ibat3l    =  535,
-    ppc_spr_dbat0u    =  536,
-    ppc_spr_dbat0l    =  537,
-    ppc_spr_dbat1u    =  538,
-    ppc_spr_dbat1l    =  539,
-    ppc_spr_dbat2u    =  540,
-    ppc_spr_dbat2l    =  541,
-    ppc_spr_dbat3u    =  542,
-    ppc_spr_dbat3l    =  543,
-    ppc_spr_ic_cst    =  560,
-    ppc_spr_ic_adr    =  561,
-    ppc_spr_ic_dat    =  562,
-    ppc_spr_dc_cst    =  568,
-    ppc_spr_dc_adr    =  569,
-    ppc_spr_dc_dat    =  570,
-    ppc_spr_dpdr      =  630,
-    ppc_spr_dpir      =  631,
-    ppc_spr_immr      =  638,
-    ppc_spr_mi_ctr    =  784,
-    ppc_spr_mi_ap     =  786,
-    ppc_spr_mi_epn    =  787,
-    ppc_spr_mi_twc    =  789,
-    ppc_spr_mi_rpn    =  790,
-    ppc_spr_mi_cam    =  816,
-    ppc_spr_mi_ram0   =  817,
-    ppc_spr_mi_ram1   =  818,
-    ppc_spr_md_ctr    =  792,
-    ppc_spr_m_casid   =  793,
-    ppc_spr_md_ap     =  794,
-    ppc_spr_md_epn    =  795,
-    ppc_spr_m_twb     =  796,
-    ppc_spr_md_twc    =  797,
-    ppc_spr_md_rpn    =  798,
-    ppc_spr_m_tw      =  799,
-    ppc_spr_mi_dbcam  =  816,
-    ppc_spr_mi_dbram0 =  817,
-    ppc_spr_mi_dbram1 =  818,
-    ppc_spr_md_dbcam  =  824,
-    ppc_spr_md_cam    =  824,
-    ppc_spr_md_dbram0 =  825,
-    ppc_spr_md_ram0   =  825,
-    ppc_spr_md_dbram1 =  826,
-    ppc_spr_md_ram1   =  826,
-    ppc_spr_ummcr0    =  936,
-    ppc_spr_upmc1     =  937,
-    ppc_spr_upmc2     =  938,
-    ppc_spr_usia      =  939,
-    ppc_spr_ummcr1    =  940,
-    ppc_spr_upmc3     =  941,
-    ppc_spr_upmc4     =  942,
-    ppc_spr_zpr       =  944,
-    ppc_spr_pid       =  945,
-    ppc_spr_mmcr0     =  952,
-    ppc_spr_pmc1      =  953,
-    ppc_spr_sgr       =  953,
-    ppc_spr_pmc2      =  954,
-    ppc_spr_dcwr      =  954,
-    ppc_spr_sia       =  955,
-    ppc_spr_mmcr1     =  956,
-    ppc_spr_pmc3      =  957,
-    ppc_spr_pmc4      =  958,
-    ppc_spr_sda       =  959,
-    ppc_spr_tbhu      =  972,
-    ppc_spr_tblu      =  973,
-    ppc_spr_dmiss     =  976,
-    ppc_spr_dcmp      =  977,
-    ppc_spr_hash1     =  978,
-    ppc_spr_hash2     =  979,
-    ppc_spr_icdbdr    =  979,
-    ppc_spr_imiss     =  980,
-    ppc_spr_esr       =  980,
-    ppc_spr_icmp      =  981,
-    ppc_spr_dear      =  981,
-    ppc_spr_rpa       =  982,
-    ppc_spr_evpr      =  982,
-    ppc_spr_cdbcr     =  983,
-    ppc_spr_tsr       =  984,
-    ppc_spr_602_tcr   =  984,
-    ppc_spr_403_tcr   =  986,
-    ppc_spr_ibr       =  986,
-    ppc_spr_pit       =  987,
-    ppc_spr_esasrr    =  988,
-    ppc_spr_tbhi      =  988,
-    ppc_spr_tblo      =  989,
-    ppc_spr_srr2      =  990,
-    ppc_spr_sebr      =  990,
-    ppc_spr_srr3      =  991,
-    ppc_spr_ser       =  991,
-    ppc_spr_hid0      = 1008,
-    ppc_spr_dbsr      = 1008,
-    ppc_spr_hid1      = 1009,
-    ppc_spr_iabr      = 1010,
-    ppc_spr_dbcr      = 1010,
-    ppc_spr_iac1      = 1012,
-    ppc_spr_dabr      = 1013,
-    ppc_spr_iac2      = 1013,
-    ppc_spr_dac1      = 1014,
-    ppc_spr_dac2      = 1015,
-    ppc_spr_l2cr      = 1017,
-    ppc_spr_dccr      = 1018,
-    ppc_spr_ictc      = 1019,
-    ppc_spr_iccr      = 1019,
-    ppc_spr_thrm1     = 1020,
-    ppc_spr_pbl1      = 1020,
-    ppc_spr_thrm2     = 1021,
-    ppc_spr_pbu1      = 1021,
-    ppc_spr_thrm3     = 1022,
-    ppc_spr_pbl2      = 1022,
-    ppc_spr_fpecr     = 1022,
-    ppc_spr_lt        = 1022,
-    ppc_spr_pir       = 1023,
-    ppc_spr_pbu2      = 1023
-  };
 
 /* Instruction size.  */
 #define PPC_INSN_SIZE 4