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authorNathan Froyd <froydnj@codesourcery.com>2010-11-12 21:53:09 +0000
committerNathan Froyd <froydnj@codesourcery.com>2010-11-12 21:53:09 +0000
commit774ffe9e9d84a0ff884bb2b21d97c8f915c5152e (patch)
tree3444d61a5e739b88c621840b945a64c5487f7c7a /gdb/rs6000-tdep.c
parent550202613b8b567107580a062f418947b689e1ed (diff)
downloadgdb-774ffe9e9d84a0ff884bb2b21d97c8f915c5152e.tar.gz
gdb/
* rs6000-tdep.c (gdb_print_insn_powerpc): Disassemble e500 instructions if debugging an E500 binary.
Diffstat (limited to 'gdb/rs6000-tdep.c')
-rw-r--r--gdb/rs6000-tdep.c14
1 files changed, 13 insertions, 1 deletions
diff --git a/gdb/rs6000-tdep.c b/gdb/rs6000-tdep.c
index 09c7f8ff9c4..611c775e3c6 100644
--- a/gdb/rs6000-tdep.c
+++ b/gdb/rs6000-tdep.c
@@ -3029,7 +3029,19 @@ static int
gdb_print_insn_powerpc (bfd_vma memaddr, disassemble_info *info)
{
if (!info->disassembler_options)
- info->disassembler_options = "any";
+ {
+ /* When debugging E500 binaries and disassembling code containing
+ E500-specific (SPE) instructions, one sometimes sees AltiVec
+ instructions instead. The opcode spaces for SPE instructions
+ and AltiVec instructions overlap, and specifiying the "any" cpu
+ looks for AltiVec instructions first. If we know we're
+ debugging an E500 binary, however, we can specify the "e500x2"
+ cpu and get much more sane disassembly output. */
+ if (info->mach == bfd_mach_ppc_e500)
+ info->disassembler_options = "e500x2";
+ else
+ info->disassembler_options = "any";
+ }
if (info->endian == BFD_ENDIAN_BIG)
return print_insn_big_powerpc (memaddr, info);