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| author | Richard Sandiford <rsandifo@nildram.co.uk> | 2013-06-23 20:12:52 +0000 |
|---|---|---|
| committer | Richard Sandiford <rsandifo@nildram.co.uk> | 2013-06-23 20:12:52 +0000 |
| commit | 25a948329f80baff44515be099a541903d6f653d (patch) | |
| tree | 201caee80732b0c48ba659c8de6634b2f275e13b /include | |
| parent | c5fd8c697168f895c5ccf6600b3ee34634c993e0 (diff) | |
| download | gdb-25a948329f80baff44515be099a541903d6f653d.tar.gz | |
include/opcode/
* mips.h: Fix comment typo: "G" is _RS rather than _RD for microMIPS.
gas/
* config/tc-mips.c (mips_ip): Fix swapped bit numbers in comments.
Diffstat (limited to 'include')
| -rw-r--r-- | include/opcode/ChangeLog | 4 | ||||
| -rw-r--r-- | include/opcode/mips.h | 2 |
2 files changed, 5 insertions, 1 deletions
diff --git a/include/opcode/ChangeLog b/include/opcode/ChangeLog index 4daf47bc094..189a1d4176c 100644 --- a/include/opcode/ChangeLog +++ b/include/opcode/ChangeLog @@ -1,3 +1,7 @@ +2013-06-23 Richard Sandiford <rdsandiford@googlemail.com> + + * mips.h: Fix comment typo: "G" is _RS rather than _RD for microMIPS. + 2013-06-17 Catherine Moore <clm@codesourcery.com> Maciej W. Rozycki <macro@codesourcery.com> Chao-Ying Fu <fu@mips.com> diff --git a/include/opcode/mips.h b/include/opcode/mips.h index 9d241e847a6..e62ecd6e6db 100644 --- a/include/opcode/mips.h +++ b/include/opcode/mips.h @@ -1811,7 +1811,7 @@ extern const int bfd_mips16_num_opcodes; Coprocessor instructions: "E" 5-bit target register (MICROMIPSOP_*_RT) - "G" 5-bit destination register (MICROMIPSOP_*_RD) + "G" 5-bit destination register (MICROMIPSOP_*_RS) "H" 3-bit sel field for (D)MTC* and (D)MFC* (MICROMIPSOP_*_SEL) "+D" combined destination register ("G") and sel ("H") for CP0 ops, for pretty-printing in disassembly only |