diff options
| author | H.J. Lu <hjl@lucon.org> | 2006-02-23 21:36:18 +0000 |
|---|---|---|
| committer | H.J. Lu <hjl@lucon.org> | 2006-02-23 21:36:18 +0000 |
| commit | 71521dc477e2ac5b110ca5ccdf2b8126592106c8 (patch) | |
| tree | 156cfb8378aed59f4b4a5cfd716cf63badc598c0 /opcodes/ia64-opc-i.c | |
| parent | a0f577daaaa4f22875bd4ea807fdeed9e380f9e0 (diff) | |
| download | gdb-71521dc477e2ac5b110ca5ccdf2b8126592106c8.tar.gz | |
bfd/
2006-02-23 H.J. Lu <hongjiu.lu@intel.com>
* cpu-ia64-opc.c (ins_immu5b): New.
(ext_immu5b): Likewise.
(elf64_ia64_operands): Add IMMU5b.
gas/
2006-02-23 H.J. Lu <hongjiu.lu@intel.com>
* config/tc-ia64.c (operand_match): Handle IA64_OPND_IMMU5b.
gas/testsuite/
2006-02-23 H.J. Lu <hongjiu.lu@intel.com>
* gas/ia64/opc-i.s: Add tests for tf.
* gas/ia64/pseudo.s: Likewise.
* gas/ia64/opc-i.d: Updated.
* gas/ia64/pseudo.d: Likewise.
include/opcode/
2006-02-23 H.J. Lu <hongjiu.lu@intel.com>
* ia64.h (ia64_opnd): Add IA64_OPND_IMMU5b.
opcodes/
2006-02-23 H.J. Lu <hongjiu.lu@intel.com>
* ia64-opc-i.c (bXc): New.
(mXc): Likewise.
(OpX2TaTbYaXcC): Likewise.
(TF). Likewise.
(TFCM). Likewise.
(ia64_opcodes_i): Add instructions for tf.
* ia64-opc.h (IMMU5b): New.
* ia64-asmtab.c: Regenerated.
Diffstat (limited to 'opcodes/ia64-opc-i.c')
| -rw-r--r-- | opcodes/ia64-opc-i.c | 30 |
1 files changed, 29 insertions, 1 deletions
diff --git a/opcodes/ia64-opc-i.c b/opcodes/ia64-opc-i.c index ad6fb1a8b1e..69cd969f6f1 100644 --- a/opcodes/ia64-opc-i.c +++ b/opcodes/ia64-opc-i.c @@ -1,5 +1,6 @@ /* ia64-opc-i.c -- IA-64 `I' opcode table. - Copyright 1998, 1999, 2000, 2002, 2005 Free Software Foundation, Inc. + Copyright 1998, 1999, 2000, 2002, 2005, 2006 + Free Software Foundation, Inc. Contributed by David Mosberger-Tang <davidm@hpl.hp.com> This file is part of GDB, GAS, and the GNU binutils. @@ -36,6 +37,7 @@ #define bWh(x) (((ia64_insn) ((x) & 0x3)) << 20) #define bX(x) (((ia64_insn) ((x) & 0x1)) << 33) #define bXb(x) (((ia64_insn) ((x) & 0x1)) << 22) +#define bXc(x) (((ia64_insn) ((x) & 0x1)) << 19) #define bX2(x) (((ia64_insn) ((x) & 0x3)) << 34) #define bX2a(x) (((ia64_insn) ((x) & 0x3)) << 34) #define bX2b(x) (((ia64_insn) ((x) & 0x3)) << 28) @@ -58,6 +60,7 @@ #define mWh bWh (-1) #define mX bX (-1) #define mXb bXb (-1) +#define mXc bXc (-1) #define mX2 bX2 (-1) #define mX2a bX2a (-1) #define mX2b bX2b (-1) @@ -83,6 +86,9 @@ #define OpX2TaTbYaC(a,b,c,d,e,f) \ (bOp (a) | bX2 (b) | bTa (c) | bTb (d) | bYa (e) | bC (f)), \ (mOp | mX2 | mTa | mTb | mYa | mC) +#define OpX2TaTbYaXcC(a,b,c,d,e,f,g) \ + (bOp (a) | bX2 (b) | bTa (c) | bTb (d) | bYa (e) | bXc (f) | bC (g)), \ + (mOp | mX2 | mTa | mTb | mYa | mXc | mC) #define OpX3(a,b) (bOp (a) | bX3 (b)), (mOp | mX3) #define OpX3X6(a,b,c) (bOp (a) | bX3 (b) | bX6(c)), \ (mOp | mX3 | mX6) @@ -164,6 +170,28 @@ struct ia64_opcode ia64_opcodes_i[] = {"dep.z", I, OpX2XYb (5, 1, 1, 0), {R1, R2, CPOS6a, LEN6}, EMPTY}, {"dep.z", I, OpX2XYb (5, 1, 1, 1), {R1, IMM8, CPOS6a, LEN6}, EMPTY}, {"dep", I, OpX2X (5, 3, 1), {R1, IMM1, R3, CPOS6b, LEN6}, EMPTY}, +#define TF(a,b,c) \ + I2, OpX2TaTbYaXcC (5, 0, a, b, 1, 1, c), {P1, P2, IMMU5b}, EMPTY +#define TFCM(a,b,c) \ + I2, OpX2TaTbYaXcC (5, 0, a, b, 1, 1, c), {P2, P1, IMMU5b}, PSEUDO, 0, NULL + {"tf.z", TF (0, 0, 0)}, + {"tf.nz", TFCM (0, 0, 0)}, + {"tf.z.unc", TF (0, 0, 1)}, + {"tf.nz.unc", TFCM (0, 0, 1)}, + {"tf.z.and", TF (0, 1, 0)}, + {"tf.nz.andcm", TFCM (0, 1, 0)}, + {"tf.nz.and", TF (0, 1, 1)}, + {"tf.z.andcm", TFCM (0, 1, 1)}, + {"tf.z.or", TF (1, 0, 0)}, + {"tf.nz.orcm", TFCM (1, 0, 0)}, + {"tf.nz.or", TF (1, 0, 1)}, + {"tf.z.orcm", TFCM (1, 0, 1)}, + {"tf.z.or.andcm", TF (1, 1, 0)}, + {"tf.nz.and.orcm", TFCM (1, 1, 0)}, + {"tf.nz.or.andcm", TF (1, 1, 1)}, + {"tf.z.and.orcm", TFCM (1, 1, 1)}, +#undef TF +#undef TFCM #define TBIT(a,b,c,d) \ I2, OpX2TaTbYaC (5, 0, a, b, c, d), {P1, P2, R3, POS6}, EMPTY #define TBITCM(a,b,c,d) \ |