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| author | Richard Sandiford <rsandifo@nildram.co.uk> | 2013-08-19 19:54:40 +0000 |
|---|---|---|
| committer | Richard Sandiford <rsandifo@nildram.co.uk> | 2013-08-19 19:54:40 +0000 |
| commit | 2d55e44be67124b3ec003795171f9cbc03d8155f (patch) | |
| tree | 1a023e6df20200f50a6633bcdaea626766f8d43a /opcodes | |
| parent | 7366de51e99df23255a6076cf99a760553772f88 (diff) | |
| download | gdb-2d55e44be67124b3ec003795171f9cbc03d8155f.tar.gz | |
include/opcode/
* mips.h (M_DEXT, M_DINS): Delete.
opcodes/
* micromips-opc.c (micromips_opcodes): Replace "dext" and "dins"
macro entries with "dextm", "dextu", "dinsm" and "dinsu" aliases.
Use +H rather than +C for the real "dext".
* mips-opc.c (mips_builtin_opcodes): Likewise.
gas/
* config/tc-mips.c (report_bad_range, report_bad_field): Delete.
(macro): Remove M_DEXT and M_DINS handling.
gas/testsuite/
* gas/mips/ext-ill.l, gas/mips/mips64r2-ill.l: Expect DEXT and DINS
error messages to have the same form as the EXT and INS ones.
* gas/mips/micromips-insn32.d, gas/mips/micromips-noinsn32.d,
gas/mips/micromips-trap.d, gas/mips/micromips.d,
gas/mips/micromips@mips64r2.d, gas/mips/mips64r2.d: Expect
"dext" and "dins" instead of "dextm", "dextu", "dinsm" and "dinsu".
Diffstat (limited to 'opcodes')
| -rw-r--r-- | opcodes/ChangeLog | 7 | ||||
| -rw-r--r-- | opcodes/micromips-opc.c | 8 | ||||
| -rw-r--r-- | opcodes/mips-opc.c | 8 |
3 files changed, 17 insertions, 6 deletions
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index b4840ee5301..af6ba2be956 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,5 +1,12 @@ 2013-08-19 Richard Sandiford <rdsandiford@googlemail.com> + * micromips-opc.c (micromips_opcodes): Replace "dext" and "dins" + macro entries with "dextm", "dextu", "dinsm" and "dinsu" aliases. + Use +H rather than +C for the real "dext". + * mips-opc.c (mips_builtin_opcodes): Likewise. + +2013-08-19 Richard Sandiford <rdsandiford@googlemail.com> + * mips-formats.h (OPTIONAL_REG, OPTIONAL_MAPPED_REG): New macros. * micromips-opc.c (decode_micromips_operand): Use OPTIONAL_REG and OPTIONAL_MAPPED_REG. diff --git a/opcodes/micromips-opc.c b/opcodes/micromips-opc.c index 33dd57e545e..da1f708d97e 100644 --- a/opcodes/micromips-opc.c +++ b/opcodes/micromips-opc.c @@ -544,8 +544,9 @@ const struct mips_opcode micromips_opcodes[] = {"dclo", "t,s", 0x58004b3c, 0xfc00ffff, WR_1|RD_2, 0, I3, 0, 0 }, {"dclz", "t,s", 0x58005b3c, 0xfc00ffff, WR_1|RD_2, 0, I3, 0, 0 }, {"deret", "", 0x0000e37c, 0xffffffff, NODS, 0, I1, 0, 0 }, -{"dext", "t,r,I,+I", 0, (int) M_DEXT, INSN_MACRO, 0, I3, 0, 0 }, -{"dext", "t,r,+A,+C", 0x5800002c, 0xfc00003f, WR_1|RD_2, 0, I3, 0, 0 }, +{"dext", "t,r,+A,+H", 0x5800002c, 0xfc00003f, WR_1|RD_2, 0, I3, 0, 0 }, +{"dext", "t,r,+A,+G", 0x58000024, 0xfc00003f, WR_1|RD_2, 0, I3, 0, 0 }, /* dextm */ +{"dext", "t,r,+E,+H", 0x58000014, 0xfc00003f, WR_1|RD_2, 0, I3, 0, 0 }, /* dextu */ {"dextm", "t,r,+A,+G", 0x58000024, 0xfc00003f, WR_1|RD_2, 0, I3, 0, 0 }, {"dextu", "t,r,+E,+H", 0x58000014, 0xfc00003f, WR_1|RD_2, 0, I3, 0, 0 }, /* For ddiv, see the comments about div. */ @@ -560,8 +561,9 @@ const struct mips_opcode micromips_opcodes[] = {"ddivu", "d,v,I", 0, (int) M_DDIVU_3I, INSN_MACRO, 0, I3, 0, 0 }, {"di", "", 0x0000477c, 0xffffffff, RD_C0, 0, I1, 0, 0 }, {"di", "s", 0x0000477c, 0xffe0ffff, WR_1|RD_C0, 0, I1, 0, 0 }, -{"dins", "t,r,I,+I", 0, (int) M_DINS, INSN_MACRO, 0, I3, 0, 0 }, {"dins", "t,r,+A,+B", 0x5800000c, 0xfc00003f, WR_1|RD_2, 0, I3, 0, 0 }, +{"dins", "t,r,+A,+F", 0x58000004, 0xfc00003f, WR_1|RD_2, 0, I3, 0, 0 }, /* dinsm */ +{"dins", "t,r,+E,+F", 0x58000034, 0xfc00003f, WR_1|RD_2, 0, I3, 0, 0 }, /* dinsu */ {"dinsm", "t,r,+A,+F", 0x58000004, 0xfc00003f, WR_1|RD_2, 0, I3, 0, 0 }, {"dinsu", "t,r,+E,+F", 0x58000034, 0xfc00003f, WR_1|RD_2, 0, I3, 0, 0 }, /* The MIPS assembler treats the div opcode with two operands as diff --git a/opcodes/mips-opc.c b/opcodes/mips-opc.c index 7fdc93865a9..6bdf60cd4d7 100644 --- a/opcodes/mips-opc.c +++ b/opcodes/mips-opc.c @@ -921,8 +921,9 @@ const struct mips_opcode mips_builtin_opcodes[] = {"dctr", "o(b)", 0xbc050000, 0xfc1f0000, RD_2, 0, I3, 0, 0 }, {"dctw", "o(b)", 0xbc090000, 0xfc1f0000, RD_2, 0, I3, 0, 0 }, {"deret", "", 0x4200001f, 0xffffffff, NODS, 0, I32|G2, 0, 0 }, -{"dext", "t,r,I,+I", 0, (int) M_DEXT, INSN_MACRO, 0, I65, 0, 0 }, -{"dext", "t,r,+A,+C", 0x7c000003, 0xfc00003f, WR_1|RD_2, 0, I65, 0, 0 }, +{"dext", "t,r,+A,+H", 0x7c000003, 0xfc00003f, WR_1|RD_2, 0, I65, 0, 0 }, +{"dext", "t,r,+A,+G", 0x7c000001, 0xfc00003f, WR_1|RD_2, 0, I65, 0, 0 }, /* dextm */ +{"dext", "t,r,+E,+H", 0x7c000002, 0xfc00003f, WR_1|RD_2, 0, I65, 0, 0 }, /* dextu */ {"dextm", "t,r,+A,+G", 0x7c000001, 0xfc00003f, WR_1|RD_2, 0, I65, 0, 0 }, {"dextu", "t,r,+E,+H", 0x7c000002, 0xfc00003f, WR_1|RD_2, 0, I65, 0, 0 }, /* For ddiv, see the comments about div. */ @@ -936,8 +937,9 @@ const struct mips_opcode mips_builtin_opcodes[] = {"di", "", 0x42000039, 0xffffffff, WR_C0, 0, EE, 0, 0 }, {"di", "", 0x41606000, 0xffffffff, WR_C0, 0, I33, 0, 0 }, {"di", "t", 0x41606000, 0xffe0ffff, WR_1|WR_C0, 0, I33, 0, 0 }, -{"dins", "t,r,I,+I", 0, (int) M_DINS, INSN_MACRO, 0, I65, 0, 0 }, {"dins", "t,r,+A,+B", 0x7c000007, 0xfc00003f, WR_1|RD_2, 0, I65, 0, 0 }, +{"dins", "t,r,+A,+F", 0x7c000005, 0xfc00003f, WR_1|RD_2, 0, I65, 0, 0 }, /* dinsm */ +{"dins", "t,r,+E,+F", 0x7c000006, 0xfc00003f, WR_1|RD_2, 0, I65, 0, 0 }, /* dinsu */ {"dinsm", "t,r,+A,+F", 0x7c000005, 0xfc00003f, WR_1|RD_2, 0, I65, 0, 0 }, {"dinsu", "t,r,+E,+F", 0x7c000006, 0xfc00003f, WR_1|RD_2, 0, I65, 0, 0 }, /* The MIPS assembler treats the div opcode with two operands as |