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| author | Alan Modra <amodra@bigpond.net.au> | 2013-07-04 01:42:08 +0000 |
|---|---|---|
| committer | Alan Modra <amodra@bigpond.net.au> | 2013-07-04 01:42:08 +0000 |
| commit | 6ca6eb40a5d2af8390af90f0ef9a577367dc5c12 (patch) | |
| tree | 4374c72af8a7cc65118e759d4c5aa11d3776d25c /opcodes | |
| parent | ac5a2a6855038988c4710d4de091659b4ad5af5e (diff) | |
| download | gdb-6ca6eb40a5d2af8390af90f0ef9a577367dc5c12.tar.gz | |
* ppc-opc.c (powerpc_opcodes): Add tdui, twui, tdu, twu, tui, tu.
Diffstat (limited to 'opcodes')
| -rw-r--r-- | opcodes/ChangeLog | 4 | ||||
| -rw-r--r-- | opcodes/ppc-opc.c | 6 |
2 files changed, 10 insertions, 0 deletions
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 28e023b67eb..e364b4b66e7 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,7 @@ +2013-07-04 Alan Modra <amodra@gmail.com> + + * ppc-opc.c (powerpc_opcodes): Add tdui, twui, tdu, twu, tui, tu. + 2013-06-26 Nick Clifton <nickc@redhat.com> * rx-decode.opc (rx_decode_opcode): Check sd field as well as ss diff --git a/opcodes/ppc-opc.c b/opcodes/ppc-opc.c index a257f861edc..82f4f1297cc 100644 --- a/opcodes/ppc-opc.c +++ b/opcodes/ppc-opc.c @@ -2792,6 +2792,7 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"tdlei", OPTO(2,TOLE), OPTO_MASK, PPC64, PPCNONE, {RA, SI}}, {"tdngi", OPTO(2,TONG), OPTO_MASK, PPC64, PPCNONE, {RA, SI}}, {"tdnei", OPTO(2,TONE), OPTO_MASK, PPC64, PPCNONE, {RA, SI}}, +{"tdui", OPTO(2,TOU), OPTO_MASK, PPC64, PPCNONE, {RA, SI}}, {"tdi", OP(2), OP_MASK, PPC64, PPCNONE, {TO, RA, SI}}, {"twlgti", OPTO(3,TOLGT), OPTO_MASK, PPCCOM, PPCNONE, {RA, SI}}, @@ -2822,6 +2823,8 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"tngi", OPTO(3,TONG), OPTO_MASK, PWRCOM, PPCNONE, {RA, SI}}, {"twnei", OPTO(3,TONE), OPTO_MASK, PPCCOM, PPCNONE, {RA, SI}}, {"tnei", OPTO(3,TONE), OPTO_MASK, PWRCOM, PPCNONE, {RA, SI}}, +{"twui", OPTO(3,TOU), OPTO_MASK, PPCCOM, PPCNONE, {RA, SI}}, +{"tui", OPTO(3,TOU), OPTO_MASK, PWRCOM, PPCNONE, {RA, SI}}, {"twi", OP(3), OP_MASK, PPCCOM, PPCNONE, {TO, RA, SI}}, {"ti", OP(3), OP_MASK, PWRCOM, PPCNONE, {TO, RA, SI}}, @@ -4350,6 +4353,8 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"twne", XTO(31,4,TONE), XTO_MASK, PPCCOM|PPCVLE, PPCNONE, {RA, RB}}, {"tne", XTO(31,4,TONE), XTO_MASK, PWRCOM, PPCNONE, {RA, RB}}, {"trap", XTO(31,4,TOU), 0xffffffff, PPCCOM|PPCVLE, PPCNONE, {0}}, +{"twu", XTO(31,4,TOU), XTO_MASK, PPCCOM|PPCVLE, PPCNONE, {RA, RB}}, +{"tu", XTO(31,4,TOU), XTO_MASK, PWRCOM, PPCNONE, {RA, RB}}, {"tw", X(31,4), X_MASK, PPCCOM|PPCVLE, PPCNONE, {TO, RA, RB}}, {"t", X(31,4), X_MASK, PWRCOM, PPCNONE, {TO, RA, RB}}, @@ -4490,6 +4495,7 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"tdle", XTO(31,68,TOLE), XTO_MASK, PPC64, PPCNONE, {RA, RB}}, {"tdng", XTO(31,68,TONG), XTO_MASK, PPC64, PPCNONE, {RA, RB}}, {"tdne", XTO(31,68,TONE), XTO_MASK, PPC64, PPCNONE, {RA, RB}}, +{"tdu", XTO(31,68,TOU), XTO_MASK, PPC64, PPCNONE, {RA, RB}}, {"td", X(31,68), X_MASK, PPC64|PPCVLE, PPCNONE, {TO, RA, RB}}, {"lwfcmx", APU(31,71,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}}, |