opcodes/

	* mips-opc.c (mips_builtin_opcodes): Remove WR_* and RD_* flags
	for operands that are hard-coded to $0.
	* micromips-opc.c (micromips_opcodes): Likewise.

3 files changed, 24 insertions, 18 deletions

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 081c9244571..324f2e94e48 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,5 +1,11 @@
 2013-08-01  Richard Sandiford  <rdsandiford@googlemail.com>
 
+	* mips-opc.c (mips_builtin_opcodes): Remove WR_* and RD_* flags
+	for operands that are hard-coded to $0.
+	* micromips-opc.c (micromips_opcodes): Likewise.
+
+2013-08-01  Richard Sandiford  <rdsandiford@googlemail.com>
+
 	* mips-opc.c (mips_builtin_opcodes): Use WR_31 rather than WR_d
 	for the single-operand forms of JALR and JALR.HB.
 	* micromips-opc.c (micromips_opcodes): Likewise JALR, JALRS, JALR.HB
diff --git a/opcodes/micromips-opc.c b/opcodes/micromips-opc.c
index 30dec8f26fd..00ee9b8c247 100644
--- a/opcodes/micromips-opc.c
+++ b/opcodes/micromips-opc.c
@@ -571,15 +571,15 @@ const struct mips_opcode micromips_opcodes[] =
 {"dextu",		"t,r,+E,+H",	0x58000014, 0xfc00003f, WR_t|RD_s,		0,		I3,		0,	0 },
 /* For ddiv, see the comments about div.  */
 {"ddiv",		"z,s,t",	0x5800ab3c, 0xfc00ffff,	RD_s|RD_t|WR_HILO,	0,		I3,		0,	0 },
-{"ddiv",		"z,t",		0x5800ab3c, 0xfc1fffff,	RD_s|RD_t|WR_HILO,	0,		I3,		0,	0 },
+{"ddiv",		"z,t",		0x5800ab3c, 0xfc1fffff,	RD_t|WR_HILO,		0,		I3,		0,	0 },
 {"ddiv",		"d,v,t",	0,    (int) M_DDIV_3,	INSN_MACRO,		0,		I3,		0,	0 },
 {"ddiv",		"d,v,I",	0,    (int) M_DDIV_3I,	INSN_MACRO,		0,		I3,		0,	0 },
 /* For ddivu, see the comments about div.  */
 {"ddivu",		"z,s,t",	0x5800bb3c, 0xfc00ffff,	RD_s|RD_t|WR_HILO,	0,		I3,		0,	0 },
-{"ddivu",		"z,t",		0x5800bb3c, 0xfc1fffff,	RD_s|RD_t|WR_HILO,	0,		I3,		0,	0 },
+{"ddivu",		"z,t",		0x5800bb3c, 0xfc1fffff,	RD_t|WR_HILO,		0,		I3,		0,	0 },
 {"ddivu",		"d,v,t",	0,    (int) M_DDIVU_3,	INSN_MACRO,		0,		I3,		0,	0 },
 {"ddivu",		"d,v,I",	0,    (int) M_DDIVU_3I,	INSN_MACRO,		0,		I3,		0,	0 },
-{"di",			"",		0x0000477c, 0xffffffff,	WR_s|RD_C0,		0,		I1,		0,	0 },
+{"di",			"",		0x0000477c, 0xffffffff,	RD_C0,			0,		I1,		0,	0 },
 {"di",			"s",		0x0000477c, 0xffe0ffff,	WR_s|RD_C0,		0,		I1,		0,	0 },
 {"dins",		"t,r,I,+I",	0,    (int) M_DINS,	INSN_MACRO,		0,		I3,		0,	0 },
 {"dins",		"t,r,+A,+B",	0x5800000c, 0xfc00003f, WR_t|RD_s,		0,		I3,		0,	0 },
@@ -590,14 +590,14 @@ const struct mips_opcode micromips_opcodes[] =
    a source and a destination).  To get the div machine instruction,
    you must use an explicit destination of $0.  */
 {"div",			"z,s,t",	0x0000ab3c, 0xfc00ffff,	RD_s|RD_t|WR_HILO,	0,		I1,		0,	0 },
-{"div",			"z,t",		0x0000ab3c, 0xfc1fffff,	RD_s|RD_t|WR_HILO,	0,		I1,		0,	0 },
+{"div",			"z,t",		0x0000ab3c, 0xfc1fffff,	RD_t|WR_HILO,		0,		I1,		0,	0 },
 {"div",			"d,v,t",	0,    (int) M_DIV_3,	INSN_MACRO,		0,		I1,		0,	0 },
 {"div",			"d,v,I",	0,    (int) M_DIV_3I,	INSN_MACRO,		0,		I1,		0,	0 },
 {"div.d",		"D,V,T",	0x540001f0, 0xfc0007ff,	WR_D|RD_S|RD_T|FP_D,	0,		I1,		0,	0 },
 {"div.s",		"D,V,T",	0x540000f0, 0xfc0007ff,	WR_D|RD_S|RD_T|FP_S,	0,		I1,		0,	0 },
 /* For divu, see the comments about div.  */
 {"divu",		"z,s,t",	0x0000bb3c, 0xfc00ffff,	RD_s|RD_t|WR_HILO,	0,		I1,		0,	0 },
-{"divu",		"z,t",		0x0000bb3c, 0xfc1fffff,	RD_s|RD_t|WR_HILO,	0,		I1,		0,	0 },
+{"divu",		"z,t",		0x0000bb3c, 0xfc1fffff,	RD_t|WR_HILO,		0,		I1,		0,	0 },
 {"divu",		"d,v,t",	0,    (int) M_DIVU_3,	INSN_MACRO,		0,		I1,		0,	0 },
 {"divu",		"d,v,I",	0,    (int) M_DIVU_3I,	INSN_MACRO,		0,		I1,		0,	0 },
 {"dla",			"t,A(b)",	0,    (int) M_DLA_AB,	INSN_MACRO,		0,		I3,		0,	0 },
@@ -671,7 +671,7 @@ const struct mips_opcode micromips_opcodes[] =
 {"dsub",		"d,v,I",	0,    (int) M_DSUB_I,	INSN_MACRO,		0,		I3,		0,	0 },
 {"dsubu",		"d,v,t",	0x580001d0, 0xfc0007ff,	WR_d|RD_s|RD_t,		0,		I3,		0,	0 },
 {"dsubu",		"d,v,I",	0,    (int) M_DSUBU_I,	INSN_MACRO,		0,		I3,		0,	0 },
-{"ei",			"",		0x0000577c, 0xffffffff,	WR_s|WR_C0,		0,		I1,		0,	0 },
+{"ei",			"",		0x0000577c, 0xffffffff,	WR_C0,			0,		I1,		0,	0 },
 {"ei",			"s",		0x0000577c, 0xffe0ffff,	WR_s|WR_C0,		0,		I1,		0,	0 },
 {"eret",		"",		0x0000f37c, 0xffffffff,	NODS,			0,		I1,		0,	0 },
 {"ext",			"t,r,+A,+C",	0x0000002c, 0xfc00003f, WR_t|RD_s,		0,		I1,		0,	0 },
@@ -897,7 +897,7 @@ const struct mips_opcode micromips_opcodes[] =
 {"nmsub.ps",		"D,R,S,T",	0x54000032, 0xfc00003f,	RD_R|RD_S|RD_T|WR_D|FP_D, 0,		I1,		0,	0 },
 /* nop is at the start of the table.  */
 {"not",			"mf,mg",	    0x4400,     0xffc0,	0,			WR_mf|RD_mg,	I1,		0,	0 }, /* put not before nor */
-{"not",			"d,v",		0x000002d0, 0xffe007ff,	WR_d|RD_s|RD_t,		0,		I1,		0,	0 }, /* nor d,s,0 */
+{"not",			"d,v",		0x000002d0, 0xffe007ff,	WR_d|RD_s,		0,		I1,		0,	0 }, /* nor d,s,0 */
 {"nor",			"mf,mz,mg",	    0x4400,     0xffc0,	0,			WR_mf|RD_mg,	I1,		0,	0 }, /* not */
 {"nor",			"mf,mg,mz",	    0x4400,     0xffc0,	0,			WR_mf|RD_mg,	I1,		0,	0 }, /* not */
 {"nor",			"d,v,t",	0x000002d0, 0xfc0007ff,	WR_d|RD_s|RD_t,		0,		I1,		0,	0 },
diff --git a/opcodes/mips-opc.c b/opcodes/mips-opc.c
index ba817f51832..7e43ac75924 100644
--- a/opcodes/mips-opc.c
+++ b/opcodes/mips-opc.c
@@ -788,7 +788,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"ddivu",		"d,v,t",	0,    (int) M_DDIVU_3,	INSN_MACRO,		0,		I3,		0,	M32 },
 {"ddivu",		"d,v,I",	0,    (int) M_DDIVU_3I,	INSN_MACRO,		0,		I3,		0,	M32 },
 {"di",			"",		0x42000039, 0xffffffff,	WR_C0,			0,		EE,		0,	0 },
-{"di",			"",		0x41606000, 0xffffffff,	WR_t|WR_C0,		0,		I33,		0,	0 },
+{"di",			"",		0x41606000, 0xffffffff,	WR_C0,			0,		I33,		0,	0 },
 {"di",			"t",		0x41606000, 0xffe0ffff,	WR_t|WR_C0,		0,		I33,		0,	0 },
 {"dins",		"t,r,I,+I",	0,    (int) M_DINS,	INSN_MACRO,		0,		I65,		0,	0 },
 {"dins",		"t,r,+A,+B",	0x7c000007, 0xfc00003f, WR_t|RD_s,    		0,		I65,		0,	0 },
@@ -799,21 +799,21 @@ const struct mips_opcode mips_builtin_opcodes[] =
    a source and a destination).  To get the div machine instruction,
    you must use an explicit destination of $0.  */
 {"div",			"z,s,t",	0x0000001a, 0xfc00ffff, RD_s|RD_t|WR_HILO,      0,		I1,		0,	0 },
-{"div",			"z,t",		0x0000001a, 0xffe0ffff, RD_s|RD_t|WR_HILO,      0,		I1,		0,	0 },
+{"div",			"z,t",		0x0000001a, 0xffe0ffff, RD_t|WR_HILO,		0,		I1,		0,	0 },
 {"div",			"d,v,t",	0,    (int) M_DIV_3,	INSN_MACRO,		0,		I1,		0,	0 },
 {"div",			"d,v,I",	0,    (int) M_DIV_3I,	INSN_MACRO,		0,		I1,		0,	0 },
 {"div1",		"z,s,t",	0x7000001a, 0xfc00ffff, RD_s|RD_t|WR_HILO,      0,		EE,		0,	0 },
-{"div1",		"z,t",		0x7000001a, 0xffe0ffff, RD_s|RD_t|WR_HILO,      0,		EE,		0,	0 },
+{"div1",		"z,t",		0x7000001a, 0xffe0ffff, RD_t|WR_HILO,		0,		EE,		0,	0 },
 {"div.d",		"D,V,T",	0x46200003, 0xffe0003f,	WR_D|RD_S|RD_T|FP_D,	0,		I1,		0,	SF },
 {"div.s",		"D,V,T",	0x46000003, 0xffe0003f,	WR_D|RD_S|RD_T|FP_S,	0,		I1,		0,	0 },
 {"div.ps",		"D,V,T",	0x46c00003, 0xffe0003f,	WR_D|RD_S|RD_T|FP_D,	0,		SB1,		0,	0 },
 /* For divu, see the comments about div.  */
 {"divu",		"z,s,t",	0x0000001b, 0xfc00ffff, RD_s|RD_t|WR_HILO,      0,		I1,		0,	0 },
-{"divu",		"z,t",		0x0000001b, 0xffe0ffff, RD_s|RD_t|WR_HILO,      0,		I1,		0,	0 },
+{"divu",		"z,t",		0x0000001b, 0xffe0ffff, RD_t|WR_HILO,		0,		I1,		0,	0 },
 {"divu",		"d,v,t",	0,    (int) M_DIVU_3,	INSN_MACRO,		0,		I1,		0,	0 },
 {"divu",		"d,v,I",	0,    (int) M_DIVU_3I,	INSN_MACRO,		0,		I1,		0,	0 },
 {"divu1",		"z,s,t",	0x7000001b, 0xfc00ffff, RD_s|RD_t|WR_HILO,      0,		EE,		0,	0 },
-{"divu1",		"z,t",		0x7000001b, 0xffe0ffff, RD_s|RD_t|WR_HILO,      0,		EE,		0,	0 },
+{"divu1",		"z,t",		0x7000001b, 0xffe0ffff, RD_t|WR_HILO,		0,		EE,		0,	0 },
 {"dla",			"t,A(b)",	0,    (int) M_DLA_AB,	INSN_MACRO,		0,		I3,		0,	0 },
 {"dlca",		"t,A(b)",	0,    (int) M_DLCA_AB,	INSN_MACRO,		0,		I3,		0,	0 },
 {"dli",			"t,j",		0x24000000, 0xffe00000, WR_t,			0,		I3,		0,	0 }, /* addiu */
@@ -910,7 +910,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"dvpe",		"",		0x41600001, 0xffffffff, TRAP,			0,		0,		MT32,	0 },
 {"dvpe",		"t",		0x41600001, 0xffe0ffff, TRAP|WR_t,		0,		0,		MT32,	0 },
 {"ei",			"",		0x42000038, 0xffffffff,	WR_C0,			0,		EE,		0,	0 },
-{"ei",			"",		0x41606020, 0xffffffff,	WR_t|WR_C0,		0,		I33,		0,	0 },
+{"ei",			"",		0x41606020, 0xffffffff,	WR_C0,			0,		I33,		0,	0 },
 {"ei",			"t",		0x41606020, 0xffe0ffff,	WR_t|WR_C0,		0,		I33,		0,	0 },
 {"emt",			"",		0x41600be1, 0xffffffff, TRAP,			0,		0,		MT32,	0 },
 {"emt",			"t",		0x41600be1, 0xffe0ffff, TRAP|WR_t,		0,		0,		MT32,	0 },
@@ -963,10 +963,10 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"laad",		"d,(b),t",	0x700004df, 0xfc0007ff, LDD|SM|WR_d|RD_t|RD_b,	0,		IOCT2,		0,	0 },
 {"lac",			"d,(b)",	0x7000039f, 0xfc1f07ff, LDD|SM|WR_d|RD_b,	0,		IOCT2,		0,	0 },
 {"lacd",		"d,(b)",	0x700003df, 0xfc1f07ff, LDD|SM|WR_d|RD_b,	0,		IOCT2,		0,	0 },
-{"lad",			"d,(b)",	0x7000019f, 0xfc1f07ff, LDD|SM|WR_d|RD_t|RD_b,	0,		IOCT2,		0,	0 },
-{"ladd",		"d,(b)",	0x700001df, 0xfc1f07ff, LDD|SM|WR_d|RD_t|RD_b,	0,		IOCT2,		0,	0 },
-{"lai",			"d,(b)",	0x7000009f, 0xfc1f07ff, LDD|SM|WR_d|RD_t|RD_b,	0,		IOCT2,		0,	0 },
-{"laid",		"d,(b)",	0x700000df, 0xfc1f07ff, LDD|SM|WR_d|RD_t|RD_b,	0,		IOCT2,		0,	0 },
+{"lad",			"d,(b)",	0x7000019f, 0xfc1f07ff, LDD|SM|WR_d|RD_b,	0,		IOCT2,		0,	0 },
+{"ladd",		"d,(b)",	0x700001df, 0xfc1f07ff, LDD|SM|WR_d|RD_b,	0,		IOCT2,		0,	0 },
+{"lai",			"d,(b)",	0x7000009f, 0xfc1f07ff, LDD|SM|WR_d|RD_b,	0,		IOCT2,		0,	0 },
+{"laid",		"d,(b)",	0x700000df, 0xfc1f07ff, LDD|SM|WR_d|RD_b,	0,		IOCT2,		0,	0 },
 {"las",			"d,(b)",	0x7000029f, 0xfc1f07ff, LDD|SM|WR_d|RD_b,	0,		IOCT2,		0,	0 },
 {"lasd",		"d,(b)",	0x700002df, 0xfc1f07ff, LDD|SM|WR_d|RD_b,	0,		IOCT2,		0,	0 },
 {"law",			"d,(b),t",	0x7000059f, 0xfc0007ff, LDD|SM|WR_d|RD_t|RD_b,	0,		IOCT2,		0,	0 },
@@ -1339,7 +1339,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"nor.ob",		"X,Y,Q",	0x7800000f, 0xfc20003f,	WR_D|RD_S|RD_T|FP_D,	0,		SB1,		MX,	0 },
 {"nor.ob",		"D,S,Q",	0x4800000f, 0xfc20003f,	WR_D|RD_S|RD_T|FP_D,	0,		N54,		0,	0 },
 {"nor.qh",		"X,Y,Q",	0x7820000f, 0xfc20003f,	WR_D|RD_S|RD_T|FP_D,	0,		0,		MX,	0 },
-{"not",			"d,v",		0x00000027, 0xfc1f07ff,	WR_d|RD_s|RD_t,		0,		I1,		0,	0 },/*nor d,s,0*/
+{"not",			"d,v",		0x00000027, 0xfc1f07ff,	WR_d|RD_s,		0,		I1,		0,	0 },/*nor d,s,0*/
 {"or",			"d,v,t",	0x00000025, 0xfc0007ff,	WR_d|RD_s|RD_t,		0,		I1,		0,	0 },
 {"or",			"t,r,I",	0,    (int) M_OR_I,	INSN_MACRO,		0,		I1,		0,	0 },
 {"or",			"D,S,T",	0x45a00000, 0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,		IL2E,		0,	0 },