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| author | H.J. Lu <hjl.tools@gmail.com> | 2013-03-02 01:57:47 +0000 |
|---|---|---|
| committer | H.J. Lu <hjl.tools@gmail.com> | 2013-03-02 01:57:47 +0000 |
| commit | 9d9879fa54fedf41b1b8c0ad2722351c3016aa40 (patch) | |
| tree | 4062761205fa610923fda44d006fb837842fced9 /opcodes | |
| parent | 6418d069fab3da999d5acd2cc9642af3e9a8781e (diff) | |
| download | gdb-9d9879fa54fedf41b1b8c0ad2722351c3016aa40.tar.gz | |
Add RegRex64 to riz
* i386-reg.tbl (riz): Add RegRex64.
* i386-tbl.h: Regenerated.
Diffstat (limited to 'opcodes')
| -rw-r--r-- | opcodes/ChangeLog | 5 | ||||
| -rw-r--r-- | opcodes/i386-reg.tbl | 2 | ||||
| -rw-r--r-- | opcodes/i386-tbl.h | 8 |
3 files changed, 10 insertions, 5 deletions
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 374bf400817..8ec6e82f6fb 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,8 @@ +2013-03-01 H.J. Lu <hongjiu.lu@intel.com> + + * i386-reg.tbl (riz): Add RegRex64. + * i386-tbl.h: Regenerated. + 2013-02-28 Yufeng Zhang <yufeng.zhang@arm.com> * aarch64-tbl.h (QL_I3SAMEW, QL_I3WWX): New macros. diff --git a/opcodes/i386-reg.tbl b/opcodes/i386-reg.tbl index 8c5b5d1faf5..8eed65b4f1a 100644 --- a/opcodes/i386-reg.tbl +++ b/opcodes/i386-reg.tbl @@ -211,8 +211,8 @@ rip, BaseIndex, RegRex64, RegRip, Dw2Inval, 16 eip, BaseIndex, RegRex64, RegEip, 8, Dw2Inval // No type will make these registers rejected for all purposes except // for addressing. +riz, BaseIndex, RegRex64, RegRiz, Dw2Inval, Dw2Inval eiz, BaseIndex, 0, RegEiz, Dw2Inval, Dw2Inval -riz, BaseIndex, 0, RegRiz, Dw2Inval, Dw2Inval // fp regs. st(0), FloatReg|FloatAcc, 0, 0, 11, 33 st(1), FloatReg, 0, 1, 12, 34 diff --git a/opcodes/i386-tbl.h b/opcodes/i386-tbl.h index cab6b07d6a5..f9a38829047 100644 --- a/opcodes/i386-tbl.h +++ b/opcodes/i386-tbl.h @@ -40246,16 +40246,16 @@ const reg_entry i386_regtab[] = 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, RegRex64, RegEip, { 8, Dw2Inval } }, - { "eiz", + { "riz", { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, - 0, RegEiz, { Dw2Inval, Dw2Inval } }, - { "riz", + RegRex64, RegRiz, { Dw2Inval, Dw2Inval } }, + { "eiz", { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, - 0, RegRiz, { Dw2Inval, Dw2Inval } }, + 0, RegEiz, { Dw2Inval, Dw2Inval } }, { "st(0)", { { 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |