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authorNick Clifton <nickc@redhat.com>2000-11-30 01:55:12 +0000
committerNick Clifton <nickc@redhat.com>2000-11-30 01:55:12 +0000
commit99901033941c5df3b5a97ef76d1a35bbc3e5313c (patch)
treead56d39c6970c9e6b6dc1e9799816d69a0fba63b /sim/arm/armos.c
parent9d105ab744f1aa43e84b88f820ac2047d4bd55b2 (diff)
downloadgdb-99901033941c5df3b5a97ef76d1a35bbc3e5313c.tar.gz
Add support for ARM's v5TE architecture and Intel's XScale extenstions
Diffstat (limited to 'sim/arm/armos.c')
-rw-r--r--sim/arm/armos.c67
1 files changed, 49 insertions, 18 deletions
diff --git a/sim/arm/armos.c b/sim/arm/armos.c
index 958d4cde6ff..62b3ff5694b 100644
--- a/sim/arm/armos.c
+++ b/sim/arm/armos.c
@@ -70,6 +70,8 @@ extern int _fisatty (FILE *);
#include "armdefs.h"
#include "armos.h"
+#include "armemu.h"
+
#ifndef NOOS
#ifndef VALIDATE
/* #ifndef ASIM */
@@ -445,11 +447,6 @@ ARMul_OSHandleSWI (ARMul_State * state, ARMword number)
state->Reg[0] = OSptr->ErrorNo;
return (TRUE);
- case SWI_Breakpoint:
- state->EndCondition = RDIError_BreakpointReached;
- state->Emulate = FALSE;
- return (TRUE);
-
case SWI_GetEnv:
state->Reg[0] = ADDRCMDLINE;
if (state->MemSize)
@@ -459,6 +456,11 @@ ARMul_OSHandleSWI (ARMul_State * state, ARMword number)
WriteCommandLineTo (state, state->Reg[0]);
return (TRUE);
+
+ case SWI_Breakpoint:
+ state->EndCondition = RDIError_BreakpointReached;
+ state->Emulate = FALSE;
+ return (TRUE);
/* Handle Angel SWIs as well as Demon ones */
case AngelSWI_ARM:
@@ -587,29 +589,58 @@ ARMul_OSHandleSWI (ARMul_State * state, ARMword number)
return TRUE;
}
+ case 0x90:
+ case 0x92:
+ /* These are used by the FPE code. */
+ return TRUE;
+
default:
- state->Emulate = FALSE;
- return (FALSE);
+ {
+ /* If there is a SWI vector installed use it. */
+ extern int SWI_vector_installed;
+
+ if (SWI_vector_installed && number != SWI_Breakpoint)
+ {
+ ARMword cpsr;
+ ARMword i_size;
+
+ cpsr = ARMul_GetCPSR (state);
+ i_size = INSN_SIZE;
+
+ ARMul_SetSPSR (state, SVC32MODE, cpsr);
+
+ cpsr &= ~0xbf;
+ cpsr |= SVC32MODE | 0x80;
+ ARMul_SetCPSR (state, cpsr);
+
+ state->RegBank[SVCBANK][14] = state->Reg[14] = state->Reg[15] - i_size;
+ state->NextInstr = RESUME;
+ state->Reg[15] = state->pc = ARMSWIV;
+ FLUSHPIPE;
+ }
+ else
+ fprintf (stderr, "unknown SWI encountered - %x - ignoring\n", number);
+ return TRUE;
+ }
}
}
#ifndef NOOS
#ifndef ASIM
-/***************************************************************************\
-* The emulator calls this routine when an Exception occurs. The second *
-* parameter is the address of the relevant exception vector. Returning *
-* FALSE from this routine causes the trap to be taken, TRUE causes it to *
-* be ignored (so set state->Emulate to FALSE!). *
-\***************************************************************************/
+/* The emulator calls this routine when an Exception occurs. The second
+ parameter is the address of the relevant exception vector. Returning
+ FALSE from this routine causes the trap to be taken, TRUE causes it to
+ be ignored (so set state->Emulate to FALSE!). */
unsigned
-ARMul_OSException (ARMul_State * state ATTRIBUTE_UNUSED, ARMword vector ATTRIBUTE_UNUSED, ARMword pc ATTRIBUTE_UNUSED)
-{ /* don't use this here */
- return (FALSE);
+ARMul_OSException (
+ ARMul_State * state ATTRIBUTE_UNUSED,
+ ARMword vector ATTRIBUTE_UNUSED,
+ ARMword pc ATTRIBUTE_UNUSED)
+{
+ return FALSE;
}
#endif
-
-
#endif /* NOOS */