import gdb-1999-08-09 snapshot

8 files changed, 1483 insertions, 1735 deletions

diff --git a/sim/m32r/ChangeLog b/sim/m32r/ChangeLog
index 2202b86189c..1f7f3d43e7d 100644
--- a/sim/m32r/ChangeLog
+++ b/sim/m32r/ChangeLog
@@ -1,3 +1,12 @@
+1999-08-09  Doug Evans  <devans@casey.cygnus.com>
+
+	* cpu.h,decode.c,decode.h,model.c,sem-switch.c,sem.c: Rebuild.
+
+1999-08-04  Doug Evans  <devans@casey.cygnus.com>
+
+	* m32r-sim.h (SEM_SKIP_INSN): Delete.
+	* cpu.h,cpuall.h,decode.c,model.c,sem-switch.c,sem.c: Rebuild.
+
 1999-05-08  Felix Lee  <flee@cygnus.com>
 
 	* configure: Regenerated to track ../common/aclocal.m4 changes.
diff --git a/sim/m32r/cpu.h b/sim/m32r/cpu.h
index 6ebe19999d3..fa475d57503 100644
--- a/sim/m32r/cpu.h
+++ b/sim/m32r/cpu.h
@@ -117,317 +117,109 @@ typedef struct {
   int empty;
 } MODEL_TEST_DATA;
 
+/* Instruction argument buffer.  */
+
 union sem_fields {
-    struct { /* empty sformat for unspecified field list */
-      int empty;
-    } fmt_empty;
-    struct { /* e.g. add $dr,$sr */
-      SI * i_dr;
-      SI * i_sr;
-      unsigned char in_dr;
-      unsigned char in_sr;
-      unsigned char out_dr;
-    } fmt_add;
-    struct { /* e.g. add3 $dr,$sr,$hash$slo16 */
-      INT f_simm16;
-      SI * i_sr;
-      SI * i_dr;
-      unsigned char in_sr;
-      unsigned char out_dr;
-    } fmt_add3;
-    struct { /* e.g. and3 $dr,$sr,$uimm16 */
-      UINT f_uimm16;
-      SI * i_sr;
-      SI * i_dr;
-      unsigned char in_sr;
-      unsigned char out_dr;
-    } fmt_and3;
-    struct { /* e.g. or3 $dr,$sr,$hash$ulo16 */
-      UINT f_uimm16;
-      SI * i_sr;
-      SI * i_dr;
-      unsigned char in_sr;
-      unsigned char out_dr;
-    } fmt_or3;
-    struct { /* e.g. addi $dr,$simm8 */
-      INT f_simm8;
-      SI * i_dr;
-      unsigned char in_dr;
-      unsigned char out_dr;
-    } fmt_addi;
-    struct { /* e.g. addv $dr,$sr */
-      SI * i_dr;
-      SI * i_sr;
-      unsigned char in_dr;
-      unsigned char in_sr;
-      unsigned char out_dr;
-    } fmt_addv;
-    struct { /* e.g. addv3 $dr,$sr,$simm16 */
-      INT f_simm16;
-      SI * i_sr;
-      SI * i_dr;
-      unsigned char in_sr;
-      unsigned char out_dr;
-    } fmt_addv3;
-    struct { /* e.g. addx $dr,$sr */
-      SI * i_dr;
-      SI * i_sr;
-      unsigned char in_dr;
-      unsigned char in_sr;
-      unsigned char out_dr;
-    } fmt_addx;
-    struct { /* e.g. cmp $src1,$src2 */
-      SI * i_src1;
-      SI * i_src2;
-      unsigned char in_src1;
-      unsigned char in_src2;
-    } fmt_cmp;
-    struct { /* e.g. cmpi $src2,$simm16 */
-      INT f_simm16;
-      SI * i_src2;
-      unsigned char in_src2;
-    } fmt_cmpi;
-    struct { /* e.g. div $dr,$sr */
-      SI * i_dr;
-      SI * i_sr;
-      unsigned char in_dr;
-      unsigned char in_sr;
-      unsigned char out_dr;
-    } fmt_div;
-    struct { /* e.g. ld $dr,@$sr */
-      SI * i_sr;
-      SI * i_dr;
-      unsigned char in_sr;
-      unsigned char out_dr;
-    } fmt_ld;
-    struct { /* e.g. ld $dr,@($slo16,$sr) */
-      INT f_simm16;
-      SI * i_sr;
-      SI * i_dr;
-      unsigned char in_sr;
-      unsigned char out_dr;
-    } fmt_ld_d;
-    struct { /* e.g. ldb $dr,@$sr */
-      SI * i_sr;
-      SI * i_dr;
-      unsigned char in_sr;
-      unsigned char out_dr;
-    } fmt_ldb;
-    struct { /* e.g. ldb $dr,@($slo16,$sr) */
-      INT f_simm16;
-      SI * i_sr;
-      SI * i_dr;
-      unsigned char in_sr;
-      unsigned char out_dr;
-    } fmt_ldb_d;
-    struct { /* e.g. ldh $dr,@$sr */
-      SI * i_sr;
-      SI * i_dr;
-      unsigned char in_sr;
-      unsigned char out_dr;
-    } fmt_ldh;
-    struct { /* e.g. ldh $dr,@($slo16,$sr) */
-      INT f_simm16;
-      SI * i_sr;
-      SI * i_dr;
-      unsigned char in_sr;
-      unsigned char out_dr;
-    } fmt_ldh_d;
-    struct { /* e.g. ld $dr,@$sr+ */
-      SI * i_sr;
-      SI * i_dr;
-      unsigned char in_sr;
-      unsigned char out_dr;
-      unsigned char out_sr;
-    } fmt_ld_plus;
-    struct { /* e.g. ld24 $dr,$uimm24 */
-      ADDR i_uimm24;
-      SI * i_dr;
-      unsigned char out_dr;
-    } fmt_ld24;
-    struct { /* e.g. ldi8 $dr,$simm8 */
-      INT f_simm8;
-      SI * i_dr;
-      unsigned char out_dr;
-    } fmt_ldi8;
-    struct { /* e.g. ldi16 $dr,$hash$slo16 */
-      INT f_simm16;
-      SI * i_dr;
-      unsigned char out_dr;
-    } fmt_ldi16;
-    struct { /* e.g. lock $dr,@$sr */
-      SI * i_sr;
-      SI * i_dr;
-      unsigned char in_sr;
-      unsigned char out_dr;
-    } fmt_lock;
-    struct { /* e.g. machi $src1,$src2 */
-      SI * i_src1;
-      SI * i_src2;
-      unsigned char in_src1;
-      unsigned char in_src2;
-    } fmt_machi;
-    struct { /* e.g. mulhi $src1,$src2 */
-      SI * i_src1;
-      SI * i_src2;
-      unsigned char in_src1;
-      unsigned char in_src2;
-    } fmt_mulhi;
-    struct { /* e.g. mv $dr,$sr */
-      SI * i_sr;
-      SI * i_dr;
-      unsigned char in_sr;
-      unsigned char out_dr;
-    } fmt_mv;
-    struct { /* e.g. mvfachi $dr */
-      SI * i_dr;
-      unsigned char out_dr;
-    } fmt_mvfachi;
-    struct { /* e.g. mvfc $dr,$scr */
-      UINT f_r2;
-      SI * i_dr;
-      unsigned char out_dr;
-    } fmt_mvfc;
-    struct { /* e.g. mvtachi $src1 */
-      SI * i_src1;
-      unsigned char in_src1;
-    } fmt_mvtachi;
-    struct { /* e.g. mvtc $sr,$dcr */
-      UINT f_r1;
-      SI * i_sr;
-      unsigned char in_sr;
-    } fmt_mvtc;
-    struct { /* e.g. nop */
-      int empty;
-    } fmt_nop;
-    struct { /* e.g. rac */
-      int empty;
-    } fmt_rac;
-    struct { /* e.g. seth $dr,$hash$hi16 */
-      UINT f_hi16;
-      SI * i_dr;
-      unsigned char out_dr;
-    } fmt_seth;
-    struct { /* e.g. sll3 $dr,$sr,$simm16 */
-      INT f_simm16;
-      SI * i_sr;
-      SI * i_dr;
-      unsigned char in_sr;
-      unsigned char out_dr;
-    } fmt_sll3;
-    struct { /* e.g. slli $dr,$uimm5 */
-      UINT f_uimm5;
-      SI * i_dr;
-      unsigned char in_dr;
-      unsigned char out_dr;
-    } fmt_slli;
-    struct { /* e.g. st $src1,@$src2 */
-      SI * i_src1;
-      SI * i_src2;
-      unsigned char in_src1;
-      unsigned char in_src2;
-    } fmt_st;
-    struct { /* e.g. st $src1,@($slo16,$src2) */
-      INT f_simm16;
-      SI * i_src1;
-      SI * i_src2;
-      unsigned char in_src1;
-      unsigned char in_src2;
-    } fmt_st_d;
-    struct { /* e.g. stb $src1,@$src2 */
-      SI * i_src1;
-      SI * i_src2;
-      unsigned char in_src1;
-      unsigned char in_src2;
-    } fmt_stb;
-    struct { /* e.g. stb $src1,@($slo16,$src2) */
-      INT f_simm16;
-      SI * i_src1;
-      SI * i_src2;
-      unsigned char in_src1;
-      unsigned char in_src2;
-    } fmt_stb_d;
-    struct { /* e.g. sth $src1,@$src2 */
-      SI * i_src1;
-      SI * i_src2;
-      unsigned char in_src1;
-      unsigned char in_src2;
-    } fmt_sth;
-    struct { /* e.g. sth $src1,@($slo16,$src2) */
-      INT f_simm16;
-      SI * i_src1;
-      SI * i_src2;
-      unsigned char in_src1;
-      unsigned char in_src2;
-    } fmt_sth_d;
-    struct { /* e.g. st $src1,@+$src2 */
-      SI * i_src1;
-      SI * i_src2;
-      unsigned char in_src1;
-      unsigned char in_src2;
-      unsigned char out_src2;
-    } fmt_st_plus;
-    struct { /* e.g. unlock $src1,@$src2 */
-      SI * i_src1;
-      SI * i_src2;
-      unsigned char in_src1;
-      unsigned char in_src2;
-    } fmt_unlock;
-  /* cti insns, kept separately so addr_cache is in fixed place */
-  struct {
-    union {
-    struct { /* e.g. bc.s $disp8 */
-      IADDR i_disp8;
-    } fmt_bc8;
-    struct { /* e.g. bc.l $disp24 */
-      IADDR i_disp24;
-    } fmt_bc24;
-    struct { /* e.g. beq $src1,$src2,$disp16 */
-      IADDR i_disp16;
-      SI * i_src1;
-      SI * i_src2;
-      unsigned char in_src1;
-      unsigned char in_src2;
-    } fmt_beq;
-    struct { /* e.g. beqz $src2,$disp16 */
-      IADDR i_disp16;
-      SI * i_src2;
-      unsigned char in_src2;
-    } fmt_beqz;
-    struct { /* e.g. bl.s $disp8 */
-      IADDR i_disp8;
-      unsigned char out_h_gr_14;
-    } fmt_bl8;
-    struct { /* e.g. bl.l $disp24 */
-      IADDR i_disp24;
-      unsigned char out_h_gr_14;
-    } fmt_bl24;
-    struct { /* e.g. bra.s $disp8 */
-      IADDR i_disp8;
-    } fmt_bra8;
-    struct { /* e.g. bra.l $disp24 */
-      IADDR i_disp24;
-    } fmt_bra24;
-    struct { /* e.g. jl $sr */
-      SI * i_sr;
-      unsigned char in_sr;
-      unsigned char out_h_gr_14;
-    } fmt_jl;
-    struct { /* e.g. jmp $sr */
-      SI * i_sr;
-      unsigned char in_sr;
-    } fmt_jmp;
-    struct { /* e.g. rte */
-      int empty;
-    } fmt_rte;
-    struct { /* e.g. trap $uimm4 */
-      UINT f_uimm4;
-    } fmt_trap;
-    } fields;
-#if WITH_SCACHE_PBB
-    SEM_PC addr_cache;
-#endif
-  } cti;
+  struct { /* no operands */
+    int empty;
+  } fmt_empty;
+  struct { /*  */
+    UINT f_uimm4;
+  } sfmt_trap;
+  struct { /*  */
+    IADDR i_disp24;
+    unsigned char out_h_gr_14;
+  } sfmt_bl24;
+  struct { /*  */
+    IADDR i_disp8;
+    unsigned char out_h_gr_14;
+  } sfmt_bl8;
+  struct { /*  */
+    SI* i_dr;
+    UINT f_hi16;
+    unsigned char out_dr;
+  } sfmt_seth;
+  struct { /*  */
+    SI* i_sr;
+    UINT f_r1;
+    unsigned char in_sr;
+  } sfmt_mvtc;
+  struct { /*  */
+    SI* i_dr;
+    UINT f_r2;
+    unsigned char out_dr;
+  } sfmt_mvfc;
+  struct { /*  */
+    ADDR i_uimm24;
+    SI* i_dr;
+    unsigned char out_dr;
+  } sfmt_ld24;
+  struct { /*  */
+    SI* i_sr;
+    unsigned char in_sr;
+    unsigned char out_h_gr_14;
+  } sfmt_jl;
+  struct { /*  */
+    SI* i_dr;
+    UINT f_uimm5;
+    unsigned char in_dr;
+    unsigned char out_dr;
+  } sfmt_slli;
+  struct { /*  */
+    SI* i_dr;
+    INT f_simm8;
+    unsigned char in_dr;
+    unsigned char out_dr;
+  } sfmt_addi;
+  struct { /*  */
+    SI* i_src1;
+    SI* i_src2;
+    unsigned char in_src1;
+    unsigned char in_src2;
+    unsigned char out_src2;
+  } sfmt_st_plus;
+  struct { /*  */
+    SI* i_src1;
+    SI* i_src2;
+    INT f_simm16;
+    unsigned char in_src1;
+    unsigned char in_src2;
+  } sfmt_st_d;
+  struct { /*  */
+    SI* i_dr;
+    SI* i_sr;
+    unsigned char in_sr;
+    unsigned char out_dr;
+    unsigned char out_sr;
+  } sfmt_ld_plus;
+  struct { /*  */
+    IADDR i_disp16;
+    SI* i_src1;
+    SI* i_src2;
+    unsigned char in_src1;
+    unsigned char in_src2;
+  } sfmt_beq;
+  struct { /*  */
+    SI* i_dr;
+    SI* i_sr;
+    UINT f_uimm16;
+    unsigned char in_sr;
+    unsigned char out_dr;
+  } sfmt_and3;
+  struct { /*  */
+    SI* i_dr;
+    SI* i_sr;
+    INT f_simm16;
+    unsigned char in_sr;
+    unsigned char out_dr;
+  } sfmt_add3;
+  struct { /*  */
+    SI* i_dr;
+    SI* i_sr;
+    unsigned char in_dr;
+    unsigned char in_sr;
+    unsigned char out_dr;
+  } sfmt_add;
 #if WITH_SCACHE_PBB
   /* Writeback handler.  */
   struct {
@@ -449,6 +241,7 @@ union sem_fields {
     int insn_count;
     /* Next pbb to execute.  */
     SCACHE *next;
+    SCACHE *branch_target;
   } chain;
 #endif
 };
@@ -460,6 +253,9 @@ struct argbuf {
   const IDESC *idesc;
   char trace_p;
   char profile_p;
+  /* ??? Temporary hack for skip insns.  */
+  char skip_count;
+  char unused;
   /* cpu specific data follows */
   union sem semantic;
   int written;
@@ -480,13 +276,11 @@ struct scache {
    These define and assign the local vars that contain the insn's fields.  */
 
 #define EXTRACT_IFMT_EMPTY_VARS \
-  /* Instruction fields.  */ \
   unsigned int length;
 #define EXTRACT_IFMT_EMPTY_CODE \
   length = 0; \
 
 #define EXTRACT_IFMT_ADD_VARS \
-  /* Instruction fields.  */ \
   UINT f_op1; \
   UINT f_r1; \
   UINT f_op2; \
@@ -494,13 +288,12 @@ struct scache {
   unsigned int length;
 #define EXTRACT_IFMT_ADD_CODE \
   length = 2; \
-  f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
-  f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
-  f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
-  f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
+  f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
+  f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
+  f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
+  f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
 
 #define EXTRACT_IFMT_ADD3_VARS \
-  /* Instruction fields.  */ \
   UINT f_op1; \
   UINT f_r1; \
   UINT f_op2; \
@@ -509,14 +302,13 @@ struct scache {
   unsigned int length;
 #define EXTRACT_IFMT_ADD3_CODE \
   length = 4; \
-  f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
-  f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
-  f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
-  f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
-  f_simm16 = EXTRACT_INT (insn, 32, 16, 16); \
+  f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
+  f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
+  f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
+  f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
+  f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16); \
 
 #define EXTRACT_IFMT_AND3_VARS \
-  /* Instruction fields.  */ \
   UINT f_op1; \
   UINT f_r1; \
   UINT f_op2; \
@@ -525,14 +317,13 @@ struct scache {
   unsigned int length;
 #define EXTRACT_IFMT_AND3_CODE \
   length = 4; \
-  f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
-  f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
-  f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
-  f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
-  f_uimm16 = EXTRACT_UINT (insn, 32, 16, 16); \
+  f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
+  f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
+  f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
+  f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
+  f_uimm16 = EXTRACT_MSB0_UINT (insn, 32, 16, 16); \
 
 #define EXTRACT_IFMT_OR3_VARS \
-  /* Instruction fields.  */ \
   UINT f_op1; \
   UINT f_r1; \
   UINT f_op2; \
@@ -541,26 +332,24 @@ struct scache {
   unsigned int length;
 #define EXTRACT_IFMT_OR3_CODE \
   length = 4; \
-  f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
-  f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
-  f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
-  f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
-  f_uimm16 = EXTRACT_UINT (insn, 32, 16, 16); \
+  f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
+  f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
+  f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
+  f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
+  f_uimm16 = EXTRACT_MSB0_UINT (insn, 32, 16, 16); \
 
 #define EXTRACT_IFMT_ADDI_VARS \
-  /* Instruction fields.  */ \
   UINT f_op1; \
   UINT f_r1; \
   INT f_simm8; \
   unsigned int length;
 #define EXTRACT_IFMT_ADDI_CODE \
   length = 2; \
-  f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
-  f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
-  f_simm8 = EXTRACT_INT (insn, 16, 8, 8); \
+  f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
+  f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
+  f_simm8 = EXTRACT_MSB0_INT (insn, 16, 8, 8); \
 
 #define EXTRACT_IFMT_ADDV3_VARS \
-  /* Instruction fields.  */ \
   UINT f_op1; \
   UINT f_r1; \
   UINT f_op2; \
@@ -569,38 +358,35 @@ struct scache {
   unsigned int length;
 #define EXTRACT_IFMT_ADDV3_CODE \
   length = 4; \
-  f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
-  f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
-  f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
-  f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
-  f_simm16 = EXTRACT_INT (insn, 32, 16, 16); \
+  f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
+  f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
+  f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
+  f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
+  f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16); \
 
 #define EXTRACT_IFMT_BC8_VARS \
-  /* Instruction fields.  */ \
   UINT f_op1; \
   UINT f_r1; \
   SI f_disp8; \
   unsigned int length;
 #define EXTRACT_IFMT_BC8_CODE \
   length = 2; \
-  f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
-  f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
-  f_disp8 = ((((EXTRACT_INT (insn, 16, 8, 8)) << (2))) + (((pc) & (-4)))); \
+  f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
+  f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
+  f_disp8 = ((((EXTRACT_MSB0_INT (insn, 16, 8, 8)) << (2))) + (((pc) & (-4)))); \
 
 #define EXTRACT_IFMT_BC24_VARS \
-  /* Instruction fields.  */ \
   UINT f_op1; \
   UINT f_r1; \
   SI f_disp24; \
   unsigned int length;
 #define EXTRACT_IFMT_BC24_CODE \
   length = 4; \
-  f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
-  f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
-  f_disp24 = ((((EXTRACT_INT (insn, 32, 8, 24)) << (2))) + (pc)); \
+  f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
+  f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
+  f_disp24 = ((((EXTRACT_MSB0_INT (insn, 32, 8, 24)) << (2))) + (pc)); \
 
 #define EXTRACT_IFMT_BEQ_VARS \
-  /* Instruction fields.  */ \
   UINT f_op1; \
   UINT f_r1; \
   UINT f_op2; \
@@ -609,14 +395,13 @@ struct scache {
   unsigned int length;
 #define EXTRACT_IFMT_BEQ_CODE \
   length = 4; \
-  f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
-  f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
-  f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
-  f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
-  f_disp16 = ((((EXTRACT_INT (insn, 32, 16, 16)) << (2))) + (pc)); \
+  f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
+  f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
+  f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
+  f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
+  f_disp16 = ((((EXTRACT_MSB0_INT (insn, 32, 16, 16)) << (2))) + (pc)); \
 
 #define EXTRACT_IFMT_BEQZ_VARS \
-  /* Instruction fields.  */ \
   UINT f_op1; \
   UINT f_r1; \
   UINT f_op2; \
@@ -625,14 +410,13 @@ struct scache {
   unsigned int length;
 #define EXTRACT_IFMT_BEQZ_CODE \
   length = 4; \
-  f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
-  f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
-  f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
-  f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
-  f_disp16 = ((((EXTRACT_INT (insn, 32, 16, 16)) << (2))) + (pc)); \
+  f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
+  f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
+  f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
+  f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
+  f_disp16 = ((((EXTRACT_MSB0_INT (insn, 32, 16, 16)) << (2))) + (pc)); \
 
 #define EXTRACT_IFMT_CMP_VARS \
-  /* Instruction fields.  */ \
   UINT f_op1; \
   UINT f_r1; \
   UINT f_op2; \
@@ -640,13 +424,12 @@ struct scache {
   unsigned int length;
 #define EXTRACT_IFMT_CMP_CODE \
   length = 2; \
-  f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
-  f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
-  f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
-  f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
+  f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
+  f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
+  f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
+  f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
 
 #define EXTRACT_IFMT_CMPI_VARS \
-  /* Instruction fields.  */ \
   UINT f_op1; \
   UINT f_r1; \
   UINT f_op2; \
@@ -655,14 +438,13 @@ struct scache {
   unsigned int length;
 #define EXTRACT_IFMT_CMPI_CODE \
   length = 4; \
-  f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
-  f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
-  f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
-  f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
-  f_simm16 = EXTRACT_INT (insn, 32, 16, 16); \
+  f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
+  f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
+  f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
+  f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
+  f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16); \
 
 #define EXTRACT_IFMT_DIV_VARS \
-  /* Instruction fields.  */ \
   UINT f_op1; \
   UINT f_r1; \
   UINT f_op2; \
@@ -671,14 +453,13 @@ struct scache {
   unsigned int length;
 #define EXTRACT_IFMT_DIV_CODE \
   length = 4; \
-  f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
-  f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
-  f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
-  f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
-  f_simm16 = EXTRACT_INT (insn, 32, 16, 16); \
+  f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
+  f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
+  f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
+  f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
+  f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16); \
 
 #define EXTRACT_IFMT_JL_VARS \
-  /* Instruction fields.  */ \
   UINT f_op1; \
   UINT f_r1; \
   UINT f_op2; \
@@ -686,25 +467,23 @@ struct scache {
   unsigned int length;
 #define EXTRACT_IFMT_JL_CODE \
   length = 2; \
-  f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
-  f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
-  f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
-  f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
+  f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
+  f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
+  f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
+  f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
 
 #define EXTRACT_IFMT_LD24_VARS \
-  /* Instruction fields.  */ \
   UINT f_op1; \
   UINT f_r1; \
   UINT f_uimm24; \
   unsigned int length;
 #define EXTRACT_IFMT_LD24_CODE \
   length = 4; \
-  f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
-  f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
-  f_uimm24 = EXTRACT_UINT (insn, 32, 8, 24); \
+  f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
+  f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
+  f_uimm24 = EXTRACT_MSB0_UINT (insn, 32, 8, 24); \
 
 #define EXTRACT_IFMT_LDI16_VARS \
-  /* Instruction fields.  */ \
   UINT f_op1; \
   UINT f_r1; \
   UINT f_op2; \
@@ -713,14 +492,13 @@ struct scache {
   unsigned int length;
 #define EXTRACT_IFMT_LDI16_CODE \
   length = 4; \
-  f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
-  f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
-  f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
-  f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
-  f_simm16 = EXTRACT_INT (insn, 32, 16, 16); \
+  f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
+  f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
+  f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
+  f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
+  f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16); \
 
 #define EXTRACT_IFMT_MVFACHI_VARS \
-  /* Instruction fields.  */ \
   UINT f_op1; \
   UINT f_r1; \
   UINT f_op2; \
@@ -728,13 +506,12 @@ struct scache {
   unsigned int length;
 #define EXTRACT_IFMT_MVFACHI_CODE \
   length = 2; \
-  f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
-  f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
-  f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
-  f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
+  f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
+  f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
+  f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
+  f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
 
 #define EXTRACT_IFMT_MVFC_VARS \
-  /* Instruction fields.  */ \
   UINT f_op1; \
   UINT f_r1; \
   UINT f_op2; \
@@ -742,13 +519,12 @@ struct scache {
   unsigned int length;
 #define EXTRACT_IFMT_MVFC_CODE \
   length = 2; \
-  f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
-  f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
-  f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
-  f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
+  f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
+  f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
+  f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
+  f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
 
 #define EXTRACT_IFMT_MVTACHI_VARS \
-  /* Instruction fields.  */ \
   UINT f_op1; \
   UINT f_r1; \
   UINT f_op2; \
@@ -756,13 +532,12 @@ struct scache {
   unsigned int length;
 #define EXTRACT_IFMT_MVTACHI_CODE \
   length = 2; \
-  f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
-  f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
-  f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
-  f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
+  f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
+  f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
+  f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
+  f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
 
 #define EXTRACT_IFMT_MVTC_VARS \
-  /* Instruction fields.  */ \
   UINT f_op1; \
   UINT f_r1; \
   UINT f_op2; \
@@ -770,13 +545,12 @@ struct scache {
   unsigned int length;
 #define EXTRACT_IFMT_MVTC_CODE \
   length = 2; \
-  f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
-  f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
-  f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
-  f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
+  f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
+  f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
+  f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
+  f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
 
 #define EXTRACT_IFMT_NOP_VARS \
-  /* Instruction fields.  */ \
   UINT f_op1; \
   UINT f_r1; \
   UINT f_op2; \
@@ -784,13 +558,12 @@ struct scache {
   unsigned int length;
 #define EXTRACT_IFMT_NOP_CODE \
   length = 2; \
-  f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
-  f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
-  f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
-  f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
+  f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
+  f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
+  f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
+  f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
 
 #define EXTRACT_IFMT_SETH_VARS \
-  /* Instruction fields.  */ \
   UINT f_op1; \
   UINT f_r1; \
   UINT f_op2; \
@@ -799,14 +572,13 @@ struct scache {
   unsigned int length;
 #define EXTRACT_IFMT_SETH_CODE \
   length = 4; \
-  f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
-  f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
-  f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
-  f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
-  f_hi16 = EXTRACT_UINT (insn, 32, 16, 16); \
+  f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
+  f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
+  f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
+  f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
+  f_hi16 = EXTRACT_MSB0_UINT (insn, 32, 16, 16); \
 
 #define EXTRACT_IFMT_SLLI_VARS \
-  /* Instruction fields.  */ \
   UINT f_op1; \
   UINT f_r1; \
   UINT f_shift_op2; \
@@ -814,13 +586,12 @@ struct scache {
   unsigned int length;
 #define EXTRACT_IFMT_SLLI_CODE \
   length = 2; \
-  f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
-  f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
-  f_shift_op2 = EXTRACT_UINT (insn, 16, 8, 3); \
-  f_uimm5 = EXTRACT_UINT (insn, 16, 11, 5); \
+  f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
+  f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
+  f_shift_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 3); \
+  f_uimm5 = EXTRACT_MSB0_UINT (insn, 16, 11, 5); \
 
 #define EXTRACT_IFMT_ST_D_VARS \
-  /* Instruction fields.  */ \
   UINT f_op1; \
   UINT f_r1; \
   UINT f_op2; \
@@ -829,14 +600,13 @@ struct scache {
   unsigned int length;
 #define EXTRACT_IFMT_ST_D_CODE \
   length = 4; \
-  f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
-  f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
-  f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
-  f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
-  f_simm16 = EXTRACT_INT (insn, 32, 16, 16); \
+  f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
+  f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
+  f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
+  f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
+  f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16); \
 
 #define EXTRACT_IFMT_TRAP_VARS \
-  /* Instruction fields.  */ \
   UINT f_op1; \
   UINT f_r1; \
   UINT f_op2; \
@@ -844,10 +614,10 @@ struct scache {
   unsigned int length;
 #define EXTRACT_IFMT_TRAP_CODE \
   length = 2; \
-  f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
-  f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
-  f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
-  f_uimm4 = EXTRACT_UINT (insn, 16, 12, 4); \
+  f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
+  f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
+  f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
+  f_uimm4 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
 
 /* Collection of various things for the trace handler to use.  */
 
diff --git a/sim/m32r/cpuall.h b/sim/m32r/cpuall.h
index 3563f744a8f..3c91931bfa1 100644
--- a/sim/m32r/cpuall.h
+++ b/sim/m32r/cpuall.h
@@ -51,6 +51,9 @@ struct argbuf {
   const IDESC *idesc;
   char trace_p;
   char profile_p;
+  /* ??? Temporary hack for skip insns.  */
+  char skip_count;
+  char unused;
   /* cpu specific data follows */
 };
 #endif
diff --git a/sim/m32r/decode.c b/sim/m32r/decode.c
index 8bac0ef9e83..2b6b77404fb 100644
--- a/sim/m32r/decode.c
+++ b/sim/m32r/decode.c
@@ -28,29 +28,6 @@ with this program; if not, write to the Free Software Foundation, Inc.,
 #include "sim-main.h"
 #include "sim-assert.h"
 
-/* FIXME: Need to review choices for the following.  */
-
-#if WITH_SEM_SWITCH_FULL
-#define FULL(fn)
-#else
-#define FULL(fn) CONCAT3 (m32rbf,_sem_,fn) ,
-#endif
-
-#if WITH_FAST
-#if WITH_SEM_SWITCH_FAST
-#define FAST(fn)
-#else
-#define FAST(fn) CONCAT3 (m32rbf,_semf_,fn) , /* f for fast */
-#endif
-#else
-#define FAST(fn)
-#endif
-
-/* The INSN_ prefix is not here and is instead part of the `insn' argument
-   to avoid collisions with header files (e.g. `AND' in ansidecl.h).  */
-#define IDX(insn) CONCAT2 (M32RBF_,insn)
-#define TYPE(insn) CONCAT2 (M32R_,insn)
-
 /* The instruction descriptor array.
    This is computed at runtime.  Space for it is not malloc'd to save a
    teensy bit of cpu in the decoder.  Moving it to malloc space is trivial
@@ -63,124 +40,117 @@ static IDESC m32rbf_insn_data[M32RBF_INSN_MAX];
 
 static const struct insn_sem m32rbf_insn_sem[] =
 {
-  { VIRTUAL_INSN_X_INVALID, IDX (INSN_X_INVALID), FULL (x_invalid) FAST (x_invalid) },
-  { VIRTUAL_INSN_X_AFTER, IDX (INSN_X_AFTER), FULL (x_after) FAST (x_after) },
-  { VIRTUAL_INSN_X_BEFORE, IDX (INSN_X_BEFORE), FULL (x_before) FAST (x_before) },
-  { VIRTUAL_INSN_X_CTI_CHAIN, IDX (INSN_X_CTI_CHAIN), FULL (x_cti_chain) FAST (x_cti_chain) },
-  { VIRTUAL_INSN_X_CHAIN, IDX (INSN_X_CHAIN), FULL (x_chain) FAST (x_chain) },
-  { VIRTUAL_INSN_X_BEGIN, IDX (INSN_X_BEGIN), FULL (x_begin) FAST (x_begin) },
-  { TYPE (INSN_ADD), IDX (INSN_ADD), FULL (add) FAST (add) },
-  { TYPE (INSN_ADD3), IDX (INSN_ADD3), FULL (add3) FAST (add3) },
-  { TYPE (INSN_AND), IDX (INSN_AND), FULL (and) FAST (and) },
-  { TYPE (INSN_AND3), IDX (INSN_AND3), FULL (and3) FAST (and3) },
-  { TYPE (INSN_OR), IDX (INSN_OR), FULL (or) FAST (or) },
-  { TYPE (INSN_OR3), IDX (INSN_OR3), FULL (or3) FAST (or3) },
-  { TYPE (INSN_XOR), IDX (INSN_XOR), FULL (xor) FAST (xor) },
-  { TYPE (INSN_XOR3), IDX (INSN_XOR3), FULL (xor3) FAST (xor3) },
-  { TYPE (INSN_ADDI), IDX (INSN_ADDI), FULL (addi) FAST (addi) },
-  { TYPE (INSN_ADDV), IDX (INSN_ADDV), FULL (addv) FAST (addv) },
-  { TYPE (INSN_ADDV3), IDX (INSN_ADDV3), FULL (addv3) FAST (addv3) },
-  { TYPE (INSN_ADDX), IDX (INSN_ADDX), FULL (addx) FAST (addx) },
-  { TYPE (INSN_BC8), IDX (INSN_BC8), FULL (bc8) FAST (bc8) },
-  { TYPE (INSN_BC24), IDX (INSN_BC24), FULL (bc24) FAST (bc24) },
-  { TYPE (INSN_BEQ), IDX (INSN_BEQ), FULL (beq) FAST (beq) },
-  { TYPE (INSN_BEQZ), IDX (INSN_BEQZ), FULL (beqz) FAST (beqz) },
-  { TYPE (INSN_BGEZ), IDX (INSN_BGEZ), FULL (bgez) FAST (bgez) },
-  { TYPE (INSN_BGTZ), IDX (INSN_BGTZ), FULL (bgtz) FAST (bgtz) },
-  { TYPE (INSN_BLEZ), IDX (INSN_BLEZ), FULL (blez) FAST (blez) },
-  { TYPE (INSN_BLTZ), IDX (INSN_BLTZ), FULL (bltz) FAST (bltz) },
-  { TYPE (INSN_BNEZ), IDX (INSN_BNEZ), FULL (bnez) FAST (bnez) },
-  { TYPE (INSN_BL8), IDX (INSN_BL8), FULL (bl8) FAST (bl8) },
-  { TYPE (INSN_BL24), IDX (INSN_BL24), FULL (bl24) FAST (bl24) },
-  { TYPE (INSN_BNC8), IDX (INSN_BNC8), FULL (bnc8) FAST (bnc8) },
-  { TYPE (INSN_BNC24), IDX (INSN_BNC24), FULL (bnc24) FAST (bnc24) },
-  { TYPE (INSN_BNE), IDX (INSN_BNE), FULL (bne) FAST (bne) },
-  { TYPE (INSN_BRA8), IDX (INSN_BRA8), FULL (bra8) FAST (bra8) },
-  { TYPE (INSN_BRA24), IDX (INSN_BRA24), FULL (bra24) FAST (bra24) },
-  { TYPE (INSN_CMP), IDX (INSN_CMP), FULL (cmp) FAST (cmp) },
-  { TYPE (INSN_CMPI), IDX (INSN_CMPI), FULL (cmpi) FAST (cmpi) },
-  { TYPE (INSN_CMPU), IDX (INSN_CMPU), FULL (cmpu) FAST (cmpu) },
-  { TYPE (INSN_CMPUI), IDX (INSN_CMPUI), FULL (cmpui) FAST (cmpui) },
-  { TYPE (INSN_DIV), IDX (INSN_DIV), FULL (div) FAST (div) },
-  { TYPE (INSN_DIVU), IDX (INSN_DIVU), FULL (divu) FAST (divu) },
-  { TYPE (INSN_REM), IDX (INSN_REM), FULL (rem) FAST (rem) },
-  { TYPE (INSN_REMU), IDX (INSN_REMU), FULL (remu) FAST (remu) },
-  { TYPE (INSN_JL), IDX (INSN_JL), FULL (jl) FAST (jl) },
-  { TYPE (INSN_JMP), IDX (INSN_JMP), FULL (jmp) FAST (jmp) },
-  { TYPE (INSN_LD), IDX (INSN_LD), FULL (ld) FAST (ld) },
-  { TYPE (INSN_LD_D), IDX (INSN_LD_D), FULL (ld_d) FAST (ld_d) },
-  { TYPE (INSN_LDB), IDX (INSN_LDB), FULL (ldb) FAST (ldb) },
-  { TYPE (INSN_LDB_D), IDX (INSN_LDB_D), FULL (ldb_d) FAST (ldb_d) },
-  { TYPE (INSN_LDH), IDX (INSN_LDH), FULL (ldh) FAST (ldh) },
-  { TYPE (INSN_LDH_D), IDX (INSN_LDH_D), FULL (ldh_d) FAST (ldh_d) },
-  { TYPE (INSN_LDUB), IDX (INSN_LDUB), FULL (ldub) FAST (ldub) },
-  { TYPE (INSN_LDUB_D), IDX (INSN_LDUB_D), FULL (ldub_d) FAST (ldub_d) },
-  { TYPE (INSN_LDUH), IDX (INSN_LDUH), FULL (lduh) FAST (lduh) },
-  { TYPE (INSN_LDUH_D), IDX (INSN_LDUH_D), FULL (lduh_d) FAST (lduh_d) },
-  { TYPE (INSN_LD_PLUS), IDX (INSN_LD_PLUS), FULL (ld_plus) FAST (ld_plus) },
-  { TYPE (INSN_LD24), IDX (INSN_LD24), FULL (ld24) FAST (ld24) },
-  { TYPE (INSN_LDI8), IDX (INSN_LDI8), FULL (ldi8) FAST (ldi8) },
-  { TYPE (INSN_LDI16), IDX (INSN_LDI16), FULL (ldi16) FAST (ldi16) },
-  { TYPE (INSN_LOCK), IDX (INSN_LOCK), FULL (lock) FAST (lock) },
-  { TYPE (INSN_MACHI), IDX (INSN_MACHI), FULL (machi) FAST (machi) },
-  { TYPE (INSN_MACLO), IDX (INSN_MACLO), FULL (maclo) FAST (maclo) },
-  { TYPE (INSN_MACWHI), IDX (INSN_MACWHI), FULL (macwhi) FAST (macwhi) },
-  { TYPE (INSN_MACWLO), IDX (INSN_MACWLO), FULL (macwlo) FAST (macwlo) },
-  { TYPE (INSN_MUL), IDX (INSN_MUL), FULL (mul) FAST (mul) },
-  { TYPE (INSN_MULHI), IDX (INSN_MULHI), FULL (mulhi) FAST (mulhi) },
-  { TYPE (INSN_MULLO), IDX (INSN_MULLO), FULL (mullo) FAST (mullo) },
-  { TYPE (INSN_MULWHI), IDX (INSN_MULWHI), FULL (mulwhi) FAST (mulwhi) },
-  { TYPE (INSN_MULWLO), IDX (INSN_MULWLO), FULL (mulwlo) FAST (mulwlo) },
-  { TYPE (INSN_MV), IDX (INSN_MV), FULL (mv) FAST (mv) },
-  { TYPE (INSN_MVFACHI), IDX (INSN_MVFACHI), FULL (mvfachi) FAST (mvfachi) },
-  { TYPE (INSN_MVFACLO), IDX (INSN_MVFACLO), FULL (mvfaclo) FAST (mvfaclo) },
-  { TYPE (INSN_MVFACMI), IDX (INSN_MVFACMI), FULL (mvfacmi) FAST (mvfacmi) },
-  { TYPE (INSN_MVFC), IDX (INSN_MVFC), FULL (mvfc) FAST (mvfc) },
-  { TYPE (INSN_MVTACHI), IDX (INSN_MVTACHI), FULL (mvtachi) FAST (mvtachi) },
-  { TYPE (INSN_MVTACLO), IDX (INSN_MVTACLO), FULL (mvtaclo) FAST (mvtaclo) },
-  { TYPE (INSN_MVTC), IDX (INSN_MVTC), FULL (mvtc) FAST (mvtc) },
-  { TYPE (INSN_NEG), IDX (INSN_NEG), FULL (neg) FAST (neg) },
-  { TYPE (INSN_NOP), IDX (INSN_NOP), FULL (nop) FAST (nop) },
-  { TYPE (INSN_NOT), IDX (INSN_NOT), FULL (not) FAST (not) },
-  { TYPE (INSN_RAC), IDX (INSN_RAC), FULL (rac) FAST (rac) },
-  { TYPE (INSN_RACH), IDX (INSN_RACH), FULL (rach) FAST (rach) },
-  { TYPE (INSN_RTE), IDX (INSN_RTE), FULL (rte) FAST (rte) },
-  { TYPE (INSN_SETH), IDX (INSN_SETH), FULL (seth) FAST (seth) },
-  { TYPE (INSN_SLL), IDX (INSN_SLL), FULL (sll) FAST (sll) },
-  { TYPE (INSN_SLL3), IDX (INSN_SLL3), FULL (sll3) FAST (sll3) },
-  { TYPE (INSN_SLLI), IDX (INSN_SLLI), FULL (slli) FAST (slli) },
-  { TYPE (INSN_SRA), IDX (INSN_SRA), FULL (sra) FAST (sra) },
-  { TYPE (INSN_SRA3), IDX (INSN_SRA3), FULL (sra3) FAST (sra3) },
-  { TYPE (INSN_SRAI), IDX (INSN_SRAI), FULL (srai) FAST (srai) },
-  { TYPE (INSN_SRL), IDX (INSN_SRL), FULL (srl) FAST (srl) },
-  { TYPE (INSN_SRL3), IDX (INSN_SRL3), FULL (srl3) FAST (srl3) },
-  { TYPE (INSN_SRLI), IDX (INSN_SRLI), FULL (srli) FAST (srli) },
-  { TYPE (INSN_ST), IDX (INSN_ST), FULL (st) FAST (st) },
-  { TYPE (INSN_ST_D), IDX (INSN_ST_D), FULL (st_d) FAST (st_d) },
-  { TYPE (INSN_STB), IDX (INSN_STB), FULL (stb) FAST (stb) },
-  { TYPE (INSN_STB_D), IDX (INSN_STB_D), FULL (stb_d) FAST (stb_d) },
-  { TYPE (INSN_STH), IDX (INSN_STH), FULL (sth) FAST (sth) },
-  { TYPE (INSN_STH_D), IDX (INSN_STH_D), FULL (sth_d) FAST (sth_d) },
-  { TYPE (INSN_ST_PLUS), IDX (INSN_ST_PLUS), FULL (st_plus) FAST (st_plus) },
-  { TYPE (INSN_ST_MINUS), IDX (INSN_ST_MINUS), FULL (st_minus) FAST (st_minus) },
-  { TYPE (INSN_SUB), IDX (INSN_SUB), FULL (sub) FAST (sub) },
-  { TYPE (INSN_SUBV), IDX (INSN_SUBV), FULL (subv) FAST (subv) },
-  { TYPE (INSN_SUBX), IDX (INSN_SUBX), FULL (subx) FAST (subx) },
-  { TYPE (INSN_TRAP), IDX (INSN_TRAP), FULL (trap) FAST (trap) },
-  { TYPE (INSN_UNLOCK), IDX (INSN_UNLOCK), FULL (unlock) FAST (unlock) },
+  { VIRTUAL_INSN_X_INVALID, M32RBF_INSN_X_INVALID, M32RBF_SFMT_EMPTY },
+  { VIRTUAL_INSN_X_AFTER, M32RBF_INSN_X_AFTER, M32RBF_SFMT_EMPTY },
+  { VIRTUAL_INSN_X_BEFORE, M32RBF_INSN_X_BEFORE, M32RBF_SFMT_EMPTY },
+  { VIRTUAL_INSN_X_CTI_CHAIN, M32RBF_INSN_X_CTI_CHAIN, M32RBF_SFMT_EMPTY },
+  { VIRTUAL_INSN_X_CHAIN, M32RBF_INSN_X_CHAIN, M32RBF_SFMT_EMPTY },
+  { VIRTUAL_INSN_X_BEGIN, M32RBF_INSN_X_BEGIN, M32RBF_SFMT_EMPTY },
+  { M32R_INSN_ADD, M32RBF_INSN_ADD, M32RBF_SFMT_ADD },
+  { M32R_INSN_ADD3, M32RBF_INSN_ADD3, M32RBF_SFMT_ADD3 },
+  { M32R_INSN_AND, M32RBF_INSN_AND, M32RBF_SFMT_ADD },
+  { M32R_INSN_AND3, M32RBF_INSN_AND3, M32RBF_SFMT_AND3 },
+  { M32R_INSN_OR, M32RBF_INSN_OR, M32RBF_SFMT_ADD },
+  { M32R_INSN_OR3, M32RBF_INSN_OR3, M32RBF_SFMT_OR3 },
+  { M32R_INSN_XOR, M32RBF_INSN_XOR, M32RBF_SFMT_ADD },
+  { M32R_INSN_XOR3, M32RBF_INSN_XOR3, M32RBF_SFMT_AND3 },
+  { M32R_INSN_ADDI, M32RBF_INSN_ADDI, M32RBF_SFMT_ADDI },
+  { M32R_INSN_ADDV, M32RBF_INSN_ADDV, M32RBF_SFMT_ADDV },
+  { M32R_INSN_ADDV3, M32RBF_INSN_ADDV3, M32RBF_SFMT_ADDV3 },
+  { M32R_INSN_ADDX, M32RBF_INSN_ADDX, M32RBF_SFMT_ADDX },
+  { M32R_INSN_BC8, M32RBF_INSN_BC8, M32RBF_SFMT_BC8 },
+  { M32R_INSN_BC24, M32RBF_INSN_BC24, M32RBF_SFMT_BC24 },
+  { M32R_INSN_BEQ, M32RBF_INSN_BEQ, M32RBF_SFMT_BEQ },
+  { M32R_INSN_BEQZ, M32RBF_INSN_BEQZ, M32RBF_SFMT_BEQZ },
+  { M32R_INSN_BGEZ, M32RBF_INSN_BGEZ, M32RBF_SFMT_BEQZ },
+  { M32R_INSN_BGTZ, M32RBF_INSN_BGTZ, M32RBF_SFMT_BEQZ },
+  { M32R_INSN_BLEZ, M32RBF_INSN_BLEZ, M32RBF_SFMT_BEQZ },
+  { M32R_INSN_BLTZ, M32RBF_INSN_BLTZ, M32RBF_SFMT_BEQZ },
+  { M32R_INSN_BNEZ, M32RBF_INSN_BNEZ, M32RBF_SFMT_BEQZ },
+  { M32R_INSN_BL8, M32RBF_INSN_BL8, M32RBF_SFMT_BL8 },
+  { M32R_INSN_BL24, M32RBF_INSN_BL24, M32RBF_SFMT_BL24 },
+  { M32R_INSN_BNC8, M32RBF_INSN_BNC8, M32RBF_SFMT_BC8 },
+  { M32R_INSN_BNC24, M32RBF_INSN_BNC24, M32RBF_SFMT_BC24 },
+  { M32R_INSN_BNE, M32RBF_INSN_BNE, M32RBF_SFMT_BEQ },
+  { M32R_INSN_BRA8, M32RBF_INSN_BRA8, M32RBF_SFMT_BRA8 },
+  { M32R_INSN_BRA24, M32RBF_INSN_BRA24, M32RBF_SFMT_BRA24 },
+  { M32R_INSN_CMP, M32RBF_INSN_CMP, M32RBF_SFMT_CMP },
+  { M32R_INSN_CMPI, M32RBF_INSN_CMPI, M32RBF_SFMT_CMPI },
+  { M32R_INSN_CMPU, M32RBF_INSN_CMPU, M32RBF_SFMT_CMP },
+  { M32R_INSN_CMPUI, M32RBF_INSN_CMPUI, M32RBF_SFMT_CMPI },
+  { M32R_INSN_DIV, M32RBF_INSN_DIV, M32RBF_SFMT_DIV },
+  { M32R_INSN_DIVU, M32RBF_INSN_DIVU, M32RBF_SFMT_DIV },
+  { M32R_INSN_REM, M32RBF_INSN_REM, M32RBF_SFMT_DIV },
+  { M32R_INSN_REMU, M32RBF_INSN_REMU, M32RBF_SFMT_DIV },
+  { M32R_INSN_JL, M32RBF_INSN_JL, M32RBF_SFMT_JL },
+  { M32R_INSN_JMP, M32RBF_INSN_JMP, M32RBF_SFMT_JMP },
+  { M32R_INSN_LD, M32RBF_INSN_LD, M32RBF_SFMT_LD },
+  { M32R_INSN_LD_D, M32RBF_INSN_LD_D, M32RBF_SFMT_LD_D },
+  { M32R_INSN_LDB, M32RBF_INSN_LDB, M32RBF_SFMT_LD },
+  { M32R_INSN_LDB_D, M32RBF_INSN_LDB_D, M32RBF_SFMT_LD_D },
+  { M32R_INSN_LDH, M32RBF_INSN_LDH, M32RBF_SFMT_LD },
+  { M32R_INSN_LDH_D, M32RBF_INSN_LDH_D, M32RBF_SFMT_LD_D },
+  { M32R_INSN_LDUB, M32RBF_INSN_LDUB, M32RBF_SFMT_LD },
+  { M32R_INSN_LDUB_D, M32RBF_INSN_LDUB_D, M32RBF_SFMT_LD_D },
+  { M32R_INSN_LDUH, M32RBF_INSN_LDUH, M32RBF_SFMT_LD },
+  { M32R_INSN_LDUH_D, M32RBF_INSN_LDUH_D, M32RBF_SFMT_LD_D },
+  { M32R_INSN_LD_PLUS, M32RBF_INSN_LD_PLUS, M32RBF_SFMT_LD_PLUS },
+  { M32R_INSN_LD24, M32RBF_INSN_LD24, M32RBF_SFMT_LD24 },
+  { M32R_INSN_LDI8, M32RBF_INSN_LDI8, M32RBF_SFMT_LDI8 },
+  { M32R_INSN_LDI16, M32RBF_INSN_LDI16, M32RBF_SFMT_LDI16 },
+  { M32R_INSN_LOCK, M32RBF_INSN_LOCK, M32RBF_SFMT_LOCK },
+  { M32R_INSN_MACHI, M32RBF_INSN_MACHI, M32RBF_SFMT_MACHI },
+  { M32R_INSN_MACLO, M32RBF_INSN_MACLO, M32RBF_SFMT_MACHI },
+  { M32R_INSN_MACWHI, M32RBF_INSN_MACWHI, M32RBF_SFMT_MACHI },
+  { M32R_INSN_MACWLO, M32RBF_INSN_MACWLO, M32RBF_SFMT_MACHI },
+  { M32R_INSN_MUL, M32RBF_INSN_MUL, M32RBF_SFMT_ADD },
+  { M32R_INSN_MULHI, M32RBF_INSN_MULHI, M32RBF_SFMT_MULHI },
+  { M32R_INSN_MULLO, M32RBF_INSN_MULLO, M32RBF_SFMT_MULHI },
+  { M32R_INSN_MULWHI, M32RBF_INSN_MULWHI, M32RBF_SFMT_MULHI },
+  { M32R_INSN_MULWLO, M32RBF_INSN_MULWLO, M32RBF_SFMT_MULHI },
+  { M32R_INSN_MV, M32RBF_INSN_MV, M32RBF_SFMT_MV },
+  { M32R_INSN_MVFACHI, M32RBF_INSN_MVFACHI, M32RBF_SFMT_MVFACHI },
+  { M32R_INSN_MVFACLO, M32RBF_INSN_MVFACLO, M32RBF_SFMT_MVFACHI },
+  { M32R_INSN_MVFACMI, M32RBF_INSN_MVFACMI, M32RBF_SFMT_MVFACHI },
+  { M32R_INSN_MVFC, M32RBF_INSN_MVFC, M32RBF_SFMT_MVFC },
+  { M32R_INSN_MVTACHI, M32RBF_INSN_MVTACHI, M32RBF_SFMT_MVTACHI },
+  { M32R_INSN_MVTACLO, M32RBF_INSN_MVTACLO, M32RBF_SFMT_MVTACHI },
+  { M32R_INSN_MVTC, M32RBF_INSN_MVTC, M32RBF_SFMT_MVTC },
+  { M32R_INSN_NEG, M32RBF_INSN_NEG, M32RBF_SFMT_MV },
+  { M32R_INSN_NOP, M32RBF_INSN_NOP, M32RBF_SFMT_NOP },
+  { M32R_INSN_NOT, M32RBF_INSN_NOT, M32RBF_SFMT_MV },
+  { M32R_INSN_RAC, M32RBF_INSN_RAC, M32RBF_SFMT_RAC },
+  { M32R_INSN_RACH, M32RBF_INSN_RACH, M32RBF_SFMT_RAC },
+  { M32R_INSN_RTE, M32RBF_INSN_RTE, M32RBF_SFMT_RTE },
+  { M32R_INSN_SETH, M32RBF_INSN_SETH, M32RBF_SFMT_SETH },
+  { M32R_INSN_SLL, M32RBF_INSN_SLL, M32RBF_SFMT_ADD },
+  { M32R_INSN_SLL3, M32RBF_INSN_SLL3, M32RBF_SFMT_SLL3 },
+  { M32R_INSN_SLLI, M32RBF_INSN_SLLI, M32RBF_SFMT_SLLI },
+  { M32R_INSN_SRA, M32RBF_INSN_SRA, M32RBF_SFMT_ADD },
+  { M32R_INSN_SRA3, M32RBF_INSN_SRA3, M32RBF_SFMT_SLL3 },
+  { M32R_INSN_SRAI, M32RBF_INSN_SRAI, M32RBF_SFMT_SLLI },
+  { M32R_INSN_SRL, M32RBF_INSN_SRL, M32RBF_SFMT_ADD },
+  { M32R_INSN_SRL3, M32RBF_INSN_SRL3, M32RBF_SFMT_SLL3 },
+  { M32R_INSN_SRLI, M32RBF_INSN_SRLI, M32RBF_SFMT_SLLI },
+  { M32R_INSN_ST, M32RBF_INSN_ST, M32RBF_SFMT_ST },
+  { M32R_INSN_ST_D, M32RBF_INSN_ST_D, M32RBF_SFMT_ST_D },
+  { M32R_INSN_STB, M32RBF_INSN_STB, M32RBF_SFMT_STB },
+  { M32R_INSN_STB_D, M32RBF_INSN_STB_D, M32RBF_SFMT_STB_D },
+  { M32R_INSN_STH, M32RBF_INSN_STH, M32RBF_SFMT_STH },
+  { M32R_INSN_STH_D, M32RBF_INSN_STH_D, M32RBF_SFMT_STH_D },
+  { M32R_INSN_ST_PLUS, M32RBF_INSN_ST_PLUS, M32RBF_SFMT_ST_PLUS },
+  { M32R_INSN_ST_MINUS, M32RBF_INSN_ST_MINUS, M32RBF_SFMT_ST_PLUS },
+  { M32R_INSN_SUB, M32RBF_INSN_SUB, M32RBF_SFMT_ADD },
+  { M32R_INSN_SUBV, M32RBF_INSN_SUBV, M32RBF_SFMT_ADDV },
+  { M32R_INSN_SUBX, M32RBF_INSN_SUBX, M32RBF_SFMT_ADDX },
+  { M32R_INSN_TRAP, M32RBF_INSN_TRAP, M32RBF_SFMT_TRAP },
+  { M32R_INSN_UNLOCK, M32RBF_INSN_UNLOCK, M32RBF_SFMT_UNLOCK },
 };
 
-static const struct insn_sem m32rbf_insn_sem_invalid =
-{
-  VIRTUAL_INSN_X_INVALID, IDX (INSN_X_INVALID), FULL (x_invalid) FAST (x_invalid)
+static const struct insn_sem m32rbf_insn_sem_invalid = {
+  VIRTUAL_INSN_X_INVALID, M32RBF_INSN_X_INVALID, M32RBF_SFMT_EMPTY
 };
 
-#undef FMT
-#undef FULL
-#undef FAST
-#undef IDX
-#undef TYPE
-
 /* Initialize an IDESC from the compile-time computable parts.  */
 
 static INLINE void
@@ -189,6 +159,7 @@ init_idesc (SIM_CPU *cpu, IDESC *id, const struct insn_sem *t)
   const CGEN_INSN *insn_table = CGEN_CPU_INSN_TABLE (CPU_CPU_DESC (cpu))->init_entries;
 
   id->num = t->index;
+  id->sfmt = t->sfmt;
   if ((int) t->type <= 0)
     id->idata = & cgen_virtual_insn_table[- (int) t->type];
   else
@@ -196,12 +167,7 @@ init_idesc (SIM_CPU *cpu, IDESC *id, const struct insn_sem *t)
   id->attrs = CGEN_INSN_ATTRS (id->idata);
   /* Oh my god, a magic number.  */
   id->length = CGEN_INSN_BITSIZE (id->idata) / 8;
-#if ! WITH_SEM_SWITCH_FULL
-  id->sem_full = t->sem_full;
-#endif
-#if WITH_FAST && ! WITH_SEM_SWITCH_FAST
-  id->sem_fast = t->sem_fast;
-#endif
+
 #if WITH_PROFILE_MODEL_P
   id->timing = & MODEL_TIMING (CPU_MODEL (cpu)) [t->index];
   {
@@ -209,6 +175,8 @@ init_idesc (SIM_CPU *cpu, IDESC *id, const struct insn_sem *t)
     SIM_ASSERT (t->index == id->timing->num);
   }
 #endif
+
+  /* Semantic pointers are initialized elsewhere.  */
 }
 
 /* Initialize the instruction descriptor table.  */
@@ -256,59 +224,59 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc,
       unsigned int val = (((insn >> 8) & (15 << 4)) | ((insn >> 4) & (15 << 0)));
       switch (val)
       {
-      case 0 : itype = M32RBF_INSN_SUBV; goto extract_fmt_addv;
-      case 1 : itype = M32RBF_INSN_SUBX; goto extract_fmt_addx;
-      case 2 : itype = M32RBF_INSN_SUB; goto extract_fmt_add;
-      case 3 : itype = M32RBF_INSN_NEG; goto extract_fmt_mv;
-      case 4 : itype = M32RBF_INSN_CMP; goto extract_fmt_cmp;
-      case 5 : itype = M32RBF_INSN_CMPU; goto extract_fmt_cmp;
-      case 8 : itype = M32RBF_INSN_ADDV; goto extract_fmt_addv;
-      case 9 : itype = M32RBF_INSN_ADDX; goto extract_fmt_addx;
-      case 10 : itype = M32RBF_INSN_ADD; goto extract_fmt_add;
-      case 11 : itype = M32RBF_INSN_NOT; goto extract_fmt_mv;
-      case 12 : itype = M32RBF_INSN_AND; goto extract_fmt_add;
-      case 13 : itype = M32RBF_INSN_XOR; goto extract_fmt_add;
-      case 14 : itype = M32RBF_INSN_OR; goto extract_fmt_add;
-      case 16 : itype = M32RBF_INSN_SRL; goto extract_fmt_add;
-      case 18 : itype = M32RBF_INSN_SRA; goto extract_fmt_add;
-      case 20 : itype = M32RBF_INSN_SLL; goto extract_fmt_add;
-      case 22 : itype = M32RBF_INSN_MUL; goto extract_fmt_add;
-      case 24 : itype = M32RBF_INSN_MV; goto extract_fmt_mv;
-      case 25 : itype = M32RBF_INSN_MVFC; goto extract_fmt_mvfc;
-      case 26 : itype = M32RBF_INSN_MVTC; goto extract_fmt_mvtc;
+      case 0 : itype = M32RBF_INSN_SUBV; goto extract_sfmt_addv;
+      case 1 : itype = M32RBF_INSN_SUBX; goto extract_sfmt_addx;
+      case 2 : itype = M32RBF_INSN_SUB; goto extract_sfmt_add;
+      case 3 : itype = M32RBF_INSN_NEG; goto extract_sfmt_mv;
+      case 4 : itype = M32RBF_INSN_CMP; goto extract_sfmt_cmp;
+      case 5 : itype = M32RBF_INSN_CMPU; goto extract_sfmt_cmp;
+      case 8 : itype = M32RBF_INSN_ADDV; goto extract_sfmt_addv;
+      case 9 : itype = M32RBF_INSN_ADDX; goto extract_sfmt_addx;
+      case 10 : itype = M32RBF_INSN_ADD; goto extract_sfmt_add;
+      case 11 : itype = M32RBF_INSN_NOT; goto extract_sfmt_mv;
+      case 12 : itype = M32RBF_INSN_AND; goto extract_sfmt_add;
+      case 13 : itype = M32RBF_INSN_XOR; goto extract_sfmt_add;
+      case 14 : itype = M32RBF_INSN_OR; goto extract_sfmt_add;
+      case 16 : itype = M32RBF_INSN_SRL; goto extract_sfmt_add;
+      case 18 : itype = M32RBF_INSN_SRA; goto extract_sfmt_add;
+      case 20 : itype = M32RBF_INSN_SLL; goto extract_sfmt_add;
+      case 22 : itype = M32RBF_INSN_MUL; goto extract_sfmt_add;
+      case 24 : itype = M32RBF_INSN_MV; goto extract_sfmt_mv;
+      case 25 : itype = M32RBF_INSN_MVFC; goto extract_sfmt_mvfc;
+      case 26 : itype = M32RBF_INSN_MVTC; goto extract_sfmt_mvtc;
       case 28 :
         {
           unsigned int val = (((insn >> 8) & (15 << 0)));
           switch (val)
           {
-          case 14 : itype = M32RBF_INSN_JL; goto extract_fmt_jl;
-          case 15 : itype = M32RBF_INSN_JMP; goto extract_fmt_jmp;
-          default : itype = M32RBF_INSN_X_INVALID; goto extract_fmt_empty;
+          case 14 : itype = M32RBF_INSN_JL; goto extract_sfmt_jl;
+          case 15 : itype = M32RBF_INSN_JMP; goto extract_sfmt_jmp;
+          default : itype = M32RBF_INSN_X_INVALID; goto extract_sfmt_empty;
           }
         }
-      case 29 : itype = M32RBF_INSN_RTE; goto extract_fmt_rte;
-      case 31 : itype = M32RBF_INSN_TRAP; goto extract_fmt_trap;
-      case 32 : itype = M32RBF_INSN_STB; goto extract_fmt_stb;
-      case 34 : itype = M32RBF_INSN_STH; goto extract_fmt_sth;
-      case 36 : itype = M32RBF_INSN_ST; goto extract_fmt_st;
-      case 37 : itype = M32RBF_INSN_UNLOCK; goto extract_fmt_unlock;
-      case 38 : itype = M32RBF_INSN_ST_PLUS; goto extract_fmt_st_plus;
-      case 39 : itype = M32RBF_INSN_ST_MINUS; goto extract_fmt_st_plus;
-      case 40 : itype = M32RBF_INSN_LDB; goto extract_fmt_ldb;
-      case 41 : itype = M32RBF_INSN_LDUB; goto extract_fmt_ldb;
-      case 42 : itype = M32RBF_INSN_LDH; goto extract_fmt_ldh;
-      case 43 : itype = M32RBF_INSN_LDUH; goto extract_fmt_ldh;
-      case 44 : itype = M32RBF_INSN_LD; goto extract_fmt_ld;
-      case 45 : itype = M32RBF_INSN_LOCK; goto extract_fmt_lock;
-      case 46 : itype = M32RBF_INSN_LD_PLUS; goto extract_fmt_ld_plus;
-      case 48 : itype = M32RBF_INSN_MULHI; goto extract_fmt_mulhi;
-      case 49 : itype = M32RBF_INSN_MULLO; goto extract_fmt_mulhi;
-      case 50 : itype = M32RBF_INSN_MULWHI; goto extract_fmt_mulhi;
-      case 51 : itype = M32RBF_INSN_MULWLO; goto extract_fmt_mulhi;
-      case 52 : itype = M32RBF_INSN_MACHI; goto extract_fmt_machi;
-      case 53 : itype = M32RBF_INSN_MACLO; goto extract_fmt_machi;
-      case 54 : itype = M32RBF_INSN_MACWHI; goto extract_fmt_machi;
-      case 55 : itype = M32RBF_INSN_MACWLO; goto extract_fmt_machi;
+      case 29 : itype = M32RBF_INSN_RTE; goto extract_sfmt_rte;
+      case 31 : itype = M32RBF_INSN_TRAP; goto extract_sfmt_trap;
+      case 32 : itype = M32RBF_INSN_STB; goto extract_sfmt_stb;
+      case 34 : itype = M32RBF_INSN_STH; goto extract_sfmt_sth;
+      case 36 : itype = M32RBF_INSN_ST; goto extract_sfmt_st;
+      case 37 : itype = M32RBF_INSN_UNLOCK; goto extract_sfmt_unlock;
+      case 38 : itype = M32RBF_INSN_ST_PLUS; goto extract_sfmt_st_plus;
+      case 39 : itype = M32RBF_INSN_ST_MINUS; goto extract_sfmt_st_plus;
+      case 40 : itype = M32RBF_INSN_LDB; goto extract_sfmt_ld;
+      case 41 : itype = M32RBF_INSN_LDUB; goto extract_sfmt_ld;
+      case 42 : itype = M32RBF_INSN_LDH; goto extract_sfmt_ld;
+      case 43 : itype = M32RBF_INSN_LDUH; goto extract_sfmt_ld;
+      case 44 : itype = M32RBF_INSN_LD; goto extract_sfmt_ld;
+      case 45 : itype = M32RBF_INSN_LOCK; goto extract_sfmt_lock;
+      case 46 : itype = M32RBF_INSN_LD_PLUS; goto extract_sfmt_ld_plus;
+      case 48 : itype = M32RBF_INSN_MULHI; goto extract_sfmt_mulhi;
+      case 49 : itype = M32RBF_INSN_MULLO; goto extract_sfmt_mulhi;
+      case 50 : itype = M32RBF_INSN_MULWHI; goto extract_sfmt_mulhi;
+      case 51 : itype = M32RBF_INSN_MULWLO; goto extract_sfmt_mulhi;
+      case 52 : itype = M32RBF_INSN_MACHI; goto extract_sfmt_machi;
+      case 53 : itype = M32RBF_INSN_MACLO; goto extract_sfmt_machi;
+      case 54 : itype = M32RBF_INSN_MACWHI; goto extract_sfmt_machi;
+      case 55 : itype = M32RBF_INSN_MACWLO; goto extract_sfmt_machi;
       case 64 : /* fall through */
       case 65 : /* fall through */
       case 66 : /* fall through */
@@ -324,34 +292,34 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc,
       case 76 : /* fall through */
       case 77 : /* fall through */
       case 78 : /* fall through */
-      case 79 : itype = M32RBF_INSN_ADDI; goto extract_fmt_addi;
+      case 79 : itype = M32RBF_INSN_ADDI; goto extract_sfmt_addi;
       case 80 : /* fall through */
-      case 81 : itype = M32RBF_INSN_SRLI; goto extract_fmt_slli;
+      case 81 : itype = M32RBF_INSN_SRLI; goto extract_sfmt_slli;
       case 82 : /* fall through */
-      case 83 : itype = M32RBF_INSN_SRAI; goto extract_fmt_slli;
+      case 83 : itype = M32RBF_INSN_SRAI; goto extract_sfmt_slli;
       case 84 : /* fall through */
-      case 85 : itype = M32RBF_INSN_SLLI; goto extract_fmt_slli;
+      case 85 : itype = M32RBF_INSN_SLLI; goto extract_sfmt_slli;
       case 87 :
         {
           unsigned int val = (((insn >> 0) & (15 << 0)));
           switch (val)
           {
-          case 0 : itype = M32RBF_INSN_MVTACHI; goto extract_fmt_mvtachi;
-          case 1 : itype = M32RBF_INSN_MVTACLO; goto extract_fmt_mvtachi;
-          default : itype = M32RBF_INSN_X_INVALID; goto extract_fmt_empty;
+          case 0 : itype = M32RBF_INSN_MVTACHI; goto extract_sfmt_mvtachi;
+          case 1 : itype = M32RBF_INSN_MVTACLO; goto extract_sfmt_mvtachi;
+          default : itype = M32RBF_INSN_X_INVALID; goto extract_sfmt_empty;
           }
         }
-      case 88 : itype = M32RBF_INSN_RACH; goto extract_fmt_rac;
-      case 89 : itype = M32RBF_INSN_RAC; goto extract_fmt_rac;
+      case 88 : itype = M32RBF_INSN_RACH; goto extract_sfmt_rac;
+      case 89 : itype = M32RBF_INSN_RAC; goto extract_sfmt_rac;
       case 95 :
         {
           unsigned int val = (((insn >> 0) & (15 << 0)));
           switch (val)
           {
-          case 0 : itype = M32RBF_INSN_MVFACHI; goto extract_fmt_mvfachi;
-          case 1 : itype = M32RBF_INSN_MVFACLO; goto extract_fmt_mvfachi;
-          case 2 : itype = M32RBF_INSN_MVFACMI; goto extract_fmt_mvfachi;
-          default : itype = M32RBF_INSN_X_INVALID; goto extract_fmt_empty;
+          case 0 : itype = M32RBF_INSN_MVFACHI; goto extract_sfmt_mvfachi;
+          case 1 : itype = M32RBF_INSN_MVFACLO; goto extract_sfmt_mvfachi;
+          case 2 : itype = M32RBF_INSN_MVFACMI; goto extract_sfmt_mvfachi;
+          default : itype = M32RBF_INSN_X_INVALID; goto extract_sfmt_empty;
           }
         }
       case 96 : /* fall through */
@@ -369,18 +337,18 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc,
       case 108 : /* fall through */
       case 109 : /* fall through */
       case 110 : /* fall through */
-      case 111 : itype = M32RBF_INSN_LDI8; goto extract_fmt_ldi8;
+      case 111 : itype = M32RBF_INSN_LDI8; goto extract_sfmt_ldi8;
       case 112 :
         {
           unsigned int val = (((insn >> 8) & (15 << 0)));
           switch (val)
           {
-          case 0 : itype = M32RBF_INSN_NOP; goto extract_fmt_nop;
-          case 12 : itype = M32RBF_INSN_BC8; goto extract_fmt_bc8;
-          case 13 : itype = M32RBF_INSN_BNC8; goto extract_fmt_bc8;
-          case 14 : itype = M32RBF_INSN_BL8; goto extract_fmt_bl8;
-          case 15 : itype = M32RBF_INSN_BRA8; goto extract_fmt_bra8;
-          default : itype = M32RBF_INSN_X_INVALID; goto extract_fmt_empty;
+          case 0 : itype = M32RBF_INSN_NOP; goto extract_sfmt_nop;
+          case 12 : itype = M32RBF_INSN_BC8; goto extract_sfmt_bc8;
+          case 13 : itype = M32RBF_INSN_BNC8; goto extract_sfmt_bc8;
+          case 14 : itype = M32RBF_INSN_BL8; goto extract_sfmt_bl8;
+          case 15 : itype = M32RBF_INSN_BRA8; goto extract_sfmt_bra8;
+          default : itype = M32RBF_INSN_X_INVALID; goto extract_sfmt_empty;
           }
         }
       case 113 : /* fall through */
@@ -402,45 +370,45 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc,
           unsigned int val = (((insn >> 8) & (15 << 0)));
           switch (val)
           {
-          case 12 : itype = M32RBF_INSN_BC8; goto extract_fmt_bc8;
-          case 13 : itype = M32RBF_INSN_BNC8; goto extract_fmt_bc8;
-          case 14 : itype = M32RBF_INSN_BL8; goto extract_fmt_bl8;
-          case 15 : itype = M32RBF_INSN_BRA8; goto extract_fmt_bra8;
-          default : itype = M32RBF_INSN_X_INVALID; goto extract_fmt_empty;
+          case 12 : itype = M32RBF_INSN_BC8; goto extract_sfmt_bc8;
+          case 13 : itype = M32RBF_INSN_BNC8; goto extract_sfmt_bc8;
+          case 14 : itype = M32RBF_INSN_BL8; goto extract_sfmt_bl8;
+          case 15 : itype = M32RBF_INSN_BRA8; goto extract_sfmt_bra8;
+          default : itype = M32RBF_INSN_X_INVALID; goto extract_sfmt_empty;
           }
         }
-      case 132 : itype = M32RBF_INSN_CMPI; goto extract_fmt_cmpi;
-      case 133 : itype = M32RBF_INSN_CMPUI; goto extract_fmt_cmpi;
-      case 136 : itype = M32RBF_INSN_ADDV3; goto extract_fmt_addv3;
-      case 138 : itype = M32RBF_INSN_ADD3; goto extract_fmt_add3;
-      case 140 : itype = M32RBF_INSN_AND3; goto extract_fmt_and3;
-      case 141 : itype = M32RBF_INSN_XOR3; goto extract_fmt_and3;
-      case 142 : itype = M32RBF_INSN_OR3; goto extract_fmt_or3;
-      case 144 : itype = M32RBF_INSN_DIV; goto extract_fmt_div;
-      case 145 : itype = M32RBF_INSN_DIVU; goto extract_fmt_div;
-      case 146 : itype = M32RBF_INSN_REM; goto extract_fmt_div;
-      case 147 : itype = M32RBF_INSN_REMU; goto extract_fmt_div;
-      case 152 : itype = M32RBF_INSN_SRL3; goto extract_fmt_sll3;
-      case 154 : itype = M32RBF_INSN_SRA3; goto extract_fmt_sll3;
-      case 156 : itype = M32RBF_INSN_SLL3; goto extract_fmt_sll3;
-      case 159 : itype = M32RBF_INSN_LDI16; goto extract_fmt_ldi16;
-      case 160 : itype = M32RBF_INSN_STB_D; goto extract_fmt_stb_d;
-      case 162 : itype = M32RBF_INSN_STH_D; goto extract_fmt_sth_d;
-      case 164 : itype = M32RBF_INSN_ST_D; goto extract_fmt_st_d;
-      case 168 : itype = M32RBF_INSN_LDB_D; goto extract_fmt_ldb_d;
-      case 169 : itype = M32RBF_INSN_LDUB_D; goto extract_fmt_ldb_d;
-      case 170 : itype = M32RBF_INSN_LDH_D; goto extract_fmt_ldh_d;
-      case 171 : itype = M32RBF_INSN_LDUH_D; goto extract_fmt_ldh_d;
-      case 172 : itype = M32RBF_INSN_LD_D; goto extract_fmt_ld_d;
-      case 176 : itype = M32RBF_INSN_BEQ; goto extract_fmt_beq;
-      case 177 : itype = M32RBF_INSN_BNE; goto extract_fmt_beq;
-      case 184 : itype = M32RBF_INSN_BEQZ; goto extract_fmt_beqz;
-      case 185 : itype = M32RBF_INSN_BNEZ; goto extract_fmt_beqz;
-      case 186 : itype = M32RBF_INSN_BLTZ; goto extract_fmt_beqz;
-      case 187 : itype = M32RBF_INSN_BGEZ; goto extract_fmt_beqz;
-      case 188 : itype = M32RBF_INSN_BLEZ; goto extract_fmt_beqz;
-      case 189 : itype = M32RBF_INSN_BGTZ; goto extract_fmt_beqz;
-      case 220 : itype = M32RBF_INSN_SETH; goto extract_fmt_seth;
+      case 132 : itype = M32RBF_INSN_CMPI; goto extract_sfmt_cmpi;
+      case 133 : itype = M32RBF_INSN_CMPUI; goto extract_sfmt_cmpi;
+      case 136 : itype = M32RBF_INSN_ADDV3; goto extract_sfmt_addv3;
+      case 138 : itype = M32RBF_INSN_ADD3; goto extract_sfmt_add3;
+      case 140 : itype = M32RBF_INSN_AND3; goto extract_sfmt_and3;
+      case 141 : itype = M32RBF_INSN_XOR3; goto extract_sfmt_and3;
+      case 142 : itype = M32RBF_INSN_OR3; goto extract_sfmt_or3;
+      case 144 : itype = M32RBF_INSN_DIV; goto extract_sfmt_div;
+      case 145 : itype = M32RBF_INSN_DIVU; goto extract_sfmt_div;
+      case 146 : itype = M32RBF_INSN_REM; goto extract_sfmt_div;
+      case 147 : itype = M32RBF_INSN_REMU; goto extract_sfmt_div;
+      case 152 : itype = M32RBF_INSN_SRL3; goto extract_sfmt_sll3;
+      case 154 : itype = M32RBF_INSN_SRA3; goto extract_sfmt_sll3;
+      case 156 : itype = M32RBF_INSN_SLL3; goto extract_sfmt_sll3;
+      case 159 : itype = M32RBF_INSN_LDI16; goto extract_sfmt_ldi16;
+      case 160 : itype = M32RBF_INSN_STB_D; goto extract_sfmt_stb_d;
+      case 162 : itype = M32RBF_INSN_STH_D; goto extract_sfmt_sth_d;
+      case 164 : itype = M32RBF_INSN_ST_D; goto extract_sfmt_st_d;
+      case 168 : itype = M32RBF_INSN_LDB_D; goto extract_sfmt_ld_d;
+      case 169 : itype = M32RBF_INSN_LDUB_D; goto extract_sfmt_ld_d;
+      case 170 : itype = M32RBF_INSN_LDH_D; goto extract_sfmt_ld_d;
+      case 171 : itype = M32RBF_INSN_LDUH_D; goto extract_sfmt_ld_d;
+      case 172 : itype = M32RBF_INSN_LD_D; goto extract_sfmt_ld_d;
+      case 176 : itype = M32RBF_INSN_BEQ; goto extract_sfmt_beq;
+      case 177 : itype = M32RBF_INSN_BNE; goto extract_sfmt_beq;
+      case 184 : itype = M32RBF_INSN_BEQZ; goto extract_sfmt_beqz;
+      case 185 : itype = M32RBF_INSN_BNEZ; goto extract_sfmt_beqz;
+      case 186 : itype = M32RBF_INSN_BLTZ; goto extract_sfmt_beqz;
+      case 187 : itype = M32RBF_INSN_BGEZ; goto extract_sfmt_beqz;
+      case 188 : itype = M32RBF_INSN_BLEZ; goto extract_sfmt_beqz;
+      case 189 : itype = M32RBF_INSN_BGTZ; goto extract_sfmt_beqz;
+      case 220 : itype = M32RBF_INSN_SETH; goto extract_sfmt_seth;
       case 224 : /* fall through */
       case 225 : /* fall through */
       case 226 : /* fall through */
@@ -456,7 +424,7 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc,
       case 236 : /* fall through */
       case 237 : /* fall through */
       case 238 : /* fall through */
-      case 239 : itype = M32RBF_INSN_LD24; goto extract_fmt_ld24;
+      case 239 : itype = M32RBF_INSN_LD24; goto extract_sfmt_ld24;
       case 240 : /* fall through */
       case 241 : /* fall through */
       case 242 : /* fall through */
@@ -477,49 +445,49 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc,
           unsigned int val = (((insn >> 8) & (15 << 0)));
           switch (val)
           {
-          case 12 : itype = M32RBF_INSN_BC24; goto extract_fmt_bc24;
-          case 13 : itype = M32RBF_INSN_BNC24; goto extract_fmt_bc24;
-          case 14 : itype = M32RBF_INSN_BL24; goto extract_fmt_bl24;
-          case 15 : itype = M32RBF_INSN_BRA24; goto extract_fmt_bra24;
-          default : itype = M32RBF_INSN_X_INVALID; goto extract_fmt_empty;
+          case 12 : itype = M32RBF_INSN_BC24; goto extract_sfmt_bc24;
+          case 13 : itype = M32RBF_INSN_BNC24; goto extract_sfmt_bc24;
+          case 14 : itype = M32RBF_INSN_BL24; goto extract_sfmt_bl24;
+          case 15 : itype = M32RBF_INSN_BRA24; goto extract_sfmt_bra24;
+          default : itype = M32RBF_INSN_X_INVALID; goto extract_sfmt_empty;
           }
         }
-      default : itype = M32RBF_INSN_X_INVALID; goto extract_fmt_empty;
+      default : itype = M32RBF_INSN_X_INVALID; goto extract_sfmt_empty;
       }
     }
   }
 
   /* The instruction has been decoded, now extract the fields.  */
 
- extract_fmt_empty:
+ extract_sfmt_empty:
   {
     const IDESC *idesc = &m32rbf_insn_data[itype];
     CGEN_INSN_INT insn = entire_insn;
 #define FLD(f) abuf->fields.fmt_empty.f
-  EXTRACT_IFMT_EMPTY_VARS /* */
 
-  EXTRACT_IFMT_EMPTY_CODE
 
   /* Record the fields for the semantic handler.  */
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_empty", (char *) 0));
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_empty", (char *) 0));
 
 #undef FLD
     return idesc;
   }
 
- extract_fmt_add:
+ extract_sfmt_add:
   {
     const IDESC *idesc = &m32rbf_insn_data[itype];
     CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.fmt_add.f
-  EXTRACT_IFMT_ADD_VARS /* f-op1 f-r1 f-op2 f-r2 */
+#define FLD(f) abuf->fields.sfmt_add.f
+    UINT f_r1;
+    UINT f_r2;
 
-  EXTRACT_IFMT_ADD_CODE
+    f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
+    f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
 
   /* Record the fields for the semantic handler.  */
   FLD (i_dr) = & CPU (h_gr)[f_r1];
   FLD (i_sr) = & CPU (h_gr)[f_r2];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_add", "dr 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, (char *) 0));
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_add", "dr 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, (char *) 0));
 
 #if WITH_PROFILE_MODEL_P
   /* Record the fields for profiling.  */
@@ -534,20 +502,24 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc,
     return idesc;
   }
 
- extract_fmt_add3:
+ extract_sfmt_add3:
   {
     const IDESC *idesc = &m32rbf_insn_data[itype];
     CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.fmt_add3.f
-  EXTRACT_IFMT_ADD3_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */
+#define FLD(f) abuf->fields.sfmt_add3.f
+    UINT f_r1;
+    UINT f_r2;
+    INT f_simm16;
 
-  EXTRACT_IFMT_ADD3_CODE
+    f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
+    f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4);
+    f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16);
 
   /* Record the fields for the semantic handler.  */
   FLD (f_simm16) = f_simm16;
   FLD (i_sr) = & CPU (h_gr)[f_r2];
   FLD (i_dr) = & CPU (h_gr)[f_r1];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_add3", "f_simm16 0x%x", 'x', f_simm16, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_add3", "f_simm16 0x%x", 'x', f_simm16, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
 
 #if WITH_PROFILE_MODEL_P
   /* Record the fields for profiling.  */
@@ -561,20 +533,24 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc,
     return idesc;
   }
 
- extract_fmt_and3:
+ extract_sfmt_and3:
   {
     const IDESC *idesc = &m32rbf_insn_data[itype];
     CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.fmt_and3.f
-  EXTRACT_IFMT_AND3_VARS /* f-op1 f-r1 f-op2 f-r2 f-uimm16 */
+#define FLD(f) abuf->fields.sfmt_and3.f
+    UINT f_r1;
+    UINT f_r2;
+    UINT f_uimm16;
 
-  EXTRACT_IFMT_AND3_CODE
+    f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
+    f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4);
+    f_uimm16 = EXTRACT_MSB0_UINT (insn, 32, 16, 16);
 
   /* Record the fields for the semantic handler.  */
   FLD (f_uimm16) = f_uimm16;
   FLD (i_sr) = & CPU (h_gr)[f_r2];
   FLD (i_dr) = & CPU (h_gr)[f_r1];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_and3", "f_uimm16 0x%x", 'x', f_uimm16, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_and3", "f_uimm16 0x%x", 'x', f_uimm16, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
 
 #if WITH_PROFILE_MODEL_P
   /* Record the fields for profiling.  */
@@ -588,20 +564,24 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc,
     return idesc;
   }
 
- extract_fmt_or3:
+ extract_sfmt_or3:
   {
     const IDESC *idesc = &m32rbf_insn_data[itype];
     CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.fmt_or3.f
-  EXTRACT_IFMT_OR3_VARS /* f-op1 f-r1 f-op2 f-r2 f-uimm16 */
+#define FLD(f) abuf->fields.sfmt_and3.f
+    UINT f_r1;
+    UINT f_r2;
+    UINT f_uimm16;
 
-  EXTRACT_IFMT_OR3_CODE
+    f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
+    f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4);
+    f_uimm16 = EXTRACT_MSB0_UINT (insn, 32, 16, 16);
 
   /* Record the fields for the semantic handler.  */
   FLD (f_uimm16) = f_uimm16;
   FLD (i_sr) = & CPU (h_gr)[f_r2];
   FLD (i_dr) = & CPU (h_gr)[f_r1];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_or3", "f_uimm16 0x%x", 'x', f_uimm16, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_or3", "f_uimm16 0x%x", 'x', f_uimm16, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
 
 #if WITH_PROFILE_MODEL_P
   /* Record the fields for profiling.  */
@@ -615,19 +595,21 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc,
     return idesc;
   }
 
- extract_fmt_addi:
+ extract_sfmt_addi:
   {
     const IDESC *idesc = &m32rbf_insn_data[itype];
     CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.fmt_addi.f
-  EXTRACT_IFMT_ADDI_VARS /* f-op1 f-r1 f-simm8 */
+#define FLD(f) abuf->fields.sfmt_addi.f
+    UINT f_r1;
+    INT f_simm8;
 
-  EXTRACT_IFMT_ADDI_CODE
+    f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
+    f_simm8 = EXTRACT_MSB0_INT (insn, 16, 8, 8);
 
   /* Record the fields for the semantic handler.  */
   FLD (f_simm8) = f_simm8;
   FLD (i_dr) = & CPU (h_gr)[f_r1];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_addi", "f_simm8 0x%x", 'x', f_simm8, "dr 0x%x", 'x', f_r1, (char *) 0));
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_addi", "f_simm8 0x%x", 'x', f_simm8, "dr 0x%x", 'x', f_r1, (char *) 0));
 
 #if WITH_PROFILE_MODEL_P
   /* Record the fields for profiling.  */
@@ -641,19 +623,21 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc,
     return idesc;
   }
 
- extract_fmt_addv:
+ extract_sfmt_addv:
   {
     const IDESC *idesc = &m32rbf_insn_data[itype];
     CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.fmt_addv.f
-  EXTRACT_IFMT_ADD_VARS /* f-op1 f-r1 f-op2 f-r2 */
+#define FLD(f) abuf->fields.sfmt_add.f
+    UINT f_r1;
+    UINT f_r2;
 
-  EXTRACT_IFMT_ADD_CODE
+    f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
+    f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
 
   /* Record the fields for the semantic handler.  */
   FLD (i_dr) = & CPU (h_gr)[f_r1];
   FLD (i_sr) = & CPU (h_gr)[f_r2];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_addv", "dr 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, (char *) 0));
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_addv", "dr 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, (char *) 0));
 
 #if WITH_PROFILE_MODEL_P
   /* Record the fields for profiling.  */
@@ -668,20 +652,24 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc,
     return idesc;
   }
 
- extract_fmt_addv3:
+ extract_sfmt_addv3:
   {
     const IDESC *idesc = &m32rbf_insn_data[itype];
     CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.fmt_addv3.f
-  EXTRACT_IFMT_ADDV3_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */
+#define FLD(f) abuf->fields.sfmt_add3.f
+    UINT f_r1;
+    UINT f_r2;
+    INT f_simm16;
 
-  EXTRACT_IFMT_ADDV3_CODE
+    f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
+    f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4);
+    f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16);
 
   /* Record the fields for the semantic handler.  */
   FLD (f_simm16) = f_simm16;
   FLD (i_sr) = & CPU (h_gr)[f_r2];
   FLD (i_dr) = & CPU (h_gr)[f_r1];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_addv3", "f_simm16 0x%x", 'x', f_simm16, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_addv3", "f_simm16 0x%x", 'x', f_simm16, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
 
 #if WITH_PROFILE_MODEL_P
   /* Record the fields for profiling.  */
@@ -695,19 +683,21 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc,
     return idesc;
   }
 
- extract_fmt_addx:
+ extract_sfmt_addx:
   {
     const IDESC *idesc = &m32rbf_insn_data[itype];
     CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.fmt_addx.f
-  EXTRACT_IFMT_ADD_VARS /* f-op1 f-r1 f-op2 f-r2 */
+#define FLD(f) abuf->fields.sfmt_add.f
+    UINT f_r1;
+    UINT f_r2;
 
-  EXTRACT_IFMT_ADD_CODE
+    f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
+    f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
 
   /* Record the fields for the semantic handler.  */
   FLD (i_dr) = & CPU (h_gr)[f_r1];
   FLD (i_sr) = & CPU (h_gr)[f_r2];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_addx", "dr 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, (char *) 0));
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_addx", "dr 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, (char *) 0));
 
 #if WITH_PROFILE_MODEL_P
   /* Record the fields for profiling.  */
@@ -722,19 +712,18 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc,
     return idesc;
   }
 
- extract_fmt_bc8:
+ extract_sfmt_bc8:
   {
     const IDESC *idesc = &m32rbf_insn_data[itype];
     CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.cti.fields.fmt_bc8.f
-  EXTRACT_IFMT_BC8_VARS /* f-op1 f-r1 f-disp8 */
+#define FLD(f) abuf->fields.sfmt_bl8.f
+    SI f_disp8;
 
-  EXTRACT_IFMT_BC8_CODE
+    f_disp8 = ((((EXTRACT_MSB0_INT (insn, 16, 8, 8)) << (2))) + (((pc) & (-4))));
 
   /* Record the fields for the semantic handler.  */
   FLD (i_disp8) = f_disp8;
-  SEM_BRANCH_INIT_EXTRACT (abuf);
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_bc8", "disp8 0x%x", 'x', f_disp8, (char *) 0));
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bc8", "disp8 0x%x", 'x', f_disp8, (char *) 0));
 
 #if WITH_PROFILE_MODEL_P
   /* Record the fields for profiling.  */
@@ -746,19 +735,18 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc,
     return idesc;
   }
 
- extract_fmt_bc24:
+ extract_sfmt_bc24:
   {
     const IDESC *idesc = &m32rbf_insn_data[itype];
     CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.cti.fields.fmt_bc24.f
-  EXTRACT_IFMT_BC24_VARS /* f-op1 f-r1 f-disp24 */
+#define FLD(f) abuf->fields.sfmt_bl24.f
+    SI f_disp24;
 
-  EXTRACT_IFMT_BC24_CODE
+    f_disp24 = ((((EXTRACT_MSB0_INT (insn, 32, 8, 24)) << (2))) + (pc));
 
   /* Record the fields for the semantic handler.  */
   FLD (i_disp24) = f_disp24;
-  SEM_BRANCH_INIT_EXTRACT (abuf);
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_bc24", "disp24 0x%x", 'x', f_disp24, (char *) 0));
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bc24", "disp24 0x%x", 'x', f_disp24, (char *) 0));
 
 #if WITH_PROFILE_MODEL_P
   /* Record the fields for profiling.  */
@@ -770,21 +758,24 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc,
     return idesc;
   }
 
- extract_fmt_beq:
+ extract_sfmt_beq:
   {
     const IDESC *idesc = &m32rbf_insn_data[itype];
     CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.cti.fields.fmt_beq.f
-  EXTRACT_IFMT_BEQ_VARS /* f-op1 f-r1 f-op2 f-r2 f-disp16 */
+#define FLD(f) abuf->fields.sfmt_beq.f
+    UINT f_r1;
+    UINT f_r2;
+    SI f_disp16;
 
-  EXTRACT_IFMT_BEQ_CODE
+    f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
+    f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4);
+    f_disp16 = ((((EXTRACT_MSB0_INT (insn, 32, 16, 16)) << (2))) + (pc));
 
   /* Record the fields for the semantic handler.  */
   FLD (i_disp16) = f_disp16;
   FLD (i_src1) = & CPU (h_gr)[f_r1];
   FLD (i_src2) = & CPU (h_gr)[f_r2];
-  SEM_BRANCH_INIT_EXTRACT (abuf);
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_beq", "disp16 0x%x", 'x', f_disp16, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_beq", "disp16 0x%x", 'x', f_disp16, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
 
 #if WITH_PROFILE_MODEL_P
   /* Record the fields for profiling.  */
@@ -798,20 +789,21 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc,
     return idesc;
   }
 
- extract_fmt_beqz:
+ extract_sfmt_beqz:
   {
     const IDESC *idesc = &m32rbf_insn_data[itype];
     CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.cti.fields.fmt_beqz.f
-  EXTRACT_IFMT_BEQZ_VARS /* f-op1 f-r1 f-op2 f-r2 f-disp16 */
+#define FLD(f) abuf->fields.sfmt_beq.f
+    UINT f_r2;
+    SI f_disp16;
 
-  EXTRACT_IFMT_BEQZ_CODE
+    f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4);
+    f_disp16 = ((((EXTRACT_MSB0_INT (insn, 32, 16, 16)) << (2))) + (pc));
 
   /* Record the fields for the semantic handler.  */
   FLD (i_disp16) = f_disp16;
   FLD (i_src2) = & CPU (h_gr)[f_r2];
-  SEM_BRANCH_INIT_EXTRACT (abuf);
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_beqz", "disp16 0x%x", 'x', f_disp16, "src2 0x%x", 'x', f_r2, (char *) 0));
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_beqz", "disp16 0x%x", 'x', f_disp16, "src2 0x%x", 'x', f_r2, (char *) 0));
 
 #if WITH_PROFILE_MODEL_P
   /* Record the fields for profiling.  */
@@ -824,19 +816,18 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc,
     return idesc;
   }
 
- extract_fmt_bl8:
+ extract_sfmt_bl8:
   {
     const IDESC *idesc = &m32rbf_insn_data[itype];
     CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.cti.fields.fmt_bl8.f
-  EXTRACT_IFMT_BC8_VARS /* f-op1 f-r1 f-disp8 */
+#define FLD(f) abuf->fields.sfmt_bl8.f
+    SI f_disp8;
 
-  EXTRACT_IFMT_BC8_CODE
+    f_disp8 = ((((EXTRACT_MSB0_INT (insn, 16, 8, 8)) << (2))) + (((pc) & (-4))));
 
   /* Record the fields for the semantic handler.  */
   FLD (i_disp8) = f_disp8;
-  SEM_BRANCH_INIT_EXTRACT (abuf);
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_bl8", "disp8 0x%x", 'x', f_disp8, (char *) 0));
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bl8", "disp8 0x%x", 'x', f_disp8, (char *) 0));
 
 #if WITH_PROFILE_MODEL_P
   /* Record the fields for profiling.  */
@@ -849,19 +840,18 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc,
     return idesc;
   }
 
- extract_fmt_bl24:
+ extract_sfmt_bl24:
   {
     const IDESC *idesc = &m32rbf_insn_data[itype];
     CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.cti.fields.fmt_bl24.f
-  EXTRACT_IFMT_BC24_VARS /* f-op1 f-r1 f-disp24 */
+#define FLD(f) abuf->fields.sfmt_bl24.f
+    SI f_disp24;
 
-  EXTRACT_IFMT_BC24_CODE
+    f_disp24 = ((((EXTRACT_MSB0_INT (insn, 32, 8, 24)) << (2))) + (pc));
 
   /* Record the fields for the semantic handler.  */
   FLD (i_disp24) = f_disp24;
-  SEM_BRANCH_INIT_EXTRACT (abuf);
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_bl24", "disp24 0x%x", 'x', f_disp24, (char *) 0));
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bl24", "disp24 0x%x", 'x', f_disp24, (char *) 0));
 
 #if WITH_PROFILE_MODEL_P
   /* Record the fields for profiling.  */
@@ -874,19 +864,18 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc,
     return idesc;
   }
 
- extract_fmt_bra8:
+ extract_sfmt_bra8:
   {
     const IDESC *idesc = &m32rbf_insn_data[itype];
     CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.cti.fields.fmt_bra8.f
-  EXTRACT_IFMT_BC8_VARS /* f-op1 f-r1 f-disp8 */
+#define FLD(f) abuf->fields.sfmt_bl8.f
+    SI f_disp8;
 
-  EXTRACT_IFMT_BC8_CODE
+    f_disp8 = ((((EXTRACT_MSB0_INT (insn, 16, 8, 8)) << (2))) + (((pc) & (-4))));
 
   /* Record the fields for the semantic handler.  */
   FLD (i_disp8) = f_disp8;
-  SEM_BRANCH_INIT_EXTRACT (abuf);
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_bra8", "disp8 0x%x", 'x', f_disp8, (char *) 0));
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bra8", "disp8 0x%x", 'x', f_disp8, (char *) 0));
 
 #if WITH_PROFILE_MODEL_P
   /* Record the fields for profiling.  */
@@ -898,19 +887,18 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc,
     return idesc;
   }
 
- extract_fmt_bra24:
+ extract_sfmt_bra24:
   {
     const IDESC *idesc = &m32rbf_insn_data[itype];
     CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.cti.fields.fmt_bra24.f
-  EXTRACT_IFMT_BC24_VARS /* f-op1 f-r1 f-disp24 */
+#define FLD(f) abuf->fields.sfmt_bl24.f
+    SI f_disp24;
 
-  EXTRACT_IFMT_BC24_CODE
+    f_disp24 = ((((EXTRACT_MSB0_INT (insn, 32, 8, 24)) << (2))) + (pc));
 
   /* Record the fields for the semantic handler.  */
   FLD (i_disp24) = f_disp24;
-  SEM_BRANCH_INIT_EXTRACT (abuf);
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_bra24", "disp24 0x%x", 'x', f_disp24, (char *) 0));
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bra24", "disp24 0x%x", 'x', f_disp24, (char *) 0));
 
 #if WITH_PROFILE_MODEL_P
   /* Record the fields for profiling.  */
@@ -922,19 +910,21 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc,
     return idesc;
   }
 
- extract_fmt_cmp:
+ extract_sfmt_cmp:
   {
     const IDESC *idesc = &m32rbf_insn_data[itype];
     CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.fmt_cmp.f
-  EXTRACT_IFMT_CMP_VARS /* f-op1 f-r1 f-op2 f-r2 */
+#define FLD(f) abuf->fields.sfmt_st_plus.f
+    UINT f_r1;
+    UINT f_r2;
 
-  EXTRACT_IFMT_CMP_CODE
+    f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
+    f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
 
   /* Record the fields for the semantic handler.  */
   FLD (i_src1) = & CPU (h_gr)[f_r1];
   FLD (i_src2) = & CPU (h_gr)[f_r2];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_cmp", "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_cmp", "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
 
 #if WITH_PROFILE_MODEL_P
   /* Record the fields for profiling.  */
@@ -948,19 +938,21 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc,
     return idesc;
   }
 
- extract_fmt_cmpi:
+ extract_sfmt_cmpi:
   {
     const IDESC *idesc = &m32rbf_insn_data[itype];
     CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.fmt_cmpi.f
-  EXTRACT_IFMT_CMPI_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */
+#define FLD(f) abuf->fields.sfmt_st_d.f
+    UINT f_r2;
+    INT f_simm16;
 
-  EXTRACT_IFMT_CMPI_CODE
+    f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4);
+    f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16);
 
   /* Record the fields for the semantic handler.  */
   FLD (f_simm16) = f_simm16;
   FLD (i_src2) = & CPU (h_gr)[f_r2];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_cmpi", "f_simm16 0x%x", 'x', f_simm16, "src2 0x%x", 'x', f_r2, (char *) 0));
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_cmpi", "f_simm16 0x%x", 'x', f_simm16, "src2 0x%x", 'x', f_r2, (char *) 0));
 
 #if WITH_PROFILE_MODEL_P
   /* Record the fields for profiling.  */
@@ -973,19 +965,21 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc,
     return idesc;
   }
 
- extract_fmt_div:
+ extract_sfmt_div:
   {
     const IDESC *idesc = &m32rbf_insn_data[itype];
     CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.fmt_div.f
-  EXTRACT_IFMT_DIV_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */
+#define FLD(f) abuf->fields.sfmt_add.f
+    UINT f_r1;
+    UINT f_r2;
 
-  EXTRACT_IFMT_DIV_CODE
+    f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
+    f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4);
 
   /* Record the fields for the semantic handler.  */
   FLD (i_dr) = & CPU (h_gr)[f_r1];
   FLD (i_sr) = & CPU (h_gr)[f_r2];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_div", "dr 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, (char *) 0));
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_div", "dr 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, (char *) 0));
 
 #if WITH_PROFILE_MODEL_P
   /* Record the fields for profiling.  */
@@ -1000,19 +994,18 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc,
     return idesc;
   }
 
- extract_fmt_jl:
+ extract_sfmt_jl:
   {
     const IDESC *idesc = &m32rbf_insn_data[itype];
     CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.cti.fields.fmt_jl.f
-  EXTRACT_IFMT_JL_VARS /* f-op1 f-r1 f-op2 f-r2 */
+#define FLD(f) abuf->fields.sfmt_jl.f
+    UINT f_r2;
 
-  EXTRACT_IFMT_JL_CODE
+    f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
 
   /* Record the fields for the semantic handler.  */
   FLD (i_sr) = & CPU (h_gr)[f_r2];
-  SEM_BRANCH_INIT_EXTRACT (abuf);
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_jl", "sr 0x%x", 'x', f_r2, (char *) 0));
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_jl", "sr 0x%x", 'x', f_r2, (char *) 0));
 
 #if WITH_PROFILE_MODEL_P
   /* Record the fields for profiling.  */
@@ -1026,97 +1019,45 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc,
     return idesc;
   }
 
- extract_fmt_jmp:
-  {
-    const IDESC *idesc = &m32rbf_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.cti.fields.fmt_jmp.f
-  EXTRACT_IFMT_JL_VARS /* f-op1 f-r1 f-op2 f-r2 */
-
-  EXTRACT_IFMT_JL_CODE
-
-  /* Record the fields for the semantic handler.  */
-  FLD (i_sr) = & CPU (h_gr)[f_r2];
-  SEM_BRANCH_INIT_EXTRACT (abuf);
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_jmp", "sr 0x%x", 'x', f_r2, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      FLD (in_sr) = f_r2;
-    }
-#endif
-#undef FLD
-    return idesc;
-  }
-
- extract_fmt_ld:
-  {
-    const IDESC *idesc = &m32rbf_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.fmt_ld.f
-  EXTRACT_IFMT_ADD_VARS /* f-op1 f-r1 f-op2 f-r2 */
-
-  EXTRACT_IFMT_ADD_CODE
-
-  /* Record the fields for the semantic handler.  */
-  FLD (i_sr) = & CPU (h_gr)[f_r2];
-  FLD (i_dr) = & CPU (h_gr)[f_r1];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ld", "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      FLD (in_sr) = f_r2;
-      FLD (out_dr) = f_r1;
-    }
-#endif
-#undef FLD
-    return idesc;
-  }
-
- extract_fmt_ld_d:
+ extract_sfmt_jmp:
   {
     const IDESC *idesc = &m32rbf_insn_data[itype];
     CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.fmt_ld_d.f
-  EXTRACT_IFMT_ADD3_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */
+#define FLD(f) abuf->fields.sfmt_mvtc.f
+    UINT f_r2;
 
-  EXTRACT_IFMT_ADD3_CODE
+    f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
 
   /* Record the fields for the semantic handler.  */
-  FLD (f_simm16) = f_simm16;
   FLD (i_sr) = & CPU (h_gr)[f_r2];
-  FLD (i_dr) = & CPU (h_gr)[f_r1];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ld_d", "f_simm16 0x%x", 'x', f_simm16, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_jmp", "sr 0x%x", 'x', f_r2, (char *) 0));
 
 #if WITH_PROFILE_MODEL_P
   /* Record the fields for profiling.  */
   if (PROFILE_MODEL_P (current_cpu))
     {
       FLD (in_sr) = f_r2;
-      FLD (out_dr) = f_r1;
     }
 #endif
 #undef FLD
     return idesc;
   }
 
- extract_fmt_ldb:
+ extract_sfmt_ld:
   {
     const IDESC *idesc = &m32rbf_insn_data[itype];
     CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.fmt_ldb.f
-  EXTRACT_IFMT_ADD_VARS /* f-op1 f-r1 f-op2 f-r2 */
+#define FLD(f) abuf->fields.sfmt_ld_plus.f
+    UINT f_r1;
+    UINT f_r2;
 
-  EXTRACT_IFMT_ADD_CODE
+    f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
+    f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
 
   /* Record the fields for the semantic handler.  */
   FLD (i_sr) = & CPU (h_gr)[f_r2];
   FLD (i_dr) = & CPU (h_gr)[f_r1];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ldb", "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ld", "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
 
 #if WITH_PROFILE_MODEL_P
   /* Record the fields for profiling.  */
@@ -1130,20 +1071,24 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc,
     return idesc;
   }
 
- extract_fmt_ldb_d:
+ extract_sfmt_ld_d:
   {
     const IDESC *idesc = &m32rbf_insn_data[itype];
     CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.fmt_ldb_d.f
-  EXTRACT_IFMT_ADD3_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */
+#define FLD(f) abuf->fields.sfmt_add3.f
+    UINT f_r1;
+    UINT f_r2;
+    INT f_simm16;
 
-  EXTRACT_IFMT_ADD3_CODE
+    f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
+    f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4);
+    f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16);
 
   /* Record the fields for the semantic handler.  */
   FLD (f_simm16) = f_simm16;
   FLD (i_sr) = & CPU (h_gr)[f_r2];
   FLD (i_dr) = & CPU (h_gr)[f_r1];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ldb_d", "f_simm16 0x%x", 'x', f_simm16, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ld_d", "f_simm16 0x%x", 'x', f_simm16, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
 
 #if WITH_PROFILE_MODEL_P
   /* Record the fields for profiling.  */
@@ -1157,72 +1102,21 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc,
     return idesc;
   }
 
- extract_fmt_ldh:
+ extract_sfmt_ld_plus:
   {
     const IDESC *idesc = &m32rbf_insn_data[itype];
     CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.fmt_ldh.f
-  EXTRACT_IFMT_ADD_VARS /* f-op1 f-r1 f-op2 f-r2 */
+#define FLD(f) abuf->fields.sfmt_ld_plus.f
+    UINT f_r1;
+    UINT f_r2;
 
-  EXTRACT_IFMT_ADD_CODE
+    f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
+    f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
 
   /* Record the fields for the semantic handler.  */
   FLD (i_sr) = & CPU (h_gr)[f_r2];
   FLD (i_dr) = & CPU (h_gr)[f_r1];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ldh", "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      FLD (in_sr) = f_r2;
-      FLD (out_dr) = f_r1;
-    }
-#endif
-#undef FLD
-    return idesc;
-  }
-
- extract_fmt_ldh_d:
-  {
-    const IDESC *idesc = &m32rbf_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.fmt_ldh_d.f
-  EXTRACT_IFMT_ADD3_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */
-
-  EXTRACT_IFMT_ADD3_CODE
-
-  /* Record the fields for the semantic handler.  */
-  FLD (f_simm16) = f_simm16;
-  FLD (i_sr) = & CPU (h_gr)[f_r2];
-  FLD (i_dr) = & CPU (h_gr)[f_r1];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ldh_d", "f_simm16 0x%x", 'x', f_simm16, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
-
-#if WITH_PROFILE_MODEL_P
-  /* Record the fields for profiling.  */
-  if (PROFILE_MODEL_P (current_cpu))
-    {
-      FLD (in_sr) = f_r2;
-      FLD (out_dr) = f_r1;
-    }
-#endif
-#undef FLD
-    return idesc;
-  }
-
- extract_fmt_ld_plus:
-  {
-    const IDESC *idesc = &m32rbf_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.fmt_ld_plus.f
-  EXTRACT_IFMT_ADD_VARS /* f-op1 f-r1 f-op2 f-r2 */
-
-  EXTRACT_IFMT_ADD_CODE
-
-  /* Record the fields for the semantic handler.  */
-  FLD (i_sr) = & CPU (h_gr)[f_r2];
-  FLD (i_dr) = & CPU (h_gr)[f_r1];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ld_plus", "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ld_plus", "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
 
 #if WITH_PROFILE_MODEL_P
   /* Record the fields for profiling.  */
@@ -1237,19 +1131,21 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc,
     return idesc;
   }
 
- extract_fmt_ld24:
+ extract_sfmt_ld24:
   {
     const IDESC *idesc = &m32rbf_insn_data[itype];
     CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.fmt_ld24.f
-  EXTRACT_IFMT_LD24_VARS /* f-op1 f-r1 f-uimm24 */
+#define FLD(f) abuf->fields.sfmt_ld24.f
+    UINT f_r1;
+    UINT f_uimm24;
 
-  EXTRACT_IFMT_LD24_CODE
+    f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
+    f_uimm24 = EXTRACT_MSB0_UINT (insn, 32, 8, 24);
 
   /* Record the fields for the semantic handler.  */
   FLD (i_uimm24) = f_uimm24;
   FLD (i_dr) = & CPU (h_gr)[f_r1];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ld24", "uimm24 0x%x", 'x', f_uimm24, "dr 0x%x", 'x', f_r1, (char *) 0));
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ld24", "uimm24 0x%x", 'x', f_uimm24, "dr 0x%x", 'x', f_r1, (char *) 0));
 
 #if WITH_PROFILE_MODEL_P
   /* Record the fields for profiling.  */
@@ -1262,19 +1158,21 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc,
     return idesc;
   }
 
- extract_fmt_ldi8:
+ extract_sfmt_ldi8:
   {
     const IDESC *idesc = &m32rbf_insn_data[itype];
     CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.fmt_ldi8.f
-  EXTRACT_IFMT_ADDI_VARS /* f-op1 f-r1 f-simm8 */
+#define FLD(f) abuf->fields.sfmt_addi.f
+    UINT f_r1;
+    INT f_simm8;
 
-  EXTRACT_IFMT_ADDI_CODE
+    f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
+    f_simm8 = EXTRACT_MSB0_INT (insn, 16, 8, 8);
 
   /* Record the fields for the semantic handler.  */
   FLD (f_simm8) = f_simm8;
   FLD (i_dr) = & CPU (h_gr)[f_r1];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ldi8", "f_simm8 0x%x", 'x', f_simm8, "dr 0x%x", 'x', f_r1, (char *) 0));
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldi8", "f_simm8 0x%x", 'x', f_simm8, "dr 0x%x", 'x', f_r1, (char *) 0));
 
 #if WITH_PROFILE_MODEL_P
   /* Record the fields for profiling.  */
@@ -1287,19 +1185,21 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc,
     return idesc;
   }
 
- extract_fmt_ldi16:
+ extract_sfmt_ldi16:
   {
     const IDESC *idesc = &m32rbf_insn_data[itype];
     CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.fmt_ldi16.f
-  EXTRACT_IFMT_LDI16_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */
+#define FLD(f) abuf->fields.sfmt_add3.f
+    UINT f_r1;
+    INT f_simm16;
 
-  EXTRACT_IFMT_LDI16_CODE
+    f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
+    f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16);
 
   /* Record the fields for the semantic handler.  */
   FLD (f_simm16) = f_simm16;
   FLD (i_dr) = & CPU (h_gr)[f_r1];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ldi16", "f_simm16 0x%x", 'x', f_simm16, "dr 0x%x", 'x', f_r1, (char *) 0));
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldi16", "f_simm16 0x%x", 'x', f_simm16, "dr 0x%x", 'x', f_r1, (char *) 0));
 
 #if WITH_PROFILE_MODEL_P
   /* Record the fields for profiling.  */
@@ -1312,19 +1212,21 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc,
     return idesc;
   }
 
- extract_fmt_lock:
+ extract_sfmt_lock:
   {
     const IDESC *idesc = &m32rbf_insn_data[itype];
     CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.fmt_lock.f
-  EXTRACT_IFMT_ADD_VARS /* f-op1 f-r1 f-op2 f-r2 */
+#define FLD(f) abuf->fields.sfmt_ld_plus.f
+    UINT f_r1;
+    UINT f_r2;
 
-  EXTRACT_IFMT_ADD_CODE
+    f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
+    f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
 
   /* Record the fields for the semantic handler.  */
   FLD (i_sr) = & CPU (h_gr)[f_r2];
   FLD (i_dr) = & CPU (h_gr)[f_r1];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_lock", "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_lock", "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
 
 #if WITH_PROFILE_MODEL_P
   /* Record the fields for profiling.  */
@@ -1338,19 +1240,21 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc,
     return idesc;
   }
 
- extract_fmt_machi:
+ extract_sfmt_machi:
   {
     const IDESC *idesc = &m32rbf_insn_data[itype];
     CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.fmt_machi.f
-  EXTRACT_IFMT_CMP_VARS /* f-op1 f-r1 f-op2 f-r2 */
+#define FLD(f) abuf->fields.sfmt_st_plus.f
+    UINT f_r1;
+    UINT f_r2;
 
-  EXTRACT_IFMT_CMP_CODE
+    f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
+    f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
 
   /* Record the fields for the semantic handler.  */
   FLD (i_src1) = & CPU (h_gr)[f_r1];
   FLD (i_src2) = & CPU (h_gr)[f_r2];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_machi", "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_machi", "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
 
 #if WITH_PROFILE_MODEL_P
   /* Record the fields for profiling.  */
@@ -1364,19 +1268,21 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc,
     return idesc;
   }
 
- extract_fmt_mulhi:
+ extract_sfmt_mulhi:
   {
     const IDESC *idesc = &m32rbf_insn_data[itype];
     CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.fmt_mulhi.f
-  EXTRACT_IFMT_CMP_VARS /* f-op1 f-r1 f-op2 f-r2 */
+#define FLD(f) abuf->fields.sfmt_st_plus.f
+    UINT f_r1;
+    UINT f_r2;
 
-  EXTRACT_IFMT_CMP_CODE
+    f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
+    f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
 
   /* Record the fields for the semantic handler.  */
   FLD (i_src1) = & CPU (h_gr)[f_r1];
   FLD (i_src2) = & CPU (h_gr)[f_r2];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_mulhi", "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mulhi", "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
 
 #if WITH_PROFILE_MODEL_P
   /* Record the fields for profiling.  */
@@ -1390,19 +1296,21 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc,
     return idesc;
   }
 
- extract_fmt_mv:
+ extract_sfmt_mv:
   {
     const IDESC *idesc = &m32rbf_insn_data[itype];
     CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.fmt_mv.f
-  EXTRACT_IFMT_ADD_VARS /* f-op1 f-r1 f-op2 f-r2 */
+#define FLD(f) abuf->fields.sfmt_ld_plus.f
+    UINT f_r1;
+    UINT f_r2;
 
-  EXTRACT_IFMT_ADD_CODE
+    f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
+    f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
 
   /* Record the fields for the semantic handler.  */
   FLD (i_sr) = & CPU (h_gr)[f_r2];
   FLD (i_dr) = & CPU (h_gr)[f_r1];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_mv", "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mv", "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
 
 #if WITH_PROFILE_MODEL_P
   /* Record the fields for profiling.  */
@@ -1416,18 +1324,18 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc,
     return idesc;
   }
 
- extract_fmt_mvfachi:
+ extract_sfmt_mvfachi:
   {
     const IDESC *idesc = &m32rbf_insn_data[itype];
     CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.fmt_mvfachi.f
-  EXTRACT_IFMT_MVFACHI_VARS /* f-op1 f-r1 f-op2 f-r2 */
+#define FLD(f) abuf->fields.sfmt_seth.f
+    UINT f_r1;
 
-  EXTRACT_IFMT_MVFACHI_CODE
+    f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
 
   /* Record the fields for the semantic handler.  */
   FLD (i_dr) = & CPU (h_gr)[f_r1];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_mvfachi", "dr 0x%x", 'x', f_r1, (char *) 0));
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mvfachi", "dr 0x%x", 'x', f_r1, (char *) 0));
 
 #if WITH_PROFILE_MODEL_P
   /* Record the fields for profiling.  */
@@ -1440,19 +1348,21 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc,
     return idesc;
   }
 
- extract_fmt_mvfc:
+ extract_sfmt_mvfc:
   {
     const IDESC *idesc = &m32rbf_insn_data[itype];
     CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.fmt_mvfc.f
-  EXTRACT_IFMT_MVFC_VARS /* f-op1 f-r1 f-op2 f-r2 */
+#define FLD(f) abuf->fields.sfmt_mvfc.f
+    UINT f_r1;
+    UINT f_r2;
 
-  EXTRACT_IFMT_MVFC_CODE
+    f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
+    f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
 
   /* Record the fields for the semantic handler.  */
   FLD (f_r2) = f_r2;
   FLD (i_dr) = & CPU (h_gr)[f_r1];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_mvfc", "f_r2 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mvfc", "f_r2 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
 
 #if WITH_PROFILE_MODEL_P
   /* Record the fields for profiling.  */
@@ -1465,18 +1375,18 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc,
     return idesc;
   }
 
- extract_fmt_mvtachi:
+ extract_sfmt_mvtachi:
   {
     const IDESC *idesc = &m32rbf_insn_data[itype];
     CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.fmt_mvtachi.f
-  EXTRACT_IFMT_MVTACHI_VARS /* f-op1 f-r1 f-op2 f-r2 */
+#define FLD(f) abuf->fields.sfmt_st_plus.f
+    UINT f_r1;
 
-  EXTRACT_IFMT_MVTACHI_CODE
+    f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
 
   /* Record the fields for the semantic handler.  */
   FLD (i_src1) = & CPU (h_gr)[f_r1];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_mvtachi", "src1 0x%x", 'x', f_r1, (char *) 0));
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mvtachi", "src1 0x%x", 'x', f_r1, (char *) 0));
 
 #if WITH_PROFILE_MODEL_P
   /* Record the fields for profiling.  */
@@ -1489,19 +1399,21 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc,
     return idesc;
   }
 
- extract_fmt_mvtc:
+ extract_sfmt_mvtc:
   {
     const IDESC *idesc = &m32rbf_insn_data[itype];
     CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.fmt_mvtc.f
-  EXTRACT_IFMT_MVTC_VARS /* f-op1 f-r1 f-op2 f-r2 */
+#define FLD(f) abuf->fields.sfmt_mvtc.f
+    UINT f_r1;
+    UINT f_r2;
 
-  EXTRACT_IFMT_MVTC_CODE
+    f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
+    f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
 
   /* Record the fields for the semantic handler.  */
   FLD (f_r1) = f_r1;
   FLD (i_sr) = & CPU (h_gr)[f_r2];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_mvtc", "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, (char *) 0));
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mvtc", "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, (char *) 0));
 
 #if WITH_PROFILE_MODEL_P
   /* Record the fields for profiling.  */
@@ -1514,50 +1426,43 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc,
     return idesc;
   }
 
- extract_fmt_nop:
+ extract_sfmt_nop:
   {
     const IDESC *idesc = &m32rbf_insn_data[itype];
     CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.fmt_nop.f
-  EXTRACT_IFMT_NOP_VARS /* f-op1 f-r1 f-op2 f-r2 */
+#define FLD(f) abuf->fields.fmt_empty.f
 
-  EXTRACT_IFMT_NOP_CODE
 
   /* Record the fields for the semantic handler.  */
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_nop", (char *) 0));
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_nop", (char *) 0));
 
 #undef FLD
     return idesc;
   }
 
- extract_fmt_rac:
+ extract_sfmt_rac:
   {
     const IDESC *idesc = &m32rbf_insn_data[itype];
     CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.fmt_rac.f
-  EXTRACT_IFMT_NOP_VARS /* f-op1 f-r1 f-op2 f-r2 */
+#define FLD(f) abuf->fields.fmt_empty.f
 
-  EXTRACT_IFMT_NOP_CODE
 
   /* Record the fields for the semantic handler.  */
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_rac", (char *) 0));
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_rac", (char *) 0));
 
 #undef FLD
     return idesc;
   }
 
- extract_fmt_rte:
+ extract_sfmt_rte:
   {
     const IDESC *idesc = &m32rbf_insn_data[itype];
     CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.cti.fields.fmt_rte.f
-  EXTRACT_IFMT_NOP_VARS /* f-op1 f-r1 f-op2 f-r2 */
+#define FLD(f) abuf->fields.fmt_empty.f
 
-  EXTRACT_IFMT_NOP_CODE
 
   /* Record the fields for the semantic handler.  */
-  SEM_BRANCH_INIT_EXTRACT (abuf);
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_rte", (char *) 0));
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_rte", (char *) 0));
 
 #if WITH_PROFILE_MODEL_P
   /* Record the fields for profiling.  */
@@ -1569,19 +1474,21 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc,
     return idesc;
   }
 
- extract_fmt_seth:
+ extract_sfmt_seth:
   {
     const IDESC *idesc = &m32rbf_insn_data[itype];
     CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.fmt_seth.f
-  EXTRACT_IFMT_SETH_VARS /* f-op1 f-r1 f-op2 f-r2 f-hi16 */
+#define FLD(f) abuf->fields.sfmt_seth.f
+    UINT f_r1;
+    UINT f_hi16;
 
-  EXTRACT_IFMT_SETH_CODE
+    f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
+    f_hi16 = EXTRACT_MSB0_UINT (insn, 32, 16, 16);
 
   /* Record the fields for the semantic handler.  */
   FLD (f_hi16) = f_hi16;
   FLD (i_dr) = & CPU (h_gr)[f_r1];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_seth", "f_hi16 0x%x", 'x', f_hi16, "dr 0x%x", 'x', f_r1, (char *) 0));
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_seth", "f_hi16 0x%x", 'x', f_hi16, "dr 0x%x", 'x', f_r1, (char *) 0));
 
 #if WITH_PROFILE_MODEL_P
   /* Record the fields for profiling.  */
@@ -1594,20 +1501,24 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc,
     return idesc;
   }
 
- extract_fmt_sll3:
+ extract_sfmt_sll3:
   {
     const IDESC *idesc = &m32rbf_insn_data[itype];
     CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.fmt_sll3.f
-  EXTRACT_IFMT_ADDV3_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */
+#define FLD(f) abuf->fields.sfmt_add3.f
+    UINT f_r1;
+    UINT f_r2;
+    INT f_simm16;
 
-  EXTRACT_IFMT_ADDV3_CODE
+    f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
+    f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4);
+    f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16);
 
   /* Record the fields for the semantic handler.  */
   FLD (f_simm16) = f_simm16;
   FLD (i_sr) = & CPU (h_gr)[f_r2];
   FLD (i_dr) = & CPU (h_gr)[f_r1];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_sll3", "f_simm16 0x%x", 'x', f_simm16, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_sll3", "f_simm16 0x%x", 'x', f_simm16, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
 
 #if WITH_PROFILE_MODEL_P
   /* Record the fields for profiling.  */
@@ -1621,19 +1532,21 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc,
     return idesc;
   }
 
- extract_fmt_slli:
+ extract_sfmt_slli:
   {
     const IDESC *idesc = &m32rbf_insn_data[itype];
     CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.fmt_slli.f
-  EXTRACT_IFMT_SLLI_VARS /* f-op1 f-r1 f-shift-op2 f-uimm5 */
+#define FLD(f) abuf->fields.sfmt_slli.f
+    UINT f_r1;
+    UINT f_uimm5;
 
-  EXTRACT_IFMT_SLLI_CODE
+    f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
+    f_uimm5 = EXTRACT_MSB0_UINT (insn, 16, 11, 5);
 
   /* Record the fields for the semantic handler.  */
   FLD (f_uimm5) = f_uimm5;
   FLD (i_dr) = & CPU (h_gr)[f_r1];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_slli", "f_uimm5 0x%x", 'x', f_uimm5, "dr 0x%x", 'x', f_r1, (char *) 0));
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_slli", "f_uimm5 0x%x", 'x', f_uimm5, "dr 0x%x", 'x', f_r1, (char *) 0));
 
 #if WITH_PROFILE_MODEL_P
   /* Record the fields for profiling.  */
@@ -1647,19 +1560,21 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc,
     return idesc;
   }
 
- extract_fmt_st:
+ extract_sfmt_st:
   {
     const IDESC *idesc = &m32rbf_insn_data[itype];
     CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.fmt_st.f
-  EXTRACT_IFMT_CMP_VARS /* f-op1 f-r1 f-op2 f-r2 */
+#define FLD(f) abuf->fields.sfmt_st_plus.f
+    UINT f_r1;
+    UINT f_r2;
 
-  EXTRACT_IFMT_CMP_CODE
+    f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
+    f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
 
   /* Record the fields for the semantic handler.  */
   FLD (i_src1) = & CPU (h_gr)[f_r1];
   FLD (i_src2) = & CPU (h_gr)[f_r2];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_st", "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_st", "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
 
 #if WITH_PROFILE_MODEL_P
   /* Record the fields for profiling.  */
@@ -1673,20 +1588,24 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc,
     return idesc;
   }
 
- extract_fmt_st_d:
+ extract_sfmt_st_d:
   {
     const IDESC *idesc = &m32rbf_insn_data[itype];
     CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.fmt_st_d.f
-  EXTRACT_IFMT_ST_D_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */
+#define FLD(f) abuf->fields.sfmt_st_d.f
+    UINT f_r1;
+    UINT f_r2;
+    INT f_simm16;
 
-  EXTRACT_IFMT_ST_D_CODE
+    f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
+    f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4);
+    f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16);
 
   /* Record the fields for the semantic handler.  */
   FLD (f_simm16) = f_simm16;
   FLD (i_src1) = & CPU (h_gr)[f_r1];
   FLD (i_src2) = & CPU (h_gr)[f_r2];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_st_d", "f_simm16 0x%x", 'x', f_simm16, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_st_d", "f_simm16 0x%x", 'x', f_simm16, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
 
 #if WITH_PROFILE_MODEL_P
   /* Record the fields for profiling.  */
@@ -1700,19 +1619,21 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc,
     return idesc;
   }
 
- extract_fmt_stb:
+ extract_sfmt_stb:
   {
     const IDESC *idesc = &m32rbf_insn_data[itype];
     CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.fmt_stb.f
-  EXTRACT_IFMT_CMP_VARS /* f-op1 f-r1 f-op2 f-r2 */
+#define FLD(f) abuf->fields.sfmt_st_plus.f
+    UINT f_r1;
+    UINT f_r2;
 
-  EXTRACT_IFMT_CMP_CODE
+    f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
+    f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
 
   /* Record the fields for the semantic handler.  */
   FLD (i_src1) = & CPU (h_gr)[f_r1];
   FLD (i_src2) = & CPU (h_gr)[f_r2];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_stb", "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_stb", "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
 
 #if WITH_PROFILE_MODEL_P
   /* Record the fields for profiling.  */
@@ -1726,20 +1647,24 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc,
     return idesc;
   }
 
- extract_fmt_stb_d:
+ extract_sfmt_stb_d:
   {
     const IDESC *idesc = &m32rbf_insn_data[itype];
     CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.fmt_stb_d.f
-  EXTRACT_IFMT_ST_D_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */
+#define FLD(f) abuf->fields.sfmt_st_d.f
+    UINT f_r1;
+    UINT f_r2;
+    INT f_simm16;
 
-  EXTRACT_IFMT_ST_D_CODE
+    f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
+    f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4);
+    f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16);
 
   /* Record the fields for the semantic handler.  */
   FLD (f_simm16) = f_simm16;
   FLD (i_src1) = & CPU (h_gr)[f_r1];
   FLD (i_src2) = & CPU (h_gr)[f_r2];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_stb_d", "f_simm16 0x%x", 'x', f_simm16, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_stb_d", "f_simm16 0x%x", 'x', f_simm16, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
 
 #if WITH_PROFILE_MODEL_P
   /* Record the fields for profiling.  */
@@ -1753,19 +1678,21 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc,
     return idesc;
   }
 
- extract_fmt_sth:
+ extract_sfmt_sth:
   {
     const IDESC *idesc = &m32rbf_insn_data[itype];
     CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.fmt_sth.f
-  EXTRACT_IFMT_CMP_VARS /* f-op1 f-r1 f-op2 f-r2 */
+#define FLD(f) abuf->fields.sfmt_st_plus.f
+    UINT f_r1;
+    UINT f_r2;
 
-  EXTRACT_IFMT_CMP_CODE
+    f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
+    f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
 
   /* Record the fields for the semantic handler.  */
   FLD (i_src1) = & CPU (h_gr)[f_r1];
   FLD (i_src2) = & CPU (h_gr)[f_r2];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_sth", "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_sth", "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
 
 #if WITH_PROFILE_MODEL_P
   /* Record the fields for profiling.  */
@@ -1779,20 +1706,24 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc,
     return idesc;
   }
 
- extract_fmt_sth_d:
+ extract_sfmt_sth_d:
   {
     const IDESC *idesc = &m32rbf_insn_data[itype];
     CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.fmt_sth_d.f
-  EXTRACT_IFMT_ST_D_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */
+#define FLD(f) abuf->fields.sfmt_st_d.f
+    UINT f_r1;
+    UINT f_r2;
+    INT f_simm16;
 
-  EXTRACT_IFMT_ST_D_CODE
+    f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
+    f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4);
+    f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16);
 
   /* Record the fields for the semantic handler.  */
   FLD (f_simm16) = f_simm16;
   FLD (i_src1) = & CPU (h_gr)[f_r1];
   FLD (i_src2) = & CPU (h_gr)[f_r2];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_sth_d", "f_simm16 0x%x", 'x', f_simm16, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_sth_d", "f_simm16 0x%x", 'x', f_simm16, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
 
 #if WITH_PROFILE_MODEL_P
   /* Record the fields for profiling.  */
@@ -1806,19 +1737,21 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc,
     return idesc;
   }
 
- extract_fmt_st_plus:
+ extract_sfmt_st_plus:
   {
     const IDESC *idesc = &m32rbf_insn_data[itype];
     CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.fmt_st_plus.f
-  EXTRACT_IFMT_CMP_VARS /* f-op1 f-r1 f-op2 f-r2 */
+#define FLD(f) abuf->fields.sfmt_st_plus.f
+    UINT f_r1;
+    UINT f_r2;
 
-  EXTRACT_IFMT_CMP_CODE
+    f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
+    f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
 
   /* Record the fields for the semantic handler.  */
   FLD (i_src1) = & CPU (h_gr)[f_r1];
   FLD (i_src2) = & CPU (h_gr)[f_r2];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_st_plus", "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_st_plus", "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
 
 #if WITH_PROFILE_MODEL_P
   /* Record the fields for profiling.  */
@@ -1833,19 +1766,18 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc,
     return idesc;
   }
 
- extract_fmt_trap:
+ extract_sfmt_trap:
   {
     const IDESC *idesc = &m32rbf_insn_data[itype];
     CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.cti.fields.fmt_trap.f
-  EXTRACT_IFMT_TRAP_VARS /* f-op1 f-r1 f-op2 f-uimm4 */
+#define FLD(f) abuf->fields.sfmt_trap.f
+    UINT f_uimm4;
 
-  EXTRACT_IFMT_TRAP_CODE
+    f_uimm4 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
 
   /* Record the fields for the semantic handler.  */
   FLD (f_uimm4) = f_uimm4;
-  SEM_BRANCH_INIT_EXTRACT (abuf);
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_trap", "f_uimm4 0x%x", 'x', f_uimm4, (char *) 0));
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_trap", "f_uimm4 0x%x", 'x', f_uimm4, (char *) 0));
 
 #if WITH_PROFILE_MODEL_P
   /* Record the fields for profiling.  */
@@ -1857,19 +1789,21 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc,
     return idesc;
   }
 
- extract_fmt_unlock:
+ extract_sfmt_unlock:
   {
     const IDESC *idesc = &m32rbf_insn_data[itype];
     CGEN_INSN_INT insn = entire_insn;
-#define FLD(f) abuf->fields.fmt_unlock.f
-  EXTRACT_IFMT_CMP_VARS /* f-op1 f-r1 f-op2 f-r2 */
+#define FLD(f) abuf->fields.sfmt_st_plus.f
+    UINT f_r1;
+    UINT f_r2;
 
-  EXTRACT_IFMT_CMP_CODE
+    f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
+    f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
 
   /* Record the fields for the semantic handler.  */
   FLD (i_src1) = & CPU (h_gr)[f_r1];
   FLD (i_src2) = & CPU (h_gr)[f_r2];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_unlock", "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
+  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_unlock", "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
 
 #if WITH_PROFILE_MODEL_P
   /* Record the fields for profiling.  */
diff --git a/sim/m32r/decode.h b/sim/m32r/decode.h
index 91471e8c143..9649accecc8 100644
--- a/sim/m32r/decode.h
+++ b/sim/m32r/decode.h
@@ -29,6 +29,8 @@ extern const IDESC *m32rbf_decode (SIM_CPU *, IADDR,
                                   CGEN_INSN_INT, CGEN_INSN_INT,
                                   ARGBUF *);
 extern void m32rbf_init_idesc_table (SIM_CPU *);
+extern void m32rbf_sem_init_idesc_table (SIM_CPU *);
+extern void m32rbf_semf_init_idesc_table (SIM_CPU *);
 
 /* Enum declaration for instructions in cpu family m32rbf.  */
 typedef enum m32rbf_insn_type {
@@ -61,134 +63,22 @@ typedef enum m32rbf_insn_type {
  , M32RBF_INSN_UNLOCK, M32RBF_INSN_MAX
 } M32RBF_INSN_TYPE;
 
-#if ! WITH_SEM_SWITCH_FULL
-#define SEMFULL(fn) extern SEMANTIC_FN CONCAT3 (m32rbf,_sem_,fn);
-#else
-#define SEMFULL(fn)
-#endif
-
-#if ! WITH_SEM_SWITCH_FAST
-#define SEMFAST(fn) extern SEMANTIC_FN CONCAT3 (m32rbf,_semf_,fn);
-#else
-#define SEMFAST(fn)
-#endif
-
-#define SEM(fn) SEMFULL (fn) SEMFAST (fn)
-
-/* The function version of the before/after handlers is always needed,
-   so we always want the SEMFULL declaration of them.  */
-extern SEMANTIC_FN CONCAT3 (m32rbf,_sem_,x_before);
-extern SEMANTIC_FN CONCAT3 (m32rbf,_sem_,x_after);
-
-SEM (x_invalid)
-SEM (x_after)
-SEM (x_before)
-SEM (x_cti_chain)
-SEM (x_chain)
-SEM (x_begin)
-SEM (add)
-SEM (add3)
-SEM (and)
-SEM (and3)
-SEM (or)
-SEM (or3)
-SEM (xor)
-SEM (xor3)
-SEM (addi)
-SEM (addv)
-SEM (addv3)
-SEM (addx)
-SEM (bc8)
-SEM (bc24)
-SEM (beq)
-SEM (beqz)
-SEM (bgez)
-SEM (bgtz)
-SEM (blez)
-SEM (bltz)
-SEM (bnez)
-SEM (bl8)
-SEM (bl24)
-SEM (bnc8)
-SEM (bnc24)
-SEM (bne)
-SEM (bra8)
-SEM (bra24)
-SEM (cmp)
-SEM (cmpi)
-SEM (cmpu)
-SEM (cmpui)
-SEM (div)
-SEM (divu)
-SEM (rem)
-SEM (remu)
-SEM (jl)
-SEM (jmp)
-SEM (ld)
-SEM (ld_d)
-SEM (ldb)
-SEM (ldb_d)
-SEM (ldh)
-SEM (ldh_d)
-SEM (ldub)
-SEM (ldub_d)
-SEM (lduh)
-SEM (lduh_d)
-SEM (ld_plus)
-SEM (ld24)
-SEM (ldi8)
-SEM (ldi16)
-SEM (lock)
-SEM (machi)
-SEM (maclo)
-SEM (macwhi)
-SEM (macwlo)
-SEM (mul)
-SEM (mulhi)
-SEM (mullo)
-SEM (mulwhi)
-SEM (mulwlo)
-SEM (mv)
-SEM (mvfachi)
-SEM (mvfaclo)
-SEM (mvfacmi)
-SEM (mvfc)
-SEM (mvtachi)
-SEM (mvtaclo)
-SEM (mvtc)
-SEM (neg)
-SEM (nop)
-SEM (not)
-SEM (rac)
-SEM (rach)
-SEM (rte)
-SEM (seth)
-SEM (sll)
-SEM (sll3)
-SEM (slli)
-SEM (sra)
-SEM (sra3)
-SEM (srai)
-SEM (srl)
-SEM (srl3)
-SEM (srli)
-SEM (st)
-SEM (st_d)
-SEM (stb)
-SEM (stb_d)
-SEM (sth)
-SEM (sth_d)
-SEM (st_plus)
-SEM (st_minus)
-SEM (sub)
-SEM (subv)
-SEM (subx)
-SEM (trap)
-SEM (unlock)
-
-#undef SEMFULL
-#undef SEMFAST
-#undef SEM
+/* Enum declaration for semantic formats in cpu family m32rbf.  */
+typedef enum m32rbf_sfmt_type {
+  M32RBF_SFMT_EMPTY, M32RBF_SFMT_ADD, M32RBF_SFMT_ADD3, M32RBF_SFMT_AND3
+ , M32RBF_SFMT_OR3, M32RBF_SFMT_ADDI, M32RBF_SFMT_ADDV, M32RBF_SFMT_ADDV3
+ , M32RBF_SFMT_ADDX, M32RBF_SFMT_BC8, M32RBF_SFMT_BC24, M32RBF_SFMT_BEQ
+ , M32RBF_SFMT_BEQZ, M32RBF_SFMT_BL8, M32RBF_SFMT_BL24, M32RBF_SFMT_BRA8
+ , M32RBF_SFMT_BRA24, M32RBF_SFMT_CMP, M32RBF_SFMT_CMPI, M32RBF_SFMT_DIV
+ , M32RBF_SFMT_JL, M32RBF_SFMT_JMP, M32RBF_SFMT_LD, M32RBF_SFMT_LD_D
+ , M32RBF_SFMT_LD_PLUS, M32RBF_SFMT_LD24, M32RBF_SFMT_LDI8, M32RBF_SFMT_LDI16
+ , M32RBF_SFMT_LOCK, M32RBF_SFMT_MACHI, M32RBF_SFMT_MULHI, M32RBF_SFMT_MV
+ , M32RBF_SFMT_MVFACHI, M32RBF_SFMT_MVFC, M32RBF_SFMT_MVTACHI, M32RBF_SFMT_MVTC
+ , M32RBF_SFMT_NOP, M32RBF_SFMT_RAC, M32RBF_SFMT_RTE, M32RBF_SFMT_SETH
+ , M32RBF_SFMT_SLL3, M32RBF_SFMT_SLLI, M32RBF_SFMT_ST, M32RBF_SFMT_ST_D
+ , M32RBF_SFMT_STB, M32RBF_SFMT_STB_D, M32RBF_SFMT_STH, M32RBF_SFMT_STH_D
+ , M32RBF_SFMT_ST_PLUS, M32RBF_SFMT_TRAP, M32RBF_SFMT_UNLOCK
+} M32RBF_SFMT_TYPE;
 
 /* Function unit handlers (user written).  */
 
diff --git a/sim/m32r/model.c b/sim/m32r/model.c
index e82881e0eec..99ca3cd1c39 100644
--- a/sim/m32r/model.c
+++ b/sim/m32r/model.c
@@ -37,7 +37,7 @@ with this program; if not, write to the Free Software Foundation, Inc.,
 static int
 model_m32r_d_add (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_add.f
+#define FLD(f) abuf->fields.sfmt_add.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -62,7 +62,7 @@ model_m32r_d_add (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_m32r_d_add3 (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_add3.f
+#define FLD(f) abuf->fields.sfmt_add3.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -85,7 +85,7 @@ model_m32r_d_add3 (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_m32r_d_and (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_add.f
+#define FLD(f) abuf->fields.sfmt_add.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -110,7 +110,7 @@ model_m32r_d_and (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_m32r_d_and3 (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_and3.f
+#define FLD(f) abuf->fields.sfmt_and3.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -133,7 +133,7 @@ model_m32r_d_and3 (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_m32r_d_or (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_add.f
+#define FLD(f) abuf->fields.sfmt_add.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -158,7 +158,7 @@ model_m32r_d_or (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_m32r_d_or3 (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_or3.f
+#define FLD(f) abuf->fields.sfmt_and3.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -181,7 +181,7 @@ model_m32r_d_or3 (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_m32r_d_xor (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_add.f
+#define FLD(f) abuf->fields.sfmt_add.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -206,7 +206,7 @@ model_m32r_d_xor (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_m32r_d_xor3 (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_and3.f
+#define FLD(f) abuf->fields.sfmt_and3.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -229,7 +229,7 @@ model_m32r_d_xor3 (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_m32r_d_addi (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_addi.f
+#define FLD(f) abuf->fields.sfmt_addi.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -252,7 +252,7 @@ model_m32r_d_addi (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_m32r_d_addv (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_addv.f
+#define FLD(f) abuf->fields.sfmt_add.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -277,7 +277,7 @@ model_m32r_d_addv (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_m32r_d_addv3 (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_addv3.f
+#define FLD(f) abuf->fields.sfmt_add3.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -300,7 +300,7 @@ model_m32r_d_addv3 (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_m32r_d_addx (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_addx.f
+#define FLD(f) abuf->fields.sfmt_add.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -325,7 +325,7 @@ model_m32r_d_addx (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_m32r_d_bc8 (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.cti.fields.fmt_bc8.f
+#define FLD(f) abuf->fields.sfmt_bl8.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -343,7 +343,7 @@ model_m32r_d_bc8 (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_m32r_d_bc24 (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.cti.fields.fmt_bc24.f
+#define FLD(f) abuf->fields.sfmt_bl24.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -361,7 +361,7 @@ model_m32r_d_bc24 (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_m32r_d_beq (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.cti.fields.fmt_beq.f
+#define FLD(f) abuf->fields.sfmt_beq.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -390,7 +390,7 @@ model_m32r_d_beq (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_m32r_d_beqz (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.cti.fields.fmt_beqz.f
+#define FLD(f) abuf->fields.sfmt_beq.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -417,7 +417,7 @@ model_m32r_d_beqz (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_m32r_d_bgez (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.cti.fields.fmt_beqz.f
+#define FLD(f) abuf->fields.sfmt_beq.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -444,7 +444,7 @@ model_m32r_d_bgez (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_m32r_d_bgtz (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.cti.fields.fmt_beqz.f
+#define FLD(f) abuf->fields.sfmt_beq.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -471,7 +471,7 @@ model_m32r_d_bgtz (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_m32r_d_blez (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.cti.fields.fmt_beqz.f
+#define FLD(f) abuf->fields.sfmt_beq.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -498,7 +498,7 @@ model_m32r_d_blez (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_m32r_d_bltz (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.cti.fields.fmt_beqz.f
+#define FLD(f) abuf->fields.sfmt_beq.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -525,7 +525,7 @@ model_m32r_d_bltz (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_m32r_d_bnez (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.cti.fields.fmt_beqz.f
+#define FLD(f) abuf->fields.sfmt_beq.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -552,7 +552,7 @@ model_m32r_d_bnez (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_m32r_d_bl8 (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.cti.fields.fmt_bl8.f
+#define FLD(f) abuf->fields.sfmt_bl8.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -570,7 +570,7 @@ model_m32r_d_bl8 (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_m32r_d_bl24 (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.cti.fields.fmt_bl24.f
+#define FLD(f) abuf->fields.sfmt_bl24.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -588,7 +588,7 @@ model_m32r_d_bl24 (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_m32r_d_bnc8 (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.cti.fields.fmt_bc8.f
+#define FLD(f) abuf->fields.sfmt_bl8.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -606,7 +606,7 @@ model_m32r_d_bnc8 (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_m32r_d_bnc24 (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.cti.fields.fmt_bc24.f
+#define FLD(f) abuf->fields.sfmt_bl24.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -624,7 +624,7 @@ model_m32r_d_bnc24 (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_m32r_d_bne (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.cti.fields.fmt_beq.f
+#define FLD(f) abuf->fields.sfmt_beq.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -653,7 +653,7 @@ model_m32r_d_bne (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_m32r_d_bra8 (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.cti.fields.fmt_bra8.f
+#define FLD(f) abuf->fields.sfmt_bl8.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -671,7 +671,7 @@ model_m32r_d_bra8 (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_m32r_d_bra24 (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.cti.fields.fmt_bra24.f
+#define FLD(f) abuf->fields.sfmt_bl24.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -689,7 +689,7 @@ model_m32r_d_bra24 (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_m32r_d_cmp (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_cmp.f
+#define FLD(f) abuf->fields.sfmt_st_plus.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -711,7 +711,7 @@ model_m32r_d_cmp (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_m32r_d_cmpi (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_cmpi.f
+#define FLD(f) abuf->fields.sfmt_st_d.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -731,7 +731,7 @@ model_m32r_d_cmpi (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_m32r_d_cmpu (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_cmp.f
+#define FLD(f) abuf->fields.sfmt_st_plus.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -753,7 +753,7 @@ model_m32r_d_cmpu (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_m32r_d_cmpui (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_cmpi.f
+#define FLD(f) abuf->fields.sfmt_st_d.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -773,7 +773,7 @@ model_m32r_d_cmpui (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_m32r_d_div (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_div.f
+#define FLD(f) abuf->fields.sfmt_add.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -798,7 +798,7 @@ model_m32r_d_div (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_m32r_d_divu (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_div.f
+#define FLD(f) abuf->fields.sfmt_add.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -823,7 +823,7 @@ model_m32r_d_divu (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_m32r_d_rem (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_div.f
+#define FLD(f) abuf->fields.sfmt_add.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -848,7 +848,7 @@ model_m32r_d_rem (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_m32r_d_remu (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_div.f
+#define FLD(f) abuf->fields.sfmt_add.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -873,7 +873,7 @@ model_m32r_d_remu (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_m32r_d_jl (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.cti.fields.fmt_jl.f
+#define FLD(f) abuf->fields.sfmt_jl.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -893,7 +893,7 @@ model_m32r_d_jl (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_m32r_d_jmp (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.cti.fields.fmt_jmp.f
+#define FLD(f) abuf->fields.sfmt_mvtc.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -913,7 +913,7 @@ model_m32r_d_jmp (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_m32r_d_ld (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_ld.f
+#define FLD(f) abuf->fields.sfmt_ld_plus.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -935,7 +935,7 @@ model_m32r_d_ld (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_m32r_d_ld_d (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_ld_d.f
+#define FLD(f) abuf->fields.sfmt_add3.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -957,7 +957,7 @@ model_m32r_d_ld_d (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_m32r_d_ldb (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_ldb.f
+#define FLD(f) abuf->fields.sfmt_ld_plus.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -979,7 +979,7 @@ model_m32r_d_ldb (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_m32r_d_ldb_d (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_ldb_d.f
+#define FLD(f) abuf->fields.sfmt_add3.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -1001,7 +1001,7 @@ model_m32r_d_ldb_d (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_m32r_d_ldh (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_ldh.f
+#define FLD(f) abuf->fields.sfmt_ld_plus.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -1023,7 +1023,7 @@ model_m32r_d_ldh (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_m32r_d_ldh_d (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_ldh_d.f
+#define FLD(f) abuf->fields.sfmt_add3.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -1045,7 +1045,7 @@ model_m32r_d_ldh_d (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_m32r_d_ldub (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_ldb.f
+#define FLD(f) abuf->fields.sfmt_ld_plus.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -1067,7 +1067,7 @@ model_m32r_d_ldub (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_m32r_d_ldub_d (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_ldb_d.f
+#define FLD(f) abuf->fields.sfmt_add3.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -1089,7 +1089,7 @@ model_m32r_d_ldub_d (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_m32r_d_lduh (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_ldh.f
+#define FLD(f) abuf->fields.sfmt_ld_plus.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -1111,7 +1111,7 @@ model_m32r_d_lduh (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_m32r_d_lduh_d (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_ldh_d.f
+#define FLD(f) abuf->fields.sfmt_add3.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -1133,7 +1133,7 @@ model_m32r_d_lduh_d (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_m32r_d_ld_plus (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_ld_plus.f
+#define FLD(f) abuf->fields.sfmt_ld_plus.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -1167,7 +1167,7 @@ model_m32r_d_ld_plus (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_m32r_d_ld24 (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_ld24.f
+#define FLD(f) abuf->fields.sfmt_ld24.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -1188,7 +1188,7 @@ model_m32r_d_ld24 (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_m32r_d_ldi8 (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_ldi8.f
+#define FLD(f) abuf->fields.sfmt_addi.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -1209,7 +1209,7 @@ model_m32r_d_ldi8 (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_m32r_d_ldi16 (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_ldi16.f
+#define FLD(f) abuf->fields.sfmt_add3.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -1230,7 +1230,7 @@ model_m32r_d_ldi16 (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_m32r_d_lock (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_lock.f
+#define FLD(f) abuf->fields.sfmt_ld_plus.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -1252,7 +1252,7 @@ model_m32r_d_lock (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_m32r_d_machi (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_machi.f
+#define FLD(f) abuf->fields.sfmt_st_plus.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -1274,7 +1274,7 @@ model_m32r_d_machi (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_m32r_d_maclo (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_machi.f
+#define FLD(f) abuf->fields.sfmt_st_plus.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -1296,7 +1296,7 @@ model_m32r_d_maclo (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_m32r_d_macwhi (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_machi.f
+#define FLD(f) abuf->fields.sfmt_st_plus.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -1318,7 +1318,7 @@ model_m32r_d_macwhi (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_m32r_d_macwlo (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_machi.f
+#define FLD(f) abuf->fields.sfmt_st_plus.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -1340,7 +1340,7 @@ model_m32r_d_macwlo (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_m32r_d_mul (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_add.f
+#define FLD(f) abuf->fields.sfmt_add.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -1365,7 +1365,7 @@ model_m32r_d_mul (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_m32r_d_mulhi (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_mulhi.f
+#define FLD(f) abuf->fields.sfmt_st_plus.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -1387,7 +1387,7 @@ model_m32r_d_mulhi (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_m32r_d_mullo (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_mulhi.f
+#define FLD(f) abuf->fields.sfmt_st_plus.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -1409,7 +1409,7 @@ model_m32r_d_mullo (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_m32r_d_mulwhi (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_mulhi.f
+#define FLD(f) abuf->fields.sfmt_st_plus.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -1431,7 +1431,7 @@ model_m32r_d_mulwhi (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_m32r_d_mulwlo (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_mulhi.f
+#define FLD(f) abuf->fields.sfmt_st_plus.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -1453,7 +1453,7 @@ model_m32r_d_mulwlo (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_m32r_d_mv (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_mv.f
+#define FLD(f) abuf->fields.sfmt_ld_plus.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -1476,7 +1476,7 @@ model_m32r_d_mv (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_m32r_d_mvfachi (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_mvfachi.f
+#define FLD(f) abuf->fields.sfmt_seth.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -1497,7 +1497,7 @@ model_m32r_d_mvfachi (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_m32r_d_mvfaclo (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_mvfachi.f
+#define FLD(f) abuf->fields.sfmt_seth.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -1518,7 +1518,7 @@ model_m32r_d_mvfaclo (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_m32r_d_mvfacmi (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_mvfachi.f
+#define FLD(f) abuf->fields.sfmt_seth.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -1539,7 +1539,7 @@ model_m32r_d_mvfacmi (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_m32r_d_mvfc (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_mvfc.f
+#define FLD(f) abuf->fields.sfmt_mvfc.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -1560,7 +1560,7 @@ model_m32r_d_mvfc (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_m32r_d_mvtachi (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_mvtachi.f
+#define FLD(f) abuf->fields.sfmt_st_plus.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -1580,7 +1580,7 @@ model_m32r_d_mvtachi (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_m32r_d_mvtaclo (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_mvtachi.f
+#define FLD(f) abuf->fields.sfmt_st_plus.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -1600,7 +1600,7 @@ model_m32r_d_mvtaclo (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_m32r_d_mvtc (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_mvtc.f
+#define FLD(f) abuf->fields.sfmt_mvtc.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -1621,7 +1621,7 @@ model_m32r_d_mvtc (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_m32r_d_neg (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_mv.f
+#define FLD(f) abuf->fields.sfmt_ld_plus.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -1644,7 +1644,7 @@ model_m32r_d_neg (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_m32r_d_nop (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_nop.f
+#define FLD(f) abuf->fields.fmt_empty.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -1663,7 +1663,7 @@ model_m32r_d_nop (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_m32r_d_not (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_mv.f
+#define FLD(f) abuf->fields.sfmt_ld_plus.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -1686,7 +1686,7 @@ model_m32r_d_not (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_m32r_d_rac (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_rac.f
+#define FLD(f) abuf->fields.fmt_empty.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -1704,7 +1704,7 @@ model_m32r_d_rac (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_m32r_d_rach (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_rac.f
+#define FLD(f) abuf->fields.fmt_empty.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -1722,7 +1722,7 @@ model_m32r_d_rach (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_m32r_d_rte (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.cti.fields.fmt_rte.f
+#define FLD(f) abuf->fields.fmt_empty.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -1741,7 +1741,7 @@ model_m32r_d_rte (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_m32r_d_seth (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_seth.f
+#define FLD(f) abuf->fields.sfmt_seth.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -1762,7 +1762,7 @@ model_m32r_d_seth (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_m32r_d_sll (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_add.f
+#define FLD(f) abuf->fields.sfmt_add.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -1787,7 +1787,7 @@ model_m32r_d_sll (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_m32r_d_sll3 (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_sll3.f
+#define FLD(f) abuf->fields.sfmt_add3.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -1810,7 +1810,7 @@ model_m32r_d_sll3 (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_m32r_d_slli (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_slli.f
+#define FLD(f) abuf->fields.sfmt_slli.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -1833,7 +1833,7 @@ model_m32r_d_slli (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_m32r_d_sra (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_add.f
+#define FLD(f) abuf->fields.sfmt_add.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -1858,7 +1858,7 @@ model_m32r_d_sra (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_m32r_d_sra3 (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_sll3.f
+#define FLD(f) abuf->fields.sfmt_add3.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -1881,7 +1881,7 @@ model_m32r_d_sra3 (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_m32r_d_srai (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_slli.f
+#define FLD(f) abuf->fields.sfmt_slli.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -1904,7 +1904,7 @@ model_m32r_d_srai (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_m32r_d_srl (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_add.f
+#define FLD(f) abuf->fields.sfmt_add.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -1929,7 +1929,7 @@ model_m32r_d_srl (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_m32r_d_srl3 (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_sll3.f
+#define FLD(f) abuf->fields.sfmt_add3.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -1952,7 +1952,7 @@ model_m32r_d_srl3 (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_m32r_d_srli (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_slli.f
+#define FLD(f) abuf->fields.sfmt_slli.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -1975,7 +1975,7 @@ model_m32r_d_srli (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_m32r_d_st (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_st.f
+#define FLD(f) abuf->fields.sfmt_st_plus.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -1997,7 +1997,7 @@ model_m32r_d_st (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_m32r_d_st_d (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_st_d.f
+#define FLD(f) abuf->fields.sfmt_st_d.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -2019,7 +2019,7 @@ model_m32r_d_st_d (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_m32r_d_stb (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_stb.f
+#define FLD(f) abuf->fields.sfmt_st_plus.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -2041,7 +2041,7 @@ model_m32r_d_stb (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_m32r_d_stb_d (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_stb_d.f
+#define FLD(f) abuf->fields.sfmt_st_d.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -2063,7 +2063,7 @@ model_m32r_d_stb_d (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_m32r_d_sth (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_sth.f
+#define FLD(f) abuf->fields.sfmt_st_plus.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -2085,7 +2085,7 @@ model_m32r_d_sth (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_m32r_d_sth_d (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_sth_d.f
+#define FLD(f) abuf->fields.sfmt_st_d.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -2107,7 +2107,7 @@ model_m32r_d_sth_d (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_m32r_d_st_plus (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_st_plus.f
+#define FLD(f) abuf->fields.sfmt_st_plus.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -2139,7 +2139,7 @@ model_m32r_d_st_plus (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_m32r_d_st_minus (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_st_plus.f
+#define FLD(f) abuf->fields.sfmt_st_plus.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -2171,7 +2171,7 @@ model_m32r_d_st_minus (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_m32r_d_sub (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_add.f
+#define FLD(f) abuf->fields.sfmt_add.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -2196,7 +2196,7 @@ model_m32r_d_sub (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_m32r_d_subv (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_addv.f
+#define FLD(f) abuf->fields.sfmt_add.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -2221,7 +2221,7 @@ model_m32r_d_subv (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_m32r_d_subx (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_addx.f
+#define FLD(f) abuf->fields.sfmt_add.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -2246,7 +2246,7 @@ model_m32r_d_subx (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_m32r_d_trap (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.cti.fields.fmt_trap.f
+#define FLD(f) abuf->fields.sfmt_trap.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -2265,7 +2265,7 @@ model_m32r_d_trap (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_m32r_d_unlock (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_unlock.f
+#define FLD(f) abuf->fields.sfmt_st_plus.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -2283,7 +2283,7 @@ model_m32r_d_unlock (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_test_add (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_add.f
+#define FLD(f) abuf->fields.sfmt_add.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -2299,7 +2299,7 @@ model_test_add (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_test_add3 (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_add3.f
+#define FLD(f) abuf->fields.sfmt_add3.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -2315,7 +2315,7 @@ model_test_add3 (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_test_and (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_add.f
+#define FLD(f) abuf->fields.sfmt_add.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -2331,7 +2331,7 @@ model_test_and (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_test_and3 (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_and3.f
+#define FLD(f) abuf->fields.sfmt_and3.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -2347,7 +2347,7 @@ model_test_and3 (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_test_or (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_add.f
+#define FLD(f) abuf->fields.sfmt_add.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -2363,7 +2363,7 @@ model_test_or (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_test_or3 (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_or3.f
+#define FLD(f) abuf->fields.sfmt_and3.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -2379,7 +2379,7 @@ model_test_or3 (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_test_xor (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_add.f
+#define FLD(f) abuf->fields.sfmt_add.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -2395,7 +2395,7 @@ model_test_xor (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_test_xor3 (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_and3.f
+#define FLD(f) abuf->fields.sfmt_and3.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -2411,7 +2411,7 @@ model_test_xor3 (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_test_addi (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_addi.f
+#define FLD(f) abuf->fields.sfmt_addi.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -2427,7 +2427,7 @@ model_test_addi (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_test_addv (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_addv.f
+#define FLD(f) abuf->fields.sfmt_add.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -2443,7 +2443,7 @@ model_test_addv (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_test_addv3 (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_addv3.f
+#define FLD(f) abuf->fields.sfmt_add3.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -2459,7 +2459,7 @@ model_test_addv3 (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_test_addx (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_addx.f
+#define FLD(f) abuf->fields.sfmt_add.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -2475,7 +2475,7 @@ model_test_addx (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_test_bc8 (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.cti.fields.fmt_bc8.f
+#define FLD(f) abuf->fields.sfmt_bl8.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -2491,7 +2491,7 @@ model_test_bc8 (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_test_bc24 (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.cti.fields.fmt_bc24.f
+#define FLD(f) abuf->fields.sfmt_bl24.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -2507,7 +2507,7 @@ model_test_bc24 (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_test_beq (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.cti.fields.fmt_beq.f
+#define FLD(f) abuf->fields.sfmt_beq.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -2523,7 +2523,7 @@ model_test_beq (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_test_beqz (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.cti.fields.fmt_beqz.f
+#define FLD(f) abuf->fields.sfmt_beq.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -2539,7 +2539,7 @@ model_test_beqz (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_test_bgez (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.cti.fields.fmt_beqz.f
+#define FLD(f) abuf->fields.sfmt_beq.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -2555,7 +2555,7 @@ model_test_bgez (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_test_bgtz (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.cti.fields.fmt_beqz.f
+#define FLD(f) abuf->fields.sfmt_beq.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -2571,7 +2571,7 @@ model_test_bgtz (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_test_blez (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.cti.fields.fmt_beqz.f
+#define FLD(f) abuf->fields.sfmt_beq.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -2587,7 +2587,7 @@ model_test_blez (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_test_bltz (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.cti.fields.fmt_beqz.f
+#define FLD(f) abuf->fields.sfmt_beq.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -2603,7 +2603,7 @@ model_test_bltz (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_test_bnez (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.cti.fields.fmt_beqz.f
+#define FLD(f) abuf->fields.sfmt_beq.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -2619,7 +2619,7 @@ model_test_bnez (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_test_bl8 (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.cti.fields.fmt_bl8.f
+#define FLD(f) abuf->fields.sfmt_bl8.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -2635,7 +2635,7 @@ model_test_bl8 (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_test_bl24 (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.cti.fields.fmt_bl24.f
+#define FLD(f) abuf->fields.sfmt_bl24.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -2651,7 +2651,7 @@ model_test_bl24 (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_test_bnc8 (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.cti.fields.fmt_bc8.f
+#define FLD(f) abuf->fields.sfmt_bl8.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -2667,7 +2667,7 @@ model_test_bnc8 (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_test_bnc24 (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.cti.fields.fmt_bc24.f
+#define FLD(f) abuf->fields.sfmt_bl24.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -2683,7 +2683,7 @@ model_test_bnc24 (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_test_bne (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.cti.fields.fmt_beq.f
+#define FLD(f) abuf->fields.sfmt_beq.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -2699,7 +2699,7 @@ model_test_bne (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_test_bra8 (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.cti.fields.fmt_bra8.f
+#define FLD(f) abuf->fields.sfmt_bl8.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -2715,7 +2715,7 @@ model_test_bra8 (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_test_bra24 (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.cti.fields.fmt_bra24.f
+#define FLD(f) abuf->fields.sfmt_bl24.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -2731,7 +2731,7 @@ model_test_bra24 (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_test_cmp (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_cmp.f
+#define FLD(f) abuf->fields.sfmt_st_plus.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -2747,7 +2747,7 @@ model_test_cmp (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_test_cmpi (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_cmpi.f
+#define FLD(f) abuf->fields.sfmt_st_d.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -2763,7 +2763,7 @@ model_test_cmpi (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_test_cmpu (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_cmp.f
+#define FLD(f) abuf->fields.sfmt_st_plus.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -2779,7 +2779,7 @@ model_test_cmpu (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_test_cmpui (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_cmpi.f
+#define FLD(f) abuf->fields.sfmt_st_d.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -2795,7 +2795,7 @@ model_test_cmpui (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_test_div (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_div.f
+#define FLD(f) abuf->fields.sfmt_add.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -2811,7 +2811,7 @@ model_test_div (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_test_divu (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_div.f
+#define FLD(f) abuf->fields.sfmt_add.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -2827,7 +2827,7 @@ model_test_divu (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_test_rem (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_div.f
+#define FLD(f) abuf->fields.sfmt_add.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -2843,7 +2843,7 @@ model_test_rem (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_test_remu (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_div.f
+#define FLD(f) abuf->fields.sfmt_add.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -2859,7 +2859,7 @@ model_test_remu (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_test_jl (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.cti.fields.fmt_jl.f
+#define FLD(f) abuf->fields.sfmt_jl.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -2875,7 +2875,7 @@ model_test_jl (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_test_jmp (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.cti.fields.fmt_jmp.f
+#define FLD(f) abuf->fields.sfmt_mvtc.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -2891,7 +2891,7 @@ model_test_jmp (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_test_ld (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_ld.f
+#define FLD(f) abuf->fields.sfmt_ld_plus.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -2907,7 +2907,7 @@ model_test_ld (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_test_ld_d (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_ld_d.f
+#define FLD(f) abuf->fields.sfmt_add3.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -2923,7 +2923,7 @@ model_test_ld_d (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_test_ldb (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_ldb.f
+#define FLD(f) abuf->fields.sfmt_ld_plus.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -2939,7 +2939,7 @@ model_test_ldb (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_test_ldb_d (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_ldb_d.f
+#define FLD(f) abuf->fields.sfmt_add3.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -2955,7 +2955,7 @@ model_test_ldb_d (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_test_ldh (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_ldh.f
+#define FLD(f) abuf->fields.sfmt_ld_plus.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -2971,7 +2971,7 @@ model_test_ldh (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_test_ldh_d (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_ldh_d.f
+#define FLD(f) abuf->fields.sfmt_add3.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -2987,7 +2987,7 @@ model_test_ldh_d (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_test_ldub (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_ldb.f
+#define FLD(f) abuf->fields.sfmt_ld_plus.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -3003,7 +3003,7 @@ model_test_ldub (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_test_ldub_d (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_ldb_d.f
+#define FLD(f) abuf->fields.sfmt_add3.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -3019,7 +3019,7 @@ model_test_ldub_d (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_test_lduh (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_ldh.f
+#define FLD(f) abuf->fields.sfmt_ld_plus.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -3035,7 +3035,7 @@ model_test_lduh (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_test_lduh_d (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_ldh_d.f
+#define FLD(f) abuf->fields.sfmt_add3.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -3051,7 +3051,7 @@ model_test_lduh_d (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_test_ld_plus (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_ld_plus.f
+#define FLD(f) abuf->fields.sfmt_ld_plus.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -3067,7 +3067,7 @@ model_test_ld_plus (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_test_ld24 (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_ld24.f
+#define FLD(f) abuf->fields.sfmt_ld24.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -3083,7 +3083,7 @@ model_test_ld24 (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_test_ldi8 (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_ldi8.f
+#define FLD(f) abuf->fields.sfmt_addi.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -3099,7 +3099,7 @@ model_test_ldi8 (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_test_ldi16 (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_ldi16.f
+#define FLD(f) abuf->fields.sfmt_add3.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -3115,7 +3115,7 @@ model_test_ldi16 (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_test_lock (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_lock.f
+#define FLD(f) abuf->fields.sfmt_ld_plus.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -3131,7 +3131,7 @@ model_test_lock (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_test_machi (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_machi.f
+#define FLD(f) abuf->fields.sfmt_st_plus.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -3147,7 +3147,7 @@ model_test_machi (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_test_maclo (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_machi.f
+#define FLD(f) abuf->fields.sfmt_st_plus.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -3163,7 +3163,7 @@ model_test_maclo (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_test_macwhi (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_machi.f
+#define FLD(f) abuf->fields.sfmt_st_plus.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -3179,7 +3179,7 @@ model_test_macwhi (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_test_macwlo (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_machi.f
+#define FLD(f) abuf->fields.sfmt_st_plus.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -3195,7 +3195,7 @@ model_test_macwlo (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_test_mul (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_add.f
+#define FLD(f) abuf->fields.sfmt_add.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -3211,7 +3211,7 @@ model_test_mul (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_test_mulhi (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_mulhi.f
+#define FLD(f) abuf->fields.sfmt_st_plus.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -3227,7 +3227,7 @@ model_test_mulhi (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_test_mullo (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_mulhi.f
+#define FLD(f) abuf->fields.sfmt_st_plus.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -3243,7 +3243,7 @@ model_test_mullo (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_test_mulwhi (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_mulhi.f
+#define FLD(f) abuf->fields.sfmt_st_plus.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -3259,7 +3259,7 @@ model_test_mulwhi (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_test_mulwlo (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_mulhi.f
+#define FLD(f) abuf->fields.sfmt_st_plus.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -3275,7 +3275,7 @@ model_test_mulwlo (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_test_mv (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_mv.f
+#define FLD(f) abuf->fields.sfmt_ld_plus.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -3291,7 +3291,7 @@ model_test_mv (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_test_mvfachi (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_mvfachi.f
+#define FLD(f) abuf->fields.sfmt_seth.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -3307,7 +3307,7 @@ model_test_mvfachi (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_test_mvfaclo (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_mvfachi.f
+#define FLD(f) abuf->fields.sfmt_seth.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -3323,7 +3323,7 @@ model_test_mvfaclo (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_test_mvfacmi (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_mvfachi.f
+#define FLD(f) abuf->fields.sfmt_seth.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -3339,7 +3339,7 @@ model_test_mvfacmi (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_test_mvfc (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_mvfc.f
+#define FLD(f) abuf->fields.sfmt_mvfc.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -3355,7 +3355,7 @@ model_test_mvfc (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_test_mvtachi (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_mvtachi.f
+#define FLD(f) abuf->fields.sfmt_st_plus.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -3371,7 +3371,7 @@ model_test_mvtachi (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_test_mvtaclo (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_mvtachi.f
+#define FLD(f) abuf->fields.sfmt_st_plus.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -3387,7 +3387,7 @@ model_test_mvtaclo (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_test_mvtc (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_mvtc.f
+#define FLD(f) abuf->fields.sfmt_mvtc.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -3403,7 +3403,7 @@ model_test_mvtc (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_test_neg (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_mv.f
+#define FLD(f) abuf->fields.sfmt_ld_plus.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -3419,7 +3419,7 @@ model_test_neg (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_test_nop (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_nop.f
+#define FLD(f) abuf->fields.fmt_empty.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -3435,7 +3435,7 @@ model_test_nop (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_test_not (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_mv.f
+#define FLD(f) abuf->fields.sfmt_ld_plus.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -3451,7 +3451,7 @@ model_test_not (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_test_rac (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_rac.f
+#define FLD(f) abuf->fields.fmt_empty.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -3467,7 +3467,7 @@ model_test_rac (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_test_rach (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_rac.f
+#define FLD(f) abuf->fields.fmt_empty.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -3483,7 +3483,7 @@ model_test_rach (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_test_rte (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.cti.fields.fmt_rte.f
+#define FLD(f) abuf->fields.fmt_empty.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -3499,7 +3499,7 @@ model_test_rte (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_test_seth (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_seth.f
+#define FLD(f) abuf->fields.sfmt_seth.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -3515,7 +3515,7 @@ model_test_seth (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_test_sll (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_add.f
+#define FLD(f) abuf->fields.sfmt_add.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -3531,7 +3531,7 @@ model_test_sll (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_test_sll3 (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_sll3.f
+#define FLD(f) abuf->fields.sfmt_add3.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -3547,7 +3547,7 @@ model_test_sll3 (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_test_slli (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_slli.f
+#define FLD(f) abuf->fields.sfmt_slli.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -3563,7 +3563,7 @@ model_test_slli (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_test_sra (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_add.f
+#define FLD(f) abuf->fields.sfmt_add.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -3579,7 +3579,7 @@ model_test_sra (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_test_sra3 (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_sll3.f
+#define FLD(f) abuf->fields.sfmt_add3.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -3595,7 +3595,7 @@ model_test_sra3 (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_test_srai (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_slli.f
+#define FLD(f) abuf->fields.sfmt_slli.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -3611,7 +3611,7 @@ model_test_srai (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_test_srl (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_add.f
+#define FLD(f) abuf->fields.sfmt_add.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -3627,7 +3627,7 @@ model_test_srl (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_test_srl3 (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_sll3.f
+#define FLD(f) abuf->fields.sfmt_add3.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -3643,7 +3643,7 @@ model_test_srl3 (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_test_srli (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_slli.f
+#define FLD(f) abuf->fields.sfmt_slli.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -3659,7 +3659,7 @@ model_test_srli (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_test_st (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_st.f
+#define FLD(f) abuf->fields.sfmt_st_plus.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -3675,7 +3675,7 @@ model_test_st (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_test_st_d (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_st_d.f
+#define FLD(f) abuf->fields.sfmt_st_d.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -3691,7 +3691,7 @@ model_test_st_d (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_test_stb (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_stb.f
+#define FLD(f) abuf->fields.sfmt_st_plus.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -3707,7 +3707,7 @@ model_test_stb (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_test_stb_d (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_stb_d.f
+#define FLD(f) abuf->fields.sfmt_st_d.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -3723,7 +3723,7 @@ model_test_stb_d (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_test_sth (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_sth.f
+#define FLD(f) abuf->fields.sfmt_st_plus.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -3739,7 +3739,7 @@ model_test_sth (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_test_sth_d (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_sth_d.f
+#define FLD(f) abuf->fields.sfmt_st_d.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -3755,7 +3755,7 @@ model_test_sth_d (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_test_st_plus (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_st_plus.f
+#define FLD(f) abuf->fields.sfmt_st_plus.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -3771,7 +3771,7 @@ model_test_st_plus (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_test_st_minus (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_st_plus.f
+#define FLD(f) abuf->fields.sfmt_st_plus.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -3787,7 +3787,7 @@ model_test_st_minus (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_test_sub (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_add.f
+#define FLD(f) abuf->fields.sfmt_add.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -3803,7 +3803,7 @@ model_test_sub (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_test_subv (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_addv.f
+#define FLD(f) abuf->fields.sfmt_add.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -3819,7 +3819,7 @@ model_test_subv (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_test_subx (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_addx.f
+#define FLD(f) abuf->fields.sfmt_add.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -3835,7 +3835,7 @@ model_test_subx (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_test_trap (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.cti.fields.fmt_trap.f
+#define FLD(f) abuf->fields.sfmt_trap.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -3851,7 +3851,7 @@ model_test_trap (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_test_unlock (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_unlock.f
+#define FLD(f) abuf->fields.sfmt_st_plus.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
diff --git a/sim/m32r/sem-switch.c b/sim/m32r/sem-switch.c
index 673b83680e2..cd7e8da2332 100644
--- a/sim/m32r/sem-switch.c
+++ b/sim/m32r/sem-switch.c
@@ -142,11 +142,13 @@ with this program; if not, write to the Free Software Foundation, Inc.,
   int i;
 
   for (i = 0; labels[i].label != 0; ++i)
+    {
 #if FAST_P
-    CPU_IDESC (current_cpu) [labels[i].index].sem_fast_lab = labels[i].label;
+      CPU_IDESC (current_cpu) [labels[i].index].sem_fast_lab = labels[i].label;
 #else
-    CPU_IDESC (current_cpu) [labels[i].index].sem_full_lab = labels[i].label;
+      CPU_IDESC (current_cpu) [labels[i].index].sem_full_lab = labels[i].label;
 #endif
+    }
 
 #undef DEFINE_LABELS
 #endif /* DEFINE_LABELS */
@@ -266,12 +268,12 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case)
 #if WITH_SCACHE_PBB_M32RBF
 #ifdef DEFINE_SWITCH
     vpc = m32rbf_pbb_cti_chain (current_cpu, sem_arg,
-			       pbb_br_npc_ptr, pbb_br_npc);
+			       pbb_br_type, pbb_br_npc);
     BREAK (sem);
 #else
     /* FIXME: Allow provision of explicit ifmt spec in insn spec.  */
     vpc = m32rbf_pbb_cti_chain (current_cpu, sem_arg,
-			       CPU_PBB_BR_NPC_PTR (current_cpu),
+			       CPU_PBB_BR_TYPE (current_cpu),
 			       CPU_PBB_BR_NPC (current_cpu));
 #endif
 #endif
@@ -332,7 +334,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case)
 {
   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_add.f
+#define FLD(f) abuf->fields.sfmt_add.f
   int UNUSED written = 0;
   IADDR UNUSED pc = abuf->addr;
   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
@@ -351,7 +353,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case)
 {
   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_add3.f
+#define FLD(f) abuf->fields.sfmt_add3.f
   int UNUSED written = 0;
   IADDR UNUSED pc = abuf->addr;
   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
@@ -370,7 +372,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case)
 {
   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_add.f
+#define FLD(f) abuf->fields.sfmt_add.f
   int UNUSED written = 0;
   IADDR UNUSED pc = abuf->addr;
   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
@@ -389,7 +391,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case)
 {
   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_and3.f
+#define FLD(f) abuf->fields.sfmt_and3.f
   int UNUSED written = 0;
   IADDR UNUSED pc = abuf->addr;
   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
@@ -408,7 +410,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case)
 {
   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_add.f
+#define FLD(f) abuf->fields.sfmt_add.f
   int UNUSED written = 0;
   IADDR UNUSED pc = abuf->addr;
   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
@@ -427,7 +429,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case)
 {
   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_or3.f
+#define FLD(f) abuf->fields.sfmt_and3.f
   int UNUSED written = 0;
   IADDR UNUSED pc = abuf->addr;
   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
@@ -446,7 +448,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case)
 {
   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_add.f
+#define FLD(f) abuf->fields.sfmt_add.f
   int UNUSED written = 0;
   IADDR UNUSED pc = abuf->addr;
   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
@@ -465,7 +467,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case)
 {
   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_and3.f
+#define FLD(f) abuf->fields.sfmt_and3.f
   int UNUSED written = 0;
   IADDR UNUSED pc = abuf->addr;
   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
@@ -484,7 +486,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case)
 {
   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_addi.f
+#define FLD(f) abuf->fields.sfmt_addi.f
   int UNUSED written = 0;
   IADDR UNUSED pc = abuf->addr;
   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
@@ -503,7 +505,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case)
 {
   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_addv.f
+#define FLD(f) abuf->fields.sfmt_add.f
   int UNUSED written = 0;
   IADDR UNUSED pc = abuf->addr;
   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
@@ -532,7 +534,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case)
 {
   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_addv3.f
+#define FLD(f) abuf->fields.sfmt_add3.f
   int UNUSED written = 0;
   IADDR UNUSED pc = abuf->addr;
   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
@@ -561,7 +563,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case)
 {
   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_addx.f
+#define FLD(f) abuf->fields.sfmt_add.f
   int UNUSED written = 0;
   IADDR UNUSED pc = abuf->addr;
   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
@@ -590,7 +592,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case)
 {
   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.cti.fields.fmt_bc8.f
+#define FLD(f) abuf->fields.sfmt_bl8.f
   int UNUSED written = 0;
   IADDR UNUSED pc = abuf->addr;
   SEM_BRANCH_INIT
@@ -599,7 +601,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case)
 if (CPU (h_cond)) {
   {
     USI opval = FLD (i_disp8);
-    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
+    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
     written |= (1 << 2);
     TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
   }
@@ -615,7 +617,7 @@ if (CPU (h_cond)) {
 {
   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.cti.fields.fmt_bc24.f
+#define FLD(f) abuf->fields.sfmt_bl24.f
   int UNUSED written = 0;
   IADDR UNUSED pc = abuf->addr;
   SEM_BRANCH_INIT
@@ -624,7 +626,7 @@ if (CPU (h_cond)) {
 if (CPU (h_cond)) {
   {
     USI opval = FLD (i_disp24);
-    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
+    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
     written |= (1 << 2);
     TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
   }
@@ -640,7 +642,7 @@ if (CPU (h_cond)) {
 {
   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.cti.fields.fmt_beq.f
+#define FLD(f) abuf->fields.sfmt_beq.f
   int UNUSED written = 0;
   IADDR UNUSED pc = abuf->addr;
   SEM_BRANCH_INIT
@@ -649,7 +651,7 @@ if (CPU (h_cond)) {
 if (EQSI (* FLD (i_src1), * FLD (i_src2))) {
   {
     USI opval = FLD (i_disp16);
-    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
+    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
     written |= (1 << 3);
     TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
   }
@@ -665,7 +667,7 @@ if (EQSI (* FLD (i_src1), * FLD (i_src2))) {
 {
   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.cti.fields.fmt_beqz.f
+#define FLD(f) abuf->fields.sfmt_beq.f
   int UNUSED written = 0;
   IADDR UNUSED pc = abuf->addr;
   SEM_BRANCH_INIT
@@ -674,7 +676,7 @@ if (EQSI (* FLD (i_src1), * FLD (i_src2))) {
 if (EQSI (* FLD (i_src2), 0)) {
   {
     USI opval = FLD (i_disp16);
-    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
+    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
     written |= (1 << 2);
     TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
   }
@@ -690,7 +692,7 @@ if (EQSI (* FLD (i_src2), 0)) {
 {
   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.cti.fields.fmt_beqz.f
+#define FLD(f) abuf->fields.sfmt_beq.f
   int UNUSED written = 0;
   IADDR UNUSED pc = abuf->addr;
   SEM_BRANCH_INIT
@@ -699,7 +701,7 @@ if (EQSI (* FLD (i_src2), 0)) {
 if (GESI (* FLD (i_src2), 0)) {
   {
     USI opval = FLD (i_disp16);
-    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
+    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
     written |= (1 << 2);
     TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
   }
@@ -715,7 +717,7 @@ if (GESI (* FLD (i_src2), 0)) {
 {
   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.cti.fields.fmt_beqz.f
+#define FLD(f) abuf->fields.sfmt_beq.f
   int UNUSED written = 0;
   IADDR UNUSED pc = abuf->addr;
   SEM_BRANCH_INIT
@@ -724,7 +726,7 @@ if (GESI (* FLD (i_src2), 0)) {
 if (GTSI (* FLD (i_src2), 0)) {
   {
     USI opval = FLD (i_disp16);
-    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
+    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
     written |= (1 << 2);
     TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
   }
@@ -740,7 +742,7 @@ if (GTSI (* FLD (i_src2), 0)) {
 {
   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.cti.fields.fmt_beqz.f
+#define FLD(f) abuf->fields.sfmt_beq.f
   int UNUSED written = 0;
   IADDR UNUSED pc = abuf->addr;
   SEM_BRANCH_INIT
@@ -749,7 +751,7 @@ if (GTSI (* FLD (i_src2), 0)) {
 if (LESI (* FLD (i_src2), 0)) {
   {
     USI opval = FLD (i_disp16);
-    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
+    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
     written |= (1 << 2);
     TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
   }
@@ -765,7 +767,7 @@ if (LESI (* FLD (i_src2), 0)) {
 {
   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.cti.fields.fmt_beqz.f
+#define FLD(f) abuf->fields.sfmt_beq.f
   int UNUSED written = 0;
   IADDR UNUSED pc = abuf->addr;
   SEM_BRANCH_INIT
@@ -774,7 +776,7 @@ if (LESI (* FLD (i_src2), 0)) {
 if (LTSI (* FLD (i_src2), 0)) {
   {
     USI opval = FLD (i_disp16);
-    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
+    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
     written |= (1 << 2);
     TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
   }
@@ -790,7 +792,7 @@ if (LTSI (* FLD (i_src2), 0)) {
 {
   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.cti.fields.fmt_beqz.f
+#define FLD(f) abuf->fields.sfmt_beq.f
   int UNUSED written = 0;
   IADDR UNUSED pc = abuf->addr;
   SEM_BRANCH_INIT
@@ -799,7 +801,7 @@ if (LTSI (* FLD (i_src2), 0)) {
 if (NESI (* FLD (i_src2), 0)) {
   {
     USI opval = FLD (i_disp16);
-    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
+    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
     written |= (1 << 2);
     TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
   }
@@ -815,7 +817,7 @@ if (NESI (* FLD (i_src2), 0)) {
 {
   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.cti.fields.fmt_bl8.f
+#define FLD(f) abuf->fields.sfmt_bl8.f
   int UNUSED written = 0;
   IADDR UNUSED pc = abuf->addr;
   SEM_BRANCH_INIT
@@ -829,7 +831,7 @@ if (NESI (* FLD (i_src2), 0)) {
   }
   {
     USI opval = FLD (i_disp8);
-    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
+    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
     TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
   }
 }
@@ -843,7 +845,7 @@ if (NESI (* FLD (i_src2), 0)) {
 {
   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.cti.fields.fmt_bl24.f
+#define FLD(f) abuf->fields.sfmt_bl24.f
   int UNUSED written = 0;
   IADDR UNUSED pc = abuf->addr;
   SEM_BRANCH_INIT
@@ -857,7 +859,7 @@ if (NESI (* FLD (i_src2), 0)) {
   }
   {
     USI opval = FLD (i_disp24);
-    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
+    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
     TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
   }
 }
@@ -871,7 +873,7 @@ if (NESI (* FLD (i_src2), 0)) {
 {
   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.cti.fields.fmt_bc8.f
+#define FLD(f) abuf->fields.sfmt_bl8.f
   int UNUSED written = 0;
   IADDR UNUSED pc = abuf->addr;
   SEM_BRANCH_INIT
@@ -880,7 +882,7 @@ if (NESI (* FLD (i_src2), 0)) {
 if (NOTBI (CPU (h_cond))) {
   {
     USI opval = FLD (i_disp8);
-    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
+    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
     written |= (1 << 2);
     TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
   }
@@ -896,7 +898,7 @@ if (NOTBI (CPU (h_cond))) {
 {
   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.cti.fields.fmt_bc24.f
+#define FLD(f) abuf->fields.sfmt_bl24.f
   int UNUSED written = 0;
   IADDR UNUSED pc = abuf->addr;
   SEM_BRANCH_INIT
@@ -905,7 +907,7 @@ if (NOTBI (CPU (h_cond))) {
 if (NOTBI (CPU (h_cond))) {
   {
     USI opval = FLD (i_disp24);
-    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
+    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
     written |= (1 << 2);
     TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
   }
@@ -921,7 +923,7 @@ if (NOTBI (CPU (h_cond))) {
 {
   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.cti.fields.fmt_beq.f
+#define FLD(f) abuf->fields.sfmt_beq.f
   int UNUSED written = 0;
   IADDR UNUSED pc = abuf->addr;
   SEM_BRANCH_INIT
@@ -930,7 +932,7 @@ if (NOTBI (CPU (h_cond))) {
 if (NESI (* FLD (i_src1), * FLD (i_src2))) {
   {
     USI opval = FLD (i_disp16);
-    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
+    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
     written |= (1 << 3);
     TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
   }
@@ -946,7 +948,7 @@ if (NESI (* FLD (i_src1), * FLD (i_src2))) {
 {
   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.cti.fields.fmt_bra8.f
+#define FLD(f) abuf->fields.sfmt_bl8.f
   int UNUSED written = 0;
   IADDR UNUSED pc = abuf->addr;
   SEM_BRANCH_INIT
@@ -954,7 +956,7 @@ if (NESI (* FLD (i_src1), * FLD (i_src2))) {
 
   {
     USI opval = FLD (i_disp8);
-    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
+    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
     TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
   }
 
@@ -967,7 +969,7 @@ if (NESI (* FLD (i_src1), * FLD (i_src2))) {
 {
   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.cti.fields.fmt_bra24.f
+#define FLD(f) abuf->fields.sfmt_bl24.f
   int UNUSED written = 0;
   IADDR UNUSED pc = abuf->addr;
   SEM_BRANCH_INIT
@@ -975,7 +977,7 @@ if (NESI (* FLD (i_src1), * FLD (i_src2))) {
 
   {
     USI opval = FLD (i_disp24);
-    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
+    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
     TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
   }
 
@@ -988,7 +990,7 @@ if (NESI (* FLD (i_src1), * FLD (i_src2))) {
 {
   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_cmp.f
+#define FLD(f) abuf->fields.sfmt_st_plus.f
   int UNUSED written = 0;
   IADDR UNUSED pc = abuf->addr;
   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
@@ -1007,7 +1009,7 @@ if (NESI (* FLD (i_src1), * FLD (i_src2))) {
 {
   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_cmpi.f
+#define FLD(f) abuf->fields.sfmt_st_d.f
   int UNUSED written = 0;
   IADDR UNUSED pc = abuf->addr;
   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
@@ -1026,7 +1028,7 @@ if (NESI (* FLD (i_src1), * FLD (i_src2))) {
 {
   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_cmp.f
+#define FLD(f) abuf->fields.sfmt_st_plus.f
   int UNUSED written = 0;
   IADDR UNUSED pc = abuf->addr;
   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
@@ -1045,7 +1047,7 @@ if (NESI (* FLD (i_src1), * FLD (i_src2))) {
 {
   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_cmpi.f
+#define FLD(f) abuf->fields.sfmt_st_d.f
   int UNUSED written = 0;
   IADDR UNUSED pc = abuf->addr;
   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
@@ -1064,7 +1066,7 @@ if (NESI (* FLD (i_src1), * FLD (i_src2))) {
 {
   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_div.f
+#define FLD(f) abuf->fields.sfmt_add.f
   int UNUSED written = 0;
   IADDR UNUSED pc = abuf->addr;
   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
@@ -1087,7 +1089,7 @@ if (NESI (* FLD (i_sr), 0)) {
 {
   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_div.f
+#define FLD(f) abuf->fields.sfmt_add.f
   int UNUSED written = 0;
   IADDR UNUSED pc = abuf->addr;
   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
@@ -1110,7 +1112,7 @@ if (NESI (* FLD (i_sr), 0)) {
 {
   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_div.f
+#define FLD(f) abuf->fields.sfmt_add.f
   int UNUSED written = 0;
   IADDR UNUSED pc = abuf->addr;
   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
@@ -1133,7 +1135,7 @@ if (NESI (* FLD (i_sr), 0)) {
 {
   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_div.f
+#define FLD(f) abuf->fields.sfmt_add.f
   int UNUSED written = 0;
   IADDR UNUSED pc = abuf->addr;
   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
@@ -1156,7 +1158,7 @@ if (NESI (* FLD (i_sr), 0)) {
 {
   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.cti.fields.fmt_jl.f
+#define FLD(f) abuf->fields.sfmt_jl.f
   int UNUSED written = 0;
   IADDR UNUSED pc = abuf->addr;
   SEM_BRANCH_INIT
@@ -1187,7 +1189,7 @@ if (NESI (* FLD (i_sr), 0)) {
 {
   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.cti.fields.fmt_jmp.f
+#define FLD(f) abuf->fields.sfmt_mvtc.f
   int UNUSED written = 0;
   IADDR UNUSED pc = abuf->addr;
   SEM_BRANCH_INIT
@@ -1208,7 +1210,7 @@ if (NESI (* FLD (i_sr), 0)) {
 {
   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_ld.f
+#define FLD(f) abuf->fields.sfmt_ld_plus.f
   int UNUSED written = 0;
   IADDR UNUSED pc = abuf->addr;
   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
@@ -1227,7 +1229,7 @@ if (NESI (* FLD (i_sr), 0)) {
 {
   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_ld_d.f
+#define FLD(f) abuf->fields.sfmt_add3.f
   int UNUSED written = 0;
   IADDR UNUSED pc = abuf->addr;
   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
@@ -1246,7 +1248,7 @@ if (NESI (* FLD (i_sr), 0)) {
 {
   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_ldb.f
+#define FLD(f) abuf->fields.sfmt_ld_plus.f
   int UNUSED written = 0;
   IADDR UNUSED pc = abuf->addr;
   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
@@ -1265,7 +1267,7 @@ if (NESI (* FLD (i_sr), 0)) {
 {
   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_ldb_d.f
+#define FLD(f) abuf->fields.sfmt_add3.f
   int UNUSED written = 0;
   IADDR UNUSED pc = abuf->addr;
   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
@@ -1284,7 +1286,7 @@ if (NESI (* FLD (i_sr), 0)) {
 {
   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_ldh.f
+#define FLD(f) abuf->fields.sfmt_ld_plus.f
   int UNUSED written = 0;
   IADDR UNUSED pc = abuf->addr;
   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
@@ -1303,7 +1305,7 @@ if (NESI (* FLD (i_sr), 0)) {
 {
   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_ldh_d.f
+#define FLD(f) abuf->fields.sfmt_add3.f
   int UNUSED written = 0;
   IADDR UNUSED pc = abuf->addr;
   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
@@ -1322,7 +1324,7 @@ if (NESI (* FLD (i_sr), 0)) {
 {
   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_ldb.f
+#define FLD(f) abuf->fields.sfmt_ld_plus.f
   int UNUSED written = 0;
   IADDR UNUSED pc = abuf->addr;
   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
@@ -1341,7 +1343,7 @@ if (NESI (* FLD (i_sr), 0)) {
 {
   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_ldb_d.f
+#define FLD(f) abuf->fields.sfmt_add3.f
   int UNUSED written = 0;
   IADDR UNUSED pc = abuf->addr;
   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
@@ -1360,7 +1362,7 @@ if (NESI (* FLD (i_sr), 0)) {
 {
   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_ldh.f
+#define FLD(f) abuf->fields.sfmt_ld_plus.f
   int UNUSED written = 0;
   IADDR UNUSED pc = abuf->addr;
   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
@@ -1379,7 +1381,7 @@ if (NESI (* FLD (i_sr), 0)) {
 {
   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_ldh_d.f
+#define FLD(f) abuf->fields.sfmt_add3.f
   int UNUSED written = 0;
   IADDR UNUSED pc = abuf->addr;
   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
@@ -1398,7 +1400,7 @@ if (NESI (* FLD (i_sr), 0)) {
 {
   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_ld_plus.f
+#define FLD(f) abuf->fields.sfmt_ld_plus.f
   int UNUSED written = 0;
   IADDR UNUSED pc = abuf->addr;
   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
@@ -1427,7 +1429,7 @@ if (NESI (* FLD (i_sr), 0)) {
 {
   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_ld24.f
+#define FLD(f) abuf->fields.sfmt_ld24.f
   int UNUSED written = 0;
   IADDR UNUSED pc = abuf->addr;
   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
@@ -1446,7 +1448,7 @@ if (NESI (* FLD (i_sr), 0)) {
 {
   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_ldi8.f
+#define FLD(f) abuf->fields.sfmt_addi.f
   int UNUSED written = 0;
   IADDR UNUSED pc = abuf->addr;
   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
@@ -1465,7 +1467,7 @@ if (NESI (* FLD (i_sr), 0)) {
 {
   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_ldi16.f
+#define FLD(f) abuf->fields.sfmt_add3.f
   int UNUSED written = 0;
   IADDR UNUSED pc = abuf->addr;
   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
@@ -1484,7 +1486,7 @@ if (NESI (* FLD (i_sr), 0)) {
 {
   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_lock.f
+#define FLD(f) abuf->fields.sfmt_ld_plus.f
   int UNUSED written = 0;
   IADDR UNUSED pc = abuf->addr;
   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
@@ -1510,7 +1512,7 @@ if (NESI (* FLD (i_sr), 0)) {
 {
   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_machi.f
+#define FLD(f) abuf->fields.sfmt_st_plus.f
   int UNUSED written = 0;
   IADDR UNUSED pc = abuf->addr;
   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
@@ -1529,7 +1531,7 @@ if (NESI (* FLD (i_sr), 0)) {
 {
   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_machi.f
+#define FLD(f) abuf->fields.sfmt_st_plus.f
   int UNUSED written = 0;
   IADDR UNUSED pc = abuf->addr;
   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
@@ -1548,7 +1550,7 @@ if (NESI (* FLD (i_sr), 0)) {
 {
   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_machi.f
+#define FLD(f) abuf->fields.sfmt_st_plus.f
   int UNUSED written = 0;
   IADDR UNUSED pc = abuf->addr;
   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
@@ -1567,7 +1569,7 @@ if (NESI (* FLD (i_sr), 0)) {
 {
   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_machi.f
+#define FLD(f) abuf->fields.sfmt_st_plus.f
   int UNUSED written = 0;
   IADDR UNUSED pc = abuf->addr;
   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
@@ -1586,7 +1588,7 @@ if (NESI (* FLD (i_sr), 0)) {
 {
   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_add.f
+#define FLD(f) abuf->fields.sfmt_add.f
   int UNUSED written = 0;
   IADDR UNUSED pc = abuf->addr;
   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
@@ -1605,7 +1607,7 @@ if (NESI (* FLD (i_sr), 0)) {
 {
   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_mulhi.f
+#define FLD(f) abuf->fields.sfmt_st_plus.f
   int UNUSED written = 0;
   IADDR UNUSED pc = abuf->addr;
   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
@@ -1624,7 +1626,7 @@ if (NESI (* FLD (i_sr), 0)) {
 {
   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_mulhi.f
+#define FLD(f) abuf->fields.sfmt_st_plus.f
   int UNUSED written = 0;
   IADDR UNUSED pc = abuf->addr;
   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
@@ -1643,7 +1645,7 @@ if (NESI (* FLD (i_sr), 0)) {
 {
   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_mulhi.f
+#define FLD(f) abuf->fields.sfmt_st_plus.f
   int UNUSED written = 0;
   IADDR UNUSED pc = abuf->addr;
   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
@@ -1662,7 +1664,7 @@ if (NESI (* FLD (i_sr), 0)) {
 {
   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_mulhi.f
+#define FLD(f) abuf->fields.sfmt_st_plus.f
   int UNUSED written = 0;
   IADDR UNUSED pc = abuf->addr;
   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
@@ -1681,7 +1683,7 @@ if (NESI (* FLD (i_sr), 0)) {
 {
   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_mv.f
+#define FLD(f) abuf->fields.sfmt_ld_plus.f
   int UNUSED written = 0;
   IADDR UNUSED pc = abuf->addr;
   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
@@ -1700,7 +1702,7 @@ if (NESI (* FLD (i_sr), 0)) {
 {
   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_mvfachi.f
+#define FLD(f) abuf->fields.sfmt_seth.f
   int UNUSED written = 0;
   IADDR UNUSED pc = abuf->addr;
   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
@@ -1719,7 +1721,7 @@ if (NESI (* FLD (i_sr), 0)) {
 {
   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_mvfachi.f
+#define FLD(f) abuf->fields.sfmt_seth.f
   int UNUSED written = 0;
   IADDR UNUSED pc = abuf->addr;
   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
@@ -1738,7 +1740,7 @@ if (NESI (* FLD (i_sr), 0)) {
 {
   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_mvfachi.f
+#define FLD(f) abuf->fields.sfmt_seth.f
   int UNUSED written = 0;
   IADDR UNUSED pc = abuf->addr;
   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
@@ -1757,7 +1759,7 @@ if (NESI (* FLD (i_sr), 0)) {
 {
   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_mvfc.f
+#define FLD(f) abuf->fields.sfmt_mvfc.f
   int UNUSED written = 0;
   IADDR UNUSED pc = abuf->addr;
   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
@@ -1776,7 +1778,7 @@ if (NESI (* FLD (i_sr), 0)) {
 {
   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_mvtachi.f
+#define FLD(f) abuf->fields.sfmt_st_plus.f
   int UNUSED written = 0;
   IADDR UNUSED pc = abuf->addr;
   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
@@ -1795,7 +1797,7 @@ if (NESI (* FLD (i_sr), 0)) {
 {
   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_mvtachi.f
+#define FLD(f) abuf->fields.sfmt_st_plus.f
   int UNUSED written = 0;
   IADDR UNUSED pc = abuf->addr;
   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
@@ -1814,7 +1816,7 @@ if (NESI (* FLD (i_sr), 0)) {
 {
   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_mvtc.f
+#define FLD(f) abuf->fields.sfmt_mvtc.f
   int UNUSED written = 0;
   IADDR UNUSED pc = abuf->addr;
   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
@@ -1833,7 +1835,7 @@ if (NESI (* FLD (i_sr), 0)) {
 {
   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_mv.f
+#define FLD(f) abuf->fields.sfmt_ld_plus.f
   int UNUSED written = 0;
   IADDR UNUSED pc = abuf->addr;
   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
@@ -1852,7 +1854,7 @@ if (NESI (* FLD (i_sr), 0)) {
 {
   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_nop.f
+#define FLD(f) abuf->fields.fmt_empty.f
   int UNUSED written = 0;
   IADDR UNUSED pc = abuf->addr;
   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
@@ -1867,7 +1869,7 @@ PROFILE_COUNT_FILLNOPS (current_cpu, abuf->addr);
 {
   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_mv.f
+#define FLD(f) abuf->fields.sfmt_ld_plus.f
   int UNUSED written = 0;
   IADDR UNUSED pc = abuf->addr;
   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
@@ -1886,7 +1888,7 @@ PROFILE_COUNT_FILLNOPS (current_cpu, abuf->addr);
 {
   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_rac.f
+#define FLD(f) abuf->fields.fmt_empty.f
   int UNUSED written = 0;
   IADDR UNUSED pc = abuf->addr;
   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
@@ -1910,7 +1912,7 @@ PROFILE_COUNT_FILLNOPS (current_cpu, abuf->addr);
 {
   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_rac.f
+#define FLD(f) abuf->fields.fmt_empty.f
   int UNUSED written = 0;
   IADDR UNUSED pc = abuf->addr;
   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
@@ -1943,7 +1945,7 @@ if (ANDIF (GEDI (tmp_tmp1, MAKEDI (8388608, 0)), LEDI (tmp_tmp1, MAKEDI (1676083
 {
   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.cti.fields.fmt_rte.f
+#define FLD(f) abuf->fields.fmt_empty.f
   int UNUSED written = 0;
   IADDR UNUSED pc = abuf->addr;
   SEM_BRANCH_INIT
@@ -1981,7 +1983,7 @@ if (ANDIF (GEDI (tmp_tmp1, MAKEDI (8388608, 0)), LEDI (tmp_tmp1, MAKEDI (1676083
 {
   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_seth.f
+#define FLD(f) abuf->fields.sfmt_seth.f
   int UNUSED written = 0;
   IADDR UNUSED pc = abuf->addr;
   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
@@ -2000,7 +2002,7 @@ if (ANDIF (GEDI (tmp_tmp1, MAKEDI (8388608, 0)), LEDI (tmp_tmp1, MAKEDI (1676083
 {
   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_add.f
+#define FLD(f) abuf->fields.sfmt_add.f
   int UNUSED written = 0;
   IADDR UNUSED pc = abuf->addr;
   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
@@ -2019,7 +2021,7 @@ if (ANDIF (GEDI (tmp_tmp1, MAKEDI (8388608, 0)), LEDI (tmp_tmp1, MAKEDI (1676083
 {
   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_sll3.f
+#define FLD(f) abuf->fields.sfmt_add3.f
   int UNUSED written = 0;
   IADDR UNUSED pc = abuf->addr;
   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
@@ -2038,7 +2040,7 @@ if (ANDIF (GEDI (tmp_tmp1, MAKEDI (8388608, 0)), LEDI (tmp_tmp1, MAKEDI (1676083
 {
   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_slli.f
+#define FLD(f) abuf->fields.sfmt_slli.f
   int UNUSED written = 0;
   IADDR UNUSED pc = abuf->addr;
   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
@@ -2057,7 +2059,7 @@ if (ANDIF (GEDI (tmp_tmp1, MAKEDI (8388608, 0)), LEDI (tmp_tmp1, MAKEDI (1676083
 {
   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_add.f
+#define FLD(f) abuf->fields.sfmt_add.f
   int UNUSED written = 0;
   IADDR UNUSED pc = abuf->addr;
   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
@@ -2076,7 +2078,7 @@ if (ANDIF (GEDI (tmp_tmp1, MAKEDI (8388608, 0)), LEDI (tmp_tmp1, MAKEDI (1676083
 {
   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_sll3.f
+#define FLD(f) abuf->fields.sfmt_add3.f
   int UNUSED written = 0;
   IADDR UNUSED pc = abuf->addr;
   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
@@ -2095,7 +2097,7 @@ if (ANDIF (GEDI (tmp_tmp1, MAKEDI (8388608, 0)), LEDI (tmp_tmp1, MAKEDI (1676083
 {
   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_slli.f
+#define FLD(f) abuf->fields.sfmt_slli.f
   int UNUSED written = 0;
   IADDR UNUSED pc = abuf->addr;
   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
@@ -2114,7 +2116,7 @@ if (ANDIF (GEDI (tmp_tmp1, MAKEDI (8388608, 0)), LEDI (tmp_tmp1, MAKEDI (1676083
 {
   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_add.f
+#define FLD(f) abuf->fields.sfmt_add.f
   int UNUSED written = 0;
   IADDR UNUSED pc = abuf->addr;
   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
@@ -2133,7 +2135,7 @@ if (ANDIF (GEDI (tmp_tmp1, MAKEDI (8388608, 0)), LEDI (tmp_tmp1, MAKEDI (1676083
 {
   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_sll3.f
+#define FLD(f) abuf->fields.sfmt_add3.f
   int UNUSED written = 0;
   IADDR UNUSED pc = abuf->addr;
   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
@@ -2152,7 +2154,7 @@ if (ANDIF (GEDI (tmp_tmp1, MAKEDI (8388608, 0)), LEDI (tmp_tmp1, MAKEDI (1676083
 {
   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_slli.f
+#define FLD(f) abuf->fields.sfmt_slli.f
   int UNUSED written = 0;
   IADDR UNUSED pc = abuf->addr;
   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
@@ -2171,7 +2173,7 @@ if (ANDIF (GEDI (tmp_tmp1, MAKEDI (8388608, 0)), LEDI (tmp_tmp1, MAKEDI (1676083
 {
   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_st.f
+#define FLD(f) abuf->fields.sfmt_st_plus.f
   int UNUSED written = 0;
   IADDR UNUSED pc = abuf->addr;
   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
@@ -2190,7 +2192,7 @@ if (ANDIF (GEDI (tmp_tmp1, MAKEDI (8388608, 0)), LEDI (tmp_tmp1, MAKEDI (1676083
 {
   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_st_d.f
+#define FLD(f) abuf->fields.sfmt_st_d.f
   int UNUSED written = 0;
   IADDR UNUSED pc = abuf->addr;
   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
@@ -2209,7 +2211,7 @@ if (ANDIF (GEDI (tmp_tmp1, MAKEDI (8388608, 0)), LEDI (tmp_tmp1, MAKEDI (1676083
 {
   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_stb.f
+#define FLD(f) abuf->fields.sfmt_st_plus.f
   int UNUSED written = 0;
   IADDR UNUSED pc = abuf->addr;
   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
@@ -2228,7 +2230,7 @@ if (ANDIF (GEDI (tmp_tmp1, MAKEDI (8388608, 0)), LEDI (tmp_tmp1, MAKEDI (1676083
 {
   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_stb_d.f
+#define FLD(f) abuf->fields.sfmt_st_d.f
   int UNUSED written = 0;
   IADDR UNUSED pc = abuf->addr;
   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
@@ -2247,7 +2249,7 @@ if (ANDIF (GEDI (tmp_tmp1, MAKEDI (8388608, 0)), LEDI (tmp_tmp1, MAKEDI (1676083
 {
   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_sth.f
+#define FLD(f) abuf->fields.sfmt_st_plus.f
   int UNUSED written = 0;
   IADDR UNUSED pc = abuf->addr;
   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
@@ -2266,7 +2268,7 @@ if (ANDIF (GEDI (tmp_tmp1, MAKEDI (8388608, 0)), LEDI (tmp_tmp1, MAKEDI (1676083
 {
   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_sth_d.f
+#define FLD(f) abuf->fields.sfmt_st_d.f
   int UNUSED written = 0;
   IADDR UNUSED pc = abuf->addr;
   vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
@@ -2285,7 +2287,7 @@ if (ANDIF (GEDI (tmp_tmp1, MAKEDI (8388608, 0)), LEDI (tmp_tmp1, MAKEDI (1676083
 {
   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_st_plus.f
+#define FLD(f) abuf->fields.sfmt_st_plus.f
   int UNUSED written = 0;
   IADDR UNUSED pc = abuf->addr;
   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
@@ -2313,7 +2315,7 @@ if (ANDIF (GEDI (tmp_tmp1, MAKEDI (8388608, 0)), LEDI (tmp_tmp1, MAKEDI (1676083
 {
   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_st_plus.f
+#define FLD(f) abuf->fields.sfmt_st_plus.f
   int UNUSED written = 0;
   IADDR UNUSED pc = abuf->addr;
   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
@@ -2341,7 +2343,7 @@ if (ANDIF (GEDI (tmp_tmp1, MAKEDI (8388608, 0)), LEDI (tmp_tmp1, MAKEDI (1676083
 {
   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_add.f
+#define FLD(f) abuf->fields.sfmt_add.f
   int UNUSED written = 0;
   IADDR UNUSED pc = abuf->addr;
   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
@@ -2360,7 +2362,7 @@ if (ANDIF (GEDI (tmp_tmp1, MAKEDI (8388608, 0)), LEDI (tmp_tmp1, MAKEDI (1676083
 {
   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_addv.f
+#define FLD(f) abuf->fields.sfmt_add.f
   int UNUSED written = 0;
   IADDR UNUSED pc = abuf->addr;
   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
@@ -2389,7 +2391,7 @@ if (ANDIF (GEDI (tmp_tmp1, MAKEDI (8388608, 0)), LEDI (tmp_tmp1, MAKEDI (1676083
 {
   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_addx.f
+#define FLD(f) abuf->fields.sfmt_add.f
   int UNUSED written = 0;
   IADDR UNUSED pc = abuf->addr;
   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
@@ -2418,7 +2420,7 @@ if (ANDIF (GEDI (tmp_tmp1, MAKEDI (8388608, 0)), LEDI (tmp_tmp1, MAKEDI (1676083
 {
   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.cti.fields.fmt_trap.f
+#define FLD(f) abuf->fields.sfmt_trap.f
   int UNUSED written = 0;
   IADDR UNUSED pc = abuf->addr;
   SEM_BRANCH_INIT
@@ -2466,7 +2468,7 @@ if (ANDIF (GEDI (tmp_tmp1, MAKEDI (8388608, 0)), LEDI (tmp_tmp1, MAKEDI (1676083
 {
   SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.fmt_unlock.f
+#define FLD(f) abuf->fields.sfmt_st_plus.f
   int UNUSED written = 0;
   IADDR UNUSED pc = abuf->addr;
   vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
diff --git a/sim/m32r/sem.c b/sim/m32r/sem.c
index 03b0a6fc6c3..b337bb86bc7 100644
--- a/sim/m32r/sem.c
+++ b/sim/m32r/sem.c
@@ -32,9 +32,20 @@ with this program; if not, write to the Free Software Foundation, Inc.,
 #undef GET_ATTR
 #define GET_ATTR(cpu, num, attr) CGEN_ATTR_VALUE (NULL, abuf->idesc->attrs, CGEN_INSN_##attr)
 
+/* This is used so that we can compile two copies of the semantic code,
+   one with full feature support and one without that runs fast(er).
+   FAST_P, when desired, is defined on the command line, -DFAST_P=1.  */
+#if FAST_P
+#define SEM_FN_NAME(cpu,fn) XCONCAT3 (cpu,_semf_,fn)
+#undef TRACE_RESULT
+#define TRACE_RESULT(cpu, abuf, name, type, val)
+#else
+#define SEM_FN_NAME(cpu,fn) XCONCAT3 (cpu,_sem_,fn)
+#endif
+
 /* x-invalid: --invalid-- */
 
-SEM_PC
+static SEM_PC
 SEM_FN_NAME (m32rbf,x_invalid) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
 #define FLD(f) abuf->fields.fmt_empty.f
@@ -59,7 +70,7 @@ SEM_FN_NAME (m32rbf,x_invalid) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 
 /* x-after: --after-- */
 
-SEM_PC
+static SEM_PC
 SEM_FN_NAME (m32rbf,x_after) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
 #define FLD(f) abuf->fields.fmt_empty.f
@@ -80,7 +91,7 @@ SEM_FN_NAME (m32rbf,x_after) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 
 /* x-before: --before-- */
 
-SEM_PC
+static SEM_PC
 SEM_FN_NAME (m32rbf,x_before) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
 #define FLD(f) abuf->fields.fmt_empty.f
@@ -101,7 +112,7 @@ SEM_FN_NAME (m32rbf,x_before) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 
 /* x-cti-chain: --cti-chain-- */
 
-SEM_PC
+static SEM_PC
 SEM_FN_NAME (m32rbf,x_cti_chain) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
 #define FLD(f) abuf->fields.fmt_empty.f
@@ -114,12 +125,12 @@ SEM_FN_NAME (m32rbf,x_cti_chain) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 #if WITH_SCACHE_PBB_M32RBF
 #ifdef DEFINE_SWITCH
     vpc = m32rbf_pbb_cti_chain (current_cpu, sem_arg,
-			       pbb_br_npc_ptr, pbb_br_npc);
+			       pbb_br_type, pbb_br_npc);
     BREAK (sem);
 #else
     /* FIXME: Allow provision of explicit ifmt spec in insn spec.  */
     vpc = m32rbf_pbb_cti_chain (current_cpu, sem_arg,
-			       CPU_PBB_BR_NPC_PTR (current_cpu),
+			       CPU_PBB_BR_TYPE (current_cpu),
 			       CPU_PBB_BR_NPC (current_cpu));
 #endif
 #endif
@@ -131,7 +142,7 @@ SEM_FN_NAME (m32rbf,x_cti_chain) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 
 /* x-chain: --chain-- */
 
-SEM_PC
+static SEM_PC
 SEM_FN_NAME (m32rbf,x_chain) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
 #define FLD(f) abuf->fields.fmt_empty.f
@@ -155,7 +166,7 @@ SEM_FN_NAME (m32rbf,x_chain) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 
 /* x-begin: --begin-- */
 
-SEM_PC
+static SEM_PC
 SEM_FN_NAME (m32rbf,x_begin) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
 #define FLD(f) abuf->fields.fmt_empty.f
@@ -182,10 +193,10 @@ SEM_FN_NAME (m32rbf,x_begin) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 
 /* add: add $dr,$sr */
 
-SEM_PC
+static SEM_PC
 SEM_FN_NAME (m32rbf,add) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_add.f
+#define FLD(f) abuf->fields.sfmt_add.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
   int UNUSED written = 0;
   IADDR UNUSED pc = abuf->addr;
@@ -203,10 +214,10 @@ SEM_FN_NAME (m32rbf,add) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 
 /* add3: add3 $dr,$sr,$hash$slo16 */
 
-SEM_PC
+static SEM_PC
 SEM_FN_NAME (m32rbf,add3) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_add3.f
+#define FLD(f) abuf->fields.sfmt_add3.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
   int UNUSED written = 0;
   IADDR UNUSED pc = abuf->addr;
@@ -224,10 +235,10 @@ SEM_FN_NAME (m32rbf,add3) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 
 /* and: and $dr,$sr */
 
-SEM_PC
+static SEM_PC
 SEM_FN_NAME (m32rbf,and) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_add.f
+#define FLD(f) abuf->fields.sfmt_add.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
   int UNUSED written = 0;
   IADDR UNUSED pc = abuf->addr;
@@ -245,10 +256,10 @@ SEM_FN_NAME (m32rbf,and) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 
 /* and3: and3 $dr,$sr,$uimm16 */
 
-SEM_PC
+static SEM_PC
 SEM_FN_NAME (m32rbf,and3) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_and3.f
+#define FLD(f) abuf->fields.sfmt_and3.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
   int UNUSED written = 0;
   IADDR UNUSED pc = abuf->addr;
@@ -266,10 +277,10 @@ SEM_FN_NAME (m32rbf,and3) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 
 /* or: or $dr,$sr */
 
-SEM_PC
+static SEM_PC
 SEM_FN_NAME (m32rbf,or) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_add.f
+#define FLD(f) abuf->fields.sfmt_add.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
   int UNUSED written = 0;
   IADDR UNUSED pc = abuf->addr;
@@ -287,10 +298,10 @@ SEM_FN_NAME (m32rbf,or) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 
 /* or3: or3 $dr,$sr,$hash$ulo16 */
 
-SEM_PC
+static SEM_PC
 SEM_FN_NAME (m32rbf,or3) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_or3.f
+#define FLD(f) abuf->fields.sfmt_and3.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
   int UNUSED written = 0;
   IADDR UNUSED pc = abuf->addr;
@@ -308,10 +319,10 @@ SEM_FN_NAME (m32rbf,or3) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 
 /* xor: xor $dr,$sr */
 
-SEM_PC
+static SEM_PC
 SEM_FN_NAME (m32rbf,xor) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_add.f
+#define FLD(f) abuf->fields.sfmt_add.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
   int UNUSED written = 0;
   IADDR UNUSED pc = abuf->addr;
@@ -329,10 +340,10 @@ SEM_FN_NAME (m32rbf,xor) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 
 /* xor3: xor3 $dr,$sr,$uimm16 */
 
-SEM_PC
+static SEM_PC
 SEM_FN_NAME (m32rbf,xor3) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_and3.f
+#define FLD(f) abuf->fields.sfmt_and3.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
   int UNUSED written = 0;
   IADDR UNUSED pc = abuf->addr;
@@ -350,10 +361,10 @@ SEM_FN_NAME (m32rbf,xor3) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 
 /* addi: addi $dr,$simm8 */
 
-SEM_PC
+static SEM_PC
 SEM_FN_NAME (m32rbf,addi) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_addi.f
+#define FLD(f) abuf->fields.sfmt_addi.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
   int UNUSED written = 0;
   IADDR UNUSED pc = abuf->addr;
@@ -371,10 +382,10 @@ SEM_FN_NAME (m32rbf,addi) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 
 /* addv: addv $dr,$sr */
 
-SEM_PC
+static SEM_PC
 SEM_FN_NAME (m32rbf,addv) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_addv.f
+#define FLD(f) abuf->fields.sfmt_add.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
   int UNUSED written = 0;
   IADDR UNUSED pc = abuf->addr;
@@ -402,10 +413,10 @@ SEM_FN_NAME (m32rbf,addv) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 
 /* addv3: addv3 $dr,$sr,$simm16 */
 
-SEM_PC
+static SEM_PC
 SEM_FN_NAME (m32rbf,addv3) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_addv3.f
+#define FLD(f) abuf->fields.sfmt_add3.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
   int UNUSED written = 0;
   IADDR UNUSED pc = abuf->addr;
@@ -433,10 +444,10 @@ SEM_FN_NAME (m32rbf,addv3) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 
 /* addx: addx $dr,$sr */
 
-SEM_PC
+static SEM_PC
 SEM_FN_NAME (m32rbf,addx) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_addx.f
+#define FLD(f) abuf->fields.sfmt_add.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
   int UNUSED written = 0;
   IADDR UNUSED pc = abuf->addr;
@@ -464,10 +475,10 @@ SEM_FN_NAME (m32rbf,addx) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 
 /* bc8: bc.s $disp8 */
 
-SEM_PC
+static SEM_PC
 SEM_FN_NAME (m32rbf,bc8) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
-#define FLD(f) abuf->fields.cti.fields.fmt_bc8.f
+#define FLD(f) abuf->fields.sfmt_bl8.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
   int UNUSED written = 0;
   IADDR UNUSED pc = abuf->addr;
@@ -477,7 +488,7 @@ SEM_FN_NAME (m32rbf,bc8) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 if (CPU (h_cond)) {
   {
     USI opval = FLD (i_disp8);
-    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
+    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
     written |= (1 << 2);
     TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
   }
@@ -491,10 +502,10 @@ if (CPU (h_cond)) {
 
 /* bc24: bc.l $disp24 */
 
-SEM_PC
+static SEM_PC
 SEM_FN_NAME (m32rbf,bc24) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
-#define FLD(f) abuf->fields.cti.fields.fmt_bc24.f
+#define FLD(f) abuf->fields.sfmt_bl24.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
   int UNUSED written = 0;
   IADDR UNUSED pc = abuf->addr;
@@ -504,7 +515,7 @@ SEM_FN_NAME (m32rbf,bc24) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 if (CPU (h_cond)) {
   {
     USI opval = FLD (i_disp24);
-    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
+    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
     written |= (1 << 2);
     TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
   }
@@ -518,10 +529,10 @@ if (CPU (h_cond)) {
 
 /* beq: beq $src1,$src2,$disp16 */
 
-SEM_PC
+static SEM_PC
 SEM_FN_NAME (m32rbf,beq) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
-#define FLD(f) abuf->fields.cti.fields.fmt_beq.f
+#define FLD(f) abuf->fields.sfmt_beq.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
   int UNUSED written = 0;
   IADDR UNUSED pc = abuf->addr;
@@ -531,7 +542,7 @@ SEM_FN_NAME (m32rbf,beq) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 if (EQSI (* FLD (i_src1), * FLD (i_src2))) {
   {
     USI opval = FLD (i_disp16);
-    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
+    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
     written |= (1 << 3);
     TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
   }
@@ -545,10 +556,10 @@ if (EQSI (* FLD (i_src1), * FLD (i_src2))) {
 
 /* beqz: beqz $src2,$disp16 */
 
-SEM_PC
+static SEM_PC
 SEM_FN_NAME (m32rbf,beqz) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
-#define FLD(f) abuf->fields.cti.fields.fmt_beqz.f
+#define FLD(f) abuf->fields.sfmt_beq.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
   int UNUSED written = 0;
   IADDR UNUSED pc = abuf->addr;
@@ -558,7 +569,7 @@ SEM_FN_NAME (m32rbf,beqz) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 if (EQSI (* FLD (i_src2), 0)) {
   {
     USI opval = FLD (i_disp16);
-    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
+    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
     written |= (1 << 2);
     TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
   }
@@ -572,10 +583,10 @@ if (EQSI (* FLD (i_src2), 0)) {
 
 /* bgez: bgez $src2,$disp16 */
 
-SEM_PC
+static SEM_PC
 SEM_FN_NAME (m32rbf,bgez) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
-#define FLD(f) abuf->fields.cti.fields.fmt_beqz.f
+#define FLD(f) abuf->fields.sfmt_beq.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
   int UNUSED written = 0;
   IADDR UNUSED pc = abuf->addr;
@@ -585,7 +596,7 @@ SEM_FN_NAME (m32rbf,bgez) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 if (GESI (* FLD (i_src2), 0)) {
   {
     USI opval = FLD (i_disp16);
-    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
+    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
     written |= (1 << 2);
     TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
   }
@@ -599,10 +610,10 @@ if (GESI (* FLD (i_src2), 0)) {
 
 /* bgtz: bgtz $src2,$disp16 */
 
-SEM_PC
+static SEM_PC
 SEM_FN_NAME (m32rbf,bgtz) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
-#define FLD(f) abuf->fields.cti.fields.fmt_beqz.f
+#define FLD(f) abuf->fields.sfmt_beq.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
   int UNUSED written = 0;
   IADDR UNUSED pc = abuf->addr;
@@ -612,7 +623,7 @@ SEM_FN_NAME (m32rbf,bgtz) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 if (GTSI (* FLD (i_src2), 0)) {
   {
     USI opval = FLD (i_disp16);
-    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
+    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
     written |= (1 << 2);
     TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
   }
@@ -626,10 +637,10 @@ if (GTSI (* FLD (i_src2), 0)) {
 
 /* blez: blez $src2,$disp16 */
 
-SEM_PC
+static SEM_PC
 SEM_FN_NAME (m32rbf,blez) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
-#define FLD(f) abuf->fields.cti.fields.fmt_beqz.f
+#define FLD(f) abuf->fields.sfmt_beq.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
   int UNUSED written = 0;
   IADDR UNUSED pc = abuf->addr;
@@ -639,7 +650,7 @@ SEM_FN_NAME (m32rbf,blez) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 if (LESI (* FLD (i_src2), 0)) {
   {
     USI opval = FLD (i_disp16);
-    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
+    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
     written |= (1 << 2);
     TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
   }
@@ -653,10 +664,10 @@ if (LESI (* FLD (i_src2), 0)) {
 
 /* bltz: bltz $src2,$disp16 */
 
-SEM_PC
+static SEM_PC
 SEM_FN_NAME (m32rbf,bltz) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
-#define FLD(f) abuf->fields.cti.fields.fmt_beqz.f
+#define FLD(f) abuf->fields.sfmt_beq.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
   int UNUSED written = 0;
   IADDR UNUSED pc = abuf->addr;
@@ -666,7 +677,7 @@ SEM_FN_NAME (m32rbf,bltz) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 if (LTSI (* FLD (i_src2), 0)) {
   {
     USI opval = FLD (i_disp16);
-    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
+    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
     written |= (1 << 2);
     TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
   }
@@ -680,10 +691,10 @@ if (LTSI (* FLD (i_src2), 0)) {
 
 /* bnez: bnez $src2,$disp16 */
 
-SEM_PC
+static SEM_PC
 SEM_FN_NAME (m32rbf,bnez) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
-#define FLD(f) abuf->fields.cti.fields.fmt_beqz.f
+#define FLD(f) abuf->fields.sfmt_beq.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
   int UNUSED written = 0;
   IADDR UNUSED pc = abuf->addr;
@@ -693,7 +704,7 @@ SEM_FN_NAME (m32rbf,bnez) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 if (NESI (* FLD (i_src2), 0)) {
   {
     USI opval = FLD (i_disp16);
-    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
+    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
     written |= (1 << 2);
     TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
   }
@@ -707,10 +718,10 @@ if (NESI (* FLD (i_src2), 0)) {
 
 /* bl8: bl.s $disp8 */
 
-SEM_PC
+static SEM_PC
 SEM_FN_NAME (m32rbf,bl8) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
-#define FLD(f) abuf->fields.cti.fields.fmt_bl8.f
+#define FLD(f) abuf->fields.sfmt_bl8.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
   int UNUSED written = 0;
   IADDR UNUSED pc = abuf->addr;
@@ -725,7 +736,7 @@ SEM_FN_NAME (m32rbf,bl8) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
   }
   {
     USI opval = FLD (i_disp8);
-    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
+    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
     TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
   }
 }
@@ -737,10 +748,10 @@ SEM_FN_NAME (m32rbf,bl8) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 
 /* bl24: bl.l $disp24 */
 
-SEM_PC
+static SEM_PC
 SEM_FN_NAME (m32rbf,bl24) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
-#define FLD(f) abuf->fields.cti.fields.fmt_bl24.f
+#define FLD(f) abuf->fields.sfmt_bl24.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
   int UNUSED written = 0;
   IADDR UNUSED pc = abuf->addr;
@@ -755,7 +766,7 @@ SEM_FN_NAME (m32rbf,bl24) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
   }
   {
     USI opval = FLD (i_disp24);
-    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
+    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
     TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
   }
 }
@@ -767,10 +778,10 @@ SEM_FN_NAME (m32rbf,bl24) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 
 /* bnc8: bnc.s $disp8 */
 
-SEM_PC
+static SEM_PC
 SEM_FN_NAME (m32rbf,bnc8) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
-#define FLD(f) abuf->fields.cti.fields.fmt_bc8.f
+#define FLD(f) abuf->fields.sfmt_bl8.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
   int UNUSED written = 0;
   IADDR UNUSED pc = abuf->addr;
@@ -780,7 +791,7 @@ SEM_FN_NAME (m32rbf,bnc8) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 if (NOTBI (CPU (h_cond))) {
   {
     USI opval = FLD (i_disp8);
-    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
+    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
     written |= (1 << 2);
     TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
   }
@@ -794,10 +805,10 @@ if (NOTBI (CPU (h_cond))) {
 
 /* bnc24: bnc.l $disp24 */
 
-SEM_PC
+static SEM_PC
 SEM_FN_NAME (m32rbf,bnc24) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
-#define FLD(f) abuf->fields.cti.fields.fmt_bc24.f
+#define FLD(f) abuf->fields.sfmt_bl24.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
   int UNUSED written = 0;
   IADDR UNUSED pc = abuf->addr;
@@ -807,7 +818,7 @@ SEM_FN_NAME (m32rbf,bnc24) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 if (NOTBI (CPU (h_cond))) {
   {
     USI opval = FLD (i_disp24);
-    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
+    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
     written |= (1 << 2);
     TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
   }
@@ -821,10 +832,10 @@ if (NOTBI (CPU (h_cond))) {
 
 /* bne: bne $src1,$src2,$disp16 */
 
-SEM_PC
+static SEM_PC
 SEM_FN_NAME (m32rbf,bne) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
-#define FLD(f) abuf->fields.cti.fields.fmt_beq.f
+#define FLD(f) abuf->fields.sfmt_beq.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
   int UNUSED written = 0;
   IADDR UNUSED pc = abuf->addr;
@@ -834,7 +845,7 @@ SEM_FN_NAME (m32rbf,bne) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 if (NESI (* FLD (i_src1), * FLD (i_src2))) {
   {
     USI opval = FLD (i_disp16);
-    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
+    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
     written |= (1 << 3);
     TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
   }
@@ -848,10 +859,10 @@ if (NESI (* FLD (i_src1), * FLD (i_src2))) {
 
 /* bra8: bra.s $disp8 */
 
-SEM_PC
+static SEM_PC
 SEM_FN_NAME (m32rbf,bra8) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
-#define FLD(f) abuf->fields.cti.fields.fmt_bra8.f
+#define FLD(f) abuf->fields.sfmt_bl8.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
   int UNUSED written = 0;
   IADDR UNUSED pc = abuf->addr;
@@ -860,7 +871,7 @@ SEM_FN_NAME (m32rbf,bra8) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 
   {
     USI opval = FLD (i_disp8);
-    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
+    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
     TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
   }
 
@@ -871,10 +882,10 @@ SEM_FN_NAME (m32rbf,bra8) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 
 /* bra24: bra.l $disp24 */
 
-SEM_PC
+static SEM_PC
 SEM_FN_NAME (m32rbf,bra24) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
-#define FLD(f) abuf->fields.cti.fields.fmt_bra24.f
+#define FLD(f) abuf->fields.sfmt_bl24.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
   int UNUSED written = 0;
   IADDR UNUSED pc = abuf->addr;
@@ -883,7 +894,7 @@ SEM_FN_NAME (m32rbf,bra24) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 
   {
     USI opval = FLD (i_disp24);
-    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
+    SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
     TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
   }
 
@@ -894,10 +905,10 @@ SEM_FN_NAME (m32rbf,bra24) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 
 /* cmp: cmp $src1,$src2 */
 
-SEM_PC
+static SEM_PC
 SEM_FN_NAME (m32rbf,cmp) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_cmp.f
+#define FLD(f) abuf->fields.sfmt_st_plus.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
   int UNUSED written = 0;
   IADDR UNUSED pc = abuf->addr;
@@ -915,10 +926,10 @@ SEM_FN_NAME (m32rbf,cmp) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 
 /* cmpi: cmpi $src2,$simm16 */
 
-SEM_PC
+static SEM_PC
 SEM_FN_NAME (m32rbf,cmpi) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_cmpi.f
+#define FLD(f) abuf->fields.sfmt_st_d.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
   int UNUSED written = 0;
   IADDR UNUSED pc = abuf->addr;
@@ -936,10 +947,10 @@ SEM_FN_NAME (m32rbf,cmpi) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 
 /* cmpu: cmpu $src1,$src2 */
 
-SEM_PC
+static SEM_PC
 SEM_FN_NAME (m32rbf,cmpu) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_cmp.f
+#define FLD(f) abuf->fields.sfmt_st_plus.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
   int UNUSED written = 0;
   IADDR UNUSED pc = abuf->addr;
@@ -957,10 +968,10 @@ SEM_FN_NAME (m32rbf,cmpu) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 
 /* cmpui: cmpui $src2,$simm16 */
 
-SEM_PC
+static SEM_PC
 SEM_FN_NAME (m32rbf,cmpui) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_cmpi.f
+#define FLD(f) abuf->fields.sfmt_st_d.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
   int UNUSED written = 0;
   IADDR UNUSED pc = abuf->addr;
@@ -978,10 +989,10 @@ SEM_FN_NAME (m32rbf,cmpui) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 
 /* div: div $dr,$sr */
 
-SEM_PC
+static SEM_PC
 SEM_FN_NAME (m32rbf,div) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_div.f
+#define FLD(f) abuf->fields.sfmt_add.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
   int UNUSED written = 0;
   IADDR UNUSED pc = abuf->addr;
@@ -1003,10 +1014,10 @@ if (NESI (* FLD (i_sr), 0)) {
 
 /* divu: divu $dr,$sr */
 
-SEM_PC
+static SEM_PC
 SEM_FN_NAME (m32rbf,divu) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_div.f
+#define FLD(f) abuf->fields.sfmt_add.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
   int UNUSED written = 0;
   IADDR UNUSED pc = abuf->addr;
@@ -1028,10 +1039,10 @@ if (NESI (* FLD (i_sr), 0)) {
 
 /* rem: rem $dr,$sr */
 
-SEM_PC
+static SEM_PC
 SEM_FN_NAME (m32rbf,rem) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_div.f
+#define FLD(f) abuf->fields.sfmt_add.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
   int UNUSED written = 0;
   IADDR UNUSED pc = abuf->addr;
@@ -1053,10 +1064,10 @@ if (NESI (* FLD (i_sr), 0)) {
 
 /* remu: remu $dr,$sr */
 
-SEM_PC
+static SEM_PC
 SEM_FN_NAME (m32rbf,remu) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_div.f
+#define FLD(f) abuf->fields.sfmt_add.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
   int UNUSED written = 0;
   IADDR UNUSED pc = abuf->addr;
@@ -1078,10 +1089,10 @@ if (NESI (* FLD (i_sr), 0)) {
 
 /* jl: jl $sr */
 
-SEM_PC
+static SEM_PC
 SEM_FN_NAME (m32rbf,jl) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
-#define FLD(f) abuf->fields.cti.fields.fmt_jl.f
+#define FLD(f) abuf->fields.sfmt_jl.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
   int UNUSED written = 0;
   IADDR UNUSED pc = abuf->addr;
@@ -1111,10 +1122,10 @@ SEM_FN_NAME (m32rbf,jl) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 
 /* jmp: jmp $sr */
 
-SEM_PC
+static SEM_PC
 SEM_FN_NAME (m32rbf,jmp) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
-#define FLD(f) abuf->fields.cti.fields.fmt_jmp.f
+#define FLD(f) abuf->fields.sfmt_mvtc.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
   int UNUSED written = 0;
   IADDR UNUSED pc = abuf->addr;
@@ -1134,10 +1145,10 @@ SEM_FN_NAME (m32rbf,jmp) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 
 /* ld: ld $dr,@$sr */
 
-SEM_PC
+static SEM_PC
 SEM_FN_NAME (m32rbf,ld) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_ld.f
+#define FLD(f) abuf->fields.sfmt_ld_plus.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
   int UNUSED written = 0;
   IADDR UNUSED pc = abuf->addr;
@@ -1155,10 +1166,10 @@ SEM_FN_NAME (m32rbf,ld) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 
 /* ld-d: ld $dr,@($slo16,$sr) */
 
-SEM_PC
+static SEM_PC
 SEM_FN_NAME (m32rbf,ld_d) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_ld_d.f
+#define FLD(f) abuf->fields.sfmt_add3.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
   int UNUSED written = 0;
   IADDR UNUSED pc = abuf->addr;
@@ -1176,10 +1187,10 @@ SEM_FN_NAME (m32rbf,ld_d) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 
 /* ldb: ldb $dr,@$sr */
 
-SEM_PC
+static SEM_PC
 SEM_FN_NAME (m32rbf,ldb) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_ldb.f
+#define FLD(f) abuf->fields.sfmt_ld_plus.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
   int UNUSED written = 0;
   IADDR UNUSED pc = abuf->addr;
@@ -1197,10 +1208,10 @@ SEM_FN_NAME (m32rbf,ldb) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 
 /* ldb-d: ldb $dr,@($slo16,$sr) */
 
-SEM_PC
+static SEM_PC
 SEM_FN_NAME (m32rbf,ldb_d) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_ldb_d.f
+#define FLD(f) abuf->fields.sfmt_add3.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
   int UNUSED written = 0;
   IADDR UNUSED pc = abuf->addr;
@@ -1218,10 +1229,10 @@ SEM_FN_NAME (m32rbf,ldb_d) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 
 /* ldh: ldh $dr,@$sr */
 
-SEM_PC
+static SEM_PC
 SEM_FN_NAME (m32rbf,ldh) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_ldh.f
+#define FLD(f) abuf->fields.sfmt_ld_plus.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
   int UNUSED written = 0;
   IADDR UNUSED pc = abuf->addr;
@@ -1239,10 +1250,10 @@ SEM_FN_NAME (m32rbf,ldh) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 
 /* ldh-d: ldh $dr,@($slo16,$sr) */
 
-SEM_PC
+static SEM_PC
 SEM_FN_NAME (m32rbf,ldh_d) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_ldh_d.f
+#define FLD(f) abuf->fields.sfmt_add3.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
   int UNUSED written = 0;
   IADDR UNUSED pc = abuf->addr;
@@ -1260,10 +1271,10 @@ SEM_FN_NAME (m32rbf,ldh_d) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 
 /* ldub: ldub $dr,@$sr */
 
-SEM_PC
+static SEM_PC
 SEM_FN_NAME (m32rbf,ldub) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_ldb.f
+#define FLD(f) abuf->fields.sfmt_ld_plus.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
   int UNUSED written = 0;
   IADDR UNUSED pc = abuf->addr;
@@ -1281,10 +1292,10 @@ SEM_FN_NAME (m32rbf,ldub) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 
 /* ldub-d: ldub $dr,@($slo16,$sr) */
 
-SEM_PC
+static SEM_PC
 SEM_FN_NAME (m32rbf,ldub_d) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_ldb_d.f
+#define FLD(f) abuf->fields.sfmt_add3.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
   int UNUSED written = 0;
   IADDR UNUSED pc = abuf->addr;
@@ -1302,10 +1313,10 @@ SEM_FN_NAME (m32rbf,ldub_d) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 
 /* lduh: lduh $dr,@$sr */
 
-SEM_PC
+static SEM_PC
 SEM_FN_NAME (m32rbf,lduh) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_ldh.f
+#define FLD(f) abuf->fields.sfmt_ld_plus.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
   int UNUSED written = 0;
   IADDR UNUSED pc = abuf->addr;
@@ -1323,10 +1334,10 @@ SEM_FN_NAME (m32rbf,lduh) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 
 /* lduh-d: lduh $dr,@($slo16,$sr) */
 
-SEM_PC
+static SEM_PC
 SEM_FN_NAME (m32rbf,lduh_d) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_ldh_d.f
+#define FLD(f) abuf->fields.sfmt_add3.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
   int UNUSED written = 0;
   IADDR UNUSED pc = abuf->addr;
@@ -1344,10 +1355,10 @@ SEM_FN_NAME (m32rbf,lduh_d) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 
 /* ld-plus: ld $dr,@$sr+ */
 
-SEM_PC
+static SEM_PC
 SEM_FN_NAME (m32rbf,ld_plus) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_ld_plus.f
+#define FLD(f) abuf->fields.sfmt_ld_plus.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
   int UNUSED written = 0;
   IADDR UNUSED pc = abuf->addr;
@@ -1375,10 +1386,10 @@ SEM_FN_NAME (m32rbf,ld_plus) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 
 /* ld24: ld24 $dr,$uimm24 */
 
-SEM_PC
+static SEM_PC
 SEM_FN_NAME (m32rbf,ld24) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_ld24.f
+#define FLD(f) abuf->fields.sfmt_ld24.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
   int UNUSED written = 0;
   IADDR UNUSED pc = abuf->addr;
@@ -1396,10 +1407,10 @@ SEM_FN_NAME (m32rbf,ld24) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 
 /* ldi8: ldi8 $dr,$simm8 */
 
-SEM_PC
+static SEM_PC
 SEM_FN_NAME (m32rbf,ldi8) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_ldi8.f
+#define FLD(f) abuf->fields.sfmt_addi.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
   int UNUSED written = 0;
   IADDR UNUSED pc = abuf->addr;
@@ -1417,10 +1428,10 @@ SEM_FN_NAME (m32rbf,ldi8) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 
 /* ldi16: ldi16 $dr,$hash$slo16 */
 
-SEM_PC
+static SEM_PC
 SEM_FN_NAME (m32rbf,ldi16) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_ldi16.f
+#define FLD(f) abuf->fields.sfmt_add3.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
   int UNUSED written = 0;
   IADDR UNUSED pc = abuf->addr;
@@ -1438,10 +1449,10 @@ SEM_FN_NAME (m32rbf,ldi16) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 
 /* lock: lock $dr,@$sr */
 
-SEM_PC
+static SEM_PC
 SEM_FN_NAME (m32rbf,lock) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_lock.f
+#define FLD(f) abuf->fields.sfmt_ld_plus.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
   int UNUSED written = 0;
   IADDR UNUSED pc = abuf->addr;
@@ -1466,10 +1477,10 @@ SEM_FN_NAME (m32rbf,lock) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 
 /* machi: machi $src1,$src2 */
 
-SEM_PC
+static SEM_PC
 SEM_FN_NAME (m32rbf,machi) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_machi.f
+#define FLD(f) abuf->fields.sfmt_st_plus.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
   int UNUSED written = 0;
   IADDR UNUSED pc = abuf->addr;
@@ -1487,10 +1498,10 @@ SEM_FN_NAME (m32rbf,machi) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 
 /* maclo: maclo $src1,$src2 */
 
-SEM_PC
+static SEM_PC
 SEM_FN_NAME (m32rbf,maclo) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_machi.f
+#define FLD(f) abuf->fields.sfmt_st_plus.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
   int UNUSED written = 0;
   IADDR UNUSED pc = abuf->addr;
@@ -1508,10 +1519,10 @@ SEM_FN_NAME (m32rbf,maclo) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 
 /* macwhi: macwhi $src1,$src2 */
 
-SEM_PC
+static SEM_PC
 SEM_FN_NAME (m32rbf,macwhi) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_machi.f
+#define FLD(f) abuf->fields.sfmt_st_plus.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
   int UNUSED written = 0;
   IADDR UNUSED pc = abuf->addr;
@@ -1529,10 +1540,10 @@ SEM_FN_NAME (m32rbf,macwhi) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 
 /* macwlo: macwlo $src1,$src2 */
 
-SEM_PC
+static SEM_PC
 SEM_FN_NAME (m32rbf,macwlo) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_machi.f
+#define FLD(f) abuf->fields.sfmt_st_plus.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
   int UNUSED written = 0;
   IADDR UNUSED pc = abuf->addr;
@@ -1550,10 +1561,10 @@ SEM_FN_NAME (m32rbf,macwlo) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 
 /* mul: mul $dr,$sr */
 
-SEM_PC
+static SEM_PC
 SEM_FN_NAME (m32rbf,mul) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_add.f
+#define FLD(f) abuf->fields.sfmt_add.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
   int UNUSED written = 0;
   IADDR UNUSED pc = abuf->addr;
@@ -1571,10 +1582,10 @@ SEM_FN_NAME (m32rbf,mul) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 
 /* mulhi: mulhi $src1,$src2 */
 
-SEM_PC
+static SEM_PC
 SEM_FN_NAME (m32rbf,mulhi) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_mulhi.f
+#define FLD(f) abuf->fields.sfmt_st_plus.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
   int UNUSED written = 0;
   IADDR UNUSED pc = abuf->addr;
@@ -1592,10 +1603,10 @@ SEM_FN_NAME (m32rbf,mulhi) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 
 /* mullo: mullo $src1,$src2 */
 
-SEM_PC
+static SEM_PC
 SEM_FN_NAME (m32rbf,mullo) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_mulhi.f
+#define FLD(f) abuf->fields.sfmt_st_plus.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
   int UNUSED written = 0;
   IADDR UNUSED pc = abuf->addr;
@@ -1613,10 +1624,10 @@ SEM_FN_NAME (m32rbf,mullo) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 
 /* mulwhi: mulwhi $src1,$src2 */
 
-SEM_PC
+static SEM_PC
 SEM_FN_NAME (m32rbf,mulwhi) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_mulhi.f
+#define FLD(f) abuf->fields.sfmt_st_plus.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
   int UNUSED written = 0;
   IADDR UNUSED pc = abuf->addr;
@@ -1634,10 +1645,10 @@ SEM_FN_NAME (m32rbf,mulwhi) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 
 /* mulwlo: mulwlo $src1,$src2 */
 
-SEM_PC
+static SEM_PC
 SEM_FN_NAME (m32rbf,mulwlo) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_mulhi.f
+#define FLD(f) abuf->fields.sfmt_st_plus.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
   int UNUSED written = 0;
   IADDR UNUSED pc = abuf->addr;
@@ -1655,10 +1666,10 @@ SEM_FN_NAME (m32rbf,mulwlo) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 
 /* mv: mv $dr,$sr */
 
-SEM_PC
+static SEM_PC
 SEM_FN_NAME (m32rbf,mv) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_mv.f
+#define FLD(f) abuf->fields.sfmt_ld_plus.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
   int UNUSED written = 0;
   IADDR UNUSED pc = abuf->addr;
@@ -1676,10 +1687,10 @@ SEM_FN_NAME (m32rbf,mv) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 
 /* mvfachi: mvfachi $dr */
 
-SEM_PC
+static SEM_PC
 SEM_FN_NAME (m32rbf,mvfachi) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_mvfachi.f
+#define FLD(f) abuf->fields.sfmt_seth.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
   int UNUSED written = 0;
   IADDR UNUSED pc = abuf->addr;
@@ -1697,10 +1708,10 @@ SEM_FN_NAME (m32rbf,mvfachi) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 
 /* mvfaclo: mvfaclo $dr */
 
-SEM_PC
+static SEM_PC
 SEM_FN_NAME (m32rbf,mvfaclo) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_mvfachi.f
+#define FLD(f) abuf->fields.sfmt_seth.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
   int UNUSED written = 0;
   IADDR UNUSED pc = abuf->addr;
@@ -1718,10 +1729,10 @@ SEM_FN_NAME (m32rbf,mvfaclo) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 
 /* mvfacmi: mvfacmi $dr */
 
-SEM_PC
+static SEM_PC
 SEM_FN_NAME (m32rbf,mvfacmi) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_mvfachi.f
+#define FLD(f) abuf->fields.sfmt_seth.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
   int UNUSED written = 0;
   IADDR UNUSED pc = abuf->addr;
@@ -1739,10 +1750,10 @@ SEM_FN_NAME (m32rbf,mvfacmi) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 
 /* mvfc: mvfc $dr,$scr */
 
-SEM_PC
+static SEM_PC
 SEM_FN_NAME (m32rbf,mvfc) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_mvfc.f
+#define FLD(f) abuf->fields.sfmt_mvfc.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
   int UNUSED written = 0;
   IADDR UNUSED pc = abuf->addr;
@@ -1760,10 +1771,10 @@ SEM_FN_NAME (m32rbf,mvfc) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 
 /* mvtachi: mvtachi $src1 */
 
-SEM_PC
+static SEM_PC
 SEM_FN_NAME (m32rbf,mvtachi) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_mvtachi.f
+#define FLD(f) abuf->fields.sfmt_st_plus.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
   int UNUSED written = 0;
   IADDR UNUSED pc = abuf->addr;
@@ -1781,10 +1792,10 @@ SEM_FN_NAME (m32rbf,mvtachi) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 
 /* mvtaclo: mvtaclo $src1 */
 
-SEM_PC
+static SEM_PC
 SEM_FN_NAME (m32rbf,mvtaclo) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_mvtachi.f
+#define FLD(f) abuf->fields.sfmt_st_plus.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
   int UNUSED written = 0;
   IADDR UNUSED pc = abuf->addr;
@@ -1802,10 +1813,10 @@ SEM_FN_NAME (m32rbf,mvtaclo) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 
 /* mvtc: mvtc $sr,$dcr */
 
-SEM_PC
+static SEM_PC
 SEM_FN_NAME (m32rbf,mvtc) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_mvtc.f
+#define FLD(f) abuf->fields.sfmt_mvtc.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
   int UNUSED written = 0;
   IADDR UNUSED pc = abuf->addr;
@@ -1823,10 +1834,10 @@ SEM_FN_NAME (m32rbf,mvtc) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 
 /* neg: neg $dr,$sr */
 
-SEM_PC
+static SEM_PC
 SEM_FN_NAME (m32rbf,neg) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_mv.f
+#define FLD(f) abuf->fields.sfmt_ld_plus.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
   int UNUSED written = 0;
   IADDR UNUSED pc = abuf->addr;
@@ -1844,10 +1855,10 @@ SEM_FN_NAME (m32rbf,neg) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 
 /* nop: nop */
 
-SEM_PC
+static SEM_PC
 SEM_FN_NAME (m32rbf,nop) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_nop.f
+#define FLD(f) abuf->fields.fmt_empty.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
   int UNUSED written = 0;
   IADDR UNUSED pc = abuf->addr;
@@ -1861,10 +1872,10 @@ PROFILE_COUNT_FILLNOPS (current_cpu, abuf->addr);
 
 /* not: not $dr,$sr */
 
-SEM_PC
+static SEM_PC
 SEM_FN_NAME (m32rbf,not) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_mv.f
+#define FLD(f) abuf->fields.sfmt_ld_plus.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
   int UNUSED written = 0;
   IADDR UNUSED pc = abuf->addr;
@@ -1882,10 +1893,10 @@ SEM_FN_NAME (m32rbf,not) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 
 /* rac: rac */
 
-SEM_PC
+static SEM_PC
 SEM_FN_NAME (m32rbf,rac) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_rac.f
+#define FLD(f) abuf->fields.fmt_empty.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
   int UNUSED written = 0;
   IADDR UNUSED pc = abuf->addr;
@@ -1908,10 +1919,10 @@ SEM_FN_NAME (m32rbf,rac) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 
 /* rach: rach */
 
-SEM_PC
+static SEM_PC
 SEM_FN_NAME (m32rbf,rach) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_rac.f
+#define FLD(f) abuf->fields.fmt_empty.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
   int UNUSED written = 0;
   IADDR UNUSED pc = abuf->addr;
@@ -1943,10 +1954,10 @@ if (ANDIF (GEDI (tmp_tmp1, MAKEDI (8388608, 0)), LEDI (tmp_tmp1, MAKEDI (1676083
 
 /* rte: rte */
 
-SEM_PC
+static SEM_PC
 SEM_FN_NAME (m32rbf,rte) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
-#define FLD(f) abuf->fields.cti.fields.fmt_rte.f
+#define FLD(f) abuf->fields.fmt_empty.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
   int UNUSED written = 0;
   IADDR UNUSED pc = abuf->addr;
@@ -1983,10 +1994,10 @@ SEM_FN_NAME (m32rbf,rte) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 
 /* seth: seth $dr,$hash$hi16 */
 
-SEM_PC
+static SEM_PC
 SEM_FN_NAME (m32rbf,seth) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_seth.f
+#define FLD(f) abuf->fields.sfmt_seth.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
   int UNUSED written = 0;
   IADDR UNUSED pc = abuf->addr;
@@ -2004,10 +2015,10 @@ SEM_FN_NAME (m32rbf,seth) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 
 /* sll: sll $dr,$sr */
 
-SEM_PC
+static SEM_PC
 SEM_FN_NAME (m32rbf,sll) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_add.f
+#define FLD(f) abuf->fields.sfmt_add.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
   int UNUSED written = 0;
   IADDR UNUSED pc = abuf->addr;
@@ -2025,10 +2036,10 @@ SEM_FN_NAME (m32rbf,sll) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 
 /* sll3: sll3 $dr,$sr,$simm16 */
 
-SEM_PC
+static SEM_PC
 SEM_FN_NAME (m32rbf,sll3) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_sll3.f
+#define FLD(f) abuf->fields.sfmt_add3.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
   int UNUSED written = 0;
   IADDR UNUSED pc = abuf->addr;
@@ -2046,10 +2057,10 @@ SEM_FN_NAME (m32rbf,sll3) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 
 /* slli: slli $dr,$uimm5 */
 
-SEM_PC
+static SEM_PC
 SEM_FN_NAME (m32rbf,slli) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_slli.f
+#define FLD(f) abuf->fields.sfmt_slli.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
   int UNUSED written = 0;
   IADDR UNUSED pc = abuf->addr;
@@ -2067,10 +2078,10 @@ SEM_FN_NAME (m32rbf,slli) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 
 /* sra: sra $dr,$sr */
 
-SEM_PC
+static SEM_PC
 SEM_FN_NAME (m32rbf,sra) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_add.f
+#define FLD(f) abuf->fields.sfmt_add.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
   int UNUSED written = 0;
   IADDR UNUSED pc = abuf->addr;
@@ -2088,10 +2099,10 @@ SEM_FN_NAME (m32rbf,sra) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 
 /* sra3: sra3 $dr,$sr,$simm16 */
 
-SEM_PC
+static SEM_PC
 SEM_FN_NAME (m32rbf,sra3) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_sll3.f
+#define FLD(f) abuf->fields.sfmt_add3.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
   int UNUSED written = 0;
   IADDR UNUSED pc = abuf->addr;
@@ -2109,10 +2120,10 @@ SEM_FN_NAME (m32rbf,sra3) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 
 /* srai: srai $dr,$uimm5 */
 
-SEM_PC
+static SEM_PC
 SEM_FN_NAME (m32rbf,srai) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_slli.f
+#define FLD(f) abuf->fields.sfmt_slli.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
   int UNUSED written = 0;
   IADDR UNUSED pc = abuf->addr;
@@ -2130,10 +2141,10 @@ SEM_FN_NAME (m32rbf,srai) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 
 /* srl: srl $dr,$sr */
 
-SEM_PC
+static SEM_PC
 SEM_FN_NAME (m32rbf,srl) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_add.f
+#define FLD(f) abuf->fields.sfmt_add.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
   int UNUSED written = 0;
   IADDR UNUSED pc = abuf->addr;
@@ -2151,10 +2162,10 @@ SEM_FN_NAME (m32rbf,srl) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 
 /* srl3: srl3 $dr,$sr,$simm16 */
 
-SEM_PC
+static SEM_PC
 SEM_FN_NAME (m32rbf,srl3) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_sll3.f
+#define FLD(f) abuf->fields.sfmt_add3.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
   int UNUSED written = 0;
   IADDR UNUSED pc = abuf->addr;
@@ -2172,10 +2183,10 @@ SEM_FN_NAME (m32rbf,srl3) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 
 /* srli: srli $dr,$uimm5 */
 
-SEM_PC
+static SEM_PC
 SEM_FN_NAME (m32rbf,srli) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_slli.f
+#define FLD(f) abuf->fields.sfmt_slli.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
   int UNUSED written = 0;
   IADDR UNUSED pc = abuf->addr;
@@ -2193,10 +2204,10 @@ SEM_FN_NAME (m32rbf,srli) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 
 /* st: st $src1,@$src2 */
 
-SEM_PC
+static SEM_PC
 SEM_FN_NAME (m32rbf,st) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_st.f
+#define FLD(f) abuf->fields.sfmt_st_plus.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
   int UNUSED written = 0;
   IADDR UNUSED pc = abuf->addr;
@@ -2214,10 +2225,10 @@ SEM_FN_NAME (m32rbf,st) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 
 /* st-d: st $src1,@($slo16,$src2) */
 
-SEM_PC
+static SEM_PC
 SEM_FN_NAME (m32rbf,st_d) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_st_d.f
+#define FLD(f) abuf->fields.sfmt_st_d.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
   int UNUSED written = 0;
   IADDR UNUSED pc = abuf->addr;
@@ -2235,10 +2246,10 @@ SEM_FN_NAME (m32rbf,st_d) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 
 /* stb: stb $src1,@$src2 */
 
-SEM_PC
+static SEM_PC
 SEM_FN_NAME (m32rbf,stb) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_stb.f
+#define FLD(f) abuf->fields.sfmt_st_plus.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
   int UNUSED written = 0;
   IADDR UNUSED pc = abuf->addr;
@@ -2256,10 +2267,10 @@ SEM_FN_NAME (m32rbf,stb) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 
 /* stb-d: stb $src1,@($slo16,$src2) */
 
-SEM_PC
+static SEM_PC
 SEM_FN_NAME (m32rbf,stb_d) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_stb_d.f
+#define FLD(f) abuf->fields.sfmt_st_d.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
   int UNUSED written = 0;
   IADDR UNUSED pc = abuf->addr;
@@ -2277,10 +2288,10 @@ SEM_FN_NAME (m32rbf,stb_d) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 
 /* sth: sth $src1,@$src2 */
 
-SEM_PC
+static SEM_PC
 SEM_FN_NAME (m32rbf,sth) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_sth.f
+#define FLD(f) abuf->fields.sfmt_st_plus.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
   int UNUSED written = 0;
   IADDR UNUSED pc = abuf->addr;
@@ -2298,10 +2309,10 @@ SEM_FN_NAME (m32rbf,sth) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 
 /* sth-d: sth $src1,@($slo16,$src2) */
 
-SEM_PC
+static SEM_PC
 SEM_FN_NAME (m32rbf,sth_d) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_sth_d.f
+#define FLD(f) abuf->fields.sfmt_st_d.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
   int UNUSED written = 0;
   IADDR UNUSED pc = abuf->addr;
@@ -2319,10 +2330,10 @@ SEM_FN_NAME (m32rbf,sth_d) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 
 /* st-plus: st $src1,@+$src2 */
 
-SEM_PC
+static SEM_PC
 SEM_FN_NAME (m32rbf,st_plus) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_st_plus.f
+#define FLD(f) abuf->fields.sfmt_st_plus.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
   int UNUSED written = 0;
   IADDR UNUSED pc = abuf->addr;
@@ -2349,10 +2360,10 @@ SEM_FN_NAME (m32rbf,st_plus) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 
 /* st-minus: st $src1,@-$src2 */
 
-SEM_PC
+static SEM_PC
 SEM_FN_NAME (m32rbf,st_minus) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_st_plus.f
+#define FLD(f) abuf->fields.sfmt_st_plus.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
   int UNUSED written = 0;
   IADDR UNUSED pc = abuf->addr;
@@ -2379,10 +2390,10 @@ SEM_FN_NAME (m32rbf,st_minus) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 
 /* sub: sub $dr,$sr */
 
-SEM_PC
+static SEM_PC
 SEM_FN_NAME (m32rbf,sub) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_add.f
+#define FLD(f) abuf->fields.sfmt_add.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
   int UNUSED written = 0;
   IADDR UNUSED pc = abuf->addr;
@@ -2400,10 +2411,10 @@ SEM_FN_NAME (m32rbf,sub) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 
 /* subv: subv $dr,$sr */
 
-SEM_PC
+static SEM_PC
 SEM_FN_NAME (m32rbf,subv) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_addv.f
+#define FLD(f) abuf->fields.sfmt_add.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
   int UNUSED written = 0;
   IADDR UNUSED pc = abuf->addr;
@@ -2431,10 +2442,10 @@ SEM_FN_NAME (m32rbf,subv) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 
 /* subx: subx $dr,$sr */
 
-SEM_PC
+static SEM_PC
 SEM_FN_NAME (m32rbf,subx) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_addx.f
+#define FLD(f) abuf->fields.sfmt_add.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
   int UNUSED written = 0;
   IADDR UNUSED pc = abuf->addr;
@@ -2462,10 +2473,10 @@ SEM_FN_NAME (m32rbf,subx) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 
 /* trap: trap $uimm4 */
 
-SEM_PC
+static SEM_PC
 SEM_FN_NAME (m32rbf,trap) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
-#define FLD(f) abuf->fields.cti.fields.fmt_trap.f
+#define FLD(f) abuf->fields.sfmt_trap.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
   int UNUSED written = 0;
   IADDR UNUSED pc = abuf->addr;
@@ -2512,10 +2523,10 @@ SEM_FN_NAME (m32rbf,trap) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 
 /* unlock: unlock $src1,@$src2 */
 
-SEM_PC
+static SEM_PC
 SEM_FN_NAME (m32rbf,unlock) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_unlock.f
+#define FLD(f) abuf->fields.sfmt_st_plus.f
   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
   int UNUSED written = 0;
   IADDR UNUSED pc = abuf->addr;
@@ -2542,3 +2553,132 @@ if (CPU (h_lock)) {
 #undef FLD
 }
 
+/* Table of all semantic fns.  */
+
+static const struct sem_fn_desc sem_fns[] = {
+  { M32RBF_INSN_X_INVALID, SEM_FN_NAME (m32rbf,x_invalid) },
+  { M32RBF_INSN_X_AFTER, SEM_FN_NAME (m32rbf,x_after) },
+  { M32RBF_INSN_X_BEFORE, SEM_FN_NAME (m32rbf,x_before) },
+  { M32RBF_INSN_X_CTI_CHAIN, SEM_FN_NAME (m32rbf,x_cti_chain) },
+  { M32RBF_INSN_X_CHAIN, SEM_FN_NAME (m32rbf,x_chain) },
+  { M32RBF_INSN_X_BEGIN, SEM_FN_NAME (m32rbf,x_begin) },
+  { M32RBF_INSN_ADD, SEM_FN_NAME (m32rbf,add) },
+  { M32RBF_INSN_ADD3, SEM_FN_NAME (m32rbf,add3) },
+  { M32RBF_INSN_AND, SEM_FN_NAME (m32rbf,and) },
+  { M32RBF_INSN_AND3, SEM_FN_NAME (m32rbf,and3) },
+  { M32RBF_INSN_OR, SEM_FN_NAME (m32rbf,or) },
+  { M32RBF_INSN_OR3, SEM_FN_NAME (m32rbf,or3) },
+  { M32RBF_INSN_XOR, SEM_FN_NAME (m32rbf,xor) },
+  { M32RBF_INSN_XOR3, SEM_FN_NAME (m32rbf,xor3) },
+  { M32RBF_INSN_ADDI, SEM_FN_NAME (m32rbf,addi) },
+  { M32RBF_INSN_ADDV, SEM_FN_NAME (m32rbf,addv) },
+  { M32RBF_INSN_ADDV3, SEM_FN_NAME (m32rbf,addv3) },
+  { M32RBF_INSN_ADDX, SEM_FN_NAME (m32rbf,addx) },
+  { M32RBF_INSN_BC8, SEM_FN_NAME (m32rbf,bc8) },
+  { M32RBF_INSN_BC24, SEM_FN_NAME (m32rbf,bc24) },
+  { M32RBF_INSN_BEQ, SEM_FN_NAME (m32rbf,beq) },
+  { M32RBF_INSN_BEQZ, SEM_FN_NAME (m32rbf,beqz) },
+  { M32RBF_INSN_BGEZ, SEM_FN_NAME (m32rbf,bgez) },
+  { M32RBF_INSN_BGTZ, SEM_FN_NAME (m32rbf,bgtz) },
+  { M32RBF_INSN_BLEZ, SEM_FN_NAME (m32rbf,blez) },
+  { M32RBF_INSN_BLTZ, SEM_FN_NAME (m32rbf,bltz) },
+  { M32RBF_INSN_BNEZ, SEM_FN_NAME (m32rbf,bnez) },
+  { M32RBF_INSN_BL8, SEM_FN_NAME (m32rbf,bl8) },
+  { M32RBF_INSN_BL24, SEM_FN_NAME (m32rbf,bl24) },
+  { M32RBF_INSN_BNC8, SEM_FN_NAME (m32rbf,bnc8) },
+  { M32RBF_INSN_BNC24, SEM_FN_NAME (m32rbf,bnc24) },
+  { M32RBF_INSN_BNE, SEM_FN_NAME (m32rbf,bne) },
+  { M32RBF_INSN_BRA8, SEM_FN_NAME (m32rbf,bra8) },
+  { M32RBF_INSN_BRA24, SEM_FN_NAME (m32rbf,bra24) },
+  { M32RBF_INSN_CMP, SEM_FN_NAME (m32rbf,cmp) },
+  { M32RBF_INSN_CMPI, SEM_FN_NAME (m32rbf,cmpi) },
+  { M32RBF_INSN_CMPU, SEM_FN_NAME (m32rbf,cmpu) },
+  { M32RBF_INSN_CMPUI, SEM_FN_NAME (m32rbf,cmpui) },
+  { M32RBF_INSN_DIV, SEM_FN_NAME (m32rbf,div) },
+  { M32RBF_INSN_DIVU, SEM_FN_NAME (m32rbf,divu) },
+  { M32RBF_INSN_REM, SEM_FN_NAME (m32rbf,rem) },
+  { M32RBF_INSN_REMU, SEM_FN_NAME (m32rbf,remu) },
+  { M32RBF_INSN_JL, SEM_FN_NAME (m32rbf,jl) },
+  { M32RBF_INSN_JMP, SEM_FN_NAME (m32rbf,jmp) },
+  { M32RBF_INSN_LD, SEM_FN_NAME (m32rbf,ld) },
+  { M32RBF_INSN_LD_D, SEM_FN_NAME (m32rbf,ld_d) },
+  { M32RBF_INSN_LDB, SEM_FN_NAME (m32rbf,ldb) },
+  { M32RBF_INSN_LDB_D, SEM_FN_NAME (m32rbf,ldb_d) },
+  { M32RBF_INSN_LDH, SEM_FN_NAME (m32rbf,ldh) },
+  { M32RBF_INSN_LDH_D, SEM_FN_NAME (m32rbf,ldh_d) },
+  { M32RBF_INSN_LDUB, SEM_FN_NAME (m32rbf,ldub) },
+  { M32RBF_INSN_LDUB_D, SEM_FN_NAME (m32rbf,ldub_d) },
+  { M32RBF_INSN_LDUH, SEM_FN_NAME (m32rbf,lduh) },
+  { M32RBF_INSN_LDUH_D, SEM_FN_NAME (m32rbf,lduh_d) },
+  { M32RBF_INSN_LD_PLUS, SEM_FN_NAME (m32rbf,ld_plus) },
+  { M32RBF_INSN_LD24, SEM_FN_NAME (m32rbf,ld24) },
+  { M32RBF_INSN_LDI8, SEM_FN_NAME (m32rbf,ldi8) },
+  { M32RBF_INSN_LDI16, SEM_FN_NAME (m32rbf,ldi16) },
+  { M32RBF_INSN_LOCK, SEM_FN_NAME (m32rbf,lock) },
+  { M32RBF_INSN_MACHI, SEM_FN_NAME (m32rbf,machi) },
+  { M32RBF_INSN_MACLO, SEM_FN_NAME (m32rbf,maclo) },
+  { M32RBF_INSN_MACWHI, SEM_FN_NAME (m32rbf,macwhi) },
+  { M32RBF_INSN_MACWLO, SEM_FN_NAME (m32rbf,macwlo) },
+  { M32RBF_INSN_MUL, SEM_FN_NAME (m32rbf,mul) },
+  { M32RBF_INSN_MULHI, SEM_FN_NAME (m32rbf,mulhi) },
+  { M32RBF_INSN_MULLO, SEM_FN_NAME (m32rbf,mullo) },
+  { M32RBF_INSN_MULWHI, SEM_FN_NAME (m32rbf,mulwhi) },
+  { M32RBF_INSN_MULWLO, SEM_FN_NAME (m32rbf,mulwlo) },
+  { M32RBF_INSN_MV, SEM_FN_NAME (m32rbf,mv) },
+  { M32RBF_INSN_MVFACHI, SEM_FN_NAME (m32rbf,mvfachi) },
+  { M32RBF_INSN_MVFACLO, SEM_FN_NAME (m32rbf,mvfaclo) },
+  { M32RBF_INSN_MVFACMI, SEM_FN_NAME (m32rbf,mvfacmi) },
+  { M32RBF_INSN_MVFC, SEM_FN_NAME (m32rbf,mvfc) },
+  { M32RBF_INSN_MVTACHI, SEM_FN_NAME (m32rbf,mvtachi) },
+  { M32RBF_INSN_MVTACLO, SEM_FN_NAME (m32rbf,mvtaclo) },
+  { M32RBF_INSN_MVTC, SEM_FN_NAME (m32rbf,mvtc) },
+  { M32RBF_INSN_NEG, SEM_FN_NAME (m32rbf,neg) },
+  { M32RBF_INSN_NOP, SEM_FN_NAME (m32rbf,nop) },
+  { M32RBF_INSN_NOT, SEM_FN_NAME (m32rbf,not) },
+  { M32RBF_INSN_RAC, SEM_FN_NAME (m32rbf,rac) },
+  { M32RBF_INSN_RACH, SEM_FN_NAME (m32rbf,rach) },
+  { M32RBF_INSN_RTE, SEM_FN_NAME (m32rbf,rte) },
+  { M32RBF_INSN_SETH, SEM_FN_NAME (m32rbf,seth) },
+  { M32RBF_INSN_SLL, SEM_FN_NAME (m32rbf,sll) },
+  { M32RBF_INSN_SLL3, SEM_FN_NAME (m32rbf,sll3) },
+  { M32RBF_INSN_SLLI, SEM_FN_NAME (m32rbf,slli) },
+  { M32RBF_INSN_SRA, SEM_FN_NAME (m32rbf,sra) },
+  { M32RBF_INSN_SRA3, SEM_FN_NAME (m32rbf,sra3) },
+  { M32RBF_INSN_SRAI, SEM_FN_NAME (m32rbf,srai) },
+  { M32RBF_INSN_SRL, SEM_FN_NAME (m32rbf,srl) },
+  { M32RBF_INSN_SRL3, SEM_FN_NAME (m32rbf,srl3) },
+  { M32RBF_INSN_SRLI, SEM_FN_NAME (m32rbf,srli) },
+  { M32RBF_INSN_ST, SEM_FN_NAME (m32rbf,st) },
+  { M32RBF_INSN_ST_D, SEM_FN_NAME (m32rbf,st_d) },
+  { M32RBF_INSN_STB, SEM_FN_NAME (m32rbf,stb) },
+  { M32RBF_INSN_STB_D, SEM_FN_NAME (m32rbf,stb_d) },
+  { M32RBF_INSN_STH, SEM_FN_NAME (m32rbf,sth) },
+  { M32RBF_INSN_STH_D, SEM_FN_NAME (m32rbf,sth_d) },
+  { M32RBF_INSN_ST_PLUS, SEM_FN_NAME (m32rbf,st_plus) },
+  { M32RBF_INSN_ST_MINUS, SEM_FN_NAME (m32rbf,st_minus) },
+  { M32RBF_INSN_SUB, SEM_FN_NAME (m32rbf,sub) },
+  { M32RBF_INSN_SUBV, SEM_FN_NAME (m32rbf,subv) },
+  { M32RBF_INSN_SUBX, SEM_FN_NAME (m32rbf,subx) },
+  { M32RBF_INSN_TRAP, SEM_FN_NAME (m32rbf,trap) },
+  { M32RBF_INSN_UNLOCK, SEM_FN_NAME (m32rbf,unlock) },
+  { 0, 0 }
+};
+
+/* Add the semantic fns to IDESC_TABLE.  */
+
+void
+SEM_FN_NAME (m32rbf,init_idesc_table) (SIM_CPU *current_cpu)
+{
+  IDESC *idesc_table = CPU_IDESC (current_cpu);
+  const struct sem_fn_desc *sf;
+
+  for (sf = &sem_fns[0]; sf->fn != 0; ++sf)
+    {
+#if FAST_P
+      idesc_table[sf->index].sem_fast = sf->fn;
+#else
+      idesc_table[sf->index].sem_full = sf->fn;
+#endif
+    }
+}
+