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author | Doug Evans <dje@google.com> | 2009-11-23 04:12:15 +0000 |
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committer | Doug Evans <dje@google.com> | 2009-11-23 04:12:15 +0000 |
commit | d3534f9ac9ddd1a2dfa26fd222ee838d8a25dd20 (patch) | |
tree | dd097cae08c1b59e399cf8d49e99fe4c8ade1897 /sim/sh64/cpu.h | |
parent | 5cde43f70d4c09cabaf991b532c44311e4fde7c3 (diff) | |
download | gdb-d3534f9ac9ddd1a2dfa26fd222ee838d8a25dd20.tar.gz |
* cgen-engine.h (EXTRACT_MSB0_LGSINT, EXTRACT_MSB0_LGUINT): Define.
(EXTRACT_LSB0_LGSINT, EXTRACT_LSB0_LGUINT): Define.
(EXTRACT_FN, SEMANTIC_FN): Use CGEN_INSN_WORD in prototype
instead of CGEN_INSN_INT.
plus, cgen files: Regenerate.
Diffstat (limited to 'sim/sh64/cpu.h')
-rw-r--r-- | sim/sh64/cpu.h | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/sim/sh64/cpu.h b/sim/sh64/cpu.h index 69e17314068..3b6c49299b6 100644 --- a/sim/sh64/cpu.h +++ b/sim/sh64/cpu.h @@ -32,6 +32,12 @@ This file is part of the GNU simulators. /* Maximum number of instructions that can be executed in parallel. */ #define MAX_PARALLEL_INSNS 1 +/* The size of an "int" needed to hold an instruction word. + This is usually 32 bits, but some architectures needs 64 bits. */ +typedef CGEN_INSN_INT CGEN_INSN_WORD; + +#include "cgen-engine.h" + /* CPU state information. */ typedef struct { /* Hardware elements. */ |