diff options
| author | sergiodj <sergiodj> | 2013-10-09 21:42:11 +0000 |
|---|---|---|
| committer | sergiodj <sergiodj> | 2013-10-09 21:42:11 +0000 |
| commit | 705ba926a5b9ad4b833d7d005b7cffedc7235be7 (patch) | |
| tree | 306cf5a91cc90f5810ae7bb4d945094dd666d858 /sim | |
| parent | 9d85f09f99debd275e97f2de37810cd6e3f716c3 (diff) | |
| download | gdb-705ba926a5b9ad4b833d7d005b7cffedc7235be7.tar.gz | |
sim/erc32/ChangeLog:
2013-10-09 Sergio Durigan Junior <sergiodj@redhat.com>
PR sim/16018:
* float.c (set_fsr): Add missing "break" statements. Reindent
code.
Diffstat (limited to 'sim')
| -rw-r--r-- | sim/erc32/ChangeLog | 6 | ||||
| -rw-r--r-- | sim/erc32/float.c | 13 |
2 files changed, 16 insertions, 3 deletions
diff --git a/sim/erc32/ChangeLog b/sim/erc32/ChangeLog index 4fff0da1bf1..d7266fd7c06 100644 --- a/sim/erc32/ChangeLog +++ b/sim/erc32/ChangeLog @@ -1,3 +1,9 @@ +2013-10-09 Sergio Durigan Junior <sergiodj@redhat.com> + + PR sim/16018: + * float.c (set_fsr): Add missing "break" statements. Reindent + code. + 2013-09-23 Alan Modra <amodra@gmail.com> * configure: Regenerate. diff --git a/sim/erc32/float.c b/sim/erc32/float.c index c1a46f8aea1..1b8f0fc76cf 100644 --- a/sim/erc32/float.c +++ b/sim/erc32/float.c @@ -91,9 +91,16 @@ uint32 fsr; fsr >>= 30; switch (fsr) { case 0: - case 2: break; - case 1: fsr = 3; - case 3: fsr = 1; + case 2: + break; + + case 1: + fsr = 3; + break; + + case 3: + fsr = 1; + break; } rawfsr = _get_cw(); rawfsr |= (fsr << 10) | 0x3ff; |