diff options
| author | Joel Brobecker <brobecker@gnat.com> | 2008-05-09 15:03:09 +0000 |
|---|---|---|
| committer | Joel Brobecker <brobecker@gnat.com> | 2008-05-09 15:03:09 +0000 |
| commit | 896d0ce78aaac26e26d114e15d8ac1f779df919a (patch) | |
| tree | 271348d3fc3ebeb3eab8001b405f3c15d4c2b7df /sim | |
| parent | 7dccee649aa6ffca6f483082c280955cbdd013aa (diff) | |
| download | gdb-896d0ce78aaac26e26d114e15d8ac1f779df919a.tar.gz | |
* ppc/altivec.igen (vperm): Latch inputs into temporaries.
Diffstat (limited to 'sim')
| -rw-r--r-- | sim/ChangeLog | 4 | ||||
| -rw-r--r-- | sim/ppc/altivec.igen | 9 |
2 files changed, 11 insertions, 2 deletions
diff --git a/sim/ChangeLog b/sim/ChangeLog index ea3b3069336..521ccfb5e35 100644 --- a/sim/ChangeLog +++ b/sim/ChangeLog @@ -1,3 +1,7 @@ +2008-05-09 Olivier Hainque <hainque@adacore.com> + + * ppc/altivec.igen (vperm): Latch inputs into temporaries. + 2008-03-25 M R Swami Reddy <MR.Swami.Reddy@nsc.com> * MAINTAINERS: Add myself as maintainer of cr16 port. diff --git a/sim/ppc/altivec.igen b/sim/ppc/altivec.igen index d933f569eb8..3a224cc016c 100644 --- a/sim/ppc/altivec.igen +++ b/sim/ppc/altivec.igen @@ -1634,12 +1634,17 @@ unsigned32::model-function::altivec_unsigned_saturate_32:signed64 val, int *sat 0.4,6.VS,11.VA,16.VB,21.VC,26.43:VX:av:vperm %VD, %VA, %VB, %VC:Vector Permute int i, who; + /* The permutation vector might have us read into the source vectors + back at positions before the iteration index, so we must latch the + sources to prevent early-clobbering in case the destination vector + is the same as one of them. */ + vreg myvA = (*vA), myvB = (*vB); for (i = 0; i < 16; i++) { who = (*vC).b[AV_BINDEX(i)] & 0x1f; if (who & 0x10) - (*vS).b[AV_BINDEX(i)] = (*vB).b[AV_BINDEX(who & 0xf)]; + (*vS).b[AV_BINDEX(i)] = myvB.b[AV_BINDEX(who & 0xf)]; else - (*vS).b[AV_BINDEX(i)] = (*vA).b[AV_BINDEX(who & 0xf)]; + (*vS).b[AV_BINDEX(i)] = myvA.b[AV_BINDEX(who & 0xf)]; } PPC_INSN_VR(VS_BITMASK, VA_BITMASK | VB_BITMASK | VC_BITMASK); |