diff options
48 files changed, 3615 insertions, 495 deletions
diff --git a/.cvsignore b/.cvsignore index dab6c3245ba..bde48527b00 100644 --- a/.cvsignore +++ b/.cvsignore @@ -28,3 +28,5 @@ configure.vrs dir.info Makefile lost+found +update.out + diff --git a/bfd/ChangeLog b/bfd/ChangeLog index df53b6a13ec..3bf5a1744d3 100644 --- a/bfd/ChangeLog +++ b/bfd/ChangeLog @@ -1,3 +1,23 @@ +2000-06-18 Stephane Carrez <stcarrez@worldnet.fr> + + * Makefile.in, bfd-in2.h, libbfd.h, configure: Rebuild. + * Makefile.am (ALL_MACHINES, ALL_MACHINES_CFILES, BFD32_BACKENDS, + BFD32_BACKENDS_CFILES): Add 68hc12, 68hc11 files. + * configure.in (bfd_elf32_m68hc12_vec): Recognize. + (bfd_elf32_m68hc11_vec): Likewise. + * config.bfd (targ_cpu): Recognize 68hc12 and 68hc11. + Supports 68hc11 & 68hc12 at the same time. + * targets.c (bfd_elf32_m68hc12_vec): Declare and put in + bfd_target_vector. + (bfd_elf32_m68hc11_vec): Likewise. + * elf.c (prep_headers): Recognize bfd_arch_m68hc12 and 68hc11. + * archures.c (bfd_m68hc12_arch): Define and register in global list + (bfd_m68hc11_arch): Likewise. + * reloc.c (BFD_RELOC_M68HC11_HI8, BFD_RELOC_M68HC11_LO8, + BFD_RELOC_M68HC11_3B): Define. + * cpu-m68hc12.c, elf32-m68hc12.c: New files for 68hc12 support. + * cpu-m68hc11.c, elf32-m68hc11.c: New files for 68hc11 support. + 2000-06-18 Ulf Carlsson <ulfc@engr.sgi.com> * elf_bfd.h (struct elf_backend_data): Add info argument to diff --git a/bfd/Makefile.am b/bfd/Makefile.am index 1b6a0a77c72..39c745533d0 100644 --- a/bfd/Makefile.am +++ b/bfd/Makefile.am @@ -57,6 +57,8 @@ ALL_MACHINES = \ cpu-i860.lo \ cpu-i960.lo \ cpu-m32r.lo \ + cpu-m68hc11.lo \ + cpu-m68hc12.lo \ cpu-m68k.lo \ cpu-m88k.lo \ cpu-m10200.lo \ @@ -96,6 +98,8 @@ ALL_MACHINES_CFILES = \ cpu-i860.c \ cpu-i960.c \ cpu-m32r.c \ + cpu-m68hc11.c \ + cpu-m68hc12.c \ cpu-m68k.c \ cpu-m88k.c \ cpu-m10200.c \ @@ -179,6 +183,8 @@ BFD32_BACKENDS = \ elf32-i860.lo \ elf32-i960.lo \ elf32-m32r.lo \ + elf32-m68hc11.lo \ + elf32-m68hc12.lo \ elf32-m68k.lo \ elf32-m88k.lo \ elf-m10200.lo \ @@ -313,6 +319,8 @@ BFD32_BACKENDS_CFILES = \ elf32-i960.c \ elf32-m32r.c \ elf32-m68k.c \ + elf32-m68hc11.c \ + elf32-m68hc12.c \ elf32-m88k.c \ elf-m10200.c \ elf-m10300.c \ @@ -721,6 +729,8 @@ cpu-i860.lo: cpu-i860.c $(INCDIR)/filenames.h cpu-i960.lo: cpu-i960.c $(INCDIR)/filenames.h cpu-m32r.lo: cpu-m32r.c $(INCDIR)/filenames.h cpu-m68k.lo: cpu-m68k.c $(INCDIR)/filenames.h +cpu-m68hc11.lo: cpu-m68hc11.c $(INCDIR)/filenames.h +cpu-m68hc12.lo: cpu-m68hc12.c $(INCDIR)/filenames.h cpu-m88k.lo: cpu-m88k.c $(INCDIR)/filenames.h cpu-m10200.lo: cpu-m10200.c $(INCDIR)/filenames.h cpu-m10300.lo: cpu-m10300.c $(INCDIR)/filenames.h @@ -913,6 +923,10 @@ elf32-fr30.lo: elf32-fr30.c $(INCDIR)/filenames.h elf-bfd.h \ elf32-gen.lo: elf32-gen.c $(INCDIR)/filenames.h elf-bfd.h \ $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \ $(INCDIR)/bfdlink.h elf32-target.h +elf32-m68hc11.lo: elf32-m68hc11.c $(INCDIR)/bfdlink.h elf-bfd.h \ + $(INCDIR)/elf/m68hc11.h elf32-target.h +elf32-m68hc12.lo: elf32-m68hc12.c $(INCDIR)/bfdlink.h elf-bfd.h \ + $(INCDIR)/elf/m68hc11.h elf32-target.h elf32-hppa.lo: elf32-hppa.c $(INCDIR)/filenames.h elf-bfd.h \ $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \ $(INCDIR)/bfdlink.h $(INCDIR)/elf/hppa.h $(INCDIR)/elf/reloc-macros.h \ diff --git a/bfd/Makefile.in b/bfd/Makefile.in index f23960a6b7a..a894da47106 100644 --- a/bfd/Makefile.in +++ b/bfd/Makefile.in @@ -172,6 +172,8 @@ ALL_MACHINES = \ cpu-i860.lo \ cpu-i960.lo \ cpu-m32r.lo \ + cpu-m68hc11.lo \ + cpu-m68hc12.lo \ cpu-m68k.lo \ cpu-m88k.lo \ cpu-m10200.lo \ @@ -212,6 +214,8 @@ ALL_MACHINES_CFILES = \ cpu-i860.c \ cpu-i960.c \ cpu-m32r.c \ + cpu-m68hc11.c \ + cpu-m68hc12.c \ cpu-m68k.c \ cpu-m88k.c \ cpu-m10200.c \ @@ -296,6 +300,8 @@ BFD32_BACKENDS = \ elf32-i860.lo \ elf32-i960.lo \ elf32-m32r.lo \ + elf32-m68hc11.lo \ + elf32-m68hc12.lo \ elf32-m68k.lo \ elf32-m88k.lo \ elf-m10200.lo \ @@ -431,6 +437,8 @@ BFD32_BACKENDS_CFILES = \ elf32-i960.c \ elf32-m32r.c \ elf32-m68k.c \ + elf32-m68hc11.c \ + elf32-m68hc12.c \ elf32-m88k.c \ elf-m10200.c \ elf-m10300.c \ @@ -663,7 +671,7 @@ configure.in DISTFILES = $(DIST_COMMON) $(SOURCES) $(HEADERS) $(TEXINFOS) $(EXTRA_DIST) -TAR = tar +TAR = gtar GZIP_ENV = --best SOURCES = $(libbfd_a_SOURCES) $(libbfd_la_SOURCES) OBJECTS = $(libbfd_a_OBJECTS) $(libbfd_la_OBJECTS) @@ -1249,6 +1257,8 @@ cpu-i860.lo: cpu-i860.c $(INCDIR)/filenames.h cpu-i960.lo: cpu-i960.c $(INCDIR)/filenames.h cpu-m32r.lo: cpu-m32r.c $(INCDIR)/filenames.h cpu-m68k.lo: cpu-m68k.c $(INCDIR)/filenames.h +cpu-m68hc11.lo: cpu-m68hc11.c $(INCDIR)/filenames.h +cpu-m68hc12.lo: cpu-m68hc12.c $(INCDIR)/filenames.h cpu-m88k.lo: cpu-m88k.c $(INCDIR)/filenames.h cpu-m10200.lo: cpu-m10200.c $(INCDIR)/filenames.h cpu-m10300.lo: cpu-m10300.c $(INCDIR)/filenames.h @@ -1441,6 +1451,10 @@ elf32-fr30.lo: elf32-fr30.c $(INCDIR)/filenames.h elf-bfd.h \ elf32-gen.lo: elf32-gen.c $(INCDIR)/filenames.h elf-bfd.h \ $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \ $(INCDIR)/bfdlink.h elf32-target.h +elf32-m68hc11.lo: elf32-m68hc11.c $(INCDIR)/bfdlink.h elf-bfd.h \ + $(INCDIR)/elf/m68hc11.h elf32-target.h +elf32-m68hc12.lo: elf32-m68hc12.c $(INCDIR)/bfdlink.h elf-bfd.h \ + $(INCDIR)/elf/m68hc11.h elf32-target.h elf32-hppa.lo: elf32-hppa.c $(INCDIR)/filenames.h elf-bfd.h \ $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \ $(INCDIR)/bfdlink.h $(INCDIR)/elf/hppa.h $(INCDIR)/elf/reloc-macros.h \ diff --git a/bfd/archures.c b/bfd/archures.c index 69e42bfa8a5..ffc79377e88 100644 --- a/bfd/archures.c +++ b/bfd/archures.c @@ -174,6 +174,8 @@ DESCRIPTION .#define bfd_mach_d10v_ts2 2 .#define bfd_mach_d10v_ts3 3 . bfd_arch_d30v, {* Mitsubishi D30V *} +. bfd_arch_m68hc11, {* Motorola 68HC11 *} +. bfd_arch_m68hc12, {* Motorola 68HC12 *} . bfd_arch_z8k, {* Zilog Z8000 *} .#define bfd_mach_z8001 1 .#define bfd_mach_z8002 2 @@ -279,6 +281,8 @@ extern const bfd_arch_info_type bfd_i386_arch; extern const bfd_arch_info_type bfd_i860_arch; extern const bfd_arch_info_type bfd_i960_arch; extern const bfd_arch_info_type bfd_m32r_arch; +extern const bfd_arch_info_type bfd_m68hc11_arch; +extern const bfd_arch_info_type bfd_m68hc12_arch; extern const bfd_arch_info_type bfd_m68k_arch; extern const bfd_arch_info_type bfd_m88k_arch; extern const bfd_arch_info_type bfd_mips_arch; @@ -322,6 +326,8 @@ static const bfd_arch_info_type * const bfd_archures_list[] = &bfd_i860_arch, &bfd_i960_arch, &bfd_m32r_arch, + &bfd_m68hc11_arch, + &bfd_m68hc12_arch, &bfd_m68k_arch, &bfd_m88k_arch, &bfd_mips_arch, diff --git a/bfd/bfd-in.h b/bfd/bfd-in.h index 26a90800d7a..f0a1d84ebde 100644 --- a/bfd/bfd-in.h +++ b/bfd/bfd-in.h @@ -23,7 +23,7 @@ You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ -/* bfd.h -- The only header file required by users of the bfd library +/* bfd.h -- The only header file required by users of the bfd library The bfd.h file is generated from bfd-in.h and various .c files; if you change it, your changes will probably be lost. @@ -109,7 +109,7 @@ typedef enum bfd_boolean {bfd_fffalse, bfd_tttrue} boolean; /* FIXME: This should be using off_t from <sys/types.h>. For now, try to avoid breaking stuff by not including <sys/types.h> here. This will break on systems with 64-bit file offsets (e.g. 4.4BSD). - Probably the best long-term answer is to avoid using file_ptr AND off_t + Probably the best long-term answer is to avoid using file_ptr AND off_t in this header file, and to handle this in the BFD implementation rather than in its interface. */ /* typedef off_t file_ptr; */ @@ -284,11 +284,11 @@ typedef struct carsym { file_ptr file_offset; /* look here to find the file */ } carsym; /* to make these you call a carsymogen */ - + /* Used in generating armaps (archive tables of contents). Perhaps just a forward definition would do? */ struct orl { /* output ranlib */ - char **name; /* symbol name */ + char **name; /* symbol name */ file_ptr pos; /* bfd* or file position */ int namidx; /* index into string table */ }; @@ -296,7 +296,7 @@ struct orl { /* output ranlib */ /* Linenumber stuff */ typedef struct lineno_cache_entry { - unsigned int line_number; /* Linenumber from start of function*/ + unsigned int line_number; /* Linenumber from start of function*/ union { struct symbol_cache_entry *sym; /* Function name */ unsigned long offset; /* Offset into section */ @@ -327,15 +327,15 @@ typedef struct sec *sec_ptr; #define bfd_set_section_alignment(bfd, ptr, val) (((ptr)->alignment_power = (val)),true) #define bfd_set_section_userdata(bfd, ptr, val) (((ptr)->userdata = (val)),true) -typedef struct stat stat_type; +typedef struct stat stat_type; typedef enum bfd_print_symbol -{ +{ bfd_print_symbol_name, bfd_print_symbol_more, bfd_print_symbol_all } bfd_print_symbol_type; - + /* Information about a symbol that nm needs. */ typedef struct _symbol_info diff --git a/bfd/bfd-in2.h b/bfd/bfd-in2.h index 92501f003c7..b0832b90ce0 100644 --- a/bfd/bfd-in2.h +++ b/bfd/bfd-in2.h @@ -23,7 +23,7 @@ You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ -/* bfd.h -- The only header file required by users of the bfd library +/* bfd.h -- The only header file required by users of the bfd library The bfd.h file is generated from bfd-in.h and various .c files; if you change it, your changes will probably be lost. @@ -109,7 +109,7 @@ typedef enum bfd_boolean {bfd_fffalse, bfd_tttrue} boolean; /* FIXME: This should be using off_t from <sys/types.h>. For now, try to avoid breaking stuff by not including <sys/types.h> here. This will break on systems with 64-bit file offsets (e.g. 4.4BSD). - Probably the best long-term answer is to avoid using file_ptr AND off_t + Probably the best long-term answer is to avoid using file_ptr AND off_t in this header file, and to handle this in the BFD implementation rather than in its interface. */ /* typedef off_t file_ptr; */ @@ -284,11 +284,11 @@ typedef struct carsym { file_ptr file_offset; /* look here to find the file */ } carsym; /* to make these you call a carsymogen */ - + /* Used in generating armaps (archive tables of contents). Perhaps just a forward definition would do? */ struct orl { /* output ranlib */ - char **name; /* symbol name */ + char **name; /* symbol name */ file_ptr pos; /* bfd* or file position */ int namidx; /* index into string table */ }; @@ -296,7 +296,7 @@ struct orl { /* output ranlib */ /* Linenumber stuff */ typedef struct lineno_cache_entry { - unsigned int line_number; /* Linenumber from start of function*/ + unsigned int line_number; /* Linenumber from start of function*/ union { struct symbol_cache_entry *sym; /* Function name */ unsigned long offset; /* Offset into section */ @@ -327,15 +327,15 @@ typedef struct sec *sec_ptr; #define bfd_set_section_alignment(bfd, ptr, val) (((ptr)->alignment_power = (val)),true) #define bfd_set_section_userdata(bfd, ptr, val) (((ptr)->userdata = (val)),true) -typedef struct stat stat_type; +typedef struct stat stat_type; typedef enum bfd_print_symbol -{ +{ bfd_print_symbol_name, bfd_print_symbol_more, bfd_print_symbol_all } bfd_print_symbol_type; - + /* Information about a symbol that nm needs. */ typedef struct _symbol_info @@ -1413,6 +1413,8 @@ enum bfd_architecture #define bfd_mach_d10v_ts2 2 #define bfd_mach_d10v_ts3 3 bfd_arch_d30v, /* Mitsubishi D30V */ + bfd_arch_m68hc11, /* Motorola 68HC11 */ + bfd_arch_m68hc12, /* Motorola 68HC12 */ bfd_arch_z8k, /* Zilog Z8000 */ #define bfd_mach_z8001 1 #define bfd_mach_z8002 2 @@ -2545,6 +2547,18 @@ this offset in the reloc's section offset. */ BFD_RELOC_IA64_LTOFF_TP22, BFD_RELOC_IA64_LTOFF22X, BFD_RELOC_IA64_LDXMOV, + +/* Motorola 68HC11 reloc. +This is the 8 bits high part of an absolute address. */ + BFD_RELOC_M68HC11_HI8, + +/* Motorola 68HC11 reloc. +This is the 8 bits low part of an absolute address. */ + BFD_RELOC_M68HC11_LO8, + +/* Motorola 68HC11 reloc. +This is the 3 bits of a value. */ + BFD_RELOC_M68HC11_3B, BFD_RELOC_UNUSED }; typedef enum bfd_reloc_code_real bfd_reloc_code_real_type; reloc_howto_type * diff --git a/bfd/coff-i386.c b/bfd/coff-i386.c index c7aa659c0e0..0f233254f13 100644 --- a/bfd/coff-i386.c +++ b/bfd/coff-i386.c @@ -176,19 +176,17 @@ coff_i386_reloc (abfd, reloc_entry, symbol, data, input_section, output_bfd, } #ifdef COFF_WITH_PE - /* Return true if this relocation should appear in the output .reloc section. */ static boolean in_reloc_p PARAMS ((bfd *, reloc_howto_type *)); static boolean in_reloc_p (abfd, howto) - bfd *abfd ATTRIBUTE_UNUSED; + bfd * abfd ATTRIBUTE_UNUSED; reloc_howto_type *howto; { return ! howto->pc_relative && howto->type != R_IMAGEBASE; } - #endif /* COFF_WITH_PE */ #ifndef PCRELOFFSET diff --git a/bfd/coff-mcore.c b/bfd/coff-mcore.c index 19cbea1dc80..f20c2ca815f 100644 --- a/bfd/coff-mcore.c +++ b/bfd/coff-mcore.c @@ -582,5 +582,9 @@ coff_mcore_relocate_section (output_bfd, info, input_bfd, input_section, extern const bfd_target TARGET_LITTLE_SYM; /* The transfer vectors that lead the outside world to all of the above. */ -CREATE_BIG_COFF_TARGET_VEC (TARGET_BIG_SYM, TARGET_BIG_NAME, D_PAGED, (SEC_LINK_ONCE | SEC_LINK_DUPLICATES), 0, & TARGET_LITTLE_SYM) -CREATE_LITTLE_COFF_TARGET_VEC (TARGET_LITTLE_SYM, TARGET_LITTLE_NAME, D_PAGED, (SEC_LINK_ONCE | SEC_LINK_DUPLICATES), 0, & TARGET_BIG_SYM) +CREATE_BIG_COFF_TARGET_VEC (TARGET_BIG_SYM, TARGET_BIG_NAME, D_PAGED, + (SEC_CODE | SEC_DATA | SEC_DEBUGGING | SEC_READONLY | SEC_LINK_ONCE | SEC_LINK_DUPLICATES), + 0, & TARGET_LITTLE_SYM) +CREATE_LITTLE_COFF_TARGET_VEC (TARGET_LITTLE_SYM, TARGET_LITTLE_NAME, D_PAGED, + (SEC_CODE | SEC_DATA | SEC_DEBUGGING | SEC_READONLY | SEC_LINK_ONCE | SEC_LINK_DUPLICATES), + 0, & TARGET_BIG_SYM) diff --git a/bfd/coffcode.h b/bfd/coffcode.h index 93444988678..f4e27fad25c 100644 --- a/bfd/coffcode.h +++ b/bfd/coffcode.h @@ -1466,8 +1466,8 @@ static const unsigned int coff_section_alignment_table_size = static boolean coff_new_section_hook (abfd, section) - bfd *abfd; - asection *section; + bfd * abfd; + asection * section; { combined_entry_type *native; @@ -3342,7 +3342,7 @@ coff_write_object_contents (abfd) && ! is_reloc_section) hasdebug = true; -#ifdef RS6000COFF_C +#ifdef RS6000COFF_C #ifndef XCOFF64 /* Indicate the use of an XCOFF overflow section header. */ if (current->reloc_count >= 0xffff || current->lineno_count >= 0xffff) @@ -3395,7 +3395,7 @@ coff_write_object_contents (abfd) SCNHDR buff; if (coff_swap_scnhdr_out (abfd, §ion, &buff) == 0 || bfd_write ((PTR) (&buff), 1, bfd_coff_scnhsz (abfd), abfd) - != bfd_coff_scnhsz (abfd)) + != bfd_coff_scnhsz (abfd)) return false; } @@ -3517,7 +3517,7 @@ coff_write_object_contents (abfd) scnhdr.s_flags = STYP_OVRFLO; if (coff_swap_scnhdr_out (abfd, &scnhdr, &buff) == 0 || bfd_write ((PTR) &buff, 1, bfd_coff_scnhsz (abfd), abfd) - != bfd_coff_scnhsz (abfd)) + != bfd_coff_scnhsz (abfd)) return false; } } @@ -4438,7 +4438,7 @@ coff_slurp_symbol_table (abfd) #endif case C_BLOCK: /* ".bb" or ".eb" */ - case C_FCN: /* ".bf" or ".ef" (or PE ".lf") */ + case C_FCN: /* ".bf" or ".ef" (or PE ".lf") */ case C_EFCN: /* physical end of function */ #if defined COFF_WITH_PE /* PE sets the symbol to a value relative to the start diff --git a/bfd/cofflink.c b/bfd/cofflink.c index b648fa19eea..01fa2e7b917 100644 --- a/bfd/cofflink.c +++ b/bfd/cofflink.c @@ -2201,7 +2201,7 @@ _bfd_coff_link_input_bfd (finfo, input_bfd) is.n_numaux, auxptr); } - skipping = false; + skipping = false; } iline.l_addr.l_symndx = indx; diff --git a/bfd/config.bfd b/bfd/config.bfd index 324a168efca..f85a6def7d0 100644 --- a/bfd/config.bfd +++ b/bfd/config.bfd @@ -37,6 +37,8 @@ c54x*) targ_archs=bfd_tic54x_arch ;; hppa*) targ_archs=bfd_hppa_arch ;; i[3456]86) targ_archs=bfd_i386_arch ;; i370) targ_archs=bfd_i370_arch ;; +m6811*|m68hc11*) targ_archs="bfd_m68hc11_arch bfd_m68hc12_arch" ;; +m6812*|m68hc12*) targ_archs="bfd_m68hc12_arch bfd_m68hc11_arch" ;; m68*) targ_archs=bfd_m68k_arch ;; m88*) targ_archs=bfd_m88k_arch ;; mips*) targ_archs=bfd_mips_arch ;; @@ -118,7 +120,7 @@ case "${targ}" in targ_selvecs="armpe_little_vec armpe_big_vec armpei_little_vec armpei_big_vec" targ_underscore=yes ;; - arm-*-aout | armel-*-aout) + arm-*-aout | armel-*-aout) targ_defvec=aout_arm_little_vec targ_selvecs=aout_arm_big_vec ;; @@ -231,7 +233,7 @@ case "${targ}" in hppa*-*-*elf* | hppa*-*-linux-gnu* | hppa*-*-lites* | hppa*-*-sysv4* | hppa*-*-rtems*) targ_defvec=bfd_elf32_hppa_vec ;; -#ifdef BFD64 +#ifdef BFD64 hppa*64*-*-hpux11*) targ_defvec=bfd_elf64_hppa_vec targ_cflags=-DHPUX_LARGE_AR_IDS @@ -404,6 +406,15 @@ case "${targ}" in targ_defvec=bfd_elf32_m32r_vec ;; + m68hc11-*-* | m6811-*-*) + targ_defvec=bfd_elf32_m68hc11_vec + targ_selvecs="bfd_elf32_m68hc11_vec bfd_elf32_m68hc12_vec" + ;; + m68hc12-*-* | m6812-*-*) + targ_defvec=bfd_elf32_m68hc12_vec + targ_selvecs="bfd_elf32_m68hc11_vec bfd_elf32_m68hc12_vec" + ;; + m68*-apollo-*) targ_defvec=apollocoff_vec ;; @@ -740,7 +751,7 @@ case "${targ}" in sparc64-*-elf*) targ_defvec=bfd_elf64_sparc_vec targ_selvecs=bfd_elf32_sparc_vec - ;; + ;; #endif /* BFD64 */ sparc*-*-coff*) targ_defvec=sparccoff_vec diff --git a/bfd/configure b/bfd/configure index ba644d2f052..092c2283d79 100755 --- a/bfd/configure +++ b/bfd/configure @@ -5144,6 +5144,8 @@ do bfd_elf64_littlemips_vec) tb="$tb elf64-mips.lo elf64.lo elf32-mips.lo elf32.lo $elf ecofflink.lo" target64=true ;; bfd_elf32_m32r_vec) tb="$tb elf32-m32r.lo elf32.lo $elf" ;; + bfd_elf32_m68hc11_vec) tb="$tb elf32-m68hc11.lo elf32.lo $elf" ;; + bfd_elf32_m68hc12_vec) tb="$tb elf32-m68hc12.lo elf32.lo $elf" ;; bfd_elf32_m68k_vec) tb="$tb elf32-m68k.lo elf32.lo $elf" ;; bfd_elf32_m88k_vec) tb="$tb elf32-m88k.lo elf32.lo $elf" ;; bfd_elf32_mcore_big_vec) tb="$tb elf32-mcore.lo elf32.lo $elf" ;; @@ -5236,8 +5238,8 @@ do shlcoff_vec) tb="$tb coff-sh.lo cofflink.lo" ;; shcoff_small_vec) tb="$tb coff-sh.lo cofflink.lo" ;; shlcoff_small_vec) tb="$tb coff-sh.lo cofflink.lo" ;; - shlpe_vec) tb="$tb pe-sh.lo coff-sh.lo cofflink.lo" ;; - shlpei_vec) tb="$tb pei-sh.lo coff-sh.lo cofflink.lo" ;; + shlpe_vec) tb="$tb pe-sh.lo coff-sh.lo peigen.lo cofflink.lo" ;; + shlpei_vec) tb="$tb pei-sh.lo coff-sh.lo peigen.lo cofflink.lo" ;; som_vec) tb="$tb som.lo" ;; sparcle_aout_vec) tb="$tb aout-sparcle.lo aout32.lo" ;; sparclinux_vec) tb="$tb sparclinux.lo aout32.lo" ;; @@ -5346,17 +5348,17 @@ for ac_hdr in unistd.h do ac_safe=`echo "$ac_hdr" | sed 'y%./+-%__p_%'` echo $ac_n "checking for $ac_hdr""... $ac_c" 1>&6 -echo "configure:5350: checking for $ac_hdr" >&5 +echo "configure:5352: checking for $ac_hdr" >&5 if eval "test \"`echo '$''{'ac_cv_header_$ac_safe'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else cat > conftest.$ac_ext <<EOF -#line 5355 "configure" +#line 5357 "configure" #include "confdefs.h" #include <$ac_hdr> EOF ac_try="$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out" -{ (eval echo configure:5360: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; } +{ (eval echo configure:5362: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; } ac_err=`grep -v '^ *+' conftest.out | grep -v "^conftest.${ac_ext}\$"` if test -z "$ac_err"; then rm -rf conftest* @@ -5385,12 +5387,12 @@ done for ac_func in getpagesize do echo $ac_n "checking for $ac_func""... $ac_c" 1>&6 -echo "configure:5389: checking for $ac_func" >&5 +echo "configure:5391: checking for $ac_func" >&5 if eval "test \"`echo '$''{'ac_cv_func_$ac_func'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else cat > conftest.$ac_ext <<EOF -#line 5394 "configure" +#line 5396 "configure" #include "confdefs.h" /* System header to define __stub macros and hopefully few prototypes, which can conflict with char $ac_func(); below. */ @@ -5413,7 +5415,7 @@ $ac_func(); ; return 0; } EOF -if { (eval echo configure:5417: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then +if { (eval echo configure:5419: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then rm -rf conftest* eval "ac_cv_func_$ac_func=yes" else @@ -5438,7 +5440,7 @@ fi done echo $ac_n "checking for working mmap""... $ac_c" 1>&6 -echo "configure:5442: checking for working mmap" >&5 +echo "configure:5444: checking for working mmap" >&5 if eval "test \"`echo '$''{'ac_cv_func_mmap_fixed_mapped'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else @@ -5446,7 +5448,7 @@ else ac_cv_func_mmap_fixed_mapped=no else cat > conftest.$ac_ext <<EOF -#line 5450 "configure" +#line 5452 "configure" #include "confdefs.h" /* Thanks to Mike Haertel and Jim Avera for this test. @@ -5586,7 +5588,7 @@ main() } EOF -if { (eval echo configure:5590: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext} && (./conftest; exit) 2>/dev/null +if { (eval echo configure:5592: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext} && (./conftest; exit) 2>/dev/null then ac_cv_func_mmap_fixed_mapped=yes else @@ -5611,12 +5613,12 @@ fi for ac_func in madvise mprotect do echo $ac_n "checking for $ac_func""... $ac_c" 1>&6 -echo "configure:5615: checking for $ac_func" >&5 +echo "configure:5617: checking for $ac_func" >&5 if eval "test \"`echo '$''{'ac_cv_func_$ac_func'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else cat > conftest.$ac_ext <<EOF -#line 5620 "configure" +#line 5622 "configure" #include "confdefs.h" /* System header to define __stub macros and hopefully few prototypes, which can conflict with char $ac_func(); below. */ @@ -5639,7 +5641,7 @@ $ac_func(); ; return 0; } EOF -if { (eval echo configure:5643: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then +if { (eval echo configure:5645: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then rm -rf conftest* eval "ac_cv_func_$ac_func=yes" else diff --git a/bfd/configure.in b/bfd/configure.in index 08daaa87997..4b1c723e5f3 100644 --- a/bfd/configure.in +++ b/bfd/configure.in @@ -501,6 +501,8 @@ do bfd_elf64_littlemips_vec) tb="$tb elf64-mips.lo elf64.lo elf32-mips.lo elf32.lo $elf ecofflink.lo" target64=true ;; bfd_elf32_m32r_vec) tb="$tb elf32-m32r.lo elf32.lo $elf" ;; + bfd_elf32_m68hc11_vec) tb="$tb elf32-m68hc11.lo elf32.lo $elf" ;; + bfd_elf32_m68hc12_vec) tb="$tb elf32-m68hc12.lo elf32.lo $elf" ;; bfd_elf32_m68k_vec) tb="$tb elf32-m68k.lo elf32.lo $elf" ;; bfd_elf32_m88k_vec) tb="$tb elf32-m88k.lo elf32.lo $elf" ;; bfd_elf32_mcore_big_vec) tb="$tb elf32-mcore.lo elf32.lo $elf" ;; @@ -593,8 +595,8 @@ do shlcoff_vec) tb="$tb coff-sh.lo cofflink.lo" ;; shcoff_small_vec) tb="$tb coff-sh.lo cofflink.lo" ;; shlcoff_small_vec) tb="$tb coff-sh.lo cofflink.lo" ;; - shlpe_vec) tb="$tb pe-sh.lo coff-sh.lo cofflink.lo" ;; - shlpei_vec) tb="$tb pei-sh.lo coff-sh.lo cofflink.lo" ;; + shlpe_vec) tb="$tb pe-sh.lo coff-sh.lo peigen.lo cofflink.lo" ;; + shlpei_vec) tb="$tb pei-sh.lo coff-sh.lo peigen.lo cofflink.lo" ;; som_vec) tb="$tb som.lo" ;; sparcle_aout_vec) tb="$tb aout-sparcle.lo aout32.lo" ;; sparclinux_vec) tb="$tb sparclinux.lo aout32.lo" ;; diff --git a/bfd/cpu-m68hc11.c b/bfd/cpu-m68hc11.c new file mode 100644 index 00000000000..0df14c8d30b --- /dev/null +++ b/bfd/cpu-m68hc11.c @@ -0,0 +1,39 @@ +/* BFD support for the Motorola 68HC11 processor + Copyright 1999, 2000 Free Software Foundation, Inc. + +This file is part of BFD, the Binary File Descriptor library. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; if not, write to the Free Software +Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#include "bfd.h" +#include "sysdep.h" +#include "libbfd.h" + +const bfd_arch_info_type bfd_m68hc11_arch = +{ + 16, /* 16 bits in a word */ + 16, /* 16 bits in an address */ + 8, /* 8 bits in a byte */ + bfd_arch_m68hc11, + 0, + "m68hc11", + "m68hc11", + 4, /* section alignment power */ + true, + bfd_default_compatible, + bfd_default_scan, + 0, +}; + diff --git a/bfd/cpu-m68hc12.c b/bfd/cpu-m68hc12.c new file mode 100644 index 00000000000..830ddb51ae5 --- /dev/null +++ b/bfd/cpu-m68hc12.c @@ -0,0 +1,38 @@ +/* BFD support for the Motorola 68HC12 processor + Copyright 1999, 2000 Free Software Foundation, Inc. + +This file is part of BFD, the Binary File Descriptor library. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; if not, write to the Free Software +Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#include "bfd.h" +#include "sysdep.h" +#include "libbfd.h" + +const bfd_arch_info_type bfd_m68hc12_arch = +{ + 16, /* 16 bits in a word */ + 16, /* 16 bits in an address */ + 8, /* 8 bits in a byte */ + bfd_arch_m68hc12, + 0, + "m68hc12", + "m68hc12", + 4, /* section alignment power */ + true, + bfd_default_compatible, + bfd_default_scan, + 0, +}; diff --git a/bfd/doc/Makefile.in b/bfd/doc/Makefile.in index e45ab482cad..80be82a2b5e 100644 --- a/bfd/doc/Makefile.in +++ b/bfd/doc/Makefile.in @@ -188,7 +188,7 @@ DIST_COMMON = ChangeLog Makefile.am Makefile.in DISTFILES = $(DIST_COMMON) $(SOURCES) $(HEADERS) $(TEXINFOS) $(EXTRA_DIST) -TAR = tar +TAR = gtar GZIP_ENV = --best all: all-redirect .SUFFIXES: diff --git a/bfd/elf-bfd.h b/bfd/elf-bfd.h index b17f7c6cda0..8489a32de35 100644 --- a/bfd/elf-bfd.h +++ b/bfd/elf-bfd.h @@ -373,8 +373,8 @@ struct elf_backend_data /* A function to set the type of the info field. Processor-specific types should be handled here. */ - int (*elf_backend_get_symbol_type) PARAMS (( Elf_Internal_Sym *, int)); - + int (*elf_backend_get_symbol_type) PARAMS (( Elf_Internal_Sym *, int)); + /* A function to do additional processing on the ELF section header just before writing it out. This is used to set the flags and type fields for some sections, or to actually write out data for @@ -638,7 +638,7 @@ struct elf_backend_data both REL and RELA relocations, and this flag is set for those backends.) */ unsigned may_use_rel_p : 1; - + /* Whether the backend may use RELA relocations. (Some backends use both REL and RELA relocations, and this flag is set for those backends.) */ @@ -647,8 +647,8 @@ struct elf_backend_data /* Whether the default relocation type is RELA. If a backend with this flag set wants REL relocations for a particular section, it must note that explicitly. Similarly, if this flag is clear, - and the backend wants RELA relocations for a particular - section. */ + and the backend wants RELA relocations for a particular + section. */ unsigned default_use_rela_p : 1; /* True if addresses "naturally" sign extend. This is used when @@ -1013,7 +1013,7 @@ extern boolean _bfd_elf_find_nearest_line PARAMS ((bfd *, asection *, #define _bfd_elf_minisymbol_to_symbol _bfd_generic_minisymbol_to_symbol extern int _bfd_elf_sizeof_headers PARAMS ((bfd *, boolean)); extern boolean _bfd_elf_new_section_hook PARAMS ((bfd *, asection *)); -extern boolean _bfd_elf_init_reloc_shdr +extern boolean _bfd_elf_init_reloc_shdr PARAMS ((bfd *, Elf_Internal_Shdr *, asection *, boolean)); /* If the target doesn't have reloc handling written yet: */ @@ -1282,11 +1282,11 @@ extern boolean _bfd_mips_elf_finish_dynamic_symbol Elf_Internal_Sym *)); extern boolean _bfd_mips_elf_finish_dynamic_sections PARAMS ((bfd *, struct bfd_link_info *)); -extern asection * _bfd_mips_elf_gc_mark_hook +extern asection * _bfd_mips_elf_gc_mark_hook PARAMS ((bfd *, struct bfd_link_info *, Elf_Internal_Rela *, struct elf_link_hash_entry *, Elf_Internal_Sym *)); -extern boolean _bfd_mips_elf_gc_sweep_hook - PARAMS ((bfd *, struct bfd_link_info *, asection *, +extern boolean _bfd_mips_elf_gc_sweep_hook + PARAMS ((bfd *, struct bfd_link_info *, asection *, const Elf_Internal_Rela *)); extern boolean _bfd_mips_elf_always_size_sections PARAMS ((bfd *, struct bfd_link_info *)); @@ -1297,7 +1297,7 @@ extern boolean _bfd_mips_elf_check_relocs const Elf_Internal_Rela *)); extern struct bfd_link_hash_table *_bfd_mips_elf_link_hash_table_create PARAMS ((bfd *)); -extern boolean _bfd_mips_elf_print_private_bfd_data +extern boolean _bfd_mips_elf_print_private_bfd_data PARAMS ((bfd *, PTR)); extern boolean _bfd_mips_elf_link_output_symbol_hook PARAMS ((bfd *, struct bfd_link_info *, const char *, Elf_Internal_Sym *, diff --git a/bfd/elf.c b/bfd/elf.c index a52d7933cd9..f88ebbd6ee4 100644 --- a/bfd/elf.c +++ b/bfd/elf.c @@ -1333,8 +1333,10 @@ bfd_section_from_shdr (abfd, shindex) /* If this reloc section does not use the main symbol table we don't treat it as a reloc section. BFD can't adequately represent such a section, so at least for now, we don't - try. We just present it as a normal section. */ - if (hdr->sh_link != elf_onesymtab (abfd)) + try. We just present it as a normal section. We also + can't use it as a reloc section if it points to the null + section. */ + if (hdr->sh_link != elf_onesymtab (abfd) || hdr->sh_info == SHN_UNDEF) return _bfd_elf_make_section_from_shdr (abfd, hdr, name); if (! bfd_section_from_shdr (abfd, hdr->sh_info)) @@ -3265,6 +3267,12 @@ prep_headers (abfd) case bfd_arch_ia64: i_ehdrp->e_machine = EM_IA_64; break; + case bfd_arch_m68hc11: + i_ehdrp->e_machine = EM_68HC11; + break; + case bfd_arch_m68hc12: + i_ehdrp->e_machine = EM_68HC12; + break; case bfd_arch_m68k: i_ehdrp->e_machine = EM_68K; break; diff --git a/bfd/elf32-m68hc11.c b/bfd/elf32-m68hc11.c new file mode 100644 index 00000000000..594d114ea9e --- /dev/null +++ b/bfd/elf32-m68hc11.c @@ -0,0 +1,281 @@ +/* Motorola 68HC11-specific support for 32-bit ELF + Copyright (C) 1999, 2000 Free Software Foundation, Inc. + Contributed by Stephane Carrez (stcarrez@worldnet.fr) + (Heavily copied from the D10V port by Martin Hunt (hunt@cygnus.com)) + +This file is part of BFD, the Binary File Descriptor library. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; if not, write to the Free Software +Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#include "bfd.h" +#include "sysdep.h" +#include "libbfd.h" +#include "elf-bfd.h" +#include "elf/m68hc11.h" + +static reloc_howto_type *bfd_elf32_bfd_reloc_type_lookup +PARAMS ((bfd * abfd, bfd_reloc_code_real_type code)); +static void m68hc11_info_to_howto_rel +PARAMS ((bfd *, arelent *, Elf32_Internal_Rel *)); + + +/* Use REL instead of RELA to save space */ +#define USE_REL + +/* The Motorola 68HC11 microcontroler only addresses 64Kb. + We must handle 8 and 16-bit relocations. The 32-bit relocation + is defined but not used except by gas when -gstabs is used (which + is wrong). + The 3-bit and 16-bit PC rel relocation is only used by 68HC12. */ +static reloc_howto_type elf_m68hc11_howto_table[] = { + /* This reloc does nothing. */ + HOWTO (R_M68HC11_NONE, /* type */ + 0, /* rightshift */ + 2, /* size (0 = byte, 1 = short, 2 = long) */ + 32, /* bitsize */ + false, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_bitfield, /* complain_on_overflow */ + bfd_elf_generic_reloc, /* special_function */ + "R_M68HC11_NONE", /* name */ + false, /* partial_inplace */ + 0, /* src_mask */ + 0, /* dst_mask */ + false), /* pcrel_offset */ + + /* A 8 bit absolute relocation */ + HOWTO (R_M68HC11_8, /* type */ + 0, /* rightshift */ + 0, /* size (0 = byte, 1 = short, 2 = long) */ + 8, /* bitsize */ + false, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_bitfield, /* complain_on_overflow */ + bfd_elf_generic_reloc, /* special_function */ + "R_M68HC11_8", /* name */ + false, /* partial_inplace */ + 0x00ff, /* src_mask */ + 0x00ff, /* dst_mask */ + false), /* pcrel_offset */ + + /* A 8 bit absolute relocation (upper address) */ + HOWTO (R_M68HC11_HI8, /* type */ + 8, /* rightshift */ + 0, /* size (0 = byte, 1 = short, 2 = long) */ + 8, /* bitsize */ + false, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_bitfield, /* complain_on_overflow */ + bfd_elf_generic_reloc, /* special_function */ + "R_M68HC11_HI8", /* name */ + false, /* partial_inplace */ + 0x00ff, /* src_mask */ + 0x00ff, /* dst_mask */ + false), /* pcrel_offset */ + + /* A 8 bit absolute relocation (upper address) */ + HOWTO (R_M68HC11_LO8, /* type */ + 0, /* rightshift */ + 0, /* size (0 = byte, 1 = short, 2 = long) */ + 8, /* bitsize */ + false, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_dont, /* complain_on_overflow */ + bfd_elf_generic_reloc, /* special_function */ + "R_M68HC11_LO8", /* name */ + false, /* partial_inplace */ + 0x00ff, /* src_mask */ + 0x00ff, /* dst_mask */ + false), /* pcrel_offset */ + + /* A 8 bit PC-rel relocation */ + HOWTO (R_M68HC11_PCREL_8, /* type */ + 0, /* rightshift */ + 0, /* size (0 = byte, 1 = short, 2 = long) */ + 8, /* bitsize */ + true, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_bitfield, /* complain_on_overflow */ + bfd_elf_generic_reloc, /* special_function */ + "R_M68HC11_PCREL_8", /* name */ + false, /* partial_inplace */ + 0x0, /* src_mask */ + 0x00ff, /* dst_mask */ + false), /* pcrel_offset */ + + /* A 16 bit absolute relocation */ + HOWTO (R_M68HC11_16, /* type */ + 0, /* rightshift */ + 1, /* size (0 = byte, 1 = short, 2 = long) */ + 16, /* bitsize */ + false, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_dont /*bitfield */ , /* complain_on_overflow */ + bfd_elf_generic_reloc, /* special_function */ + "R_M68HC11_16", /* name */ + false, /* partial_inplace */ + 0xffff, /* src_mask */ + 0xffff, /* dst_mask */ + false), /* pcrel_offset */ + + /* A 32 bit absolute relocation. This one is never used for the + code relocation. It's used by gas for -gstabs generation. */ + HOWTO (R_M68HC11_32, /* type */ + 0, /* rightshift */ + 2, /* size (0 = byte, 1 = short, 2 = long) */ + 32, /* bitsize */ + false, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_bitfield, /* complain_on_overflow */ + bfd_elf_generic_reloc, /* special_function */ + "R_M68HC11_32", /* name */ + false, /* partial_inplace */ + 0xffffffff, /* src_mask */ + 0xffffffff, /* dst_mask */ + false), /* pcrel_offset */ + + /* A 3 bit absolute relocation */ + HOWTO (R_M68HC11_3B, /* type */ + 0, /* rightshift */ + 0, /* size (0 = byte, 1 = short, 2 = long) */ + 3, /* bitsize */ + false, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_bitfield, /* complain_on_overflow */ + bfd_elf_generic_reloc, /* special_function */ + "R_M68HC11_4B", /* name */ + false, /* partial_inplace */ + 0x003, /* src_mask */ + 0x003, /* dst_mask */ + false), /* pcrel_offset */ + + /* A 16 bit PC-rel relocation */ + HOWTO (R_M68HC11_PCREL_16, /* type */ + 0, /* rightshift */ + 1, /* size (0 = byte, 1 = short, 2 = long) */ + 16, /* bitsize */ + true, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_dont, /* complain_on_overflow */ + bfd_elf_generic_reloc, /* special_function */ + "R_M68HC11_PCREL_16", /* name */ + false, /* partial_inplace */ + 0x0, /* src_mask */ + 0xffff, /* dst_mask */ + false), /* pcrel_offset */ + + /* GNU extension to record C++ vtable hierarchy */ + HOWTO (R_M68HC11_GNU_VTINHERIT, /* type */ + 0, /* rightshift */ + 1, /* size (0 = byte, 1 = short, 2 = long) */ + 0, /* bitsize */ + false, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_dont, /* complain_on_overflow */ + NULL, /* special_function */ + "R_M68HC11_GNU_VTINHERIT", /* name */ + false, /* partial_inplace */ + 0, /* src_mask */ + 0, /* dst_mask */ + false), /* pcrel_offset */ + + /* GNU extension to record C++ vtable member usage */ + HOWTO (R_M68HC11_GNU_VTENTRY, /* type */ + 0, /* rightshift */ + 1, /* size (0 = byte, 1 = short, 2 = long) */ + 0, /* bitsize */ + false, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_dont, /* complain_on_overflow */ + _bfd_elf_rel_vtable_reloc_fn, /* special_function */ + "R_M68HC11_GNU_VTENTRY", /* name */ + false, /* partial_inplace */ + 0, /* src_mask */ + 0, /* dst_mask */ + false), /* pcrel_offset */ +}; + +/* Map BFD reloc types to M68HC11 ELF reloc types. */ + +struct m68hc11_reloc_map +{ + bfd_reloc_code_real_type bfd_reloc_val; + unsigned char elf_reloc_val; +}; + +static const struct m68hc11_reloc_map m68hc11_reloc_map[] = { + {BFD_RELOC_NONE, R_M68HC11_NONE,}, + {BFD_RELOC_8, R_M68HC11_8}, + {BFD_RELOC_M68HC11_HI8, R_M68HC11_HI8}, + {BFD_RELOC_M68HC11_LO8, R_M68HC11_LO8}, + {BFD_RELOC_8_PCREL, R_M68HC11_PCREL_8}, + {BFD_RELOC_16_PCREL, R_M68HC11_PCREL_16}, + {BFD_RELOC_16, R_M68HC11_16}, + {BFD_RELOC_32, R_M68HC11_32}, + {BFD_RELOC_M68HC11_3B, R_M68HC11_3B}, + + /* The following relocs are defined but they probably don't work yet. */ + {BFD_RELOC_VTABLE_INHERIT, R_M68HC11_GNU_VTINHERIT}, + {BFD_RELOC_VTABLE_ENTRY, R_M68HC11_GNU_VTENTRY}, +}; + +static reloc_howto_type * +bfd_elf32_bfd_reloc_type_lookup (abfd, code) + bfd *abfd ATTRIBUTE_UNUSED; + bfd_reloc_code_real_type code; +{ + unsigned int i; + + for (i = 0; + i < sizeof (m68hc11_reloc_map) / sizeof (struct m68hc11_reloc_map); + i++) + { + if (m68hc11_reloc_map[i].bfd_reloc_val == code) + return &elf_m68hc11_howto_table[m68hc11_reloc_map[i].elf_reloc_val]; + } + + return NULL; +} + +/* Set the howto pointer for an M68HC11 ELF reloc. */ + +static void +m68hc11_info_to_howto_rel (abfd, cache_ptr, dst) + bfd *abfd ATTRIBUTE_UNUSED; + arelent *cache_ptr; + Elf32_Internal_Rel *dst; +{ + unsigned int r_type; + + r_type = ELF32_R_TYPE (dst->r_info); + BFD_ASSERT (r_type < (unsigned int) R_M68HC11_max); + cache_ptr->howto = &elf_m68hc11_howto_table[r_type]; +} + +/* Below is the only difference between elf32-m68hc12.c and elf32-m68hc11.c. + The Motorola spec says to use a different Elf machine code. */ +#define ELF_ARCH bfd_arch_m68hc11 +#define ELF_MACHINE_CODE EM_68HC11 +#define ELF_MAXPAGESIZE 0x1000 + +#define TARGET_BIG_SYM bfd_elf32_m68hc11_vec +#define TARGET_BIG_NAME "elf32-m68hc11" + +#define elf_info_to_howto 0 +#define elf_info_to_howto_rel m68hc11_info_to_howto_rel +#define elf_backend_object_p 0 +#define elf_backend_final_write_processing 0 + +#include "elf32-target.h" diff --git a/bfd/elf32-m68hc12.c b/bfd/elf32-m68hc12.c new file mode 100644 index 00000000000..b4db9bc58e1 --- /dev/null +++ b/bfd/elf32-m68hc12.c @@ -0,0 +1,281 @@ +/* Motorola 68HC12-specific support for 32-bit ELF + Copyright (C) 1999, 2000 Free Software Foundation, Inc. + Contributed by Stephane Carrez (stcarrez@worldnet.fr) + (Heavily copied from the D10V port by Martin Hunt (hunt@cygnus.com)) + +This file is part of BFD, the Binary File Descriptor library. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; if not, write to the Free Software +Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#include "bfd.h" +#include "sysdep.h" +#include "libbfd.h" +#include "elf-bfd.h" +#include "elf/m68hc11.h" + +static reloc_howto_type *bfd_elf32_bfd_reloc_type_lookup +PARAMS ((bfd * abfd, bfd_reloc_code_real_type code)); +static void m68hc11_info_to_howto_rel +PARAMS ((bfd *, arelent *, Elf32_Internal_Rel *)); + + +/* Use REL instead of RELA to save space */ +#define USE_REL + +/* The Motorola 68HC11 microcontroler only addresses 64Kb. + We must handle 8 and 16-bit relocations. The 32-bit relocation + is defined but not used except by gas when -gstabs is used (which + is wrong). + The 3-bit and 16-bit PC rel relocation is only used by 68HC12. */ +static reloc_howto_type elf_m68hc11_howto_table[] = { + /* This reloc does nothing. */ + HOWTO (R_M68HC11_NONE, /* type */ + 0, /* rightshift */ + 2, /* size (0 = byte, 1 = short, 2 = long) */ + 32, /* bitsize */ + false, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_bitfield, /* complain_on_overflow */ + bfd_elf_generic_reloc, /* special_function */ + "R_M68HC11_NONE", /* name */ + false, /* partial_inplace */ + 0, /* src_mask */ + 0, /* dst_mask */ + false), /* pcrel_offset */ + + /* A 8 bit absolute relocation */ + HOWTO (R_M68HC11_8, /* type */ + 0, /* rightshift */ + 0, /* size (0 = byte, 1 = short, 2 = long) */ + 8, /* bitsize */ + false, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_bitfield, /* complain_on_overflow */ + bfd_elf_generic_reloc, /* special_function */ + "R_M68HC11_8", /* name */ + false, /* partial_inplace */ + 0x00ff, /* src_mask */ + 0x00ff, /* dst_mask */ + false), /* pcrel_offset */ + + /* A 8 bit absolute relocation (upper address) */ + HOWTO (R_M68HC11_HI8, /* type */ + 8, /* rightshift */ + 0, /* size (0 = byte, 1 = short, 2 = long) */ + 8, /* bitsize */ + false, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_bitfield, /* complain_on_overflow */ + bfd_elf_generic_reloc, /* special_function */ + "R_M68HC11_HI8", /* name */ + false, /* partial_inplace */ + 0x00ff, /* src_mask */ + 0x00ff, /* dst_mask */ + false), /* pcrel_offset */ + + /* A 8 bit absolute relocation (upper address) */ + HOWTO (R_M68HC11_LO8, /* type */ + 0, /* rightshift */ + 0, /* size (0 = byte, 1 = short, 2 = long) */ + 8, /* bitsize */ + false, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_dont, /* complain_on_overflow */ + bfd_elf_generic_reloc, /* special_function */ + "R_M68HC11_LO8", /* name */ + false, /* partial_inplace */ + 0x00ff, /* src_mask */ + 0x00ff, /* dst_mask */ + false), /* pcrel_offset */ + + /* A 8 bit PC-rel relocation */ + HOWTO (R_M68HC11_PCREL_8, /* type */ + 0, /* rightshift */ + 0, /* size (0 = byte, 1 = short, 2 = long) */ + 8, /* bitsize */ + true, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_bitfield, /* complain_on_overflow */ + bfd_elf_generic_reloc, /* special_function */ + "R_M68HC11_PCREL_8", /* name */ + false, /* partial_inplace */ + 0x0, /* src_mask */ + 0x00ff, /* dst_mask */ + false), /* pcrel_offset */ + + /* A 16 bit absolute relocation */ + HOWTO (R_M68HC11_16, /* type */ + 0, /* rightshift */ + 1, /* size (0 = byte, 1 = short, 2 = long) */ + 16, /* bitsize */ + false, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_dont /*bitfield */ , /* complain_on_overflow */ + bfd_elf_generic_reloc, /* special_function */ + "R_M68HC11_16", /* name */ + false, /* partial_inplace */ + 0xffff, /* src_mask */ + 0xffff, /* dst_mask */ + false), /* pcrel_offset */ + + /* A 32 bit absolute relocation. This one is never used for the + code relocation. It's used by gas for -gstabs generation. */ + HOWTO (R_M68HC11_32, /* type */ + 0, /* rightshift */ + 2, /* size (0 = byte, 1 = short, 2 = long) */ + 32, /* bitsize */ + false, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_bitfield, /* complain_on_overflow */ + bfd_elf_generic_reloc, /* special_function */ + "R_M68HC11_32", /* name */ + false, /* partial_inplace */ + 0xffffffff, /* src_mask */ + 0xffffffff, /* dst_mask */ + false), /* pcrel_offset */ + + /* A 3 bit absolute relocation */ + HOWTO (R_M68HC11_3B, /* type */ + 0, /* rightshift */ + 0, /* size (0 = byte, 1 = short, 2 = long) */ + 3, /* bitsize */ + false, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_bitfield, /* complain_on_overflow */ + bfd_elf_generic_reloc, /* special_function */ + "R_M68HC11_4B", /* name */ + false, /* partial_inplace */ + 0x003, /* src_mask */ + 0x003, /* dst_mask */ + false), /* pcrel_offset */ + + /* A 16 bit PC-rel relocation */ + HOWTO (R_M68HC11_PCREL_16, /* type */ + 0, /* rightshift */ + 1, /* size (0 = byte, 1 = short, 2 = long) */ + 16, /* bitsize */ + true, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_dont, /* complain_on_overflow */ + bfd_elf_generic_reloc, /* special_function */ + "R_M68HC11_PCREL_16", /* name */ + false, /* partial_inplace */ + 0x0, /* src_mask */ + 0xffff, /* dst_mask */ + false), /* pcrel_offset */ + + /* GNU extension to record C++ vtable hierarchy */ + HOWTO (R_M68HC11_GNU_VTINHERIT, /* type */ + 0, /* rightshift */ + 1, /* size (0 = byte, 1 = short, 2 = long) */ + 0, /* bitsize */ + false, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_dont, /* complain_on_overflow */ + NULL, /* special_function */ + "R_M68HC11_GNU_VTINHERIT", /* name */ + false, /* partial_inplace */ + 0, /* src_mask */ + 0, /* dst_mask */ + false), /* pcrel_offset */ + + /* GNU extension to record C++ vtable member usage */ + HOWTO (R_M68HC11_GNU_VTENTRY, /* type */ + 0, /* rightshift */ + 1, /* size (0 = byte, 1 = short, 2 = long) */ + 0, /* bitsize */ + false, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_dont, /* complain_on_overflow */ + _bfd_elf_rel_vtable_reloc_fn, /* special_function */ + "R_M68HC11_GNU_VTENTRY", /* name */ + false, /* partial_inplace */ + 0, /* src_mask */ + 0, /* dst_mask */ + false), /* pcrel_offset */ +}; + +/* Map BFD reloc types to M68HC11 ELF reloc types. */ + +struct m68hc11_reloc_map +{ + bfd_reloc_code_real_type bfd_reloc_val; + unsigned char elf_reloc_val; +}; + +static const struct m68hc11_reloc_map m68hc11_reloc_map[] = { + {BFD_RELOC_NONE, R_M68HC11_NONE,}, + {BFD_RELOC_8, R_M68HC11_8}, + {BFD_RELOC_M68HC11_HI8, R_M68HC11_HI8}, + {BFD_RELOC_M68HC11_LO8, R_M68HC11_LO8}, + {BFD_RELOC_8_PCREL, R_M68HC11_PCREL_8}, + {BFD_RELOC_16_PCREL, R_M68HC11_PCREL_16}, + {BFD_RELOC_16, R_M68HC11_16}, + {BFD_RELOC_32, R_M68HC11_32}, + {BFD_RELOC_M68HC11_3B, R_M68HC11_3B}, + + /* The following relocs are defined but they probably don't work yet. */ + {BFD_RELOC_VTABLE_INHERIT, R_M68HC11_GNU_VTINHERIT}, + {BFD_RELOC_VTABLE_ENTRY, R_M68HC11_GNU_VTENTRY}, +}; + +static reloc_howto_type * +bfd_elf32_bfd_reloc_type_lookup (abfd, code) + bfd *abfd ATTRIBUTE_UNUSED; + bfd_reloc_code_real_type code; +{ + unsigned int i; + + for (i = 0; + i < sizeof (m68hc11_reloc_map) / sizeof (struct m68hc11_reloc_map); + i++) + { + if (m68hc11_reloc_map[i].bfd_reloc_val == code) + return &elf_m68hc11_howto_table[m68hc11_reloc_map[i].elf_reloc_val]; + } + + return NULL; +} + +/* Set the howto pointer for an M68HC11 ELF reloc. */ + +static void +m68hc11_info_to_howto_rel (abfd, cache_ptr, dst) + bfd *abfd ATTRIBUTE_UNUSED; + arelent *cache_ptr; + Elf32_Internal_Rel *dst; +{ + unsigned int r_type; + + r_type = ELF32_R_TYPE (dst->r_info); + BFD_ASSERT (r_type < (unsigned int) R_M68HC11_max); + cache_ptr->howto = &elf_m68hc11_howto_table[r_type]; +} + +/* Below is the only difference between elf32-m68hc12.c and elf32-m68hc11.c. + The Motorola spec says to use a different Elf machine code. */ +#define ELF_ARCH bfd_arch_m68hc12 +#define ELF_MACHINE_CODE EM_68HC12 +#define ELF_MAXPAGESIZE 0x1000 + +#define TARGET_BIG_SYM bfd_elf32_m68hc12_vec +#define TARGET_BIG_NAME "elf32-m68hc12" + +#define elf_info_to_howto 0 +#define elf_info_to_howto_rel m68hc11_info_to_howto_rel +#define elf_backend_object_p 0 +#define elf_backend_final_write_processing 0 + +#include "elf32-target.h" diff --git a/bfd/elfcode.h b/bfd/elfcode.h index b1ce9d820fd..cd8e9a6a35a 100644 --- a/bfd/elfcode.h +++ b/bfd/elfcode.h @@ -167,7 +167,7 @@ static void elf_swap_shdr_out #define section_from_elf_index bfd_section_from_elf_index -static boolean elf_slurp_reloc_table_from_section +static boolean elf_slurp_reloc_table_from_section PARAMS ((bfd *, asection *, Elf_Internal_Shdr *, bfd_size_type, arelent *, asymbol **, boolean)); @@ -1224,7 +1224,7 @@ error_return: return -1; } -/* Read relocations for ASECT from REL_HDR. There are RELOC_COUNT of +/* Read relocations for ASECT from REL_HDR. There are RELOC_COUNT of them. */ static boolean @@ -1349,7 +1349,7 @@ elf_slurp_reloc_table (abfd, asect, symbols, dynamic) rel_hdr = &d->rel_hdr; reloc_count = rel_hdr->sh_size / rel_hdr->sh_entsize; rel_hdr2 = d->rel_hdr2; - reloc_count2 = (rel_hdr2 + reloc_count2 = (rel_hdr2 ? (rel_hdr2->sh_size / rel_hdr2->sh_entsize) : 0); @@ -1373,8 +1373,8 @@ elf_slurp_reloc_table (abfd, asect, symbols, dynamic) reloc_count2 = 0; } - relents = ((arelent *) - bfd_alloc (abfd, + relents = ((arelent *) + bfd_alloc (abfd, (reloc_count + reloc_count2) * sizeof (arelent))); if (relents == NULL) return false; @@ -1384,15 +1384,15 @@ elf_slurp_reloc_table (abfd, asect, symbols, dynamic) relents, symbols, dynamic)) return false; - - if (rel_hdr2 + + if (rel_hdr2 && !elf_slurp_reloc_table_from_section (abfd, asect, rel_hdr2, reloc_count2, relents + reloc_count, symbols, dynamic)) return false; - + asect->relocation = relents; return true; } diff --git a/bfd/elfcore.h b/bfd/elfcore.h index ec03ec3f637..11bfeac734f 100644 --- a/bfd/elfcore.h +++ b/bfd/elfcore.h @@ -99,9 +99,7 @@ elf_core_file_p (abfd) /* Check the magic number. */ if (elf_file_p (&x_ehdr) == false) - { - goto wrong; - } + goto wrong; /* FIXME: Check EI_VERSION here ! */ diff --git a/bfd/elfxx-target.h b/bfd/elfxx-target.h index b1f4867e569..3b9b434fcf3 100644 --- a/bfd/elfxx-target.h +++ b/bfd/elfxx-target.h @@ -313,7 +313,6 @@ Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ #define elf_backend_hide_symbol _bfd_elf_link_hash_hide_symbol #endif - /* Previously, backends could only use SHT_REL or SHT_RELA relocation sections, but not both. They defined USE_REL to indicate SHT_REL sections, and left it undefined to indicated SHT_RELA sections. diff --git a/bfd/libbfd.h b/bfd/libbfd.h index effb0e819b0..d7e77308e1e 100644 --- a/bfd/libbfd.h +++ b/bfd/libbfd.h @@ -965,6 +965,9 @@ static const char *const bfd_reloc_code_real_names[] = { "@@uninitialized@@", "BFD_RELOC_IA64_LTOFF_TP22", "BFD_RELOC_IA64_LTOFF22X", "BFD_RELOC_IA64_LDXMOV", + "BFD_RELOC_M68HC11_HI8", + "BFD_RELOC_M68HC11_LO8", + "BFD_RELOC_M68HC11_3B", "@@overflow: BFD_RELOC_UNUSED@@", }; #endif diff --git a/bfd/peicode.h b/bfd/peicode.h index 56bc1c31d3c..8f64453a3f4 100644 --- a/bfd/peicode.h +++ b/bfd/peicode.h @@ -69,7 +69,6 @@ static boolean (*pe_saved_coff_bfd_print_private_bfd_data) static boolean pe_print_private_bfd_data PARAMS ((bfd *, PTR)); #define coff_bfd_print_private_bfd_data pe_print_private_bfd_data - static boolean (*pe_saved_coff_bfd_copy_private_bfd_data) PARAMS ((bfd *, bfd *)) = #ifndef coff_bfd_copy_private_bfd_data @@ -243,7 +242,6 @@ coff_swap_filehdr_in (abfd, src, dst) #define coff_swap_filehdr_out _bfd_pe_only_swap_filehdr_out #endif - static void coff_swap_scnhdr_in (abfd, ext, in) bfd *abfd; diff --git a/bfd/po/POTFILES.in b/bfd/po/POTFILES.in index 94b82823eed..aecb88ec78f 100644 --- a/bfd/po/POTFILES.in +++ b/bfd/po/POTFILES.in @@ -1,14 +1,14 @@ aix386-core.c +aout0.c +aout32.c +aout64.c aout-adobe.c aout-arm.c +aoutf1.h aout-ns32k.c aout-sparcle.c aout-target.h aout-tic30.c -aout0.c -aout32.c -aout64.c -aoutf1.h aoutx.h archive.c archures.c @@ -21,17 +21,21 @@ cf-i386lynx.c cf-m68klynx.c cf-sparclynx.c cisco-core.c +coff64-rs6000.c coff-a29k.c coff-alpha.c coff-apollo.c coff-arm.c coff-aux.c +coffcode.h +coffgen.c coff-go32.c coff-h8300.c coff-h8500.c coff-i386.c coff-i860.c coff-i960.c +cofflink.c coff-m68k.c coff-m88k.c coff-mips.c @@ -41,21 +45,20 @@ coff-sh.c coff-sparc.c coff-stgo32.c coff-svm68k.c +coffswap.h coff-tic30.c +coff-tic54x.c coff-tic80.c coff-u68k.c coff-w65.c coff-we32k.c coff-z8k.c -coffcode.h -coffgen.c -cofflink.c -coffswap.h corefile.c cpu-a29k.c cpu-alpha.c cpu-arc.c cpu-arm.c +cpu-avr.c cpu-d10v.c cpu-d30v.c cpu-fr30.c @@ -66,9 +69,12 @@ cpu-i370.c cpu-i386.c cpu-i860.c cpu-i960.c +cpu-ia64.c cpu-m10200.c cpu-m10300.c cpu-m32r.c +cpu-m68hc11.c +cpu-m68hc12.c cpu-m68k.c cpu-m88k.c cpu-mcore.c @@ -80,6 +86,7 @@ cpu-rs6000.c cpu-sh.c cpu-sparc.c cpu-tic30.c +cpu-tic54x.c cpu-tic80.c cpu-v850.c cpu-vax.c @@ -92,21 +99,25 @@ dwarf2.c ecoff.c ecofflink.c ecoffswap.h -elf-bfd.h -elf-m10200.c -elf-m10300.c -elf.c +efi-app-ia32.c +efi-app-ia64.c elf32-arc.c elf32-arm.h +elf32-avr.c +elf32.c elf32-d10v.c elf32-d30v.c elf32-fr30.c elf32-gen.c +elf32-hppa.c +elf32-hppa.h elf32-i370.c elf32-i386.c elf32-i860.c elf32-i960.c elf32-m32r.c +elf32-m68hc11.c +elf32-m68hc12.c elf32-m68k.c elf32-m88k.c elf32-mcore.c @@ -116,20 +127,25 @@ elf32-ppc.c elf32-sh.c elf32-sparc.c elf32-v850.c -elf32.c elf64-alpha.c +elf64.c elf64-gen.c elf64-hppa.c elf64-hppa.h +elf64-ia64.c elf64-mips.c elf64-sparc.c -elf64.c elfarm-nabi.c elfarm-oabi.c +elf-bfd.h +elf.c elfcode.h elfcore.h +elf-hppa.h elflink.c elflink.h +elf-m10200.c +elf-m10300.c epoc-pe-arm.c epoc-pei-arm.c format.c @@ -139,6 +155,7 @@ go32stub.h hash.c hp300bsd.c hp300hpux.c +hppa_stubs.h hpux-core.c i386aout.c i386bsd.c @@ -174,16 +191,16 @@ m88kmach3.c mipsbsd.c netbsd.h newsos3.c -nlm-target.h -nlm.c nlm32-alpha.c +nlm32.c nlm32-i386.c nlm32-ppc.c nlm32-sparc.c -nlm32.c nlm64.c +nlm.c nlmcode.h nlmswap.h +nlm-target.h ns32k.h ns32knetbsd.c oasys.c @@ -192,17 +209,21 @@ osf-core.c pc532-mach.c pe-arm.c pe-i386.c -pe-mcore.c -pe-ppc.c pei-arm.c +peicode.h +peigen.c pei-i386.c pei-mcore.c +pei-mips.c pei-ppc.c -peicode.h -peigen.c +pei-sh.c +pe-mcore.c +pe-mips.c +pe-ppc.c +pe-sh.c ppcboot.c -reloc.c reloc16.c +reloc.c riscix.c sco5-core.c section.c @@ -212,8 +233,8 @@ sparclinux.c sparclynx.c sparcnetbsd.c srec.c -stab-syms.c stabs.c +stab-syms.c sunos.c syms.c targets.c @@ -221,10 +242,11 @@ tekhex.c trad-core.c vaxnetbsd.c versados.c +vms.c vms-gsd.c +vms.h vms-hdr.c vms-misc.c vms-tir.c -vms.c -vms.h xcofflink.c +xcoff-target.h diff --git a/bfd/po/bfd.pot b/bfd/po/bfd.pot index 10ce3220b9f..3275437c3ad 100644 --- a/bfd/po/bfd.pot +++ b/bfd/po/bfd.pot @@ -6,7 +6,7 @@ msgid "" msgstr "" "Project-Id-Version: PACKAGE VERSION\n" -"POT-Creation-Date: 2000-04-04 23:18+0930\n" +"POT-Creation-Date: 2000-06-18 17:36-0700\n" "PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n" "Last-Translator: FULL NAME <EMAIL@ADDRESS>\n" "Language-Team: LANGUAGE <LL@li.org>\n" @@ -39,16 +39,16 @@ msgstr "" msgid "%s: relocateable link from %s to %s not supported" msgstr "" -#: archive.c:1724 +#: archive.c:1808 msgid "Warning: writing archive was slow: rewriting timestamp\n" msgstr "" -#: archive.c:1990 +#: archive.c:2074 msgid "Reading archive file mod timestamp" msgstr "" #. FIXME: bfd can't call perror. -#: archive.c:2014 +#: archive.c:2098 msgid "Writing updated armap timestamp" msgstr "" @@ -176,7 +176,7 @@ msgstr "" msgid "GP relative relocation used when GP not defined" msgstr "" -#: coff-alpha.c:1486 elf64-alpha.c:3990 +#: coff-alpha.c:1486 elf64-alpha.c:3993 msgid "using multiple gp values" msgstr "" @@ -213,7 +213,7 @@ msgstr "" msgid " consider relinking with --support-old-code enabled" msgstr "" -#: coff-arm.c:1722 coff-tic80.c:682 cofflink.c:2980 +#: coff-arm.c:1722 coff-tic80.c:682 cofflink.c:2979 #, c-format msgid "%s: bad reloc address 0x%lx in section `%s'" msgstr "" @@ -271,19 +271,19 @@ msgstr "" msgid "private flags = %x:" msgstr "" -#: coff-arm.c:2293 elf32-arm.h:2089 +#: coff-arm.c:2293 elf32-arm.h:2142 msgid " [floats passed in float registers]" msgstr "" -#: coff-arm.c:2295 elf32-arm.h:2091 +#: coff-arm.c:2295 msgid " [floats passed in integer registers]" msgstr "" -#: coff-arm.c:2298 elf32-arm.h:2094 +#: coff-arm.c:2298 elf32-arm.h:2145 msgid " [position independent]" msgstr "" -#: coff-arm.c:2300 elf32-arm.h:2096 +#: coff-arm.c:2300 msgid " [absolute position]" msgstr "" @@ -311,144 +311,154 @@ msgstr "" msgid "Warning: Clearing the interworking flag of %s due to outside request" msgstr "" -#: coff-i960.c:136 coff-i960.c:485 -msgid "uncertain calling convention for non-COFF symbol" -msgstr "" - -#: coff-mips.c:875 elf32-mips.c:1406 -msgid "GP relative relocation when _gp not defined" -msgstr "" - -#: coff-mips.c:2433 -msgid "unsupported reloc type" -msgstr "" - -#. No other sections should appear in -membedded-pic -#. code. -#: coff-mips.c:2470 -msgid "reloc against unsupported section" -msgstr "" - -#: coff-mips.c:2478 -msgid "reloc not properly aligned" -msgstr "" - -#: coff-tic80.c:445 +#: coffcode.h:2101 #, c-format -msgid "Unrecognized reloc type 0x%x" +msgid "Unrecognized TI COFF target id '0x%x'" msgstr "" -#: coff-w65.c:383 -#, c-format -msgid "ignoring reloc %s\n" -msgstr "" - -#: coffcode.h:3965 +#: coffcode.h:4121 #, c-format msgid "%s: warning: illegal symbol index %ld in line numbers" msgstr "" -#: coffcode.h:3979 +#: coffcode.h:4135 #, c-format msgid "%s: warning: duplicate line number information for `%s'" msgstr "" -#: coffcode.h:4334 +#: coffcode.h:4495 #, c-format msgid "%s: Unrecognized storage class %d for %s symbol `%s'" msgstr "" -#: coffcode.h:4465 +#: coffcode.h:4626 #, c-format msgid "warning: %s: local symbol `%s' has no section" msgstr "" -#: coffcode.h:4578 +#: coff-tic54x.c:377 coffcode.h:4739 #, c-format msgid "%s: warning: illegal symbol index %ld in relocs" msgstr "" -#: coffcode.h:4616 +#: coffcode.h:4777 #, c-format msgid "%s: illegal relocation type %d at address 0x%lx" msgstr "" -#: coffgen.c:1613 +#: coffgen.c:1635 #, c-format msgid "%s: bad string table size %lu" msgstr "" -#: coffgen.c:2076 +#: coffgen.c:2098 #, c-format msgid "AUX tagndx %ld ttlsiz 0x%lx lnnos %ld next %ld" msgstr "" -#: cofflink.c:518 elflink.h:1568 +#: coff-i960.c:136 coff-i960.c:485 +msgid "uncertain calling convention for non-COFF symbol" +msgstr "" + +#: cofflink.c:518 elflink.h:1567 #, c-format msgid "Warning: type of symbol `%s' changed from %d to %d in %s" msgstr "" -#: cofflink.c:2285 +#: cofflink.c:2284 #, c-format msgid "%s: relocs in section `%s', but it has no contents" msgstr "" -#: cofflink.c:2619 coffswap.h:904 +#: cofflink.c:2618 coffswap.h:897 #, c-format msgid "%s: %s: reloc overflow: 0x%lx > 0xffff" msgstr "" -#: cofflink.c:2628 coffswap.h:891 +#: cofflink.c:2627 coffswap.h:883 #, c-format msgid "%s: warning: %s: line number overflow: 0x%lx > 0xffff" msgstr "" -#: dwarf2.c:429 +#: coff-mips.c:875 elf32-mips.c:1406 +msgid "GP relative relocation when _gp not defined" +msgstr "" + +#: coff-mips.c:2433 +msgid "unsupported reloc type" +msgstr "" + +#. No other sections should appear in -membedded-pic +#. code. +#: coff-mips.c:2470 +msgid "reloc against unsupported section" +msgstr "" + +#: coff-mips.c:2478 +msgid "reloc not properly aligned" +msgstr "" + +#: coff-tic54x.c:264 coff-tic80.c:445 +#, c-format +msgid "Unrecognized reloc type 0x%x" +msgstr "" + +#: coff-w65.c:383 +#, c-format +msgid "ignoring reloc %s\n" +msgstr "" + +#: dwarf2.c:432 msgid "Dwarf Error: Can't find .debug_abbrev section." msgstr "" -#: dwarf2.c:447 +#: dwarf2.c:450 #, c-format msgid "Dwarf Error: Abbrev offset (%u) bigger than abbrev size (%u)." msgstr "" -#: dwarf2.c:627 +#: dwarf2.c:630 #, c-format msgid "Dwarf Error: Invalid or unhandled FORM value: %d." msgstr "" -#: dwarf2.c:700 +#: dwarf2.c:704 msgid "Dwarf Error: mangled line number section (bad file number)." msgstr "" -#: dwarf2.c:791 +#: dwarf2.c:793 msgid "Dwarf Error: Can't find .debug_line section." msgstr "" -#: dwarf2.c:963 +#: dwarf2.c:817 +#, c-format +msgid "Dwarf Error: Line offset (%u) bigger than line size (%u)." +msgstr "" + +#: dwarf2.c:976 msgid "Dwarf Error: mangled line number section." msgstr "" -#: dwarf2.c:1151 dwarf2.c:1307 +#: dwarf2.c:1164 dwarf2.c:1320 #, c-format msgid "Dwarf Error: Could not find abbrev number %d." msgstr "" -#: dwarf2.c:1268 +#: dwarf2.c:1281 #, c-format msgid "" "Dwarf Error: found dwarf version '%hu', this reader only handles version 2 " "information." msgstr "" -#: dwarf2.c:1275 +#: dwarf2.c:1288 #, c-format msgid "" "Dwarf Error: found address size '%u', this reader can not handle sizes " "greater than '%u'." msgstr "" -#: dwarf2.c:1298 +#: dwarf2.c:1311 #, c-format msgid "Dwarf Error: Bad abbrev number: %d." msgstr "" @@ -514,230 +524,185 @@ msgid "" " Type: %s" msgstr "" -#: elf-m10200.c:455 elf-m10300.c:670 elf32-arm.h:1853 elf32-d10v.c:493 -#: elf32-fr30.c:651 elf32-m32r.c:1265 elf32-v850.c:1677 -msgid "internal error: out of range error" -msgstr "" - -#: elf-m10200.c:459 elf-m10300.c:674 elf32-arm.h:1857 elf32-d10v.c:497 -#: elf32-fr30.c:655 elf32-m32r.c:1269 elf32-v850.c:1681 -msgid "internal error: unsupported relocation error" -msgstr "" - -#: elf-m10200.c:463 elf-m10300.c:678 elf32-arm.h:1861 elf32-d10v.c:501 -#: elf32-m32r.c:1273 -msgid "internal error: dangerous error" -msgstr "" - -#: elf-m10200.c:467 elf-m10300.c:682 elf32-arm.h:1865 elf32-d10v.c:505 -#: elf32-fr30.c:663 elf32-m32r.c:1277 elf32-v850.c:1701 -msgid "internal error: unknown error" -msgstr "" - -#: elf.c:323 -#, c-format -msgid "%s: invalid string offset %u >= %lu for section `%s'" -msgstr "" - -#: elf.c:546 -msgid "" -"\n" -"Program Header:\n" -msgstr "" - -#: elf.c:594 -msgid "" -"\n" -"Dynamic Section:\n" -msgstr "" - -#: elf.c:696 -msgid "" -"\n" -"Version definitions:\n" -msgstr "" - -#: elf.c:719 -msgid "" -"\n" -"Version References:\n" -msgstr "" - -#: elf.c:724 +#: elf32-arm.h:1188 #, c-format -msgid " required from %s:\n" +msgid "%s: Warning: Arm BLX instruction targets Arm function '%s'." msgstr "" -#: elf.c:1286 +#: elf32-arm.h:1377 #, c-format -msgid "%s: invalid link %lu for reloc section %s (index %u)" +msgid "%s: Warning: Thumb BLX instruction targets thumb function '%s'." msgstr "" -#: elf.c:2045 +#: elf-hppa.h:1329 elf-hppa.h:1362 elf32-arm.h:1825 elf32-i386.c:1418 +#: elf32-ppc.c:3082 #, c-format msgid "" -"creating section symbol, name = %s, value = 0x%.8lx, index = %d, section = " -"0x%.8lx\n" -msgstr "" - -#: elf.c:2648 -#, c-format -msgid "%s: Not enough room for program headers (allocated %u, need %u)" -msgstr "" - -#: elf.c:2747 -#, c-format -msgid "%s: Not enough room for program headers, try linking with -N" -msgstr "" - -#: elf.c:2873 -#, c-format -msgid "Error: First section in segment (%s) starts at 0x%x" -msgstr "" - -#: elf.c:2876 -#, c-format -msgid " whereas segment starts at 0x%x" -msgstr "" - -#: elf.c:3146 -#, c-format -msgid "%s: warning: allocated section `%s' not in segment" -msgstr "" - -#: elf.c:3528 -#, c-format -msgid "%s: symbol `%s' required but not present" +"%s: warning: unresolvable relocation against symbol `%s' from %s section" msgstr "" -#: elf.c:3537 -#, c-format -msgid "" -"elf_symbol_from_bfd_symbol 0x%.8lx, name = %s, sym num = %d, flags = " -"0x%.8lx%s\n" +#: elf-m10200.c:455 elf-m10300.c:670 elf32-arm.h:1894 elf32-avr.c:844 +#: elf32-d10v.c:479 elf32-fr30.c:651 elf32-m32r.c:1265 elf32-v850.c:1677 +msgid "internal error: out of range error" msgstr "" -#: elf.c:3679 -#, c-format -msgid "%s: warning: Empty loadable segment detected\n" +#: elf-m10200.c:459 elf-m10300.c:674 elf32-arm.h:1898 elf32-avr.c:848 +#: elf32-d10v.c:483 elf32-fr30.c:655 elf32-m32r.c:1269 elf32-v850.c:1681 +msgid "internal error: unsupported relocation error" msgstr "" -#: elf.c:4956 -#, c-format -msgid "%s: unsupported relocation type %s" +#: elf-m10200.c:463 elf-m10300.c:678 elf32-arm.h:1902 elf32-d10v.c:487 +#: elf32-m32r.c:1273 +msgid "internal error: dangerous error" msgstr "" -#: elf32-arm.h:1787 elf32-i386.c:1304 elf32-ppc.c:3092 -#, c-format -msgid "" -"%s: warning: unresolvable relocation against symbol `%s' from %s section" +#: elf-m10200.c:467 elf-m10300.c:682 elf32-arm.h:1906 elf32-avr.c:856 +#: elf32-d10v.c:491 elf32-fr30.c:663 elf32-m32r.c:1277 elf32-v850.c:1701 +msgid "internal error: unknown error" msgstr "" -#: elf32-arm.h:1891 +#: elf32-arm.h:1934 #, c-format msgid "" "Warning: Not setting interwork flag of %s since it has already been " "specified as non-interworking" msgstr "" -#: elf32-arm.h:1895 +#: elf32-arm.h:1938 #, c-format msgid "Warning: Clearing the interwork flag of %s due to outside request" msgstr "" -#: elf32-arm.h:1943 +#: elf32-arm.h:1989 #, c-format msgid "" "Warning: Clearing the interwork flag in %s because non-interworking code in " "%s has been linked with it" msgstr "" -#: elf32-arm.h:1977 +#: elf32-arm.h:2058 #, c-format -msgid "%s: compiled for a %s endian system and target is %s endian" +msgid "" +"Error: %s compiled for EABI version %d, whereas %s is compiled for version %d" msgstr "" -#: elf32-arm.h:2023 +#: elf32-arm.h:2070 #, c-format msgid "Error: %s compiled for APCS-%d, whereas %s is compiled for APCS-%d" msgstr "" -#: elf32-arm.h:2031 +#: elf32-arm.h:2078 #, c-format msgid "" "Error: %s passes floats in %s registers, whereas %s passes them in %s " "registers" msgstr "" -#: elf32-arm.h:2034 elf32-arm.h:2036 +#: elf32-arm.h:2081 elf32-arm.h:2083 msgid "float" msgstr "" -#: elf32-arm.h:2034 elf32-arm.h:2036 +#: elf32-arm.h:2081 elf32-arm.h:2083 msgid "integer" msgstr "" -#: elf32-arm.h:2039 +#: elf32-arm.h:2086 #, c-format msgid "Error: %s is compiled as position %s code, whereas %s is not" msgstr "" -#: elf32-arm.h:2042 +#: elf32-arm.h:2089 msgid "independent" msgstr "" -#: elf32-arm.h:2042 +#: elf32-arm.h:2089 msgid "dependent" msgstr "" -#: elf32-arm.h:2048 +#: elf32-arm.h:2095 #, c-format msgid "Warning: %s %s interworking, whereas %s %s" msgstr "" -#: elf32-arm.h:2051 +#: elf32-arm.h:2098 msgid "supports" msgstr "" -#: elf32-arm.h:2051 +#: elf32-arm.h:2098 msgid "does not support" msgstr "" -#: elf32-arm.h:2053 +#: elf32-arm.h:2100 msgid "does not" msgstr "" -#: elf32-arm.h:2053 +#: elf32-arm.h:2100 msgid "does" msgstr "" #. Ignore init flag - it may not be set, despite the flags field containing valid data. -#: elf32-arm.h:2076 elf32-m68k.c:430 elf32-mips.c:2634 +#: elf32-arm.h:2125 elf32-m68k.c:430 elf32-mips.c:2621 #, c-format msgid "private flags = %lx:" msgstr "" -#: elf32-arm.h:2079 +#: elf32-arm.h:2134 msgid " [interworking enabled]" msgstr "" -#: elf32-arm.h:2081 -msgid " [interworking not enabled]" -msgstr "" - -#: elf32-arm.h:2084 +#: elf32-arm.h:2137 msgid " [APCS-26]" msgstr "" -#: elf32-arm.h:2086 +#: elf32-arm.h:2139 msgid " [APCS-32]" msgstr "" -#: elf32-fr30.c:659 elf32-v850.c:1685 +#: elf32-arm.h:2148 +msgid " [new ABI]" +msgstr "" + +#: elf32-arm.h:2151 +msgid " [old ABI]" +msgstr "" + +#: elf32-arm.h:2154 +msgid " [software FP]" +msgstr "" + +#: elf32-arm.h:2161 +msgid " [Version1 EABI]" +msgstr "" + +#: elf32-arm.h:2164 +msgid " [sorted symbol table]" +msgstr "" + +#: elf32-arm.h:2166 +msgid " [unsorted symbol table]" +msgstr "" + +#: elf32-arm.h:2172 +msgid " <EABI version unrecognised>" +msgstr "" + +#: elf32-arm.h:2179 +msgid " [relocatable executable]" +msgstr "" + +#: elf32-arm.h:2182 +msgid " [has entry point]" +msgstr "" + +#: elf32-arm.h:2187 +msgid "<Unrecognised flag bits set>" +msgstr "" + +#: elf32-avr.c:852 elf32-fr30.c:659 elf32-v850.c:1685 msgid "internal error: dangerous relocation" msgstr "" -#: elf32-i386.c:239 +#: elf32-i386.c:274 #, c-format msgid "%s: invalid relocation type %d" msgstr "" @@ -746,7 +711,7 @@ msgstr "" msgid "SDA relocation when _SDA_BASE_ not defined" msgstr "" -#: elf32-m32r.c:1000 elf32-ppc.c:2963 +#: elf32-m32r.c:1000 elf32-ppc.c:2950 elf64-ia64.c:3185 #, c-format msgid "%s: unknown relocation type %d" msgstr "" @@ -778,17 +743,12 @@ msgstr "" msgid " [cpu32]" msgstr "" -#: elf32-mcore.c:329 -#, c-format -msgid "%s: compiled for a %s endian system and target is %s endian.\n" -msgstr "" - -#: elf32-mcore.c:377 elf32-mcore.c:504 +#: elf32-mcore.c:367 elf32-mcore.c:494 #, c-format msgid "%s: Relocation %s (%d) is not currently supported.\n" msgstr "" -#: elf32-mcore.c:463 +#: elf32-mcore.c:453 #, c-format msgid "%s: Unknown relocation type %d\n" msgstr "" @@ -802,228 +762,218 @@ msgstr "" msgid "Linking mips16 objects into %s format is not supported" msgstr "" -#: elf32-mips.c:2469 elf32-ppc.c:1408 -#, c-format -msgid "%s: compiled for a big endian system and target is little endian" -msgstr "" - -#: elf32-mips.c:2471 elf32-ppc.c:1410 -#, c-format -msgid "%s: compiled for a little endian system and target is big endian" -msgstr "" - -#: elf32-mips.c:2520 +#: elf32-mips.c:2507 #, c-format msgid "%s: linking PIC files with non-PIC files" msgstr "" -#: elf32-mips.c:2530 +#: elf32-mips.c:2517 #, c-format msgid "%s: linking abicalls files with non-abicalls files" msgstr "" -#: elf32-mips.c:2560 +#: elf32-mips.c:2547 #, c-format msgid "%s: ISA mismatch (-mips%d) with previous modules (-mips%d)" msgstr "" -#: elf32-mips.c:2569 +#: elf32-mips.c:2556 #, c-format msgid "%s: ISA mismatch (%d) with previous modules (%d)" msgstr "" -#: elf32-mips.c:2592 +#: elf32-mips.c:2579 #, c-format msgid "%s: ABI mismatch: linking %s module with previous %s modules" msgstr "" -#: elf32-mips.c:2606 elf32-ppc.c:1477 elf64-sparc.c:2844 +#: elf32-mips.c:2593 elf32-ppc.c:1464 elf64-sparc.c:2957 #, c-format msgid "%s: uses different e_flags (0x%lx) fields than previous modules (0x%lx)" msgstr "" -#: elf32-mips.c:2637 +#: elf32-mips.c:2624 msgid " [abi=O32]" msgstr "" -#: elf32-mips.c:2639 +#: elf32-mips.c:2626 msgid " [abi=O64]" msgstr "" -#: elf32-mips.c:2641 +#: elf32-mips.c:2628 msgid " [abi=EABI32]" msgstr "" -#: elf32-mips.c:2643 +#: elf32-mips.c:2630 msgid " [abi=EABI64]" msgstr "" -#: elf32-mips.c:2645 +#: elf32-mips.c:2632 msgid " [abi unknown]" msgstr "" -#: elf32-mips.c:2647 +#: elf32-mips.c:2634 msgid " [abi=N32]" msgstr "" -#: elf32-mips.c:2649 +#: elf32-mips.c:2636 msgid " [abi=64]" msgstr "" -#: elf32-mips.c:2651 +#: elf32-mips.c:2638 msgid " [no abi set]" msgstr "" -#: elf32-mips.c:2654 +#: elf32-mips.c:2641 msgid " [mips1]" msgstr "" -#: elf32-mips.c:2656 +#: elf32-mips.c:2643 msgid " [mips2]" msgstr "" -#: elf32-mips.c:2658 +#: elf32-mips.c:2645 msgid " [mips3]" msgstr "" -#: elf32-mips.c:2660 +#: elf32-mips.c:2647 msgid " [mips4]" msgstr "" -#: elf32-mips.c:2662 +#: elf32-mips.c:2649 msgid " [unknown ISA]" msgstr "" -#: elf32-mips.c:2665 +#: elf32-mips.c:2652 msgid " [32bitmode]" msgstr "" -#: elf32-mips.c:2667 +#: elf32-mips.c:2654 msgid " [not 32bitmode]" msgstr "" -#: elf32-mips.c:4270 +#: elf32-mips.c:4257 msgid "static procedure (no name)" msgstr "" -#: elf32-mips.c:4887 elf64-alpha.c:4364 +#: elf32-mips.c:4874 elf64-alpha.c:4367 #, c-format msgid "%s: illegal section name `%s'" msgstr "" -#: elf32-mips.c:5414 +#: elf32-mips.c:5401 msgid "not enough GOT space for local GOT entries" msgstr "" -#: elf32-mips.c:6493 +#: elf32-mips.c:6495 #, c-format msgid "%s: %s+0x%lx: jump to stub routine which is not jal" msgstr "" -#: elf32-mips.c:7521 +#: elf32-mips.c:7523 #, c-format msgid "%s: CALL16 reloc at 0x%lx not against global symbol" msgstr "" -#: elf32-ppc.c:1443 +#: elf32-ppc.c:1430 #, c-format msgid "" "%s: compiled with -mrelocatable and linked with modules compiled normally" msgstr "" -#: elf32-ppc.c:1451 +#: elf32-ppc.c:1438 #, c-format msgid "" "%s: compiled normally and linked with modules compiled with -mrelocatable" msgstr "" -#: elf32-ppc.c:1578 +#: elf32-ppc.c:1565 #, c-format msgid "%s: Unknown special linker type %d" msgstr "" -#: elf32-ppc.c:2251 elf32-ppc.c:2285 elf32-ppc.c:2320 +#: elf32-ppc.c:2238 elf32-ppc.c:2272 elf32-ppc.c:2307 #, c-format msgid "%s: relocation %s cannot be used when making a shared object" msgstr "" -#: elf32-ppc.c:3123 +#: elf32-ppc.c:3116 #, c-format msgid "%s: unknown relocation type %d for symbol %s" msgstr "" -#: elf32-ppc.c:3491 elf32-ppc.c:3513 elf32-ppc.c:3562 +#: elf32-ppc.c:3484 elf32-ppc.c:3506 elf32-ppc.c:3555 #, c-format msgid "" "%s: The target (%s) of a %s relocation is in the wrong output section (%s)" msgstr "" -#: elf32-ppc.c:3628 +#: elf32-ppc.c:3621 #, c-format msgid "%s: Relocation %s is not yet supported for symbol %s." msgstr "" -#: elf32-sh.c:681 +#: elf32-sh.c:819 #, c-format msgid "%s: 0x%lx: warning: bad R_SH_USES offset" msgstr "" -#: elf32-sh.c:693 +#: elf32-sh.c:831 #, c-format msgid "%s: 0x%lx: warning: R_SH_USES points to unrecognized insn 0x%x" msgstr "" -#: elf32-sh.c:710 +#: elf32-sh.c:848 #, c-format msgid "%s: 0x%lx: warning: bad R_SH_USES load offset" msgstr "" -#: elf32-sh.c:725 +#: elf32-sh.c:863 #, c-format msgid "%s: 0x%lx: warning: could not find expected reloc" msgstr "" -#: elf32-sh.c:762 +#: elf32-sh.c:900 #, c-format msgid "%s: 0x%lx: warning: symbol in unexpected section" msgstr "" -#: elf32-sh.c:884 +#: elf32-sh.c:1022 #, c-format msgid "%s: 0x%lx: warning: could not find expected COUNT reloc" msgstr "" -#: elf32-sh.c:893 +#: elf32-sh.c:1031 #, c-format msgid "%s: 0x%lx: warning: bad count" msgstr "" -#: elf32-sh.c:1279 elf32-sh.c:1666 +#: elf32-sh.c:1424 elf32-sh.c:1811 #, c-format msgid "%s: 0x%lx: fatal: reloc overflow while relaxing" msgstr "" -#: elf32-sparc.c:1486 elf64-sparc.c:2242 +#: elf32-sparc.c:1509 elf64-sparc.c:2262 #, c-format msgid "%s: probably compiled without -fPIC?" msgstr "" -#: elf32-sparc.c:1856 +#: elf32-sparc.c:1970 #, c-format msgid "%s: compiled for a v8plus system and target is v8" msgstr "" -#: elf32-sparc.c:1865 +#: elf32-sparc.c:1979 #, c-format msgid "%s: compiled for a v8plusa system and target is v8plus" msgstr "" -#: elf32-sparc.c:1873 +#: elf32-sparc.c:1987 #, c-format msgid "%s: compiled for a 64 bit system and target is 32 bit" msgstr "" -#: elf32-sparc.c:1888 +#: elf32-sparc.c:2002 #, c-format msgid "%s: linking little endian files with big endian files" msgstr "" @@ -1104,77 +1054,227 @@ msgstr "" msgid "%s: .got subsegment exceeds 64K (size %d)" msgstr "" -#: elf64-sparc.c:1249 +#: elf64-ia64.c:1826 +msgid "@pltoff reloc against local symbol" +msgstr "" + +#: elf64-ia64.c:1873 +msgid "non-zero addend in @fptr reloc" +msgstr "" + +#: elf64-ia64.c:3060 +#, c-format +msgid "%s: short data segment overflowed (0x%lx >= 0x400000)" +msgstr "" + +#: elf64-ia64.c:3071 +#, c-format +msgid "%s: __gp does not cover short data segment" +msgstr "" + +#: elf64-ia64.c:3335 +#, c-format +msgid "%s: linking non-pic code in a shared library" +msgstr "" + +#: elf64-ia64.c:3365 +#, c-format +msgid "%s: @gprel relocation against dynamic symbol %s" +msgstr "" + +#: elf64-ia64.c:3500 +#, c-format +msgid "%s: dynamic relocation against speculation fixup" +msgstr "" + +#: elf64-ia64.c:3508 +#, c-format +msgid "%s: speculation fixup against undefined weak symbol" +msgstr "" + +#: elf64-ia64.c:3665 +msgid "unsupported reloc" +msgstr "" + +#: elf64-ia64.c:3979 +#, c-format +msgid "%s: linking trap-on-NULL-dereference with non-trapping files" +msgstr "" + +#: elf64-ia64.c:3988 +#, c-format +msgid "%s: linking big-endian files with little-endian files" +msgstr "" + +#: elf64-ia64.c:3997 +#, c-format +msgid "%s: linking 64-bit files with 32-bit files" +msgstr "" + +#: elf64-sparc.c:1250 #, c-format msgid "%s: check_relocs: unhandled reloc type %d" msgstr "" -#: elf64-sparc.c:1286 +#: elf64-sparc.c:1287 msgid "%s: Only registers %%g[2367] can be declared using STT_REGISTER" msgstr "" -#: elf64-sparc.c:1306 +#: elf64-sparc.c:1307 msgid "" "Register %%g%d used incompatibly: previously declared in %s to %s, in %s " "redefined to %s" msgstr "" -#: elf64-sparc.c:1329 +#: elf64-sparc.c:1330 #, c-format msgid "Symbol `%s' has differing types: previously %s, REGISTER in %s" msgstr "" -#: elf64-sparc.c:1375 +#: elf64-sparc.c:1376 #, c-format msgid "Symbol `%s' has differing types: REGISTER in %s, %s in %s" msgstr "" -#: elf64-sparc.c:2825 +#: elf64-sparc.c:2938 #, c-format msgid "%s: linking UltraSPARC specific with HAL specific code" msgstr "" -#: elfcode.h:1061 +#: elf.c:327 +#, c-format +msgid "%s: invalid string offset %u >= %lu for section `%s'" +msgstr "" + +#: elf.c:550 +msgid "" +"\n" +"Program Header:\n" +msgstr "" + +#: elf.c:598 +msgid "" +"\n" +"Dynamic Section:\n" +msgstr "" + +#: elf.c:700 +msgid "" +"\n" +"Version definitions:\n" +msgstr "" + +#: elf.c:723 +msgid "" +"\n" +"Version References:\n" +msgstr "" + +#: elf.c:728 +#, c-format +msgid " required from %s:\n" +msgstr "" + +#: elf.c:1292 +#, c-format +msgid "%s: invalid link %lu for reloc section %s (index %u)" +msgstr "" + +#: elf.c:2069 +#, c-format +msgid "" +"creating section symbol, name = %s, value = 0x%.8lx, index = %d, section = " +"0x%.8lx\n" +msgstr "" + +#: elf.c:2672 +#, c-format +msgid "%s: Not enough room for program headers (allocated %u, need %u)" +msgstr "" + +#: elf.c:2771 +#, c-format +msgid "%s: Not enough room for program headers, try linking with -N" +msgstr "" + +#: elf.c:2897 +#, c-format +msgid "Error: First section in segment (%s) starts at 0x%x" +msgstr "" + +#: elf.c:2900 +#, c-format +msgid " whereas segment starts at 0x%x" +msgstr "" + +#: elf.c:3173 +#, c-format +msgid "%s: warning: allocated section `%s' not in segment" +msgstr "" + +#: elf.c:3564 +#, c-format +msgid "%s: symbol `%s' required but not present" +msgstr "" + +#: elf.c:3573 +#, c-format +msgid "" +"elf_symbol_from_bfd_symbol 0x%.8lx, name = %s, sym num = %d, flags = " +"0x%.8lx%s\n" +msgstr "" + +#: elf.c:3715 +#, c-format +msgid "%s: warning: Empty loadable segment detected\n" +msgstr "" + +#: elf.c:5030 +#, c-format +msgid "%s: unsupported relocation type %s" +msgstr "" + +#: elfcode.h:1059 #, c-format msgid "%s: version count (%ld) does not match symbol count (%ld)" msgstr "" -#: elflink.c:423 +#: elflink.c:416 #, c-format msgid "%s: Section %s is already to large to put hole of %ld bytes in" msgstr "" -#: elflink.h:1388 +#: elflink.h:1387 #, c-format msgid "%s: %s: invalid version %u (max %d)" msgstr "" -#: elflink.h:1429 +#: elflink.h:1428 #, c-format msgid "%s: %s: invalid needed version %d" msgstr "" -#: elflink.h:1546 +#: elflink.h:1545 #, c-format msgid "Warning: size of symbol `%s' changed from %lu to %lu in %s" msgstr "" -#: elflink.h:1790 +#: elflink.h:1789 #, c-format msgid "%s: warning: unexpected redefinition of `%s'" msgstr "" -#: elflink.h:3480 +#: elflink.h:3496 #, c-format msgid "warning: type and size of dynamic symbol `%s' are not defined" msgstr "" -#: elflink.h:3752 +#: elflink.h:3768 #, c-format msgid "%s: undefined versioned symbol name %s" msgstr "" -#: elflink.h:4983 +#: elflink.h:5012 #, c-format msgid "%s: could not find output section %s for input section %s" msgstr "" @@ -1283,6 +1383,16 @@ msgstr "" msgid "not mapping: env var not set\n" msgstr "" +#: libbfd.c:1315 +#, c-format +msgid "%s: compiled for a big endian system and target is little endian" +msgstr "" + +#: libbfd.c:1317 +#, c-format +msgid "%s: compiled for a little endian system and target is big endian" +msgstr "" + #: linker.c:2679 #, c-format msgid "Attempt to do relocateable link with %s input and %s output" @@ -1299,330 +1409,328 @@ msgid "Unhandled OSF/1 core file section type %d\n" msgstr "" #. XXX code yet to be written. -#: peicode.h:806 +#: peicode.h:804 #, c-format msgid "%s: Unhandled import type; %x" msgstr "" -#: peicode.h:811 +#: peicode.h:809 #, c-format msgid "%s: Unrecognised import type; %x" msgstr "" -#: peicode.h:825 +#: peicode.h:823 #, c-format msgid "%s: Unrecognised import name type; %x" msgstr "" -#: peicode.h:1182 +#: peicode.h:1180 #, c-format msgid "%s: Unrecognised machine type (0x%x) in Import Library Format archive" msgstr "" -#: peicode.h:1194 +#: peicode.h:1192 #, c-format msgid "" "%s: Recognised but unhandled machine type (0x%x) in Import Library Format " "archive" msgstr "" -#: peicode.h:1211 +#: peicode.h:1209 #, c-format msgid "%s: size field is zero in Import Library Format header" msgstr "" -#: peicode.h:1239 +#: peicode.h:1237 #, c-format msgid "%s: string not null terminated in ILF object file." msgstr "" -#: peigen.c:938 +#: peigen.c:968 #, c-format msgid "%s: line number overflow: 0x%lx > 0xffff" msgstr "" -#: peigen.c:950 +#: peigen.c:980 #, c-format msgid "%s: reloc overflow: 0x%lx > 0xffff" msgstr "" -#: peigen.c:963 +#: peigen.c:993 msgid "Export Directory [.edata (or where ever we found it)]" msgstr "" -#: peigen.c:964 +#: peigen.c:994 msgid "Import Directory [parts of .idata]" msgstr "" -#: peigen.c:965 +#: peigen.c:995 msgid "Resource Directory [.rsrc]" msgstr "" -#: peigen.c:966 +#: peigen.c:996 msgid "Exception Directory [.pdata]" msgstr "" -#: peigen.c:967 +#: peigen.c:997 msgid "Security Directory" msgstr "" -#: peigen.c:968 +#: peigen.c:998 msgid "Base Relocation Directory [.reloc]" msgstr "" -#: peigen.c:969 +#: peigen.c:999 msgid "Debug Directory" msgstr "" -#: peigen.c:970 +#: peigen.c:1000 msgid "Description Directory" msgstr "" -#: peigen.c:971 +#: peigen.c:1001 msgid "Special Directory" msgstr "" -#: peigen.c:972 +#: peigen.c:1002 msgid "Thread Storage Directory [.tls]" msgstr "" -#: peigen.c:973 +#: peigen.c:1003 msgid "Load Configuration Directory" msgstr "" -#: peigen.c:974 +#: peigen.c:1004 msgid "Bound Import Directory" msgstr "" -#: peigen.c:975 +#: peigen.c:1005 msgid "Import Address Table Directory" msgstr "" -#: peigen.c:976 peigen.c:977 peigen.c:978 -msgid "Reserved" +#: peigen.c:1006 +msgid "Delay Import Directory" msgstr "" -#: peigen.c:1022 -msgid "" -"\n" -"The import table is the .idata section\n" +#: peigen.c:1007 peigen.c:1008 +msgid "Reserved" msgstr "" -#: peigen.c:1044 +#: peigen.c:1072 msgid "" "\n" "There is an import table, but the section containing it could not be found\n" msgstr "" -#: peigen.c:1048 +#: peigen.c:1077 #, c-format msgid "" "\n" "There is an import table in %s at 0x%lx\n" msgstr "" -#: peigen.c:1089 +#: peigen.c:1116 #, c-format msgid "" "\n" "Function descriptor located at the start address: %04lx\n" msgstr "" -#: peigen.c:1092 +#: peigen.c:1119 #, c-format msgid "\tcode-base %08lx toc (loadable/actual) %08lx/%08lx\n" msgstr "" -#: peigen.c:1098 +#: peigen.c:1125 msgid "" "\n" "No reldata section! Function descriptor not decoded.\n" msgstr "" -#: peigen.c:1103 +#: peigen.c:1130 +#, c-format msgid "" "\n" -"The Import Tables (interpreted .idata section contents)\n" +"The Import Tables (interpreted %s section contents)\n" msgstr "" -#: peigen.c:1105 +#: peigen.c:1133 msgid " vma: Hint Time Forward DLL First\n" msgstr "" -#: peigen.c:1107 +#: peigen.c:1135 msgid " Table Stamp Chain Name Thunk\n" msgstr "" -#: peigen.c:1157 +#: peigen.c:1185 #, c-format msgid "" "\n" "\tDLL Name: %s\n" msgstr "" -#: peigen.c:1161 peigen.c:1224 +#: peigen.c:1189 peigen.c:1252 msgid "\tvma: Hint/Ord Member-Name\n" msgstr "" -#: peigen.c:1223 +#: peigen.c:1251 msgid "\tThe Import Address Table (difference found)\n" msgstr "" -#: peigen.c:1230 +#: peigen.c:1258 msgid "\t>>> Ran out of IAT members!\n" msgstr "" -#: peigen.c:1248 +#: peigen.c:1277 msgid "\tThe Import Address Table is identical\n" msgstr "" -#: peigen.c:1297 -msgid "" -"\n" -"The export table is the .edata section\n" -msgstr "" - -#: peigen.c:1319 +#: peigen.c:1351 msgid "" "\n" "There is an export table, but the section containing it could not be found\n" msgstr "" -#: peigen.c:1323 +#: peigen.c:1356 #, c-format msgid "" "\n" "There is an export table in %s at 0x%lx\n" msgstr "" -#: peigen.c:1355 +#: peigen.c:1387 +#, c-format msgid "" "\n" -"The Export Tables (interpreted .edata section contents)\n" +"The Export Tables (interpreted %s section contents)\n" "\n" msgstr "" -#: peigen.c:1358 +#: peigen.c:1391 #, c-format msgid "Export Flags \t\t\t%lx\n" msgstr "" -#: peigen.c:1361 +#: peigen.c:1394 #, c-format msgid "Time/Date stamp \t\t%lx\n" msgstr "" -#: peigen.c:1364 +#: peigen.c:1397 #, c-format msgid "Major/Minor \t\t\t%d/%d\n" msgstr "" -#: peigen.c:1367 +#: peigen.c:1400 msgid "Name \t\t\t\t" msgstr "" -#: peigen.c:1373 +#: peigen.c:1406 #, c-format msgid "Ordinal Base \t\t\t%ld\n" msgstr "" -#: peigen.c:1376 +#: peigen.c:1409 msgid "Number in:\n" msgstr "" -#: peigen.c:1379 +#: peigen.c:1412 #, c-format -msgid "\tExport Address Table \t\t%lx\n" +msgid "\tExport Address Table \t\t%08lx\n" msgstr "" -#: peigen.c:1383 +#: peigen.c:1416 #, c-format -msgid "\t[Name Pointer/Ordinal] Table\t%lu\n" +msgid "\t[Name Pointer/Ordinal] Table\t%08lx\n" msgstr "" -#: peigen.c:1386 +#: peigen.c:1419 msgid "Table Addresses\n" msgstr "" -#: peigen.c:1389 +#: peigen.c:1422 msgid "\tExport Address Table \t\t" msgstr "" -#: peigen.c:1394 +#: peigen.c:1427 msgid "\tName Pointer Table \t\t" msgstr "" -#: peigen.c:1399 +#: peigen.c:1432 msgid "\tOrdinal Table \t\t\t" msgstr "" -#: peigen.c:1415 +#: peigen.c:1448 #, c-format msgid "" "\n" "Export Address Table -- Ordinal Base %ld\n" msgstr "" -#: peigen.c:1436 +#: peigen.c:1467 msgid "Forwarder RVA" msgstr "" -#: peigen.c:1444 +#: peigen.c:1478 msgid "Export RVA" msgstr "" -#: peigen.c:1451 +#: peigen.c:1485 msgid "" "\n" "[Ordinal/Name Pointer] Table\n" msgstr "" -#: peigen.c:1496 +#: peigen.c:1539 #, c-format msgid "Warning, .pdata section size (%ld) is not a multiple of %d\n" msgstr "" -#: peigen.c:1500 +#: peigen.c:1543 msgid "" "\n" "The Function Table (interpreted .pdata section contents)\n" msgstr "" -#: peigen.c:1502 +#: peigen.c:1546 +msgid " vma:\t\t\tBegin Address End Address Unwind Info\n" +msgstr "" + +#: peigen.c:1549 msgid " vma:\t\tBegin End EH EH PrologEnd Exception\n" msgstr "" -#: peigen.c:1504 +#: peigen.c:1551 msgid " \t\tAddress Address Handler Data Address Mask\n" msgstr "" -#: peigen.c:1576 +#: peigen.c:1624 msgid " Register save millicode" msgstr "" -#: peigen.c:1579 +#: peigen.c:1627 msgid " Register restore millicode" msgstr "" -#: peigen.c:1582 +#: peigen.c:1630 msgid " Glue code sequence" msgstr "" -#: peigen.c:1628 +#: peigen.c:1682 msgid "" "\n" "\n" "PE File Base Relocations (interpreted .reloc section contents)\n" msgstr "" -#: peigen.c:1663 +#: peigen.c:1717 #, c-format msgid "" "\n" "Virtual Address: %08lx Chunk size %ld (0x%lx) Number of fixups %ld\n" msgstr "" -#: peigen.c:1676 +#: peigen.c:1730 #, c-format msgid "\treloc %4d offset %4x [%4lx] %s" msgstr "" @@ -1630,57 +1738,72 @@ msgstr "" #. The MS dumpbin program reportedly ands with 0xff0f before #. printing the characteristics field. Not sure why. No reason to #. emulate it here. -#: peigen.c:1714 +#: peigen.c:1769 #, c-format msgid "" "\n" "Characteristics 0x%x\n" msgstr "" -#: ppcboot.c:418 +#: pe-mips.c:657 +#, c-format +msgid "%s: `ld -r' not supported with PE MIPS objects\n" +msgstr "" + +#: pe-mips.c:820 +#, c-format +msgid "%s: jump too far away\n" +msgstr "" + +#: pe-mips.c:847 +#, c-format +msgid "%s: bad pair/reflo after refhi\n" +msgstr "" + +#: ppcboot.c:422 msgid "" "\n" "ppcboot header:\n" msgstr "" -#: ppcboot.c:419 +#: ppcboot.c:423 #, c-format msgid "Entry offset = 0x%.8lx (%ld)\n" msgstr "" -#: ppcboot.c:420 +#: ppcboot.c:424 #, c-format msgid "Length = 0x%.8lx (%ld)\n" msgstr "" -#: ppcboot.c:423 +#: ppcboot.c:427 #, c-format msgid "Flag field = 0x%.2x\n" msgstr "" -#: ppcboot.c:429 +#: ppcboot.c:433 #, c-format msgid "Partition name = \"%s\"\n" msgstr "" -#: ppcboot.c:448 +#: ppcboot.c:452 #, c-format msgid "" "\n" "Partition[%d] start = { 0x%.2x, 0x%.2x, 0x%.2x, 0x%.2x }\n" msgstr "" -#: ppcboot.c:454 +#: ppcboot.c:458 #, c-format msgid "Partition[%d] end = { 0x%.2x, 0x%.2x, 0x%.2x, 0x%.2x }\n" msgstr "" -#: ppcboot.c:460 +#: ppcboot.c:464 #, c-format msgid "Partition[%d] sector = 0x%.8lx (%ld)\n" msgstr "" -#: ppcboot.c:461 +#: ppcboot.c:465 #, c-format msgid "Partition[%d] length = 0x%.8lx (%ld)\n" msgstr "" @@ -1722,29 +1845,29 @@ msgstr "" msgid "Object module NOT error-free !\n" msgstr "" -#: vms-misc.c:541 +#: vms-misc.c:544 #, c-format msgid "Stack overflow (%d) in _bfd_vms_push" msgstr "" -#: vms-misc.c:560 +#: vms-misc.c:563 msgid "Stack underflow in _bfd_vms_pop" msgstr "" -#: vms-misc.c:931 +#: vms-misc.c:934 msgid "_bfd_vms_output_counted called with zero bytes" msgstr "" -#: vms-misc.c:936 +#: vms-misc.c:939 msgid "_bfd_vms_output_counted called with too many bytes" msgstr "" -#: vms-misc.c:1069 +#: vms-misc.c:1072 #, c-format msgid "Symbol %s replaced by %s\n" msgstr "" -#: vms-misc.c:1133 +#: vms-misc.c:1136 #, c-format msgid "failed to enter %s" msgstr "" @@ -1940,97 +2063,97 @@ msgstr "" msgid "Unhandled relocation %s" msgstr "" -#: xcofflink.c:1661 +#: xcofflink.c:1653 #, c-format msgid "%s: `%s' has line numbers but no enclosing section" msgstr "" -#: xcofflink.c:1713 +#: xcofflink.c:1705 #, c-format msgid "%s: class %d symbol `%s' has no aux entries" msgstr "" -#: xcofflink.c:1736 +#: xcofflink.c:1728 #, c-format msgid "%s: symbol `%s' has unrecognized csect type %d" msgstr "" -#: xcofflink.c:1748 +#: xcofflink.c:1740 #, c-format msgid "%s: bad XTY_ER symbol `%s': class %d scnum %d scnlen %d" msgstr "" -#: xcofflink.c:1787 +#: xcofflink.c:1779 #, c-format msgid "%s: XMC_TC0 symbol `%s' is class %d scnlen %d" msgstr "" -#: xcofflink.c:1911 +#: xcofflink.c:1903 #, c-format msgid "%s: symbol `%s' has unrecognized smclas %d" msgstr "" -#: xcofflink.c:1930 +#: xcofflink.c:1922 #, c-format msgid "%s: csect `%s' not in enclosing section" msgstr "" -#: xcofflink.c:2034 +#: xcofflink.c:2026 #, c-format msgid "%s: misplaced XTY_LD `%s'" msgstr "" -#: xcofflink.c:2345 +#: xcofflink.c:2337 #, c-format msgid "%s: reloc %s:%d not in csect" msgstr "" -#: xcofflink.c:2480 +#: xcofflink.c:2472 #, c-format msgid "%s: XCOFF shared object when not producing XCOFF output" msgstr "" -#: xcofflink.c:2501 +#: xcofflink.c:2493 #, c-format msgid "%s: dynamic object with no .loader section" msgstr "" -#: xcofflink.c:3141 +#: xcofflink.c:3133 #, c-format msgid "%s: no such symbol" msgstr "" -#: xcofflink.c:3733 +#: xcofflink.c:3725 #, c-format msgid "warning: attempt to export undefined symbol `%s'" msgstr "" -#: xcofflink.c:4709 +#: xcofflink.c:4701 #, c-format msgid "TOC overflow: 0x%lx > 0x10000; try -mminimal-toc when compiling" msgstr "" -#: xcofflink.c:5534 xcofflink.c:5890 xcofflink.c:5927 xcofflink.c:6244 +#: xcofflink.c:5526 xcofflink.c:5882 xcofflink.c:5919 xcofflink.c:6236 #, c-format msgid "%s: loader reloc in unrecognized section `%s'" msgstr "" -#: xcofflink.c:5556 xcofflink.c:6255 +#: xcofflink.c:5548 xcofflink.c:6247 #, c-format msgid "%s: `%s' in loader reloc but not loader sym" msgstr "" -#: xcofflink.c:5571 +#: xcofflink.c:5563 #, c-format msgid "%s: loader reloc in read-only section %s" msgstr "" -#: xcofflink.c:6451 +#: xcofflink.c:6443 #, c-format msgid "%s: unsupported relocation type 0x%02x" msgstr "" -#: xcofflink.c:6497 +#: xcofflink.c:6489 #, c-format msgid "%s: TOC reloc at 0x%x to symbol `%s' with no TOC entry" msgstr "" diff --git a/bfd/reloc.c b/bfd/reloc.c index a14d552d502..119aea9bdf0 100644 --- a/bfd/reloc.c +++ b/bfd/reloc.c @@ -2881,6 +2881,23 @@ ENUMX BFD_RELOC_IA64_LDXMOV ENUMDOC Intel IA64 Relocations. + +ENUM + BFD_RELOC_M68HC11_HI8 +ENUMDOC + Motorola 68HC11 reloc. + This is the 8 bits high part of an absolute address. +ENUM + BFD_RELOC_M68HC11_LO8 +ENUMDOC + Motorola 68HC11 reloc. + This is the 8 bits low part of an absolute address. +ENUM + BFD_RELOC_M68HC11_3B +ENUMDOC + Motorola 68HC11 reloc. + This is the 3 bits of a value. + ENDSENUM BFD_RELOC_UNUSED CODE_FRAGMENT diff --git a/bfd/section.c b/bfd/section.c index ff977fd78a9..be881d84264 100644 --- a/bfd/section.c +++ b/bfd/section.c @@ -552,25 +552,25 @@ static const asymbol global_syms[] = const asymbol * const SYM = (asymbol *) &global_syms[IDX]; \ const asection SEC = \ /* name, index, next, flags, set_vma, reloc_done, linker_mark, gc_mark */ \ - { NAME, 0, 0, FLAGS, 0, 0, 0, 0, \ + { NAME, 0, NULL, FLAGS, 0, 0, 0, 0, \ \ /* vma, lma, _cooked_size, _raw_size, output_offset, output_section, */ \ 0, 0, 0, 0, 0, (struct sec *) &SEC, \ \ /* alig..., reloc..., orel..., reloc_count, filepos, rel_..., line_... */ \ - 0, 0, 0, 0, 0, 0, 0, \ + 0, NULL, NULL, 0, 0, 0, 0, \ \ /* userdata, contents, lineno, lineno_count */ \ - 0, 0, 0, 0, \ + NULL, NULL, NULL, 0, \ \ /* comdat_info, moving_line_filepos, target_index, used_by_bfd, */ \ - NULL, 0, 0, 0, \ + NULL, 0, 0, NULL, \ \ /* cons..., owner, symbol */ \ - 0, 0, (struct symbol_cache_entry *) &global_syms[IDX], \ + NULL, NULL, (struct symbol_cache_entry *) &global_syms[IDX], \ \ /* symbol_ptr_ptr, link_order_head, ..._tail */ \ - (struct symbol_cache_entry **) &SYM, 0, 0 \ + (struct symbol_cache_entry **) &SYM, NULL, NULL \ } STD_SECTION (bfd_com_section, SEC_IS_COMMON, bfd_com_symbol, diff --git a/bfd/targets.c b/bfd/targets.c index 980f95c5498..c9f7f959b54 100644 --- a/bfd/targets.c +++ b/bfd/targets.c @@ -533,6 +533,8 @@ extern const bfd_target bfd_elf32_little_generic_vec; extern const bfd_target bfd_elf32_littlemips_vec; extern const bfd_target bfd_elf64_littlemips_vec; extern const bfd_target bfd_elf32_m32r_vec; +extern const bfd_target bfd_elf32_m68hc11_vec; +extern const bfd_target bfd_elf32_m68hc12_vec; extern const bfd_target bfd_elf32_m68k_vec; extern const bfd_target bfd_elf32_m88k_vec; extern const bfd_target bfd_elf32_mn10200_vec; @@ -738,6 +740,8 @@ const bfd_target * const bfd_target_vector[] = { &bfd_elf32_m32r_vec, &bfd_elf32_mn10200_vec, &bfd_elf32_mn10300_vec, + &bfd_elf32_m68hc11_vec, + &bfd_elf32_m68hc12_vec, &bfd_elf32_m68k_vec, &bfd_elf32_m88k_vec, &bfd_elf32_sparc_vec, diff --git a/include/ChangeLog b/include/ChangeLog index 5d3b6c40aea..2440179b236 100644 --- a/include/ChangeLog +++ b/include/ChangeLog @@ -1,3 +1,8 @@ +2000-06-18 Stephane Carrez <stcarrez@worldnet.fr> + + * dis-asm.h (print_insn_m68hc12): Define. + (print_insn_m68hc11): Likewise. + 2000-06-18 Nick Clifton <nickc@redhat.com> * os9k.h: Change values of MODSYNC and CRCCON due to bug report diff --git a/include/dis-asm.h b/include/dis-asm.h index 7efd4e0ec98..c34ce5cff78 100644 --- a/include/dis-asm.h +++ b/include/dis-asm.h @@ -159,6 +159,8 @@ extern int print_insn_i386_att PARAMS ((bfd_vma, disassemble_info*)); extern int print_insn_i386_intel PARAMS ((bfd_vma, disassemble_info*)); extern int print_insn_ia64 PARAMS ((bfd_vma, disassemble_info*)); extern int print_insn_i370 PARAMS ((bfd_vma, disassemble_info*)); +extern int print_insn_m68hc11 PARAMS ((bfd_vma, disassemble_info*)); +extern int print_insn_m68hc12 PARAMS ((bfd_vma, disassemble_info*)); extern int print_insn_m68k PARAMS ((bfd_vma, disassemble_info*)); extern int print_insn_z8001 PARAMS ((bfd_vma, disassemble_info*)); extern int print_insn_z8002 PARAMS ((bfd_vma, disassemble_info*)); diff --git a/include/elf/ChangeLog b/include/elf/ChangeLog index 8783be89dd6..0a103ae7852 100644 --- a/include/elf/ChangeLog +++ b/include/elf/ChangeLog @@ -1,3 +1,7 @@ +2000-06-18 Stephane Carrez <stcarrez@worldnet.fr> + + * m68hc11.h: New file, definitions for the Motorola 68hc11. + 2000-06-06 Alan Modra <alan@linuxcare.com.au> * reloc-macros.h (START_RELOC_NUMBERS): Don't define initial dummy @@ -120,6 +124,12 @@ Thu Feb 17 00:18:33 2000 J"orn Rennecke <amylaar@cygnus.co.uk> (EF_SH3, EF_SH_HAS_DSP, EF_SH_DSP, EF_SH3_DSP): Likewise. (EF_SH_HAS_FP, EF_SH3E, EF_SH4, EF_SH_MERGE_MACH): Likewise. +2000-03-10 Geoffrey Keating <geoffk@cygnus.com> + + * mips.h: Add R_MIPS_GNU_REL_HI16, R_MIPS_GNU_REL_LO16, + R_MIPS_GNU_REL16_S2, R_MIPS_PC64 and R_MIPS_PC32 relocation + numbers. + 2000-02-03 H.J. Lu <hjl@gnu.org> * arm-oabi.h: Duplicate changes made to arm.h on Jan. 27, @@ -245,6 +255,20 @@ Mon Oct 4 17:42:38 1999 Doug Evans <devans@canuck.cygnus.com> * pj.h: New file. * common.h (EM_PJ): Define. +Wed Dec 1 03:02:15 1999 Jeffrey A Law (law@cygnus.com) + + * mn10300.h (E_MN10300_MACH_AM33): Define. + +Mon Oct 11 22:42:37 1999 Jeffrey A Law (law@cygnus.com) + + * hppa.h (PF_HP_PAGE_SIZE): Define. + (PF_HP_FAR_SHARED, PF_HP_NEAR_SHARED, PF_HP_CODE): Likewise. + (PF_HP_MODIFY, PF_HP_LAZYSWAP, PF_HP_SBP): Likewise. + +1999-09-15 Ulrich Drepper <drepper@cygnus.com> + + * hppa.h: Add DT_HP_GST_SIZE, DT_HP_GST_VERSION, and DT_HP_GST_HASHVAL. + 1999-09-02 Ulrich Drepper <drepper@cygnus.com> * hppa.h: Add HPUX specific symbol type definitions. diff --git a/include/elf/m68hc11.h b/include/elf/m68hc11.h new file mode 100644 index 00000000000..30e0556a9e9 --- /dev/null +++ b/include/elf/m68hc11.h @@ -0,0 +1,42 @@ +/* m68hc11 & m68hc12 ELF support for BFD. + Copyright (C) 1999, 2000 Free Software Foundation, Inc. + + This file is part of BFD, the Binary File Descriptor library. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software Foundation, + Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#ifndef _ELF_M68HC11_H +#define _ELF_M68HC11_H + +#include "elf/reloc-macros.h" + +/* Relocation types. */ +START_RELOC_NUMBERS (elf_m68hc11_reloc_type) + RELOC_NUMBER (R_M68HC11_NONE, 0) + RELOC_NUMBER (R_M68HC11_8, 1) + RELOC_NUMBER (R_M68HC11_HI8, 2) + RELOC_NUMBER (R_M68HC11_LO8, 3) + RELOC_NUMBER (R_M68HC11_PCREL_8, 4) + RELOC_NUMBER (R_M68HC11_16, 5) + RELOC_NUMBER (R_M68HC11_32, 6) + RELOC_NUMBER (R_M68HC11_3B, 7) + RELOC_NUMBER (R_M68HC11_PCREL_16, 8) + + /* These are GNU extensions to enable C++ vtable garbage collection. */ + RELOC_NUMBER (R_M68HC11_GNU_VTINHERIT, 9) + RELOC_NUMBER (R_M68HC11_GNU_VTENTRY, 10) +END_RELOC_NUMBERS (R_M68HC11_max) + +#endif diff --git a/include/opcode/ChangeLog b/include/opcode/ChangeLog index e3605e45b33..73504e24ad9 100644 --- a/include/opcode/ChangeLog +++ b/include/opcode/ChangeLog @@ -1,3 +1,7 @@ +2000-06-18 Stephane Carrez <stcarrez@worldnet.fr> + + * m68hc11.h: New file for support of Motorola 68hc11. + Fri Jun 9 21:51:50 2000 Denis Chertykov <denisc@overta.ru> * avr.h: clr,lsl,rol, ... moved after add,adc, ... diff --git a/include/opcode/cgen.h b/include/opcode/cgen.h index 1db272bbb11..ff897856c23 100644 --- a/include/opcode/cgen.h +++ b/include/opcode/cgen.h @@ -736,7 +736,7 @@ typedef struct the data is recorded in the parse/insert/extract/print switch statements. */ /* This should be at least as large as necessary for any target. */ -#define CGEN_MAX_SYNTAX_BYTES 32 +#define CGEN_MAX_SYNTAX_BYTES 40 /* A target may know its own precise maximum. Assert that it falls below the above limit. */ diff --git a/include/opcode/m68hc11.h b/include/opcode/m68hc11.h new file mode 100644 index 00000000000..52a24613078 --- /dev/null +++ b/include/opcode/m68hc11.h @@ -0,0 +1,418 @@ +/* m68hc11.h -- Header file for Motorola 68HC11 & 68HC12 opcode table + Copyright 1999, 2000 Free Software Foundation, Inc. + Written by Stephane Carrez (stcarrez@worldnet.fr) + +This file is part of GDB, GAS, and the GNU binutils. + +GDB, GAS, and the GNU binutils are free software; you can redistribute +them and/or modify them under the terms of the GNU General Public +License as published by the Free Software Foundation; either version +1, or (at your option) any later version. + +GDB, GAS, and the GNU binutils are distributed in the hope that they +will be useful, but WITHOUT ANY WARRANTY; without even the implied +warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See +the GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this file; see the file COPYING. If not, write to the Free +Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#ifndef _OPCODE_M68HC11_H +#define _OPCODE_M68HC11_H + +/* Flags for the definition of the 68HC11 & 68HC12 CCR. */ +#define M6811_S_BIT 0x80 /* Stop disable */ +#define M6811_X_BIT 0x40 /* X-interrupt mask */ +#define M6811_H_BIT 0x20 /* Half carry flag */ +#define M6811_I_BIT 0x10 /* I-interrupt mask */ +#define M6811_N_BIT 0x08 /* Negative */ +#define M6811_Z_BIT 0x04 /* Zero */ +#define M6811_V_BIT 0x02 /* Overflow */ +#define M6811_C_BIT 0x01 /* Carry */ + +/* 68HC11 register address offsets (range 0..0x3F or 0..64). + The absolute address of the I/O register depends on the setting + of the M6811_INIT register. At init time, the I/O registers are + mapped at 0x1000. Address of registers is then: + + 0x1000 + M6811_xxx +*/ +#define M6811_PORTA 0x00 /* Port A register */ +#define M6811__RES1 0x01 /* Unused/Reserved */ +#define M6811_PIOC 0x02 /* Parallel I/O Control register */ +#define M6811_PORTC 0x03 /* Port C register */ +#define M6811_PORTB 0x04 /* Port B register */ +#define M6811_PORTCL 0x05 /* Alternate latched port C */ +#define M6811__RES6 0x06 /* Unused/Reserved */ +#define M6811_DDRC 0x07 /* Data direction register for port C */ +#define M6811_PORTD 0x08 /* Port D register */ +#define M6811_DDRD 0x09 /* Data direction register for port D */ +#define M6811_PORTE 0x0A /* Port E input register */ +#define M6811_CFORC 0x0B /* Compare Force Register */ +#define M6811_OC1M 0x0C /* OC1 Action Mask register */ +#define M6811_OC1D 0x0D /* OC1 Action Data register */ +#define M6811_TCTN 0x0E /* Timer Counter Register */ +#define M6811_TCTN_H 0x0E /* " " " High part */ +#define M6811_TCTN_L 0x0F /* " " " Low part */ +#define M6811_TIC1 0x10 /* Input capture 1 register */ +#define M6811_TIC1_H 0x10 /* " " " High part */ +#define M6811_TIC1_L 0x11 /* " " " Low part */ +#define M6811_TIC2 0x12 /* Input capture 2 register */ +#define M6811_TIC2_H 0x12 /* " " " High part */ +#define M6811_TIC2_L 0x13 /* " " " Low part */ +#define M6811_TIC3 0x14 /* Input capture 3 register */ +#define M6811_TIC3_H 0x14 /* " " " High part */ +#define M6811_TIC3_L 0x15 /* " " " Low part */ +#define M6811_TOC1 0x16 /* Output Compare 1 register */ +#define M6811_TOC1_H 0x16 /* " " " High part */ +#define M6811_TOC1_L 0x17 /* " " " Low part */ +#define M6811_TOC2 0x18 /* Output Compare 2 register */ +#define M6811_TOC2_H 0x18 /* " " " High part */ +#define M6811_TOC2_L 0x19 /* " " " Low part */ +#define M6811_TOC3 0x1A /* Output Compare 3 register */ +#define M6811_TOC3_H 0x1A /* " " " High part */ +#define M6811_TOC3_L 0x1B /* " " " Low part */ +#define M6811_TOC4 0x1C /* Output Compare 4 register */ +#define M6811_TOC4_H 0x1C /* " " " High part */ +#define M6811_TOC4_L 0x1D /* " " " Low part */ +#define M6811_TOC5 0x1E /* Output Compare 5 register */ +#define M6811_TOC5_H 0x1E /* " " " High part */ +#define M6811_TOC5_L 0x1F /* " " " Low part */ +#define M6811_TCTL1 0x20 /* Timer Control register 1 */ +#define M6811_TCTL2 0x21 /* Timer Control register 2 */ +#define M6811_TMSK1 0x22 /* Timer Interrupt Mask Register 1 */ +#define M6811_TFLG1 0x23 /* Timer Interrupt Flag Register 1 */ +#define M6811_TMSK2 0x24 /* Timer Interrupt Mask Register 2 */ +#define M6811_TFLG2 0x25 /* Timer Interrupt Flag Register 2 */ +#define M6811_PACTL 0x26 /* Pulse Accumulator Control Register */ +#define M6811_PACNT 0x27 /* Pulse Accumulator Count Register */ +#define M6811_SPCR 0x28 /* SPI Control register */ +#define M6811_SPSR 0x29 /* SPI Status register */ +#define M6811_SPDR 0x2A /* SPI Data register */ +#define M6811_BAUD 0x2B /* SCI Baud register */ +#define M6811_SCCR1 0x2C /* SCI Control register 1 */ +#define M6811_SCCR2 0x2D /* SCI Control register 2 */ +#define M6811_SCSR 0x2E /* SCI Status register */ +#define M6811_SCDR 0x2F /* SCI Data (Read => RDR, Write => TDR) */ +#define M6811_ADCTL 0x30 /* A/D Control register */ +#define M6811_ADR1 0x31 /* A/D, Analog Result register 1 */ +#define M6811_ADR2 0x32 /* A/D, Analog Result register 2 */ +#define M6811_ADR3 0x33 /* A/D, Analog Result register 3 */ +#define M6811_ADR4 0x34 /* A/D, Analog Result register 4 */ +#define M6811__RES35 0x35 +#define M6811__RES36 0x36 +#define M6811__RES37 0x37 +#define M6811__RES38 0x38 +#define M6811_OPTION 0x39 /* System Configuration Options */ +#define M6811_COPRST 0x3A /* Arm/Reset COP Timer Circuitry */ +#define M6811_PPROG 0x3B /* EEPROM Programming Control Register */ +#define M6811_HPRIO 0x3C /* Highest priority I-Bit int and misc */ +#define M6811_INIT 0x3D /* Ram and I/O mapping register */ +#define M6811_TEST1 0x3E /* Factory test control register */ +#define M6811_CONFIG 0x3F /* COP, ROM and EEPROM enables */ + + +/* Flags of the CONFIG register (in EEPROM). */ +#define M6811_NOSEC 0x08 /* Security mode disable */ +#define M6811_NOCOP 0x04 /* COP system disable */ +#define M6811_ROMON 0x02 /* Enable on-chip rom */ +#define M6811_EEON 0x01 /* Enable on-chip eeprom */ + +/* Flags of the PPROG register. */ +#define M6811_BYTE 0x10 /* Byte mode */ +#define M6811_ROW 0x08 /* Row mode */ +#define M6811_ERASE 0x04 /* Erase mode select (1 = erase, 0 = read) */ +#define M6811_EELAT 0x02 /* EEPROM Latch Control */ +#define M6811_EEPGM 0x01 /* EEPROM Programming Voltage Enable */ + +/* Flags of the PIOC register. */ +#define M6811_STAF 0x80 /* Strobe A Interrupt Status Flag */ +#define M6811_STAI 0x40 /* Strobe A Interrupt Enable Mask */ +#define M6811_CWOM 0x20 /* Port C Wire OR mode */ +#define M6811_HNDS 0x10 /* Handshake mode */ +#define M6811_OIN 0x08 /* Output or Input handshaking */ +#define M6811_PLS 0x04 /* Pulse/Interlocked Handshake Operation */ +#define M6811_EGA 0x02 /* Active Edge for Strobe A */ +#define M6811_INVB 0x01 /* Invert Strobe B */ + +/* Flags of the SCCR1 register. */ +#define M6811_R8 0x80 /* Receive Data bit 8 */ +#define M6811_T8 0x40 /* Transmit data bit 8 */ +#define M6811__SCCR1_5 0x20 /* Unused */ +#define M6811_M 0x10 /* SCI Character length */ +#define M6811_WAKE 0x08 /* Wake up method select (0=idle, 1=addr mark) */ + +/* Flags of the SCCR2 register. */ +#define M6811_TIE 0x80 /* Transmit Interrupt enable */ +#define M6811_TCIE 0x40 /* Transmit Complete Interrupt Enable */ +#define M6811_RIE 0x20 /* Receive Interrupt Enable */ +#define M6811_ILIE 0x10 /* Idle Line Interrupt Enable */ +#define M6811_TE 0x08 /* Transmit Enable */ +#define M6811_RE 0x04 /* Receive Enable */ +#define M6811_RWU 0x02 /* Receiver Wake Up */ +#define M6811_SBK 0x01 /* Send Break */ + +/* Flags of the SCSR register. */ +#define M6811_TDRE 0x80 /* Transmit Data Register Empty */ +#define M6811_TC 0x40 /* Transmit Complete */ +#define M6811_RDRF 0x20 /* Receive Data Register Full */ +#define M6811_IDLE 0x10 /* Idle Line Detect */ +#define M6811_OR 0x08 /* Overrun Error */ +#define M6811_NF 0x04 /* Noise Flag */ +#define M6811_FE 0x02 /* Framing Error */ +#define M6811__SCSR_0 0x01 /* Unused */ + +/* Flags of the BAUD register. */ +#define M6811_TCLR 0x80 /* Clear Baud Rate (TEST mode) */ +#define M6811__BAUD_6 0x40 /* Not used */ +#define M6811_SCP1 0x20 /* SCI Baud rate prescaler select */ +#define M6811_SCP0 0x10 +#define M6811_RCKB 0x08 /* Baud Rate Clock Check (TEST mode) */ +#define M6811_SCR2 0x04 /* SCI Baud rate select */ +#define M6811_SCR1 0x02 +#define M6811_SCR0 0x01 + +#define M6811_BAUD_DIV_1 (0) +#define M6811_BAUD_DIV_3 (M6811_SCP0) +#define M6811_BAUD_DIV_4 (M6811_SCP1) +#define M6811_BAUD_DIV_13 (M6811_SCP1|M6811_SCP0) + +/* Flags of the SPCR register. */ +#define M6811_SPIE 0x80 /* Serial Peripheral Interrupt Enable */ +#define M6811_SPE 0x40 /* Serial Peripheral System Enable */ +#define M6811_DWOM 0x20 /* Port D Wire-OR mode option */ +#define M6811_MSTR 0x10 /* Master Mode Select */ +#define M6811_CPOL 0x08 /* Clock Polarity */ +#define M6811_CPHA 0x04 /* Clock Phase */ +#define M6811_SPR1 0x02 /* SPI Clock Rate Select */ +#define M6811_SPR0 0x01 + +/* Flags of the SPSR register. */ +#define M6811_SPIF 0x80 /* SPI Transfer Complete flag */ +#define M6811_WCOL 0x40 /* Write Collision */ +#define M6811_MODF 0x20 /* Mode Fault */ + +/* Flags of the ADCTL register. */ +#define M6811_CCF 0x80 /* Conversions Complete Flag */ +#define M6811_SCAN 0x20 /* Continuous Scan Control */ +#define M6811_MULT 0x10 /* Multiple Channel/Single Channel Control */ +#define M6811_CD 0x08 /* Channel Select D */ +#define M6811_CC 0x04 /* C */ +#define M6811_CB 0x02 /* B */ +#define M6811_CA 0x01 /* A */ + +/* Flags of the CFORC register. */ +#define M6811_FOC1 0x80 /* Force Output Compare 1 */ +#define M6811_FOC2 0x40 /* 2 */ +#define M6811_FOC3 0x20 /* 3 */ +#define M6811_FOC4 0x10 /* 4 */ +#define M6811_FOC5 0x08 /* 5 */ + +/* Flags of the OC1M register. */ +#define M6811_OC1M7 0x80 /* Output Compare 7 */ +#define M6811_OC1M6 0x40 /* 6 */ +#define M6811_OC1M5 0x40 /* 5 */ +#define M6811_OC1M4 0x40 /* 4 */ +#define M6811_OC1M3 0x08 /* 3 */ + +/* Flags of the OC1D register. */ +#define M6811_OC1D7 0x80 +#define M6811_OC1D6 0x40 +#define M6811_OC1D5 0x20 +#define M6811_OC1D4 0x10 +#define M6811_OC1D3 0x08 + +/* Flags of the TCTL1 register. */ +#define M6811_OM2 0x80 /* Output Mode 2 */ +#define M6811_OL2 0x40 /* Output Level 2 */ +#define M6811_OM3 0x20 +#define M6811_OL3 0x10 +#define M6811_OM4 0x08 +#define M6811_OL4 0x04 +#define M6811_OM5 0x02 +#define M6811_OL5 0x01 + +/* Flags of the TCTL2 register. */ +#define M6811_EDG1B 0x20 /* Input Edge Capture Control 1 */ +#define M6811_EDG1A 0x10 +#define M6811_EDG2B 0x08 /* Input 2 */ +#define M6811_EDG2A 0x04 +#define M6811_EDG3B 0x02 /* Input 3 */ +#define M6811_EDG3A 0x01 + +/* Flags of the TMSK1 register. */ +#define M6811_OC1I 0x80 /* Output Compare 1 Interrupt */ +#define M6811_OC2I 0x40 /* 2 */ +#define M6811_OC3I 0x20 /* 3 */ +#define M6811_OC4I 0x10 /* 4 */ +#define M6811_OC5I 0x08 /* 5 */ +#define M6811_IC1I 0x04 /* Input Capture 1 Interrupt */ +#define M6811_IC2I 0x02 /* 2 */ +#define M6811_IC3I 0x01 /* 3 */ + +/* Flags of the TFLG1 register. */ +#define M6811_OC1F 0x80 /* Output Compare 1 Flag */ +#define M6811_OC2F 0x40 /* 2 */ +#define M6811_OC3F 0x20 /* 3 */ +#define M6811_OC4F 0x10 /* 4 */ +#define M6811_OC5F 0x08 /* 5 */ +#define M6811_IC1F 0x04 /* Input Capture 1 Flag */ +#define M6811_IC2F 0x02 /* 2 */ +#define M6811_IC3F 0x01 /* 3 */ + +/* Flags of Timer Interrupt Mask Register 2 (TMSK2). */ +#define M6811_TOI 0x80 /* Timer Overflow Interrupt Enable */ +#define M6811_RTII 0x40 /* RTI Interrupt Enable */ +#define M6811_PAOVI 0x20 /* Pulse Accumulator Overflow Interrupt En. */ +#define M6811_PAII 0x10 /* Pulse Accumulator Interrupt Enable */ +#define M6811_PR1 0x02 /* Timer prescaler */ +#define M6811_PR0 0x01 /* Timer prescaler */ +#define M6811_TPR_1 0x00 /* " " prescale div 1 */ +#define M6811_TPR_4 0x01 /* " " prescale div 4 */ +#define M6811_TPR_8 0x02 /* " " prescale div 8 */ +#define M6811_TPR_16 0x03 /* " " prescale div 16 */ + +/* Flags of Timer Interrupt Flag Register 2 (M6811_TFLG2). */ +#define M6811_TOF 0x80 /* Timer overflow bit */ +#define M6811_RTIF 0x40 /* Read time interrupt flag */ +#define M6811_PAOVF 0x20 /* Pulse accumulator overflow Interrupt flag */ +#define M6811_PAIF 0x10 /* Pulse accumulator Input Edge " " " */ + +/* Flags of Pulse Accumulator Control Register (PACTL). */ +#define M6811_DDRA7 0x80 /* Data direction for port A bit 7 */ +#define M6811_PAEN 0x40 /* Pulse accumulator system enable */ +#define M6811_PAMOD 0x20 /* Pulse accumulator mode */ +#define M6811_PEDGE 0x10 /* Pulse accumulator edge control */ +#define M6811_RTR1 0x02 /* RTI Interrupt rates select */ +#define M6811_RTR0 0x01 /* " " " " */ + +/* Flags of the Options register. */ +#define M6811_ADPU 0x80 /* A/D Powerup */ +#define M6811_CSEL 0x40 /* A/D/EE Charge pump clock source select */ +#define M6811_IRQE 0x20 /* IRQ Edge/Level sensitive */ +#define M6811_DLY 0x10 /* Stop exit turn on delay */ +#define M6811_CME 0x08 /* Clock Monitor enable */ +#define M6811_CR1 0x02 /* COP timer rate select */ +#define M6811_CR0 0x01 /* COP timer rate select */ + +/* Flags of the HPRIO register. */ +#define M6811_RBOOT 0x80 /* Read Bootstrap ROM */ +#define M6811_SMOD 0x40 /* Special Mode */ +#define M6811_MDA 0x20 /* Mode Select A */ +#define M6811_IRV 0x10 /* Internal Read Visibility */ +#define M6811_PSEL3 0x08 /* Priority Select */ +#define M6811_PSEL2 0x04 +#define M6811_PSEL1 0x02 +#define M6811_PSEL0 0x01 + +/* Some insns used by gas to turn relative branches into absolute ones. */ +#define M6811_BRA 0x20 +#define M6811_JMP 0x7e +#define M6811_BSR 0x8d +#define M6811_JSR 0xbd +#define M6812_JMP 0x06 +#define M6812_BSR 0x07 +#define M6812_JSR 0x16 + +/* Instruction code pages. Code page 1 is the default. */ +/*#define M6811_OPCODE_PAGE1 0x00*/ +#define M6811_OPCODE_PAGE2 0x18 +#define M6811_OPCODE_PAGE3 0x1A +#define M6811_OPCODE_PAGE4 0xCD + + +/* 68HC11 operands formats as stored in the m6811_opcode table. These + flags do not correspond to anything in the 68HC11 or 68HC12. + They are only used by GAS to recognize operands. */ +#define M6811_OP_NONE 0 /* No operand */ +#define M6811_OP_DIRECT 0x0001 /* Page 0 addressing: *<val-8bits> */ +#define M6811_OP_IMM8 0x0002 /* 8 bits immediat: #<val-8bits> */ +#define M6811_OP_IMM16 0x0004 /* 16 bits immediat: #<val-16bits> */ +#define M6811_OP_IND16 0x0008 /* Indirect abs: <val-16> */ +#define M6812_OP_IND16_P2 0x0010 /* Second parameter indirect abs. */ +#define M6812_OP_REG 0x0020 /* Register operand 1 */ +#define M6812_OP_REG_2 0x0040 /* Register operand 2 */ + +#define M6811_OP_IX 0x0080 /* Indirect IX: <val-8>,x */ +#define M6811_OP_IY 0x0100 /* Indirect IY: <val-8>,y */ +#define M6812_OP_IDX 0x0200 /* Indirect: N,r N,[+-]r[+-] N:5-bits */ +#define M6812_OP_IDX_1 0x0400 /* N,r N:9-bits */ +#define M6812_OP_IDX_2 0x0800 /* N,r N:16-bits */ +#define M6812_OP_D_IDX 0x1000 /* Indirect indexed: [D,r] */ +#define M6812_OP_D_IDX_2 0x2000 /* [N,r] N:16-bits */ +#define M6811_OP_MASK 0x0FFFF +#define M6811_OP_BITMASK 0x00010000 /* Bitmask: #<val-8> */ +#define M6811_OP_JUMP_REL 0x00020000 /* Pc-Relative: <val-8> */ +#define M6812_OP_JUMP_REL16 0x00040000 /* Pc-relative: <val-16> */ +#define M6811_OP_PAGE1 0x0000 +#define M6811_OP_PAGE2 0x00080000 /* Need a page2 opcode before */ +#define M6811_OP_PAGE3 0x00100000 /* Need a page3 opcode before */ +#define M6811_OP_PAGE4 0x00200000 /* Need a page4 opcode before */ +#define M6811_MAX_OPERANDS 3 /* Max operands: brset <dst> <mask> <b> */ + +#define M6812_ACC_OFFSET 0x00400000 /* A,r B,r D,r */ +#define M6812_ACC_IND 0x00800000 /* [D,r] */ +#define M6812_PRE_INC 0x01000000 /* n,+r n = -8..8 */ +#define M6812_PRE_DEC 0x02000000 /* n,-r */ +#define M6812_POST_INC 0x04000000 /* n,r+ */ +#define M6812_POST_DEC 0x08000000 /* n,r- */ +#define M6812_INDEXED_IND 0x10000000 /* [n,r] n = 16-bits */ +#define M6812_INDEXED 0x20000000 /* n,r n = 5, 9 or 16-bits */ +#define M6812_OP_IDX_P2 0x40000000 + +/* Markers to identify some instructions. */ +#define M6812_OP_EXG_MARKER 0x01000000 /* exg r1,r2 */ +#define M6812_OP_TFR_MARKER 0x02000000 /* tfr r1,r2 */ +#define M6812_OP_SEX_MARKER 0x04000000 /* sex r1,r2 */ + +#define M6812_OP_EQ_MARKER 0x80000000 /* dbeq/ibeq/tbeq */ +#define M6812_OP_DBCC_MARKER 0x04000000 /* dbeq/dbne */ +#define M6812_OP_IBCC_MARKER 0x02000000 /* ibeq/ibne */ +#define M6812_OP_TBCC_MARKER 0x01000000 + +#define M6812_OP_TRAP_ID 0x80000000 /* trap #N */ + +#define M6811_OP_HIGH_ADDR 0x01000000 /* Used internally by gas. */ +#define M6811_OP_LOW_ADDR 0x02000000 + +/* CPU identification. */ +#define cpu6811 0x01 +#define cpu6812 0x02 + +/* The opcode table is an array of struct m68hc11_opcode. */ +struct m68hc11_opcode { + const char* name; /* Op-code name */ + long format; + unsigned char size; + unsigned char opcode; + unsigned char cycles_low; + unsigned char cycles_high; + unsigned char set_flags_mask; + unsigned char clr_flags_mask; + unsigned char chg_flags_mask; + unsigned char arch; +}; + +/* Alias definition for 68HC12. */ +struct m68hc12_opcode_alias +{ + const char* name; + const char* translation; + unsigned char size; + unsigned char code1; + unsigned char code2; +}; + +/* The opcode table. The table contains all the opcodes (all pages). + You can't rely on the order. */ +extern const struct m68hc11_opcode m68hc11_opcodes[]; +extern const int m68hc11_num_opcodes; + +/* Alias table for 68HC12. It translates some 68HC11 insn which are not + implemented in 68HC12 but have equivalent translations. */ +extern const struct m68hc12_opcode_alias m68hc12_alias[]; +extern const int m68hc12_num_alias; + +#endif /* _OPCODE_M68HC11_H */ + @@ -1183,7 +1183,7 @@ EOF $DLLTOOL --as=$AS --dllname $soname --exclude-symbols DllMain@12,_cygwin_dll_entry@12,_cygwin_noncygwin_dll_entry@12 --def $objdir/$soname-def --base-file $objdir/$soname-base --output-exp $objdir/$soname-exp~ $CC $objdir/$soname-exp -Wl,--dll -nostartfiles -Wl,-e,__cygwin_dll_entry@12 -o $lib $objdir/$soname-ltdll.$objext $libobjs $deplibs $linkopts' - old_archive_from_new_cmds='$DLLTOOL --as=$AS --dllname $soname --def $objdir/$soname-def --output-lib $objdir/$libname.a' + old_archive_from_new_cmds='$DLLTOOL --as=$AS --dllname $soname --def $objdir/$soname-def --output-lib $objdir/$libname.a' ;; netbsd*) diff --git a/opcodes/Makefile.am b/opcodes/Makefile.am index 9b2385cc9b0..14ce4247064 100644 --- a/opcodes/Makefile.am +++ b/opcodes/Makefile.am @@ -79,6 +79,8 @@ CFILES = \ m32r-ibld.c \ m32r-opc.c \ m32r-opinst.c \ + m68hc11-dis.c \ + m68hc11-opc.c \ m68k-dis.c \ m68k-opc.c \ m88k-dis.c \ @@ -145,6 +147,8 @@ ALL_MACHINES = \ m32r-ibld.lo \ m32r-opc.lo \ m32r-opinst.lo \ + m68hc11-dis.lo \ + m68hc11-opc.lo \ m68k-dis.lo \ m68k-opc.lo \ m88k-dis.lo \ @@ -387,6 +391,10 @@ m32r-opc.lo: m32r-opc.c sysdep.h config.h $(INCDIR)/ansidecl.h \ m32r-opinst.lo: m32r-opinst.c sysdep.h config.h $(INCDIR)/ansidecl.h \ $(BFD_H) $(INCDIR)/symcat.h m32r-desc.h $(INCDIR)/opcode/cgen.h \ m32r-opc.h +m68hc11-dis.lo: m68hc11-dis.c $(INCDIR)/dis-asm.h $(BFD_H) \ + $(INCDIR)/ansidecl.h $(INCDIR)/floatformat.h \ + $(INCDIR)/opcode/m68hc11.h +m68hc11-opc.lo: m68hc11-opc.c $(INCDIR)/ansidecl.h $(INCDIR)/opcode/m68hc11.h m68k-dis.lo: m68k-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \ $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/floatformat.h \ opintl.h $(INCDIR)/opcode/m68k.h diff --git a/opcodes/Makefile.in b/opcodes/Makefile.in index c5c1d01020e..3391d778c4d 100644 --- a/opcodes/Makefile.in +++ b/opcodes/Makefile.in @@ -183,6 +183,8 @@ CFILES = \ m32r-ibld.c \ m32r-opc.c \ m32r-opinst.c \ + m68hc11-dis.c \ + m68hc11-opc.c \ m68k-dis.c \ m68k-opc.c \ m88k-dis.c \ @@ -250,6 +252,8 @@ ALL_MACHINES = \ m32r-ibld.lo \ m32r-opc.lo \ m32r-opinst.lo \ + m68hc11-dis.lo \ + m68hc11-opc.lo \ m68k-dis.lo \ m68k-opc.lo \ m88k-dis.lo \ @@ -330,7 +334,7 @@ acinclude.m4 aclocal.m4 config.in configure configure.in DISTFILES = $(DIST_COMMON) $(SOURCES) $(HEADERS) $(TEXINFOS) $(EXTRA_DIST) -TAR = tar +TAR = gtar GZIP_ENV = --best SOURCES = libopcodes.a.c $(libopcodes_la_SOURCES) OBJECTS = libopcodes.a.o $(libopcodes_la_OBJECTS) @@ -885,6 +889,10 @@ m32r-opc.lo: m32r-opc.c sysdep.h config.h $(INCDIR)/ansidecl.h \ m32r-opinst.lo: m32r-opinst.c sysdep.h config.h $(INCDIR)/ansidecl.h \ $(BFD_H) $(INCDIR)/symcat.h m32r-desc.h $(INCDIR)/opcode/cgen.h \ m32r-opc.h +m68hc11-dis.lo: m68hc11-dis.c $(INCDIR)/dis-asm.h $(BFD_H) \ + $(INCDIR)/ansidecl.h $(INCDIR)/floatformat.h \ + $(INCDIR)/opcode/m68hc11.h +m68hc11-opc.lo: m68hc11-opc.c $(INCDIR)/ansidecl.h $(INCDIR)/opcode/m68hc11.h m68k-dis.lo: m68k-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \ $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/floatformat.h \ opintl.h $(INCDIR)/opcode/m68k.h diff --git a/opcodes/configure b/opcodes/configure index 1655fe78145..5c8f609a077 100755 --- a/opcodes/configure +++ b/opcodes/configure @@ -3957,6 +3957,8 @@ if test x${all_targets} = xfalse ; then bfd_i960_arch) ta="$ta i960-dis.lo" ;; bfd_ia64_arch) ta="$ta ia64-dis.lo ia64-opc.lo" ;; bfd_m32r_arch) ta="$ta m32r-asm.lo m32r-desc.lo m32r-dis.lo m32r-ibld.lo m32r-opc.lo m32r-opinst.lo" using_cgen=yes ;; + bfd_m68hc11_arch) ta="$ta m68hc11-dis.lo m68hc11-opc.lo" ;; + bfd_m68hc12_arch) ta="$ta m68hc11-dis.lo m68hc11-opc.lo" ;; bfd_m68k_arch) ta="$ta m68k-dis.lo m68k-opc.lo" ;; bfd_m88k_arch) ta="$ta m88k-dis.lo" ;; bfd_mcore_arch) ta="$ta mcore-dis.lo" ;; diff --git a/opcodes/configure.in b/opcodes/configure.in index 6f94bfcd87b..0e947fb50a2 100644 --- a/opcodes/configure.in +++ b/opcodes/configure.in @@ -168,6 +168,8 @@ if test x${all_targets} = xfalse ; then bfd_i960_arch) ta="$ta i960-dis.lo" ;; bfd_ia64_arch) ta="$ta ia64-dis.lo ia64-opc.lo" ;; bfd_m32r_arch) ta="$ta m32r-asm.lo m32r-desc.lo m32r-dis.lo m32r-ibld.lo m32r-opc.lo m32r-opinst.lo" using_cgen=yes ;; + bfd_m68hc11_arch) ta="$ta m68hc11-dis.lo m68hc11-opc.lo" ;; + bfd_m68hc12_arch) ta="$ta m68hc11-dis.lo m68hc11-opc.lo" ;; bfd_m68k_arch) ta="$ta m68k-dis.lo m68k-opc.lo" ;; bfd_m88k_arch) ta="$ta m88k-dis.lo" ;; bfd_mcore_arch) ta="$ta mcore-dis.lo" ;; diff --git a/opcodes/disassemble.c b/opcodes/disassemble.c index 3f463c9306f..a9b62e8fc5c 100644 --- a/opcodes/disassemble.c +++ b/opcodes/disassemble.c @@ -37,6 +37,8 @@ Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ #define ARCH_fr30 #define ARCH_m32r #define ARCH_m68k +#define ARCH_m68hc11 +#define ARCH_m68hc12 #define ARCH_m88k #define ARCH_mcore #define ARCH_mips @@ -164,6 +166,14 @@ disassembler (abfd) disassemble = print_insn_m32r; break; #endif +#if defined(ARCH_m68hc11) || defined(ARCH_m68hc12) + case bfd_arch_m68hc11: + disassemble = print_insn_m68hc11; + break; + case bfd_arch_m68hc12: + disassemble = print_insn_m68hc12; + break; +#endif #ifdef ARCH_m68k case bfd_arch_m68k: disassemble = print_insn_m68k; diff --git a/opcodes/m68hc11-dis.c b/opcodes/m68hc11-dis.c new file mode 100644 index 00000000000..2ef241cf7d0 --- /dev/null +++ b/opcodes/m68hc11-dis.c @@ -0,0 +1,608 @@ +/* m68hc11-dis.c -- Motorola 68HC11 & 68HC12 disassembly + Copyright (C) 1999, 2000 Free Software Foundation, Inc. + Written by Stephane Carrez (stcarrez@worldnet.fr) + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; if not, write to the Free Software +Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#include <stdio.h> + +#include "ansidecl.h" +#include "opcode/m68hc11.h" +#include "dis-asm.h" + +static const char *const reg_name[] = { + "X", "Y", "SP", "PC" +}; + +static const char *const reg_src_table[] = { + "A", "B", "CCR", "TMP3", "D", "X", "Y", "SP" +}; + +static const char *const reg_dst_table[] = { + "A", "B", "CCR", "TMP2", "D", "X", "Y", "SP" +}; + +#define OP_PAGE_MASK (M6811_OP_PAGE2|M6811_OP_PAGE3|M6811_OP_PAGE4) + +static int +read_memory (memaddr, buffer, size, info) + bfd_vma memaddr; + bfd_byte *buffer; + int size; + struct disassemble_info *info; +{ + int status; + + /* Get first byte. Only one at a time because we don't know the + size of the insn. */ + status = (*info->read_memory_func) (memaddr, buffer, size, info); + if (status != 0) + { + (*info->memory_error_func) (status, memaddr, info); + return -1; + } + return 0; +} + + +/* Read the 68HC12 indexed operand byte and print the corresponding mode. + Returns the number of bytes read or -1 if failure. */ +static int +print_indexed_operand (memaddr, info, mov_insn) + bfd_vma memaddr; + struct disassemble_info *info; + int mov_insn; +{ + bfd_byte buffer[4]; + int reg; + int status; + short sval; + int pos = 1; + + status = read_memory (memaddr, &buffer[0], 1, info); + if (status != 0) + { + return status; + } + + /* n,r with 5-bits signed constant. */ + if ((buffer[0] & 0x20) == 0) + { + reg = (buffer[0] >> 6) & 3; + sval = (buffer[0] & 0x1f); + if (sval & 0x10) + sval |= 0xfff0; + (*info->fprintf_func) (info->stream, "%d,%s", + (int) sval, reg_name[reg]); + } + + /* Auto pre/post increment/decrement. */ + else if ((buffer[0] & 0xc0) != 0xc0) + { + const char *mode; + + reg = (buffer[0] >> 6) & 3; + sval = (buffer[0] & 0x0f); + if (sval & 0x8) + { + sval |= 0xfff0; + sval = -sval; + mode = "-"; + } + else + { + sval = sval + 1; + mode = "+"; + } + (*info->fprintf_func) (info->stream, "%d,%s%s%s", + (int) sval, + (buffer[0] & 0x10 ? "" : mode), + reg_name[reg], (buffer[0] & 0x10 ? mode : "")); + } + + /* [n,r] 16-bits offset indexed indirect. */ + else if ((buffer[0] & 0x07) == 3) + { + if (mov_insn) + { + (*info->fprintf_func) (info->stream, "<invalid op: 0x%x>", + buffer[0] & 0x0ff); + return 0; + } + reg = (buffer[0] >> 3) & 0x03; + status = read_memory (memaddr + pos, &buffer[0], 2, info); + if (status != 0) + { + return status; + } + + pos += 2; + sval = ((buffer[0] << 8) | (buffer[1] & 0x0FF)); + (*info->fprintf_func) (info->stream, "[%u,%s]", + sval & 0x0ffff, reg_name[reg]); + } + else if ((buffer[0] & 0x4) == 0) + { + if (mov_insn) + { + (*info->fprintf_func) (info->stream, "<invalid op: 0x%x>", + buffer[0] & 0x0ff); + return 0; + } + reg = (buffer[0] >> 3) & 0x03; + status = read_memory (memaddr + pos, + &buffer[1], (buffer[0] & 0x2 ? 2 : 1), info); + if (status != 0) + { + return status; + } + if (buffer[0] & 2) + { + sval = ((buffer[1] << 8) | (buffer[2] & 0x0FF)); + sval &= 0x0FFFF; + pos += 2; + } + else + { + sval = buffer[1] & 0x00ff; + if (buffer[0] & 0x01) + sval |= 0xff00; + pos++; + } + (*info->fprintf_func) (info->stream, "%d,%s", + (int) sval, reg_name[reg]); + } + else + { + reg = (buffer[0] >> 3) & 0x03; + switch (buffer[0] & 3) + { + case 0: + (*info->fprintf_func) (info->stream, "A,%s", reg_name[reg]); + break; + case 1: + (*info->fprintf_func) (info->stream, "B,%s", reg_name[reg]); + break; + case 2: + (*info->fprintf_func) (info->stream, "D,%s", reg_name[reg]); + break; + case 3: + default: + (*info->fprintf_func) (info->stream, "[D,%s]", reg_name[reg]); + break; + } + } + + return pos; +} + +/* Disassemble one instruction at address 'memaddr'. Returns the number + of bytes used by that instruction. */ +static int +print_insn (memaddr, info, arch) + bfd_vma memaddr; + struct disassemble_info *info; + int arch; +{ + int status; + bfd_byte buffer[4]; + unsigned char code; + long format, pos, i; + short sval; + const struct m68hc11_opcode *opcode; + + /* Get first byte. Only one at a time because we don't know the + size of the insn. */ + status = read_memory (memaddr, buffer, 1, info); + if (status != 0) + { + return status; + } + + format = 0; + code = buffer[0]; + pos = 0; + + /* Look for page2,3,4 opcodes. */ + if (code == M6811_OPCODE_PAGE2) + { + pos++; + format = M6811_OP_PAGE2; + } + else if (code == M6811_OPCODE_PAGE3 && arch == cpu6811) + { + pos++; + format = M6811_OP_PAGE3; + } + else if (code == M6811_OPCODE_PAGE4 && arch == cpu6811) + { + pos++; + format = M6811_OP_PAGE4; + } + + /* We are in page2,3,4; get the real opcode. */ + if (pos == 1) + { + status = read_memory (memaddr + pos, &buffer[1], 1, info); + if (status != 0) + { + return status; + } + code = buffer[1]; + } + + + /* Look first for a 68HC12 alias. All of them are 2-bytes long and + in page 1. There is no operand to print. We read the second byte + only when we have a possible match. */ + if ((arch & cpu6812) && format == 0) + { + int must_read = 1; + + /* Walk the alias table to find a code1+code2 match. */ + for (i = 0; i < m68hc12_num_alias; i++) + { + if (m68hc12_alias[i].code1 == code) + { + if (must_read) + { + status = read_memory (memaddr + pos + 1, + &buffer[1], 1, info); + if (status != 0) + break; + + must_read = 1; + } + if (m68hc12_alias[i].code2 == (unsigned char) buffer[1]) + { + (*info->fprintf_func) (info->stream, "%s", + m68hc12_alias[i].name); + return 2; + } + } + } + } + + pos++; + + /* Scan the opcode table until we find the opcode + with the corresponding page. */ + opcode = m68hc11_opcodes; + for (i = 0; i < m68hc11_num_opcodes; i++, opcode++) + { + int offset; + + if ((opcode->arch & arch) == 0) + continue; + if (opcode->opcode != code) + continue; + if ((opcode->format & OP_PAGE_MASK) != format) + continue; + + if (opcode->format & M6812_OP_REG) + { + int j; + int is_jump; + + if (opcode->format & M6811_OP_JUMP_REL) + is_jump = 1; + else + is_jump = 0; + + status = read_memory (memaddr + pos, &buffer[0], 1, info); + if (status != 0) + { + return status; + } + for (j = 0; i + j < m68hc11_num_opcodes; j++) + { + if ((opcode[j].arch & arch) == 0) + continue; + if (opcode[j].opcode != code) + continue; + if (is_jump) + { + if (!(opcode[j].format & M6811_OP_JUMP_REL)) + continue; + + if ((opcode[j].format & M6812_OP_IBCC_MARKER) + && (buffer[0] & 0xc0) != 0x80) + continue; + if ((opcode[j].format & M6812_OP_TBCC_MARKER) + && (buffer[0] & 0xc0) != 0x40) + continue; + if ((opcode[j].format & M6812_OP_DBCC_MARKER) + && (buffer[0] & 0xc0) != 0) + continue; + if ((opcode[j].format & M6812_OP_EQ_MARKER) + && (buffer[0] & 0x20) == 0) + break; + if (!(opcode[j].format & M6812_OP_EQ_MARKER) + && (buffer[0] & 0x20) != 0) + break; + continue; + } + if (opcode[j].format & M6812_OP_EXG_MARKER && buffer[0] & 0x80) + break; + if ((opcode[j].format & M6812_OP_SEX_MARKER) + && (((buffer[0] & 0x07) >= 3 && (buffer[0] & 7) <= 7)) + && ((buffer[0] & 0x0f0) <= 0x20)) + break; + if (opcode[j].format & M6812_OP_TFR_MARKER + && !(buffer[0] & 0x80)) + break; + } + if (i + j < m68hc11_num_opcodes) + opcode = &opcode[j]; + } + + /* We have found the opcode. Extract the operand and print it. */ + (*info->fprintf_func) (info->stream, "%s", opcode->name); + + format = opcode->format; + if (format & (M6811_OP_MASK | M6811_OP_BITMASK + | M6811_OP_JUMP_REL | M6812_OP_JUMP_REL16)) + { + (*info->fprintf_func) (info->stream, "\t"); + } + + /* The movb and movw must be handled in a special way... */ + offset = 0; + if (format & (M6812_OP_IDX_P2 | M6812_OP_IND16_P2)) + { + if ((format & M6812_OP_IDX_P2) + && (format & (M6811_OP_IMM8 | M6811_OP_IMM16 | M6811_OP_IND16))) + offset = 1; + } + + /* Operand with one more byte: - immediate, offset, + direct-low address. */ + if (format & + (M6811_OP_IMM8 | M6811_OP_IX | M6811_OP_IY | M6811_OP_DIRECT)) + { + status = read_memory (memaddr + pos + offset, &buffer[0], 1, info); + if (status != 0) + { + return status; + } + + pos++; + offset = -1; + if (format & M6811_OP_IMM8) + { + (*info->fprintf_func) (info->stream, "#%d", (int) buffer[0]); + format &= ~M6811_OP_IMM8; + } + else if (format & M6811_OP_IX) + { + /* Offsets are in range 0..255, print them unsigned. */ + (*info->fprintf_func) (info->stream, "%u,x", buffer[0] & 0x0FF); + format &= ~M6811_OP_IX; + } + else if (format & M6811_OP_IY) + { + (*info->fprintf_func) (info->stream, "%u,y", buffer[0] & 0x0FF); + format &= ~M6811_OP_IY; + } + else if (format & M6811_OP_DIRECT) + { + (*info->fprintf_func) (info->stream, "*"); + (*info->print_address_func) (buffer[0] & 0x0FF, info); + format &= ~M6811_OP_DIRECT; + } + } + +#define M6812_INDEXED_FLAGS (M6812_OP_IDX|M6812_OP_IDX_1|M6812_OP_IDX_2) + /* Analyze the 68HC12 indexed byte. */ + if (format & M6812_INDEXED_FLAGS) + { + status = print_indexed_operand (memaddr + pos, info, 0); + if (status < 0) + { + return status; + } + pos += status; + } + + /* 68HC12 dbcc/ibcc/tbcc operands. */ + if ((format & M6812_OP_REG) && (format & M6811_OP_JUMP_REL)) + { + status = read_memory (memaddr + pos, &buffer[0], 2, info); + if (status != 0) + { + return status; + } + (*info->fprintf_func) (info->stream, "%s,", + reg_src_table[buffer[0] & 0x07]); + sval = buffer[1] & 0x0ff; + if (buffer[0] & 0x10) + sval |= 0xff00; + + pos += 2; + (*info->print_address_func) (memaddr + pos + sval, info); + format &= ~(M6812_OP_REG | M6811_OP_JUMP_REL); + } + else if (format & (M6812_OP_REG | M6812_OP_REG_2)) + { + status = read_memory (memaddr + pos, &buffer[0], 1, info); + if (status != 0) + { + return status; + } + + pos++; + (*info->fprintf_func) (info->stream, "%s,%s", + reg_src_table[(buffer[0] >> 4) & 7], + reg_dst_table[(buffer[0] & 7)]); + } + + /* M6811_OP_BITMASK and M6811_OP_JUMP_REL must be treated separately + and in that order. The brset/brclr insn have a bitmask and then + a relative branch offset. */ + if (format & M6811_OP_BITMASK) + { + status = read_memory (memaddr + pos, &buffer[0], 1, info); + if (status != 0) + { + return status; + } + pos++; + (*info->fprintf_func) (info->stream, " #$%02x%s", + buffer[0] & 0x0FF, + (format & M6811_OP_JUMP_REL ? " " : "")); + format &= ~M6811_OP_BITMASK; + } + if (format & M6811_OP_JUMP_REL) + { + int val; + + status = read_memory (memaddr + pos, &buffer[0], 1, info); + if (status != 0) + { + return status; + } + + pos++; + val = (buffer[0] & 0x80) ? buffer[0] | 0xFFFFFF00 : buffer[0]; + (*info->print_address_func) (memaddr + pos + val, info); + format &= ~M6811_OP_JUMP_REL; + } + else if (format & M6812_OP_JUMP_REL16) + { + int val; + + status = read_memory (memaddr + pos, &buffer[0], 2, info); + if (status != 0) + { + return status; + } + + pos += 2; + val = ((buffer[0] << 8) | (buffer[1] & 0x0FF)); + if (val & 0x8000) + val |= 0xffff0000; + + (*info->print_address_func) (memaddr + pos + val, info); + format &= ~M6812_OP_JUMP_REL16; + } + if (format & (M6811_OP_IMM16 | M6811_OP_IND16)) + { + int val; + + status = read_memory (memaddr + pos + offset, &buffer[0], 2, info); + if (status != 0) + { + return status; + } + if (format & M6812_OP_IDX_P2) + offset = -2; + else + offset = 0; + pos += 2; + + val = ((buffer[0] << 8) | (buffer[1] & 0x0FF)); + val &= 0x0FFFF; + if (format & M6811_OP_IMM16) + { + format &= ~M6811_OP_IMM16; + (*info->fprintf_func) (info->stream, "#"); + } + else + format &= ~M6811_OP_IND16; + + (*info->print_address_func) (val, info); + } + + if (format & M6812_OP_IDX_P2) + { + (*info->fprintf_func) (info->stream, ", "); + status = print_indexed_operand (memaddr + pos + offset, info, 1); + if (status < 0) + return status; + pos += status; + } + + if (format & M6812_OP_IND16_P2) + { + int val; + + (*info->fprintf_func) (info->stream, ", "); + + status = read_memory (memaddr + pos + offset, &buffer[0], 2, info); + if (status != 0) + { + return status; + } + pos += 2; + + val = ((buffer[0] << 8) | (buffer[1] & 0x0FF)); + val &= 0x0FFFF; + (*info->print_address_func) (val, info); + } + +#ifdef DEBUG + /* Consistency check. 'format' must be 0, so that we have handled + all formats; and the computed size of the insn must match the + opcode table content. */ + if (format & ~(M6811_OP_PAGE4 | M6811_OP_PAGE3 | M6811_OP_PAGE2)) + { + (*info->fprintf_func) (info->stream, "; Error, format: %x", format); + } + if (pos != opcode->size) + { + (*info->fprintf_func) (info->stream, "; Error, size: %d expect %d", + pos, opcode->size); + } +#endif + return pos; + } + + /* Opcode not recognized. */ + if (format == M6811_OP_PAGE2 && arch & cpu6812 + && ((code >= 0x30 && code <= 0x39) || (code >= 0x40 && code <= 0xff))) + (*info->fprintf_func) (info->stream, "trap\t#%d", code & 0x0ff); + + else if (format == M6811_OP_PAGE2) + (*info->fprintf_func) (info->stream, ".byte\t0x%02x, 0x%02x", + M6811_OPCODE_PAGE2, code); + else if (format == M6811_OP_PAGE3) + (*info->fprintf_func) (info->stream, ".byte\t0x%02x, 0x%02x", + M6811_OPCODE_PAGE3, code); + else if (format == M6811_OP_PAGE4) + (*info->fprintf_func) (info->stream, ".byte\t0x%02x, 0x%02x", + M6811_OPCODE_PAGE4, code); + else + (*info->fprintf_func) (info->stream, ".byte\t0x%02x", code); + + return pos; +} + +/* Disassemble one instruction at address 'memaddr'. Returns the number + of bytes used by that instruction. */ +int +print_insn_m68hc11 (memaddr, info) + bfd_vma memaddr; + struct disassemble_info *info; +{ + return print_insn (memaddr, info, cpu6811); +} + +int +print_insn_m68hc12 (memaddr, info) + bfd_vma memaddr; + struct disassemble_info *info; +{ + return print_insn (memaddr, info, cpu6812); +} diff --git a/opcodes/m68hc11-opc.c b/opcodes/m68hc11-opc.c new file mode 100644 index 00000000000..1e37971ee81 --- /dev/null +++ b/opcodes/m68hc11-opc.c @@ -0,0 +1,1074 @@ +/* m68hc11-opc.c -- Motorola 68HC11 & 68HC12 opcode list + Copyright 1999, 2000 Free Software Foundation, Inc. + Written by Stephane Carrez (stcarrez@worldnet.fr) + +This file is part of GDB, GAS, and the GNU binutils. + +GDB, GAS, and the GNU binutils are free software; you can redistribute +them and/or modify them under the terms of the GNU General Public +License as published by the Free Software Foundation; either version +2, or (at your option) any later version. + +GDB, GAS, and the GNU binutils are distributed in the hope that they +will be useful, but WITHOUT ANY WARRANTY; without even the implied +warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See +the GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this file; see the file COPYING. If not, write to the Free +Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. +*/ + +#include <stdio.h> +#include "ansidecl.h" +#include "opcode/m68hc11.h" + +#define TABLE_SIZE(X) (sizeof(X) / sizeof(X[0])) + +/* Combination of CCR flags. */ +#define M6811_ZC_BIT M6811_Z_BIT|M6811_C_BIT +#define M6811_NZ_BIT M6811_N_BIT|M6811_Z_BIT +#define M6811_NZV_BIT M6811_N_BIT|M6811_Z_BIT|M6811_V_BIT +#define M6811_NZC_BIT M6811_N_BIT|M6811_Z_BIT|M6811_C_BIT +#define M6811_NVC_BIT M6811_N_BIT|M6811_V_BIT|M6811_C_BIT +#define M6811_ZVC_BIT M6811_Z_BIT|M6811_V_BIT|M6811_C_BIT +#define M6811_NZVC_BIT M6811_ZVC_BIT|M6811_N_BIT +#define M6811_HNZVC_BIT M6811_NZVC_BIT|M6811_H_BIT +#define M6811_HNVC_BIT M6811_NVC_BIT|M6811_H_BIT +#define M6811_VC_BIT M6811_V_BIT|M6811_C_BIT + +/* Flags when the insn only changes some CCR flags. */ +#define CHG_NONE 0,0,0 +#define CHG_Z 0,0,M6811_Z_BIT +#define CHG_C 0,0,M6811_C_BIT +#define CHG_ZVC 0,0,M6811_ZVC_BIT +#define CHG_NZC 0,0,M6811_NZC_BIT +#define CHG_NZV 0,0,M6811_NZV_BIT +#define CHG_NZVC 0,0,M6811_NZVC_BIT +#define CHG_HNZVC 0,0,M6811_HNZVC_BIT +#define CHG_ALL 0,0,0xff + +/* The insn clears and changes some flags. */ +#define CLR_I 0,M6811_I_BIT,0 +#define CLR_C 0,M6811_C_BIT,0 +#define CLR_V 0,M6811_V_BIT,0 +#define CLR_V_CHG_ZC 0,M6811_V_BIT,M6811_ZC_BIT +#define CLR_V_CHG_NZ 0,M6811_V_BIT,M6811_NZ_BIT +#define CLR_V_CHG_ZVC 0,M6811_V_BIT,M6811_ZVC_BIT +#define CLR_N_CHG_ZVC 0,M6811_N_BIT,M6811_ZVC_BIT /* Used by lsr */ +#define CLR_VC_CHG_NZ 0,M6811_VC_BIT,M6811_NZ_BIT + +/* The insn sets some flags. */ +#define SET_I M6811_I_BIT,0,0 +#define SET_C M6811_C_BIT,0,0 +#define SET_V M6811_V_BIT,0,0 +#define SET_Z_CLR_NVC M6811_Z_BIT,M6811_NVC_BIT,0 +#define SET_C_CLR_V_CHG_NZ M6811_C_BIT,M6811_V_BIT,M6811_NZ_BIT +#define SET_Z_CHG_HNVC M6811_Z_BIT,0,M6811_HNVC_BIT + +#define _M 0xff +#define OP_NONE M6811_OP_NONE +#define OP_PAGE2 M6811_OP_PAGE2 +#define OP_PAGE3 M6811_OP_PAGE3 +#define OP_PAGE4 M6811_OP_PAGE4 +#define OP_IMM8 M6811_OP_IMM8 +#define OP_IMM16 M6811_OP_IMM16 +#define OP_IX M6811_OP_IX +#define OP_IY M6811_OP_IY +#define OP_IND16 M6811_OP_IND16 +#define OP_IDX M6812_OP_IDX +#define OP_IDX_1 M6812_OP_IDX_1 +#define OP_IDX_2 M6812_OP_IDX_2 +#define OP_D_IDX M6812_OP_D_IDX +#define OP_D_IDX_2 M6812_OP_D_IDX_2 +#define OP_DIRECT M6811_OP_DIRECT +#define OP_BITMASK M6811_OP_BITMASK +#define OP_JUMP_REL M6811_OP_JUMP_REL +#define OP_JUMP_REL16 M6812_OP_JUMP_REL16 +#define OP_REG M6812_OP_REG +#define OP_REG_1 M6812_OP_REG +#define OP_REG_2 M6812_OP_REG_2 +#define OP_IDX_p2 M6812_OP_IDX_P2 +#define OP_IND16_p2 M6812_OP_IND16_P2 +#define OP_TRAP_ID M6812_OP_TRAP_ID +#define OP_EXG_MARKER M6812_OP_EXG_MARKER +#define OP_TFR_MARKER M6812_OP_TFR_MARKER +#define OP_DBEQ_MARKER (M6812_OP_DBCC_MARKER|M6812_OP_EQ_MARKER) +#define OP_DBNE_MARKER (M6812_OP_DBCC_MARKER) +#define OP_TBEQ_MARKER (M6812_OP_TBCC_MARKER|M6812_OP_EQ_MARKER) +#define OP_TBNE_MARKER (M6812_OP_TBCC_MARKER) +#define OP_IBEQ_MARKER (M6812_OP_IBCC_MARKER|M6812_OP_EQ_MARKER) +#define OP_IBNE_MARKER (M6812_OP_IBCC_MARKER) + +/* + { "test", OP_NONE, 1, 0x00, 5, _M, CHG_NONE, cpu6811 }, + +-- cpu + Name -+ +------- Insn CCR changes + Format ------+ +----------- Max # cycles + Size --------------------+ +--------------- Min # cycles + +--------------------- Opcode +*/ +const struct m68hc11_opcode m68hc11_opcodes[] = { + { "aba", OP_NONE, 1, 0x1b, 2, 2, CHG_HNZVC, cpu6811 }, + { "aba", OP_NONE | OP_PAGE2,2, 0x06, 2, 2, CHG_HNZVC, cpu6812 }, + { "abx", OP_NONE, 1, 0x3a, 3, 3, CHG_NONE, cpu6811 }, + { "aby", OP_NONE | OP_PAGE2,2, 0x3a, 4, 4, CHG_NONE, cpu6811 }, + + { "adca", OP_IMM8, 2, 0x89, 1, 1, CHG_HNZVC, cpu6811|cpu6812 }, + { "adca", OP_DIRECT, 2, 0x99, 3, 3, CHG_HNZVC, cpu6811|cpu6812 }, + { "adca", OP_IND16, 3, 0xb9, 3, 3, CHG_HNZVC, cpu6811|cpu6812 }, + { "adca", OP_IX, 2, 0xa9, 4, 4, CHG_HNZVC, cpu6811 }, + { "adca", OP_IY | OP_PAGE2, 3, 0xa9, 5, 5, CHG_HNZVC, cpu6811 }, + { "adca", OP_IDX, 2, 0xa9, 3, 3, CHG_HNZVC, cpu6812 }, + { "adca", OP_IDX_1, 3, 0xa9, 3, 3, CHG_HNZVC, cpu6812 }, + { "adca", OP_IDX_2, 4, 0xa9, 4, 4, CHG_HNZVC, cpu6812 }, + { "adca", OP_D_IDX, 2, 0xa9, 6, 6, CHG_HNZVC, cpu6812 }, + { "adca", OP_D_IDX_2, 4, 0xa9, 6, 6, CHG_HNZVC, cpu6812 }, + + { "adcb", OP_IMM8, 2, 0xc9, 1, 1, CHG_HNZVC, cpu6811|cpu6812 }, + { "adcb", OP_DIRECT, 2, 0xd9, 3, 3, CHG_HNZVC, cpu6811|cpu6812 }, + { "adcb", OP_IND16, 3, 0xf9, 3, 3, CHG_HNZVC, cpu6811|cpu6812 }, + { "adcb", OP_IX, 2, 0xe9, 4, 4, CHG_HNZVC, cpu6811 }, + { "adcb", OP_IY | OP_PAGE2, 3, 0xe9, 5, 5, CHG_HNZVC, cpu6811 }, + { "adcb", OP_IDX, 2, 0xe9, 3, 3, CHG_HNZVC, cpu6812 }, + { "adcb", OP_IDX_1, 3, 0xe9, 3, 3, CHG_HNZVC, cpu6812 }, + { "adcb", OP_IDX_2, 4, 0xe9, 4, 4, CHG_HNZVC, cpu6812 }, + { "adcb", OP_D_IDX, 2, 0xe9, 6, 6, CHG_HNZVC, cpu6812 }, + { "adcb", OP_D_IDX_2, 4, 0xe9, 6, 6, CHG_HNZVC, cpu6812 }, + + { "adda", OP_IMM8, 2, 0x8b, 1, 1, CHG_HNZVC, cpu6811|cpu6812 }, + { "adda", OP_DIRECT, 2, 0x9b, 3, 3, CHG_HNZVC, cpu6811|cpu6812 }, + { "adda", OP_IND16, 3, 0xbb, 3, 3, CHG_HNZVC, cpu6811|cpu6812 }, + { "adda", OP_IX, 2, 0xab, 4, 4, CHG_HNZVC, cpu6811 }, + { "adda", OP_IY | OP_PAGE2, 3, 0xab, 5, 5, CHG_HNZVC, cpu6811 }, + { "adda", OP_IDX, 2, 0xab, 3, 3, CHG_HNZVC, cpu6812 }, + { "adda", OP_IDX_1, 3, 0xab, 3, 3, CHG_HNZVC, cpu6812 }, + { "adda", OP_IDX_2, 4, 0xab, 4, 4, CHG_HNZVC, cpu6812 }, + { "adda", OP_D_IDX, 2, 0xab, 6, 6, CHG_HNZVC, cpu6812 }, + { "adda", OP_D_IDX_2, 4, 0xab, 6, 6, CHG_HNZVC, cpu6812 }, + + { "addb", OP_IMM8, 2, 0xcb, 1, 1, CHG_HNZVC, cpu6811|cpu6812 }, + { "addb", OP_DIRECT, 2, 0xdb, 3, 3, CHG_HNZVC, cpu6811|cpu6812 }, + { "addb", OP_IND16, 3, 0xfb, 3, 3, CHG_HNZVC, cpu6811|cpu6812 }, + { "addb", OP_IX, 2, 0xeb, 4, 4, CHG_HNZVC, cpu6811 }, + { "addb", OP_IY | OP_PAGE2, 3, 0xeb, 5, 5, CHG_HNZVC, cpu6811 }, + { "addb", OP_IDX, 2, 0xeb, 3, 3, CHG_HNZVC, cpu6812 }, + { "addb", OP_IDX_1, 3, 0xeb, 3, 3, CHG_HNZVC, cpu6812 }, + { "addb", OP_IDX_2, 4, 0xeb, 4, 4, CHG_HNZVC, cpu6812 }, + { "addb", OP_D_IDX, 2, 0xeb, 6, 6, CHG_HNZVC, cpu6812 }, + { "addb", OP_D_IDX_2, 4, 0xeb, 6, 6, CHG_HNZVC, cpu6812 }, + + { "addd", OP_IMM16, 3, 0xc3, 2, 2, CHG_NZVC, cpu6811|cpu6812 }, + { "addd", OP_DIRECT, 2, 0xd3, 3, 3, CHG_NZVC, cpu6811|cpu6812 }, + { "addd", OP_IND16, 3, 0xf3, 3, 3, CHG_NZVC, cpu6811|cpu6812 }, + { "addd", OP_IX, 2, 0xe3, 6, 6, CHG_NZVC, cpu6811 }, + { "addd", OP_IY | OP_PAGE2, 3, 0xe3, 7, 7, CHG_NZVC, cpu6811 }, + { "addd", OP_IDX, 2, 0xe3, 3, 3, CHG_NZVC, cpu6812 }, + { "addd", OP_IDX_1, 3, 0xe3, 3, 3, CHG_NZVC, cpu6812 }, + { "addd", OP_IDX_2, 4, 0xe3, 4, 4, CHG_NZVC, cpu6812 }, + { "addd", OP_D_IDX, 2, 0xe3, 6, 6, CHG_NZVC, cpu6812 }, + { "addd", OP_D_IDX_2, 4, 0xe3, 6, 6, CHG_NZVC, cpu6812 }, + + { "anda", OP_IMM8, 2, 0x84, 1, 1, CLR_V_CHG_NZ, cpu6811|cpu6812 }, + { "anda", OP_DIRECT, 2, 0x94, 3, 3, CLR_V_CHG_NZ, cpu6811|cpu6812 }, + { "anda", OP_IND16, 3, 0xb4, 3, 3, CLR_V_CHG_NZ, cpu6811|cpu6812 }, + { "anda", OP_IX, 2, 0xa4, 4, 4, CLR_V_CHG_NZ, cpu6811 }, + { "anda", OP_IY | OP_PAGE2, 3, 0xa4, 5, 5, CLR_V_CHG_NZ, cpu6811 }, + { "anda", OP_IDX, 2, 0xa4, 3, 3, CLR_V_CHG_NZ, cpu6812 }, + { "anda", OP_IDX_1, 3, 0xa4, 3, 3, CLR_V_CHG_NZ, cpu6812 }, + { "anda", OP_IDX_2, 4, 0xa4, 4, 4, CLR_V_CHG_NZ, cpu6812 }, + { "anda", OP_D_IDX, 2, 0xa4, 6, 6, CLR_V_CHG_NZ, cpu6812 }, + { "anda", OP_D_IDX_2, 4, 0xa4, 6, 6, CLR_V_CHG_NZ, cpu6812 }, + + { "andb", OP_IMM8, 2, 0xc4, 1, 1, CLR_V_CHG_NZ, cpu6811|cpu6812 }, + { "andb", OP_DIRECT, 2, 0xd4, 3, 3, CLR_V_CHG_NZ, cpu6811|cpu6812 }, + { "andb", OP_IND16, 3, 0xf4, 3, 3, CLR_V_CHG_NZ, cpu6811|cpu6812 }, + { "andb", OP_IX, 2, 0xe4, 4, 4, CLR_V_CHG_NZ, cpu6811 }, + { "andb", OP_IY | OP_PAGE2, 3, 0xe4, 5, 5, CLR_V_CHG_NZ, cpu6811 }, + { "andb", OP_IDX, 2, 0xe4, 3, 3, CLR_V_CHG_NZ, cpu6812 }, + { "andb", OP_IDX_1, 3, 0xe4, 3, 3, CLR_V_CHG_NZ, cpu6812 }, + { "andb", OP_IDX_2, 4, 0xe4, 4, 4, CLR_V_CHG_NZ, cpu6812 }, + { "andb", OP_D_IDX, 2, 0xe4, 6, 6, CLR_V_CHG_NZ, cpu6812 }, + { "andb", OP_D_IDX_2, 4, 0xe4, 6, 6, CLR_V_CHG_NZ, cpu6812 }, + + { "andcc", OP_IMM8, 2, 0x10, 1, 1, CHG_ALL, cpu6812 }, + + { "asl", OP_IND16, 3, 0x78, 4, 4, CHG_NZVC, cpu6811|cpu6812 }, + { "asl", OP_IX, 2, 0x68, 6, 6, CHG_NZVC, cpu6811 }, + { "asl", OP_IY | OP_PAGE2, 3, 0x68, 7, 7, CHG_NZVC, cpu6811 }, + { "asl", OP_IDX, 2, 0x68, 3, 3, CHG_NZVC, cpu6812 }, + { "asl", OP_IDX_1, 3, 0x68, 4, 4, CHG_NZVC, cpu6812 }, + { "asl", OP_IDX_2, 4, 0x68, 5, 5, CHG_NZVC, cpu6812 }, + { "asl", OP_D_IDX, 2, 0x68, 6, 6, CHG_NZVC, cpu6812 }, + { "asl", OP_D_IDX_2, 4, 0x68, 6, 6, CHG_NZVC, cpu6812 }, + + { "asla", OP_NONE, 1, 0x48, 1, 1, CHG_NZVC, cpu6811|cpu6812 }, + { "aslb", OP_NONE, 1, 0x58, 1, 1, CHG_NZVC, cpu6811|cpu6812 }, + { "asld", OP_NONE, 1, 0x05, 3, 3, CHG_NZVC, cpu6811 }, + { "asld", OP_NONE, 1, 0x59, 1, 1, CHG_NZVC, cpu6812 }, + + { "asr", OP_IND16, 3, 0x77, 4, 4, CHG_NZVC, cpu6811|cpu6812 }, + { "asr", OP_IX, 2, 0x67, 6, 6, CHG_NZVC, cpu6811 }, + { "asr", OP_IY | OP_PAGE2, 3, 0x67, 7, 7, CHG_NZVC, cpu6811 }, + { "asr", OP_IDX, 2, 0x67, 3, 3, CHG_NZVC, cpu6812 }, + { "asr", OP_IDX_1, 3, 0x67, 4, 4, CHG_NZVC, cpu6812 }, + { "asr", OP_IDX_2, 4, 0x67, 5, 5, CHG_NZVC, cpu6812 }, + { "asr", OP_D_IDX, 2, 0x67, 6, 6, CHG_NZVC, cpu6812 }, + { "asr", OP_D_IDX_2, 4, 0x67, 6, 6, CHG_NZVC, cpu6812 }, + + { "asra", OP_NONE, 1, 0x47, 1, 1, CHG_NZVC, cpu6811|cpu6812 }, + { "asrb", OP_NONE, 1, 0x57, 1, 1, CHG_NZVC, cpu6811|cpu6812 }, + + { "bcc", OP_JUMP_REL, 2, 0x24, 1, 3, CHG_NONE, cpu6811|cpu6812 }, + + { "bclr", OP_BITMASK|OP_DIRECT, 3, 0x15, 6, 6, CLR_V_CHG_NZ, cpu6811 }, + { "bclr", OP_BITMASK|OP_IX, 3, 0x1d, 7, 7, CLR_V_CHG_NZ, cpu6811 }, + { "bclr", OP_BITMASK|OP_IY|OP_PAGE2, 4, 0x1d, 8, 8, CLR_V_CHG_NZ, cpu6811}, + { "bclr", OP_BITMASK|OP_DIRECT, 3, 0x4d, 4, 4, CLR_V_CHG_NZ, cpu6812 }, + { "bclr", OP_BITMASK|OP_IND16, 4, 0x1d, 4, 4, CLR_V_CHG_NZ, cpu6812 }, + { "bclr", OP_BITMASK|OP_IDX, 3, 0x0d, 4, 4, CLR_V_CHG_NZ, cpu6812 }, + { "bclr", OP_BITMASK|OP_IDX_1, 4, 0x0d, 4, 4, CLR_V_CHG_NZ, cpu6812 }, + { "bclr", OP_BITMASK|OP_IDX_2, 5, 0x0d, 6, 6, CLR_V_CHG_NZ, cpu6812 }, + + { "bcs", OP_JUMP_REL, 2, 0x25, 1, 3, CHG_NONE, cpu6811 | cpu6812 }, + { "beq", OP_JUMP_REL, 2, 0x27, 1, 3, CHG_NONE, cpu6811 | cpu6812 }, + { "bge", OP_JUMP_REL, 2, 0x2c, 1, 3, CHG_NONE, cpu6811 | cpu6812 }, + + { "bgnd", OP_NONE, 1, 0x00, 5, 5, CHG_NONE, cpu6811 | cpu6812 }, + + { "bgt", OP_JUMP_REL, 2, 0x2e, 1, 3, CHG_NONE, cpu6811 | cpu6812 }, + { "bhi", OP_JUMP_REL, 2, 0x22, 1, 3, CHG_NONE, cpu6811 | cpu6812 }, + { "bhs", OP_JUMP_REL, 2, 0x24, 1, 3, CHG_NONE, cpu6811 | cpu6812 }, + + { "bita", OP_IMM8, 2, 0x85, 1, 1, CLR_V_CHG_NZ, cpu6811|cpu6812 }, + { "bita", OP_DIRECT, 2, 0x95, 3, 3, CLR_V_CHG_NZ, cpu6811|cpu6812 }, + { "bita", OP_IND16, 3, 0xb5, 3, 3, CLR_V_CHG_NZ, cpu6811|cpu6812 }, + { "bita", OP_IX, 2, 0xa5, 4, 4, CLR_V_CHG_NZ, cpu6811 }, + { "bita", OP_IY | OP_PAGE2, 3, 0xa5, 5, 5, CLR_V_CHG_NZ, cpu6811 }, + { "bita", OP_IDX, 2, 0xa5, 3, 3, CLR_V_CHG_NZ, cpu6812 }, + { "bita", OP_IDX_1, 3, 0xa5, 3, 3, CLR_V_CHG_NZ, cpu6812 }, + { "bita", OP_IDX_2, 4, 0xa5, 4, 4, CLR_V_CHG_NZ, cpu6812 }, + { "bita", OP_D_IDX, 2, 0xa5, 6, 6, CLR_V_CHG_NZ, cpu6812 }, + { "bita", OP_D_IDX_2, 4, 0xa5, 6, 6, CLR_V_CHG_NZ, cpu6812 }, + + { "bitb", OP_IMM8, 2, 0xc5, 1, 1, CLR_V_CHG_NZ, cpu6811|cpu6812 }, + { "bitb", OP_DIRECT, 2, 0xd5, 3, 3, CLR_V_CHG_NZ, cpu6811|cpu6812 }, + { "bitb", OP_IND16, 3, 0xf5, 3, 3, CLR_V_CHG_NZ, cpu6811|cpu6812 }, + { "bitb", OP_IX, 2, 0xe5, 4, 4, CLR_V_CHG_NZ, cpu6811 }, + { "bitb", OP_IY | OP_PAGE2, 3, 0xe5, 5, 5, CLR_V_CHG_NZ, cpu6811 }, + { "bitb", OP_IDX, 2, 0xe5, 3, 3, CLR_V_CHG_NZ, cpu6812 }, + { "bitb", OP_IDX_1, 3, 0xe5, 3, 3, CLR_V_CHG_NZ, cpu6812 }, + { "bitb", OP_IDX_2, 4, 0xe5, 4, 4, CLR_V_CHG_NZ, cpu6812 }, + { "bitb", OP_D_IDX, 2, 0xe5, 6, 6, CLR_V_CHG_NZ, cpu6812 }, + { "bitb", OP_D_IDX_2, 4, 0xe5, 6, 6, CLR_V_CHG_NZ, cpu6812 }, + + { "ble", OP_JUMP_REL, 2, 0x2f, 1, 3, CHG_NONE, cpu6811 | cpu6812 }, + { "blo", OP_JUMP_REL, 2, 0x25, 1, 3, CHG_NONE, cpu6811 | cpu6812 }, + { "bls", OP_JUMP_REL, 2, 0x23, 1, 3, CHG_NONE, cpu6811 | cpu6812 }, + { "blt", OP_JUMP_REL, 2, 0x2d, 1, 3, CHG_NONE, cpu6811 | cpu6812 }, + { "bmi", OP_JUMP_REL, 2, 0x2b, 1, 3, CHG_NONE, cpu6811 | cpu6812 }, + { "bne", OP_JUMP_REL, 2, 0x26, 1, 3, CHG_NONE, cpu6811 | cpu6812 }, + { "bpl", OP_JUMP_REL, 2, 0x2a, 1, 3, CHG_NONE, cpu6811 | cpu6812 }, + { "bra", OP_JUMP_REL, 2, 0x20, 1, 3, CHG_NONE, cpu6811 | cpu6812 }, + + { "brclr", OP_BITMASK | OP_JUMP_REL + | OP_DIRECT, 4, 0x13, 6, 6, CHG_NONE, cpu6811 }, + { "brclr", OP_BITMASK | OP_JUMP_REL + | OP_IX, 4, 0x1f, 7, 7, CHG_NONE, cpu6811 }, + { "brclr", OP_BITMASK | OP_JUMP_REL + | OP_IY | OP_PAGE2, 5, 0x1f, 8, 8, CHG_NONE, cpu6811 }, + { "brclr", OP_BITMASK | OP_JUMP_REL + | OP_DIRECT, 4, 0x4f, 4, 4, CHG_NONE, cpu6812 }, + { "brclr", OP_BITMASK | OP_JUMP_REL + | OP_IND16, 5, 0x1f, 5, 5, CHG_NONE, cpu6812 }, + { "brclr", OP_BITMASK | OP_JUMP_REL + | OP_IDX, 4, 0x0f, 4, 4, CHG_NONE, cpu6812 }, + { "brclr", OP_BITMASK | OP_JUMP_REL + | OP_IDX_1, 5, 0x0f, 6, 6, CHG_NONE, cpu6812 }, + { "brclr", OP_BITMASK + | OP_JUMP_REL + | OP_IDX_2, 6, 0x0f, 8, 8, CHG_NONE, cpu6812 }, + + { "brn", OP_JUMP_REL, 2, 0x21, 1, 3, CHG_NONE, cpu6811|cpu6812 }, + + { "brset", OP_BITMASK | OP_JUMP_REL + | OP_DIRECT, 4, 0x12, 6, 6, CHG_NONE, cpu6811 }, + { "brset", OP_BITMASK + | OP_JUMP_REL + | OP_IX, 4, 0x1e, 7, 7, CHG_NONE, cpu6811 }, + { "brset", OP_BITMASK | OP_JUMP_REL + | OP_IY | OP_PAGE2, 5, 0x1e, 8, 8, CHG_NONE, cpu6811 }, + { "brset", OP_BITMASK | OP_JUMP_REL + | OP_DIRECT, 4, 0x4e, 4, 4, CHG_NONE, cpu6812 }, + { "brset", OP_BITMASK | OP_JUMP_REL + | OP_IND16, 5, 0x1e, 5, 5, CHG_NONE, cpu6812 }, + { "brset", OP_BITMASK | OP_JUMP_REL + | OP_IDX, 4, 0x0e, 4, 4, CHG_NONE, cpu6812 }, + { "brset", OP_BITMASK | OP_JUMP_REL + | OP_IDX_1, 5, 0x0e, 6, 6, CHG_NONE, cpu6812 }, + { "brset", OP_BITMASK | OP_JUMP_REL + | OP_IDX_2, 6, 0x0e, 8, 8, CHG_NONE, cpu6812 }, + + + { "bset", OP_BITMASK | OP_DIRECT, 3, 0x14, 6, 6, CLR_V_CHG_NZ, cpu6811 }, + { "bset", OP_BITMASK | OP_IX, 3, 0x1c, 7, 7, CLR_V_CHG_NZ, cpu6811 }, + { "bset", OP_BITMASK|OP_IY|OP_PAGE2, 4, 0x1c, 8, 8, CLR_V_CHG_NZ, cpu6811 }, + { "bset", OP_BITMASK|OP_DIRECT, 3, 0x4c, 4, 4, CLR_V_CHG_NZ, cpu6812 }, + { "bset", OP_BITMASK|OP_IND16, 4, 0x1c, 4, 4, CLR_V_CHG_NZ, cpu6812 }, + { "bset", OP_BITMASK|OP_IDX, 3, 0x0c, 4, 4, CLR_V_CHG_NZ, cpu6812 }, + { "bset", OP_BITMASK|OP_IDX_1, 4, 0x0c, 4, 4, CLR_V_CHG_NZ, cpu6812 }, + { "bset", OP_BITMASK|OP_IDX_2, 5, 0x0c, 6, 6, CLR_V_CHG_NZ, cpu6812 }, + + { "bsr", OP_JUMP_REL, 2, 0x8d, 6, 6, CHG_NONE, cpu6811 }, + { "bsr", OP_JUMP_REL, 2, 0x07, 4, 4, CHG_NONE, cpu6812 }, + + { "bvc", OP_JUMP_REL, 2, 0x28, 1, 3, CHG_NONE, cpu6811 | cpu6812 }, + { "bvs", OP_JUMP_REL, 2, 0x29, 1, 3, CHG_NONE, cpu6811 | cpu6812 }, + + { "call", OP_IND16, 4, 0x4a, 8, 8, CHG_NONE, cpu6812 }, + { "call", OP_IDX, 3, 0x4b, 8, 8, CHG_NONE, cpu6812 }, + { "call", OP_IDX_1, 4, 0x4b, 8, 8, CHG_NONE, cpu6812 }, + { "call", OP_IDX_2, 5, 0x4b, 9, 9, CHG_NONE, cpu6812 }, + { "call", OP_D_IDX, 2, 0x4b, 10, 10, CHG_NONE, cpu6812 }, + { "call", OP_D_IDX_2, 4, 0x4b, 10, 10, CHG_NONE, cpu6812 }, + + { "cba", OP_NONE, 1, 0x11, 2, 2, CHG_NZVC, cpu6811 }, + { "cba", OP_NONE | OP_PAGE2,2, 0x17, 2, 2, CHG_NZVC, cpu6812 }, + + { "clc", OP_NONE, 1, 0x0c, 2, 2, CLR_C, cpu6811 }, + { "cli", OP_NONE, 1, 0x0e, 2, 2, CLR_I, cpu6811 }, + + { "clr", OP_IND16, 3, 0x7f, 6, 6, SET_Z_CLR_NVC, cpu6811 }, + { "clr", OP_IX, 2, 0x6f, 6, 6, SET_Z_CLR_NVC, cpu6811 }, + { "clr", OP_IY | OP_PAGE2, 3, 0x6f, 7, 7, SET_Z_CLR_NVC, cpu6811 }, + { "clr", OP_IND16, 3, 0x79, 3, 3, SET_Z_CLR_NVC, cpu6812 }, + { "clr", OP_IDX, 2, 0x69, 2, 2, SET_Z_CLR_NVC, cpu6812 }, + { "clr", OP_IDX_1, 3, 0x69, 3, 3, SET_Z_CLR_NVC, cpu6812 }, + { "clr", OP_IDX_2, 4, 0x69, 4, 4, SET_Z_CLR_NVC, cpu6812 }, + { "clr", OP_D_IDX, 2, 0x69, 5, 5, SET_Z_CLR_NVC, cpu6812 }, + { "clr", OP_D_IDX_2, 4, 0x69, 5, 5, SET_Z_CLR_NVC, cpu6812 }, + + { "clra", OP_NONE, 1, 0x4f, 2, 2, SET_Z_CLR_NVC, cpu6811 }, + { "clrb", OP_NONE, 1, 0x5f, 2, 2, SET_Z_CLR_NVC, cpu6811 }, + { "clra", OP_NONE, 1, 0x87, 1, 1, SET_Z_CLR_NVC, cpu6812 }, + { "clrb", OP_NONE, 1, 0xc7, 1, 1, SET_Z_CLR_NVC, cpu6812 }, + + { "clv", OP_NONE, 1, 0x0a, 2, 2, CLR_V, cpu6811 }, + + { "cmpa", OP_IMM8, 2, 0x81, 1, 1, CHG_NZVC, cpu6811|cpu6812 }, + { "cmpa", OP_DIRECT, 2, 0x91, 3, 3, CHG_NZVC, cpu6811|cpu6812 }, + { "cmpa", OP_IND16, 3, 0xb1, 3, 3, CHG_NZVC, cpu6811|cpu6812 }, + { "cmpa", OP_IX, 2, 0xa1, 4, 4, CHG_NZVC, cpu6811 }, + { "cmpa", OP_IY | OP_PAGE2, 3, 0xa1, 5, 5, CHG_NZVC, cpu6811 }, + { "cmpa", OP_IDX, 2, 0xa1, 3, 3, CHG_NZVC, cpu6812 }, + { "cmpa", OP_IDX_1, 3, 0xa1, 3, 3, CHG_NZVC, cpu6812 }, + { "cmpa", OP_IDX_2, 4, 0xa1, 4, 4, CHG_NZVC, cpu6812 }, + { "cmpa", OP_D_IDX, 2, 0xa1, 6, 6, CHG_NZVC, cpu6812 }, + { "cmpa", OP_D_IDX_2, 4, 0xa1, 6, 6, CHG_NZVC, cpu6812 }, + + { "cmpb", OP_IMM8, 2, 0xc1, 1, 1, CHG_NZVC, cpu6811|cpu6812 }, + { "cmpb", OP_DIRECT, 2, 0xd1, 3, 3, CHG_NZVC, cpu6811|cpu6812 }, + { "cmpb", OP_IND16, 3, 0xf1, 3, 3, CHG_NZVC, cpu6811|cpu6812 }, + { "cmpb", OP_IX, 2, 0xe1, 4, 4, CHG_NZVC, cpu6811 }, + { "cmpb", OP_IY | OP_PAGE2, 3, 0xe1, 5, 5, CHG_NZVC, cpu6811 }, + { "cmpb", OP_IDX, 2, 0xe1, 3, 3, CHG_NZVC, cpu6812 }, + { "cmpb", OP_IDX_1, 3, 0xe1, 3, 3, CHG_NZVC, cpu6812 }, + { "cmpb", OP_IDX_2, 4, 0xe1, 4, 4, CHG_NZVC, cpu6812 }, + { "cmpb", OP_D_IDX, 2, 0xe1, 6, 6, CHG_NZVC, cpu6812 }, + { "cmpb", OP_D_IDX_2, 4, 0xe1, 6, 6, CHG_NZVC, cpu6812 }, + + { "com", OP_IND16, 3, 0x73, 6, 6, SET_C_CLR_V_CHG_NZ, cpu6811 }, + { "com", OP_IX, 2, 0x63, 6, 6, SET_C_CLR_V_CHG_NZ, cpu6811 }, + { "com", OP_IY | OP_PAGE2, 3, 0x63, 7, 7, SET_C_CLR_V_CHG_NZ, cpu6811 }, + { "com", OP_IND16, 3, 0x71, 4, 4, SET_C_CLR_V_CHG_NZ, cpu6812 }, + { "com", OP_IDX, 2, 0x61, 3, 3, SET_C_CLR_V_CHG_NZ, cpu6812 }, + { "com", OP_IDX_1, 3, 0x61, 4, 4, SET_C_CLR_V_CHG_NZ, cpu6812 }, + { "com", OP_IDX_2, 4, 0x61, 5, 5, SET_C_CLR_V_CHG_NZ, cpu6812 }, + { "com", OP_D_IDX, 2, 0x61, 6, 6, SET_C_CLR_V_CHG_NZ, cpu6812 }, + { "com", OP_D_IDX_2, 4, 0x61, 6, 6, SET_C_CLR_V_CHG_NZ, cpu6812 }, + + { "coma", OP_NONE, 1, 0x43, 2, 2, SET_C_CLR_V_CHG_NZ, cpu6811 }, + { "coma", OP_NONE, 1, 0x41, 1, 1, SET_C_CLR_V_CHG_NZ, cpu6812 }, + { "comb", OP_NONE, 1, 0x53, 2, 2, SET_C_CLR_V_CHG_NZ, cpu6811 }, + { "comb", OP_NONE, 1, 0x51, 1, 1, SET_C_CLR_V_CHG_NZ, cpu6812 }, + + { "cpd", OP_IMM16 | OP_PAGE3, 4, 0x83, 5, 5, CHG_NZVC, cpu6811 }, + { "cpd", OP_DIRECT | OP_PAGE3, 3, 0x93, 6, 6, CHG_NZVC, cpu6811 }, + { "cpd", OP_IND16 | OP_PAGE3, 4, 0xb3, 7, 7, CHG_NZVC, cpu6811 }, + { "cpd", OP_IX | OP_PAGE3, 3, 0xa3, 7, 7, CHG_NZVC, cpu6811 }, + { "cpd", OP_IY | OP_PAGE4, 3, 0xa3, 7, 7, CHG_NZVC, cpu6811 }, + { "cpd", OP_IMM16, 3, 0x8c, 2, 2, CHG_NZVC, cpu6812 }, + { "cpd", OP_DIRECT, 2, 0x9c, 3, 3, CHG_NZVC, cpu6812 }, + { "cpd", OP_IND16, 3, 0xbc, 3, 3, CHG_NZVC, cpu6812 }, + { "cpd", OP_IDX, 2, 0xac, 3, 3, CHG_NZVC, cpu6812 }, + { "cpd", OP_IDX_1, 3, 0xac, 3, 3, CHG_NZVC, cpu6812 }, + { "cpd", OP_IDX_2, 4, 0xac, 4, 4, CHG_NZVC, cpu6812 }, + { "cpd", OP_D_IDX, 2, 0xac, 6, 6, CHG_NZVC, cpu6812 }, + { "cpd", OP_D_IDX_2, 4, 0xac, 6, 6, CHG_NZVC, cpu6812 }, + + { "cps", OP_IMM16, 3, 0x8f, 2, 2, CHG_NZVC, cpu6812 }, + { "cps", OP_DIRECT, 2, 0x9f, 3, 3, CHG_NZVC, cpu6812 }, + { "cps", OP_IND16, 3, 0xbf, 3, 3, CHG_NZVC, cpu6812 }, + { "cps", OP_IDX, 2, 0xaf, 3, 3, CHG_NZVC, cpu6812 }, + { "cps", OP_IDX_1, 3, 0xaf, 3, 3, CHG_NZVC, cpu6812 }, + { "cps", OP_IDX_2, 4, 0xaf, 4, 4, CHG_NZVC, cpu6812 }, + { "cps", OP_D_IDX, 2, 0xaf, 6, 6, CHG_NZVC, cpu6812 }, + { "cps", OP_D_IDX_2, 4, 0xaf, 6, 6, CHG_NZVC, cpu6812 }, + + { "cpx", OP_IMM16, 3, 0x8c, 4, 4, CHG_NZVC, cpu6811 }, + { "cpx", OP_DIRECT, 2, 0x9c, 5, 5, CHG_NZVC, cpu6811 }, + { "cpx", OP_IND16, 3, 0xbc, 5, 5, CHG_NZVC, cpu6811 }, + { "cpx", OP_IX, 2, 0xac, 6, 6, CHG_NZVC, cpu6811 }, + { "cpx", OP_IY | OP_PAGE4, 3, 0xac, 7, 7, CHG_NZVC, cpu6811 }, + { "cpx", OP_IMM16, 3, 0x8e, 2, 2, CHG_NZVC, cpu6812 }, + { "cpx", OP_DIRECT, 2, 0x9e, 3, 3, CHG_NZVC, cpu6812 }, + { "cpx", OP_IND16, 3, 0xbe, 3, 3, CHG_NZVC, cpu6812 }, + { "cpx", OP_IDX, 2, 0xae, 3, 3, CHG_NZVC, cpu6812 }, + { "cpx", OP_IDX_1, 3, 0xae, 3, 3, CHG_NZVC, cpu6812 }, + { "cpx", OP_IDX_2, 4, 0xae, 4, 4, CHG_NZVC, cpu6812 }, + { "cpx", OP_D_IDX, 2, 0xae, 6, 6, CHG_NZVC, cpu6812 }, + { "cpx", OP_D_IDX_2, 4, 0xae, 6, 6, CHG_NZVC, cpu6812 }, + + { "cpy", OP_PAGE2 | OP_IMM16, 4, 0x8c, 5, 5, CHG_NZVC, cpu6811 }, + { "cpy", OP_PAGE2 | OP_DIRECT, 3, 0x9c, 6, 6, CHG_NZVC, cpu6811 }, + { "cpy", OP_PAGE2 | OP_IY, 3, 0xac, 7, 7, CHG_NZVC, cpu6811 }, + { "cpy", OP_PAGE2 | OP_IND16, 4, 0xbc, 7, 7, CHG_NZVC, cpu6811 }, + { "cpy", OP_PAGE3 | OP_IX, 3, 0xac, 7, 7, CHG_NZVC, cpu6811 }, + { "cpy", OP_IMM16, 3, 0x8d, 2, 2, CHG_NZVC, cpu6812 }, + { "cpy", OP_DIRECT, 2, 0x9d, 3, 3, CHG_NZVC, cpu6812 }, + { "cpy", OP_IND16, 3, 0xbd, 3, 3, CHG_NZVC, cpu6812 }, + { "cpy", OP_IDX, 2, 0xad, 3, 3, CHG_NZVC, cpu6812 }, + { "cpy", OP_IDX_1, 3, 0xad, 3, 3, CHG_NZVC, cpu6812 }, + { "cpy", OP_IDX_2, 4, 0xad, 4, 4, CHG_NZVC, cpu6812 }, + { "cpy", OP_D_IDX, 2, 0xad, 6, 6, CHG_NZVC, cpu6812 }, + { "cpy", OP_D_IDX_2, 4, 0xad, 6, 6, CHG_NZVC, cpu6812 }, + + /* After 'daa', the Z flag is undefined. Mark it as changed. */ + { "daa", OP_NONE, 1, 0x19, 2, 2, CHG_NZVC, cpu6811 }, + { "daa", OP_NONE | OP_PAGE2, 2, 0x07, 3, 3, CHG_NZVC, cpu6812 }, + + { "dbeq", OP_DBEQ_MARKER + | OP_REG | OP_JUMP_REL,3, 0x04, 3, 3, CHG_NONE, cpu6812 }, + { "dbne", OP_DBNE_MARKER + | OP_REG | OP_JUMP_REL,3, 0x04, 3, 3, CHG_NONE, cpu6812 }, + + { "dec", OP_IX, 2, 0x6a, 6, 6, CHG_NZV, cpu6811 }, + { "dec", OP_IND16, 3, 0x7a, 6, 6, CHG_NZV, cpu6811 }, + { "dec", OP_IY | OP_PAGE2, 3, 0x6a, 7, 7, CHG_NZV, cpu6811 }, + { "dec", OP_IND16, 3, 0x73, 4, 4, CHG_NZV, cpu6812 }, + { "dec", OP_IDX, 2, 0x63, 3, 3, CHG_NZV, cpu6812 }, + { "dec", OP_IDX_1, 3, 0x63, 4, 4, CHG_NZV, cpu6812 }, + { "dec", OP_IDX_2, 4, 0x63, 5, 5, CHG_NZV, cpu6812 }, + { "dec", OP_D_IDX, 2, 0x63, 6, 6, CHG_NZV, cpu6812 }, + { "dec", OP_D_IDX_2, 4, 0x63, 6, 6, CHG_NZV, cpu6812 }, + + { "des", OP_NONE, 1, 0x34, 3, 3, CHG_NONE, cpu6811 }, + + { "deca", OP_NONE, 1, 0x4a, 2, 2, CHG_NZV, cpu6811 }, + { "deca", OP_NONE, 1, 0x43, 1, 1, CHG_NZV, cpu6812 }, + { "decb", OP_NONE, 1, 0x5a, 2, 2, CHG_NZV, cpu6811 }, + { "decb", OP_NONE, 1, 0x53, 1, 1, CHG_NZV, cpu6812 }, + + { "dex", OP_NONE, 1, 0x09, 1, 1, CHG_Z, cpu6812|cpu6811 }, + { "dey", OP_NONE | OP_PAGE2, 2, 0x09, 4, 4, CHG_Z, cpu6811 }, + { "dey", OP_NONE, 1, 0x03, 1, 1, CHG_Z, cpu6812 }, + + { "ediv", OP_NONE, 1, 0x11, 11, 11, CHG_NZVC, cpu6812 }, + { "edivs", OP_NONE | OP_PAGE2, 2, 0x14, 12, 12, CHG_NZVC, cpu6812 }, + { "emacs", OP_IND16 | OP_PAGE2, 4, 0x12, 13, 13, CHG_NZVC, cpu6812 }, + + { "emaxd", OP_IDX | OP_PAGE2, 3, 0x1a, 4, 4, CHG_NZVC, cpu6812 }, + { "emaxd", OP_IDX_1 | OP_PAGE2, 4, 0x1a, 4, 4, CHG_NZVC, cpu6812 }, + { "emaxd", OP_IDX_2 | OP_PAGE2, 5, 0x1a, 5, 5, CHG_NZVC, cpu6812 }, + { "emaxd", OP_D_IDX | OP_PAGE2, 3, 0x1a, 7, 7, CHG_NZVC, cpu6812 }, + { "emaxd", OP_D_IDX_2 | OP_PAGE2, 5, 0x1a, 7, 7, CHG_NZVC, cpu6812 }, + + { "emaxm", OP_IDX | OP_PAGE2, 3, 0x1e, 4, 4, CHG_NZVC, cpu6812 }, + { "emaxm", OP_IDX_1 | OP_PAGE2, 4, 0x1e, 5, 5, CHG_NZVC, cpu6812 }, + { "emaxm", OP_IDX_2 | OP_PAGE2, 5, 0x1e, 6, 6, CHG_NZVC, cpu6812 }, + { "emaxm", OP_D_IDX | OP_PAGE2, 3, 0x1e, 7, 7, CHG_NZVC, cpu6812 }, + { "emaxm", OP_D_IDX_2 | OP_PAGE2, 5, 0x1e, 7, 7, CHG_NZVC, cpu6812 }, + + { "emind", OP_IDX | OP_PAGE2, 3, 0x1b, 4, 4, CHG_NZVC, cpu6812 }, + { "emind", OP_IDX_1 | OP_PAGE2, 4, 0x1b, 4, 4, CHG_NZVC, cpu6812 }, + { "emind", OP_IDX_2 | OP_PAGE2, 5, 0x1b, 5, 5, CHG_NZVC, cpu6812 }, + { "emind", OP_D_IDX | OP_PAGE2, 3, 0x1b, 7, 7, CHG_NZVC, cpu6812 }, + { "emind", OP_D_IDX_2 | OP_PAGE2, 5, 0x1b, 7, 7, CHG_NZVC, cpu6812 }, + + { "eminm", OP_IDX | OP_PAGE2, 3, 0x1f, 4, 4, CHG_NZVC, cpu6812 }, + { "eminm", OP_IDX_1 | OP_PAGE2, 4, 0x1f, 5, 5, CHG_NZVC, cpu6812 }, + { "eminm", OP_IDX_2 | OP_PAGE2, 5, 0x1f, 6, 6, CHG_NZVC, cpu6812 }, + { "eminm", OP_D_IDX | OP_PAGE2, 3, 0x1f, 7, 7, CHG_NZVC, cpu6812 }, + { "eminm", OP_D_IDX_2 | OP_PAGE2, 5, 0x1f, 7, 7, CHG_NZVC, cpu6812 }, + + { "emul", OP_NONE, 1, 0x13, 3, 3, CHG_NZC, cpu6812 }, + { "emuls", OP_NONE | OP_PAGE2, 2, 0x13, 3, 3, CHG_NZC, cpu6812 }, + + { "eora", OP_IMM8, 2, 0x88, 1, 1, CLR_V_CHG_NZ, cpu6811|cpu6812 }, + { "eora", OP_DIRECT, 2, 0x98, 3, 3, CLR_V_CHG_NZ, cpu6811|cpu6812 }, + { "eora", OP_IND16, 3, 0xb8, 3, 3, CLR_V_CHG_NZ, cpu6811|cpu6812 }, + { "eora", OP_IX, 2, 0xa8, 4, 4, CLR_V_CHG_NZ, cpu6811 }, + { "eora", OP_IY | OP_PAGE2, 3, 0xa8, 5, 5, CLR_V_CHG_NZ, cpu6811 }, + { "eora", OP_IDX, 2, 0xa8, 3, 3, CLR_V_CHG_NZ, cpu6812 }, + { "eora", OP_IDX_1, 3, 0xa8, 3, 3, CLR_V_CHG_NZ, cpu6812 }, + { "eora", OP_IDX_2, 4, 0xa8, 4, 4, CLR_V_CHG_NZ, cpu6812 }, + { "eora", OP_D_IDX, 2, 0xa8, 6, 6, CLR_V_CHG_NZ, cpu6812 }, + { "eora", OP_D_IDX_2, 4, 0xa8, 6, 6, CLR_V_CHG_NZ, cpu6812 }, + + { "eorb", OP_IMM8, 2, 0xc8, 1, 1, CLR_V_CHG_NZ, cpu6811|cpu6812 }, + { "eorb", OP_DIRECT, 2, 0xd8, 3, 3, CLR_V_CHG_NZ, cpu6811|cpu6812 }, + { "eorb", OP_IND16, 3, 0xf8, 3, 3, CLR_V_CHG_NZ, cpu6811|cpu6812 }, + { "eorb", OP_IX, 2, 0xe8, 4, 4, CLR_V_CHG_NZ, cpu6811 }, + { "eorb", OP_IY | OP_PAGE2, 3, 0xe8, 5, 5, CLR_V_CHG_NZ, cpu6811 }, + { "eorb", OP_IDX, 2, 0xe8, 3, 3, CLR_V_CHG_NZ, cpu6812 }, + { "eorb", OP_IDX_1, 3, 0xe8, 3, 3, CLR_V_CHG_NZ, cpu6812 }, + { "eorb", OP_IDX_2, 4, 0xe8, 4, 4, CLR_V_CHG_NZ, cpu6812 }, + { "eorb", OP_D_IDX, 2, 0xe8, 6, 6, CLR_V_CHG_NZ, cpu6812 }, + { "eorb", OP_D_IDX_2, 4, 0xe8, 6, 6, CLR_V_CHG_NZ, cpu6812 }, + + { "etbl", OP_IDX | OP_PAGE2,3, 0x3f, 10, 10, CHG_NZC, cpu6812 }, + + { "exg", OP_EXG_MARKER + | OP_REG | OP_REG_2, 2, 0xb7, 1, 1, CHG_NONE, cpu6812 }, + + { "fdiv", OP_NONE, 1, 0x03, 3, 41, CHG_ZVC, cpu6811}, + { "fdiv", OP_NONE | OP_PAGE2, 2, 0x11, 12, 12, CHG_ZVC, cpu6812 }, + + { "ibeq", OP_IBEQ_MARKER + | OP_REG | OP_JUMP_REL, 3, 0x04, 3, 3, CHG_NONE, cpu6812 }, + { "ibne", OP_IBNE_MARKER + | OP_REG | OP_JUMP_REL, 3, 0x04, 3, 3, CHG_NONE, cpu6812 }, + + { "idiv", OP_NONE, 1, 0x02, 3, 41, CLR_V_CHG_ZC, cpu6811}, + { "idiv", OP_NONE | OP_PAGE2, 2, 0x10, 12, 12, CLR_V_CHG_ZC, cpu6812 }, + { "idivs", OP_NONE | OP_PAGE2, 2, 0x15, 12, 12, CHG_NZVC, cpu6812 }, + + { "inc", OP_IX, 2, 0x6c, 6, 6, CHG_NZV, cpu6811 }, + { "inc", OP_IND16, 3, 0x7c, 6, 6, CHG_NZV, cpu6811 }, + { "inc", OP_IY | OP_PAGE2, 3, 0x6c, 7, 7, CHG_NZV, cpu6811 }, + { "inc", OP_IND16, 3, 0x72, 4, 4, CHG_NZV, cpu6812 }, + { "inc", OP_IDX, 2, 0x62, 3, 3, CHG_NZV, cpu6812 }, + { "inc", OP_IDX_1, 3, 0x62, 4, 4, CHG_NZV, cpu6812 }, + { "inc", OP_IDX_2, 4, 0x62, 5, 5, CHG_NZV, cpu6812 }, + { "inc", OP_D_IDX, 2, 0x62, 6, 6, CHG_NZV, cpu6812 }, + { "inc", OP_D_IDX_2, 4, 0x62, 6, 6, CHG_NZV, cpu6812 }, + + { "inca", OP_NONE, 1, 0x4c, 2, 2, CHG_NZV, cpu6811 }, + { "inca", OP_NONE, 1, 0x42, 1, 1, CHG_NZV, cpu6812 }, + { "incb", OP_NONE, 1, 0x5c, 2, 2, CHG_NZV, cpu6811 }, + { "incb", OP_NONE, 1, 0x52, 1, 1, CHG_NZV, cpu6812 }, + + { "ins", OP_NONE, 1, 0x31, 3, 3, CHG_NONE, cpu6811 }, + + { "inx", OP_NONE, 1, 0x08, 1, 1, CHG_Z, cpu6811|cpu6812 }, + { "iny", OP_NONE |OP_PAGE2, 2, 0x08, 4, 4, CHG_Z, cpu6811 }, + { "iny", OP_NONE, 1, 0x02, 1, 1, CHG_Z, cpu6812 }, + + { "jmp", OP_IND16, 3, 0x7e, 3, 3, CHG_NONE, cpu6811 }, + { "jmp", OP_IX, 2, 0x6e, 3, 3, CHG_NONE, cpu6811 }, + { "jmp", OP_IY | OP_PAGE2, 3, 0x6e, 4, 4, CHG_NONE, cpu6811 }, + { "jmp", OP_IND16, 3, 0x06, 3, 3, CHG_NONE, cpu6812 }, + { "jmp", OP_IDX, 2, 0x05, 3, 3, CHG_NONE, cpu6812 }, + { "jmp", OP_IDX_1, 3, 0x05, 3, 3, CHG_NONE, cpu6812 }, + { "jmp", OP_IDX_2, 4, 0x05, 4, 4, CHG_NONE, cpu6812 }, + { "jmp", OP_D_IDX, 2, 0x05, 6, 6, CHG_NONE, cpu6812 }, + { "jmp", OP_D_IDX_2, 4, 0x05, 6, 6, CHG_NONE, cpu6812 }, + + { "jsr", OP_DIRECT, 2, 0x9d, 5, 5, CHG_NONE, cpu6811 }, + { "jsr", OP_IND16, 3, 0xbd, 6, 6, CHG_NONE, cpu6811 }, + { "jsr", OP_IX, 2, 0xad, 6, 6, CHG_NONE, cpu6811 }, + { "jsr", OP_IY | OP_PAGE2, 3, 0xad, 6, 6, CHG_NONE, cpu6811 }, + { "jsr", OP_DIRECT, 2, 0x17, 4, 4, CHG_NONE, cpu6812 }, + { "jsr", OP_IND16, 3, 0x16, 4, 3, CHG_NONE, cpu6812 }, + { "jsr", OP_IDX, 2, 0x15, 4, 4, CHG_NONE, cpu6812 }, + { "jsr", OP_IDX_1, 3, 0x15, 4, 4, CHG_NONE, cpu6812 }, + { "jsr", OP_IDX_2, 4, 0x15, 5, 5, CHG_NONE, cpu6812 }, + { "jsr", OP_D_IDX, 2, 0x15, 7, 7, CHG_NONE, cpu6812 }, + { "jsr", OP_D_IDX_2, 4, 0x15, 7, 7, CHG_NONE, cpu6812 }, + + { "lbcc", OP_JUMP_REL16 | OP_PAGE2, 4, 0x24, 3, 4, CHG_NONE, cpu6812 }, + { "lbcs", OP_JUMP_REL16 | OP_PAGE2, 4, 0x25, 3, 4, CHG_NONE, cpu6812 }, + { "lbeq", OP_JUMP_REL16 | OP_PAGE2, 4, 0x27, 3, 4, CHG_NONE, cpu6812 }, + { "lbge", OP_JUMP_REL16 | OP_PAGE2, 4, 0x2c, 3, 4, CHG_NONE, cpu6812 }, + { "lbgt", OP_JUMP_REL16 | OP_PAGE2, 4, 0x2e, 3, 4, CHG_NONE, cpu6812 }, + { "lbhi", OP_JUMP_REL16 | OP_PAGE2, 4, 0x22, 3, 4, CHG_NONE, cpu6812 }, + { "lbhs", OP_JUMP_REL16 | OP_PAGE2, 4, 0x24, 3, 4, CHG_NONE, cpu6812 }, + { "lble", OP_JUMP_REL16 | OP_PAGE2, 4, 0x2f, 3, 4, CHG_NONE, cpu6812 }, + { "lblo", OP_JUMP_REL16 | OP_PAGE2, 4, 0x25, 3, 4, CHG_NONE, cpu6812 }, + { "lbls", OP_JUMP_REL16 | OP_PAGE2, 4, 0x23, 3, 4, CHG_NONE, cpu6812 }, + { "lblt", OP_JUMP_REL16 | OP_PAGE2, 4, 0x2d, 3, 4, CHG_NONE, cpu6812 }, + { "lbmi", OP_JUMP_REL16 | OP_PAGE2, 4, 0x2b, 3, 4, CHG_NONE, cpu6812 }, + { "lbne", OP_JUMP_REL16 | OP_PAGE2, 4, 0x26, 3, 4, CHG_NONE, cpu6812 }, + { "lbpl", OP_JUMP_REL16 | OP_PAGE2, 4, 0x2a, 3, 4, CHG_NONE, cpu6812 }, + { "lbra", OP_JUMP_REL16 | OP_PAGE2, 4, 0x20, 4, 4, CHG_NONE, cpu6812 }, + { "lbrn", OP_JUMP_REL16 | OP_PAGE2, 4, 0x21, 3, 3, CHG_NONE, cpu6812 }, + { "lbvc", OP_JUMP_REL16 | OP_PAGE2, 4, 0x28, 3, 4, CHG_NONE, cpu6812 }, + { "lbvs", OP_JUMP_REL16 | OP_PAGE2, 4, 0x29, 3, 4, CHG_NONE, cpu6812 }, + + { "ldaa", OP_IMM8, 2, 0x86, 1, 1, CLR_V_CHG_NZ, cpu6811|cpu6812 }, + { "ldaa", OP_DIRECT, 2, 0x96, 3, 3, CLR_V_CHG_NZ, cpu6811|cpu6812 }, + { "ldaa", OP_IND16, 3, 0xb6, 3, 3, CLR_V_CHG_NZ, cpu6811|cpu6812 }, + { "ldaa", OP_IX, 2, 0xa6, 4, 4, CLR_V_CHG_NZ, cpu6811 }, + { "ldaa", OP_IY | OP_PAGE2, 3, 0xa6, 5, 5, CLR_V_CHG_NZ, cpu6811 }, + { "ldaa", OP_IDX, 2, 0xa6, 3, 3, CLR_V_CHG_NZ, cpu6812 }, + { "ldaa", OP_IDX_1, 3, 0xa6, 3, 3, CLR_V_CHG_NZ, cpu6812 }, + { "ldaa", OP_IDX_2, 4, 0xa6, 4, 4, CLR_V_CHG_NZ, cpu6812 }, + { "ldaa", OP_D_IDX, 2, 0xa6, 6, 6, CLR_V_CHG_NZ, cpu6812 }, + { "ldaa", OP_D_IDX_2, 4, 0xa6, 6, 6, CLR_V_CHG_NZ, cpu6812 }, + + { "ldab", OP_IMM8, 2, 0xc6, 1, 1, CLR_V_CHG_NZ, cpu6811|cpu6812 }, + { "ldab", OP_DIRECT, 2, 0xd6, 3, 3, CLR_V_CHG_NZ, cpu6811|cpu6812 }, + { "ldab", OP_IND16, 3, 0xf6, 3, 3, CLR_V_CHG_NZ, cpu6811|cpu6812 }, + { "ldab", OP_IX, 2, 0xe6, 4, 4, CLR_V_CHG_NZ, cpu6811 }, + { "ldab", OP_IY | OP_PAGE2, 3, 0xe6, 5, 5, CLR_V_CHG_NZ, cpu6811 }, + { "ldab", OP_IDX, 2, 0xe6, 3, 3, CLR_V_CHG_NZ, cpu6812 }, + { "ldab", OP_IDX_1, 3, 0xe6, 3, 3, CLR_V_CHG_NZ, cpu6812 }, + { "ldab", OP_IDX_2, 4, 0xe6, 4, 4, CLR_V_CHG_NZ, cpu6812 }, + { "ldab", OP_D_IDX, 2, 0xe6, 6, 6, CLR_V_CHG_NZ, cpu6812 }, + { "ldab", OP_D_IDX_2, 4, 0xe6, 6, 6, CLR_V_CHG_NZ, cpu6812 }, + + { "ldd", OP_IMM16, 3, 0xcc, 2, 2, CLR_V_CHG_NZ, cpu6811|cpu6812 }, + { "ldd", OP_DIRECT, 2, 0xdc, 3, 3, CLR_V_CHG_NZ, cpu6811|cpu6812 }, + { "ldd", OP_IND16, 3, 0xfc, 3, 3, CLR_V_CHG_NZ, cpu6811|cpu6812 }, + { "ldd", OP_IX, 2, 0xec, 5, 5, CLR_V_CHG_NZ, cpu6811 }, + { "ldd", OP_IY | OP_PAGE2, 3, 0xec, 6, 6, CLR_V_CHG_NZ, cpu6811 }, + { "ldd", OP_IDX, 2, 0xec, 3, 3, CLR_V_CHG_NZ, cpu6812 }, + { "ldd", OP_IDX_1, 3, 0xec, 3, 3, CLR_V_CHG_NZ, cpu6812 }, + { "ldd", OP_IDX_2, 4, 0xec, 4, 4, CLR_V_CHG_NZ, cpu6812 }, + { "ldd", OP_D_IDX, 2, 0xec, 6, 6, CLR_V_CHG_NZ, cpu6812 }, + { "ldd", OP_D_IDX_2, 4, 0xec, 6, 6, CLR_V_CHG_NZ, cpu6812 }, + + { "lds", OP_IMM16, 3, 0x8e, 3, 3, CLR_V_CHG_NZ, cpu6811 }, + { "lds", OP_DIRECT, 2, 0x9e, 4, 4, CLR_V_CHG_NZ, cpu6811 }, + { "lds", OP_IND16, 3, 0xbe, 5, 5, CLR_V_CHG_NZ, cpu6811 }, + { "lds", OP_IX, 2, 0xae, 5, 5, CLR_V_CHG_NZ, cpu6811 }, + { "lds", OP_IY | OP_PAGE2, 3, 0xae, 6, 6, CLR_V_CHG_NZ, cpu6811 }, + { "lds", OP_IMM16, 3, 0xcf, 2, 2, CLR_V_CHG_NZ, cpu6812 }, + { "lds", OP_DIRECT, 2, 0xdf, 3, 3, CLR_V_CHG_NZ, cpu6812 }, + { "lds", OP_IND16, 3, 0xff, 3, 3, CLR_V_CHG_NZ, cpu6812 }, + { "lds", OP_IDX, 2, 0xef, 3, 3, CLR_V_CHG_NZ, cpu6812 }, + { "lds", OP_IDX_1, 3, 0xef, 3, 3, CLR_V_CHG_NZ, cpu6812 }, + { "lds", OP_IDX_2, 4, 0xef, 4, 4, CLR_V_CHG_NZ, cpu6812 }, + { "lds", OP_D_IDX, 2, 0xef, 6, 6, CLR_V_CHG_NZ, cpu6812 }, + { "lds", OP_D_IDX_2, 4, 0xef, 6, 6, CLR_V_CHG_NZ, cpu6812 }, + + { "ldx", OP_IMM16, 3, 0xce, 2, 2, CLR_V_CHG_NZ, cpu6811|cpu6812 }, + { "ldx", OP_DIRECT, 2, 0xde, 3, 3, CLR_V_CHG_NZ, cpu6811|cpu6812 }, + { "ldx", OP_IND16, 3, 0xfe, 3, 3, CLR_V_CHG_NZ, cpu6811|cpu6812 }, + { "ldx", OP_IX, 2, 0xee, 5, 5, CLR_V_CHG_NZ, cpu6811 }, + { "ldx", OP_IY | OP_PAGE4, 3, 0xee, 6, 6, CLR_V_CHG_NZ, cpu6811 }, + { "ldx", OP_IDX, 2, 0xee, 3, 3, CLR_V_CHG_NZ, cpu6812 }, + { "ldx", OP_IDX_1, 3, 0xee, 3, 3, CLR_V_CHG_NZ, cpu6812 }, + { "ldx", OP_IDX_2, 4, 0xee, 4, 4, CLR_V_CHG_NZ, cpu6812 }, + { "ldx", OP_D_IDX, 2, 0xee, 6, 6, CLR_V_CHG_NZ, cpu6812 }, + { "ldx", OP_D_IDX_2, 4, 0xee, 6, 6, CLR_V_CHG_NZ, cpu6812 }, + + { "ldy", OP_IMM16 | OP_PAGE2, 4, 0xce, 4, 4, CLR_V_CHG_NZ, cpu6811 }, + { "ldy", OP_DIRECT | OP_PAGE2, 3, 0xde, 5, 5, CLR_V_CHG_NZ, cpu6811 }, + { "ldy", OP_IND16 | OP_PAGE2, 4, 0xfe, 6, 6, CLR_V_CHG_NZ, cpu6811 }, + { "ldy", OP_IX | OP_PAGE3, 3, 0xee, 6, 6, CLR_V_CHG_NZ, cpu6811 }, + { "ldy", OP_IY | OP_PAGE2, 3, 0xee, 6, 6, CLR_V_CHG_NZ, cpu6811 }, + { "ldy", OP_IMM16, 3, 0xcd, 2, 2, CLR_V_CHG_NZ, cpu6812 }, + { "ldy", OP_DIRECT, 2, 0xdd, 3, 3, CLR_V_CHG_NZ, cpu6812 }, + { "ldy", OP_IND16, 3, 0xfd, 3, 3, CLR_V_CHG_NZ, cpu6812 }, + { "ldy", OP_IDX, 2, 0xed, 3, 3, CLR_V_CHG_NZ, cpu6812 }, + { "ldy", OP_IDX_1, 3, 0xed, 3, 3, CLR_V_CHG_NZ, cpu6812 }, + { "ldy", OP_IDX_2, 4, 0xed, 4, 4, CLR_V_CHG_NZ, cpu6812 }, + { "ldy", OP_D_IDX, 2, 0xed, 6, 6, CLR_V_CHG_NZ, cpu6812 }, + { "ldy", OP_D_IDX_2, 4, 0xed, 6, 6, CLR_V_CHG_NZ, cpu6812 }, + + { "leas", OP_IDX, 2, 0x1b, 2, 2, CHG_NONE, cpu6812 }, + { "leas", OP_IDX_1, 3, 0x1b, 2, 2, CHG_NONE, cpu6812 }, + { "leas", OP_IDX_2, 4, 0x1b, 2, 2, CHG_NONE, cpu6812 }, + + { "leax", OP_IDX, 2, 0x1a, 2, 2, CHG_NONE, cpu6812 }, + { "leax", OP_IDX_1, 3, 0x1a, 2, 2, CHG_NONE, cpu6812 }, + { "leax", OP_IDX_2, 4, 0x1a, 2, 2, CHG_NONE, cpu6812 }, + + { "leay", OP_IDX, 2, 0x19, 2, 2, CHG_NONE, cpu6812 }, + { "leay", OP_IDX_1, 3, 0x19, 2, 2, CHG_NONE, cpu6812 }, + { "leay", OP_IDX_2, 4, 0x19, 2, 2, CHG_NONE, cpu6812 }, + + { "lsl", OP_IND16, 3, 0x78, 4, 4, CHG_NZVC, cpu6811|cpu6812 }, + { "lsl", OP_IX, 2, 0x68, 6, 6, CHG_NZVC, cpu6811 }, + { "lsl", OP_IY | OP_PAGE2, 3, 0x68, 7, 7, CHG_NZVC, cpu6811 }, + { "lsl", OP_IDX, 2, 0x68, 3, 3, CHG_NZVC, cpu6812 }, + { "lsl", OP_IDX_1, 3, 0x68, 4, 4, CHG_NZVC, cpu6812 }, + { "lsl", OP_IDX_2, 4, 0x68, 5, 5, CHG_NZVC, cpu6812 }, + { "lsl", OP_D_IDX, 2, 0x68, 6, 6, CHG_NZVC, cpu6812 }, + { "lsl", OP_D_IDX_2, 4, 0x68, 6, 6, CHG_NZVC, cpu6812 }, + + { "lsla", OP_NONE, 1, 0x48, 1, 1, CHG_NZVC, cpu6811|cpu6812 }, + { "lslb", OP_NONE, 1, 0x58, 1, 1, CHG_NZVC, cpu6811|cpu6812 }, + { "lsld", OP_NONE, 1, 0x05, 3, 3, CHG_NZVC, cpu6811 }, + { "lsld", OP_NONE, 1, 0x59, 1, 1, CHG_NZVC, cpu6812 }, + + { "lsr", OP_IND16, 3, 0x74, 4, 4, CLR_N_CHG_ZVC, cpu6811|cpu6812}, + { "lsr", OP_IX, 2, 0x64, 6, 6, CLR_N_CHG_ZVC, cpu6811 }, + { "lsr", OP_IY | OP_PAGE2, 3, 0x64, 7, 7, CLR_V_CHG_ZVC, cpu6811 }, + { "lsr", OP_IDX, 2, 0x64, 3, 3, CLR_N_CHG_ZVC, cpu6812 }, + { "lsr", OP_IDX_1, 3, 0x64, 4, 4, CLR_N_CHG_ZVC, cpu6812 }, + { "lsr", OP_IDX_2, 4, 0x64, 5, 5, CLR_N_CHG_ZVC, cpu6812 }, + { "lsr", OP_D_IDX, 2, 0x64, 6, 6, CLR_N_CHG_ZVC, cpu6812 }, + { "lsr", OP_D_IDX_2, 4, 0x64, 6, 6, CLR_N_CHG_ZVC, cpu6812 }, + + { "lsra", OP_NONE, 1, 0x44, 1, 1, CLR_N_CHG_ZVC, cpu6811|cpu6812}, + { "lsrb", OP_NONE, 1, 0x54, 1, 1, CLR_N_CHG_ZVC, cpu6811|cpu6812}, + { "lsrd", OP_NONE, 1, 0x04, 3, 3, CLR_N_CHG_ZVC, cpu6811 }, + { "lsrd", OP_NONE, 1, 0x49, 1, 1, CLR_N_CHG_ZVC, cpu6812 }, + + { "maxa", OP_IDX | OP_PAGE2, 3, 0x18, 4, 4, CHG_NZVC, cpu6812 }, + { "maxa", OP_IDX_1 | OP_PAGE2, 4, 0x18, 4, 4, CHG_NZVC, cpu6812 }, + { "maxa", OP_IDX_2 | OP_PAGE2, 5, 0x18, 5, 5, CHG_NZVC, cpu6812 }, + { "maxa", OP_D_IDX | OP_PAGE2, 3, 0x18, 7, 7, CHG_NZVC, cpu6812 }, + { "maxa", OP_D_IDX_2 | OP_PAGE2, 5, 0x18, 7, 7, CHG_NZVC, cpu6812 }, + + { "maxm", OP_IDX | OP_PAGE2, 3, 0x1c, 4, 4, CHG_NZVC, cpu6812 }, + { "maxm", OP_IDX_1 | OP_PAGE2, 4, 0x1c, 5, 5, CHG_NZVC, cpu6812 }, + { "maxm", OP_IDX_2 | OP_PAGE2, 5, 0x1c, 6, 6, CHG_NZVC, cpu6812 }, + { "maxm", OP_D_IDX | OP_PAGE2, 3, 0x1c, 7, 7, CHG_NZVC, cpu6812 }, + { "maxm", OP_D_IDX_2 | OP_PAGE2, 5, 0x1c, 7, 7, CHG_NZVC, cpu6812 }, + + { "mem", OP_NONE, 1, 0x01, 5, 5, CHG_HNZVC, cpu6812 }, + + { "mina", OP_IDX | OP_PAGE2, 3, 0x19, 4, 4, CHG_NZVC, cpu6812 }, + { "mina", OP_IDX_1 | OP_PAGE2, 4, 0x19, 4, 4, CHG_NZVC, cpu6812 }, + { "mina", OP_IDX_2 | OP_PAGE2, 5, 0x19, 5, 5, CHG_NZVC, cpu6812 }, + { "mina", OP_D_IDX | OP_PAGE2, 3, 0x19, 7, 7, CHG_NZVC, cpu6812 }, + { "mina", OP_D_IDX_2 | OP_PAGE2, 5, 0x19, 7, 7, CHG_NZVC, cpu6812 }, + + { "minm", OP_IDX | OP_PAGE2, 3, 0x1d, 4, 4, CHG_NZVC, cpu6812 }, + { "minm", OP_IDX_1 | OP_PAGE2, 4, 0x1d, 5, 5, CHG_NZVC, cpu6812 }, + { "minm", OP_IDX_2 | OP_PAGE2, 5, 0x1d, 6, 6, CHG_NZVC, cpu6812 }, + { "minm", OP_D_IDX | OP_PAGE2, 3, 0x1d, 7, 7, CHG_NZVC, cpu6812 }, + { "minm", OP_D_IDX_2 | OP_PAGE2, 5, 0x1d, 7, 7, CHG_NZVC, cpu6812 }, + + { "movb", OP_IMM8|OP_IND16_p2|OP_PAGE2, 5, 0x0b, 4, 4, CHG_NONE, cpu6812 }, + { "movb", OP_IMM8|OP_IDX_p2|OP_PAGE2, 4, 0x08, 4, 4, CHG_NONE, cpu6812 }, + { "movb", OP_IND16|OP_IND16_p2|OP_PAGE2, 6, 0x0c, 6, 6, CHG_NONE, cpu6812 }, + { "movb", OP_IND16 | OP_IDX_p2 | OP_PAGE2, 5, 0x09, 5, 5, CHG_NONE, cpu6812 }, + { "movb", OP_IDX | OP_IND16_p2 | OP_PAGE2, 5, 0x0d, 5, 5, CHG_NONE, cpu6812 }, + { "movb", OP_IDX | OP_IDX_p2 | OP_PAGE2, 4, 0x0a, 5, 5, CHG_NONE, cpu6812 }, + + { "movw", OP_IMM16 | OP_IND16_p2 | OP_PAGE2, 6, 0x03, 5, 5, CHG_NONE, cpu6812 }, + { "movw", OP_IMM16 | OP_IDX_p2 | OP_PAGE2, 5, 0x00, 4, 4, CHG_NONE, cpu6812 }, + { "movw", OP_IND16 | OP_IND16_p2 | OP_PAGE2, 6, 0x04, 6, 6, CHG_NONE, cpu6812 }, + { "movw", OP_IND16 | OP_IDX_p2 | OP_PAGE2, 5, 0x01, 5, 5, CHG_NONE, cpu6812 }, + { "movw", OP_IDX | OP_IND16_p2 | OP_PAGE2, 5, 0x05, 5, 5, CHG_NONE, cpu6812 }, + { "movw", OP_IDX | OP_IDX_p2 | OP_PAGE2, 4, 0x02, 5, 5, CHG_NONE, cpu6812 }, + + { "mul", OP_NONE, 1, 0x3d, 3, 10, CHG_C, cpu6811 }, + { "mul", OP_NONE, 1, 0x12, 3, 3, CHG_C, cpu6812 }, + + { "neg", OP_IND16, 3, 0x70, 4, 4, CHG_NZVC, cpu6811|cpu6812 }, + { "neg", OP_IX, 2, 0x60, 6, 6, CHG_NZVC, cpu6811 }, + { "neg", OP_IY | OP_PAGE2, 3, 0x60, 7, 7, CHG_NZVC, cpu6811 }, + { "neg", OP_IDX, 2, 0x60, 3, 3, CHG_NZVC, cpu6812 }, + { "neg", OP_IDX_1, 3, 0x60, 4, 4, CHG_NZVC, cpu6812 }, + { "neg", OP_IDX_2, 4, 0x60, 5, 5, CHG_NZVC, cpu6812 }, + { "neg", OP_D_IDX, 2, 0x60, 6, 6, CHG_NZVC, cpu6812 }, + { "neg", OP_D_IDX_2, 4, 0x60, 6, 6, CHG_NZVC, cpu6812 }, + + { "nega", OP_NONE, 1, 0x40, 1, 1, CHG_NZVC, cpu6811|cpu6812 }, + { "negb", OP_NONE, 1, 0x50, 1, 1, CHG_NZVC, cpu6811|cpu6812 }, + { "nop", OP_NONE, 1, 0x01, 2, 2, CHG_NONE, cpu6811 }, + { "nop", OP_NONE, 1, 0xa7, 1, 1, CHG_NONE, cpu6812 }, + + { "oraa", OP_IMM8, 2, 0x8a, 1, 1, CLR_V_CHG_NZ, cpu6811|cpu6812 }, + { "oraa", OP_DIRECT, 2, 0x9a, 3, 3, CLR_V_CHG_NZ, cpu6811|cpu6812 }, + { "oraa", OP_IND16, 3, 0xba, 3, 3, CLR_V_CHG_NZ, cpu6811|cpu6812 }, + { "oraa", OP_IX, 2, 0xaa, 4, 4, CLR_V_CHG_NZ, cpu6811 }, + { "oraa", OP_IY | OP_PAGE2, 3, 0xaa, 5, 5, CLR_V_CHG_NZ, cpu6811 }, + { "oraa", OP_IDX, 2, 0xaa, 3, 3, CLR_V_CHG_NZ, cpu6812 }, + { "oraa", OP_IDX_1, 3, 0xaa, 3, 3, CLR_V_CHG_NZ, cpu6812 }, + { "oraa", OP_IDX_2, 4, 0xaa, 4, 4, CLR_V_CHG_NZ, cpu6812 }, + { "oraa", OP_D_IDX, 2, 0xaa, 6, 6, CLR_V_CHG_NZ, cpu6812 }, + { "oraa", OP_D_IDX_2, 4, 0xaa, 6, 6, CLR_V_CHG_NZ, cpu6812 }, + + { "orab", OP_IMM8, 2, 0xca, 1, 1, CLR_V_CHG_NZ, cpu6811|cpu6812 }, + { "orab", OP_DIRECT, 2, 0xda, 3, 3, CLR_V_CHG_NZ, cpu6811|cpu6812 }, + { "orab", OP_IND16, 3, 0xfa, 3, 3, CLR_V_CHG_NZ, cpu6811|cpu6812 }, + { "orab", OP_IX, 2, 0xea, 4, 4, CLR_V_CHG_NZ, cpu6811 }, + { "orab", OP_IY | OP_PAGE2, 3, 0xea, 5, 5, CLR_V_CHG_NZ, cpu6811 }, + { "orab", OP_IDX, 2, 0xea, 3, 3, CLR_V_CHG_NZ, cpu6812 }, + { "orab", OP_IDX_1, 3, 0xea, 3, 3, CLR_V_CHG_NZ, cpu6812 }, + { "orab", OP_IDX_2, 4, 0xea, 4, 4, CLR_V_CHG_NZ, cpu6812 }, + { "orab", OP_D_IDX, 2, 0xea, 6, 6, CLR_V_CHG_NZ, cpu6812 }, + { "orab", OP_D_IDX_2, 4, 0xea, 6, 6, CLR_V_CHG_NZ, cpu6812 }, + + { "orcc", OP_IMM8, 2, 0x14, 1, 1, CHG_ALL, cpu6812 }, + + { "psha", OP_NONE, 1, 0x36, 2, 2, CHG_NONE, cpu6811|cpu6812 }, + { "pshb", OP_NONE, 1, 0x37, 2, 2, CHG_NONE, cpu6811|cpu6812 }, + { "pshc", OP_NONE, 1, 0x39, 2, 2, CHG_NONE, cpu6812 }, + { "pshd", OP_NONE, 1, 0x3b, 2, 2, CHG_NONE, cpu6812 }, + { "pshx", OP_NONE, 1, 0x3c, 4, 4, CHG_NONE, cpu6811 }, + { "pshx", OP_NONE, 1, 0x34, 2, 2, CHG_NONE, cpu6812 }, + { "pshy", OP_NONE | OP_PAGE2,2, 0x3c, 5, 5, CHG_NONE, cpu6811 }, + { "pshy", OP_NONE, 1, 0x35, 2, 2, CHG_NONE, cpu6812 }, + + { "pula", OP_NONE, 1, 0x32, 3, 3, CHG_NONE, cpu6811|cpu6812 }, + { "pulb", OP_NONE, 1, 0x33, 3, 3, CHG_NONE, cpu6811|cpu6812 }, + { "pulc", OP_NONE, 1, 0x38, 3, 3, CHG_NONE, cpu6812 }, + { "puld", OP_NONE, 1, 0x3a, 3, 3, CHG_NONE, cpu6812 }, + { "pulx", OP_NONE, 1, 0x38, 5, 5, CHG_NONE, cpu6811 }, + { "pulx", OP_NONE, 1, 0x30, 3, 3, CHG_NONE, cpu6812 }, + { "puly", OP_NONE | OP_PAGE2,2, 0x38, 6, 6, CHG_NONE, cpu6811 }, + { "puly", OP_NONE, 1, 0x31, 3, 3, CHG_NONE, cpu6812 }, + + { "rev", OP_NONE | OP_PAGE2, 2, 0x3a, _M, _M, CHG_HNZVC, cpu6812 }, + { "revw", OP_NONE | OP_PAGE2, 2, 0x3b, _M, _M, CHG_HNZVC, cpu6812 }, + + { "rol", OP_IND16, 3, 0x79, 6, 6, CHG_NZVC, cpu6811 }, + { "rol", OP_IX, 2, 0x69, 6, 6, CHG_NZVC, cpu6811 }, + { "rol", OP_IY | OP_PAGE2, 3, 0x69, 7, 7, CHG_NZVC, cpu6811 }, + { "rol", OP_IND16, 3, 0x75, 4, 4, CHG_NZVC, cpu6812 }, + { "rol", OP_IDX, 2, 0x65, 3, 3, CHG_NZVC, cpu6812 }, + { "rol", OP_IDX_1, 3, 0x65, 4, 4, CHG_NZVC, cpu6812 }, + { "rol", OP_IDX_2, 4, 0x65, 5, 5, CHG_NZVC, cpu6812 }, + { "rol", OP_D_IDX, 2, 0x65, 6, 6, CHG_NZVC, cpu6812 }, + { "rol", OP_D_IDX_2, 4, 0x65, 6, 6, CHG_NZVC, cpu6812 }, + + { "rola", OP_NONE, 1, 0x49, 2, 2, CHG_NZVC, cpu6811 }, + { "rola", OP_NONE, 1, 0x45, 1, 1, CHG_NZVC, cpu6812 }, + { "rolb", OP_NONE, 1, 0x59, 2, 2, CHG_NZVC, cpu6811 }, + { "rolb", OP_NONE, 1, 0x55, 1, 1, CHG_NZVC, cpu6812 }, + + { "ror", OP_IND16, 3, 0x76, 4, 4, CHG_NZVC, cpu6811|cpu6812 }, + { "ror", OP_IX, 2, 0x66, 6, 6, CHG_NZVC, cpu6811 }, + { "ror", OP_IY | OP_PAGE2, 3, 0x66, 7, 7, CHG_NZVC, cpu6811 }, + { "ror", OP_IDX, 2, 0x66, 3, 3, CHG_NZVC, cpu6812 }, + { "ror", OP_IDX_1, 3, 0x66, 4, 4, CHG_NZVC, cpu6812 }, + { "ror", OP_IDX_2, 4, 0x66, 5, 5, CHG_NZVC, cpu6812 }, + { "ror", OP_D_IDX, 2, 0x66, 6, 6, CHG_NZVC, cpu6812 }, + { "ror", OP_D_IDX_2, 4, 0x66, 6, 6, CHG_NZVC, cpu6812 }, + + { "rora", OP_NONE, 1, 0x46, 1, 1, CHG_NZVC, cpu6811|cpu6812 }, + { "rorb", OP_NONE, 1, 0x56, 1, 1, CHG_NZVC, cpu6811|cpu6812 }, + + { "rtc", OP_NONE, 1, 0x0a, 6, 6, CHG_NONE, cpu6812 }, + { "rti", OP_NONE, 1, 0x3b, 12, 12, CHG_ALL, cpu6811}, + { "rti", OP_NONE, 1, 0x0b, 8, 10, CHG_ALL, cpu6812}, + { "rts", OP_NONE, 1, 0x39, 5, 5, CHG_NONE, cpu6811 }, + { "rts", OP_NONE, 1, 0x3d, 5, 5, CHG_NONE, cpu6812 }, + + { "sba", OP_NONE, 1, 0x10, 2, 2, CHG_NZVC, cpu6811 }, + { "sba", OP_NONE | OP_PAGE2, 2, 0x16, 2, 2, CHG_NZVC, cpu6812 }, + + { "sbca", OP_IMM8, 2, 0x82, 1, 1, CHG_NZVC, cpu6811|cpu6812 }, + { "sbca", OP_DIRECT, 2, 0x92, 3, 3, CHG_NZVC, cpu6811|cpu6812 }, + { "sbca", OP_IND16, 3, 0xb2, 3, 3, CHG_NZVC, cpu6811|cpu6812 }, + { "sbca", OP_IX, 2, 0xa2, 4, 4, CHG_NZVC, cpu6811 }, + { "sbca", OP_IY | OP_PAGE2, 3, 0xa2, 5, 5, CHG_NZVC, cpu6811 }, + { "sbca", OP_IDX, 2, 0xa2, 3, 3, CHG_NZVC, cpu6812 }, + { "sbca", OP_IDX_1, 3, 0xa2, 3, 3, CHG_NZVC, cpu6812 }, + { "sbca", OP_IDX_2, 4, 0xa2, 4, 4, CHG_NZVC, cpu6812 }, + { "sbca", OP_D_IDX, 2, 0xa2, 6, 6, CHG_NZVC, cpu6812 }, + { "sbca", OP_D_IDX_2, 4, 0xa2, 6, 6, CHG_NZVC, cpu6812 }, + + { "sbcb", OP_IMM8, 2, 0xc2, 1, 1, CHG_NZVC, cpu6811|cpu6812 }, + { "sbcb", OP_DIRECT, 2, 0xd2, 3, 3, CHG_NZVC, cpu6811|cpu6812 }, + { "sbcb", OP_IND16, 3, 0xf2, 3, 3, CHG_NZVC, cpu6811|cpu6812 }, + { "sbcb", OP_IX, 2, 0xe2, 4, 4, CHG_NZVC, cpu6811 }, + { "sbcb", OP_IY | OP_PAGE2, 3, 0xe2, 5, 5, CHG_NZVC, cpu6811 }, + { "sbcb", OP_IDX, 2, 0xe2, 3, 3, CHG_NZVC, cpu6812 }, + { "sbcb", OP_IDX_1, 3, 0xe2, 3, 3, CHG_NZVC, cpu6812 }, + { "sbcb", OP_IDX_2, 4, 0xe2, 4, 4, CHG_NZVC, cpu6812 }, + { "sbcb", OP_D_IDX, 2, 0xe2, 6, 6, CHG_NZVC, cpu6812 }, + { "sbcb", OP_D_IDX_2, 4, 0xe2, 6, 6, CHG_NZVC, cpu6812 }, + + { "sec", OP_NONE, 1, 0x0d, 2, 2, SET_C, cpu6811 }, + { "sei", OP_NONE, 1, 0x0f, 2, 2, SET_I, cpu6811 }, + { "sev", OP_NONE, 1, 0x0b, 2, 2, SET_V, cpu6811 }, + + { "sex", M6812_OP_SEX_MARKER + | OP_REG | OP_REG_2, 2, 0xb7, 1, 1, CHG_NONE, cpu6812 }, + + { "staa", OP_IND16, 3, 0xb7, 4, 4, CLR_V_CHG_NZ, cpu6811 }, + { "staa", OP_DIRECT, 2, 0x97, 3, 3, CLR_V_CHG_NZ, cpu6811 }, + { "staa", OP_IX, 2, 0xa7, 4, 4, CLR_V_CHG_NZ, cpu6811 }, + { "staa", OP_IY | OP_PAGE2, 3, 0xa7, 5, 5, CLR_V_CHG_NZ, cpu6811 }, + { "staa", OP_DIRECT, 2, 0x5a, 2, 2, CLR_V_CHG_NZ, cpu6812 }, + { "staa", OP_IND16, 3, 0x7a, 3, 3, CLR_V_CHG_NZ, cpu6812 }, + { "staa", OP_IDX, 2, 0x6a, 2, 2, CLR_V_CHG_NZ, cpu6812 }, + { "staa", OP_IDX_1, 3, 0x6a, 3, 3, CLR_V_CHG_NZ, cpu6812 }, + { "staa", OP_IDX_2, 4, 0x6a, 3, 3, CLR_V_CHG_NZ, cpu6812 }, + { "staa", OP_D_IDX, 2, 0x6a, 5, 5, CLR_V_CHG_NZ, cpu6812 }, + { "staa", OP_D_IDX_2, 4, 0x6a, 5, 5, CLR_V_CHG_NZ, cpu6812 }, + + { "stab", OP_IND16, 3, 0xf7, 4, 4, CLR_V_CHG_NZ, cpu6811 }, + { "stab", OP_DIRECT, 2, 0xd7, 3, 3, CLR_V_CHG_NZ, cpu6811 }, + { "stab", OP_IX, 2, 0xe7, 4, 4, CLR_V_CHG_NZ, cpu6811 }, + { "stab", OP_IY | OP_PAGE2, 3, 0xe7, 5, 5, CLR_V_CHG_NZ, cpu6811 }, + { "stab", OP_DIRECT, 2, 0x5b, 2, 2, CLR_V_CHG_NZ, cpu6812 }, + { "stab", OP_IND16, 3, 0x7b, 3, 3, CLR_V_CHG_NZ, cpu6812 }, + { "stab", OP_IDX, 2, 0x6b, 2, 2, CLR_V_CHG_NZ, cpu6812 }, + { "stab", OP_IDX_1, 3, 0x6b, 3, 3, CLR_V_CHG_NZ, cpu6812 }, + { "stab", OP_IDX_2, 4, 0x6b, 3, 3, CLR_V_CHG_NZ, cpu6812 }, + { "stab", OP_D_IDX, 2, 0x6b, 5, 5, CLR_V_CHG_NZ, cpu6812 }, + { "stab", OP_D_IDX_2, 4, 0x6b, 5, 5, CLR_V_CHG_NZ, cpu6812 }, + + { "std", OP_IND16, 3, 0xfd, 5, 5, CLR_V_CHG_NZ, cpu6811 }, + { "std", OP_DIRECT, 2, 0xdd, 4, 4, CLR_V_CHG_NZ, cpu6811 }, + { "std", OP_IX, 2, 0xed, 5, 5, CLR_V_CHG_NZ, cpu6811 }, + { "std", OP_IY | OP_PAGE2, 3, 0xed, 6, 6, CLR_V_CHG_NZ, cpu6811 }, + { "std", OP_DIRECT, 2, 0x5c, 2, 2, CLR_V_CHG_NZ, cpu6812 }, + { "std", OP_IND16, 3, 0x7c, 3, 3, CLR_V_CHG_NZ, cpu6812 }, + { "std", OP_IDX, 2, 0x6c, 2, 2, CLR_V_CHG_NZ, cpu6812 }, + { "std", OP_IDX_1, 3, 0x6c, 3, 3, CLR_V_CHG_NZ, cpu6812 }, + { "std", OP_IDX_2, 4, 0x6c, 3, 3, CLR_V_CHG_NZ, cpu6812 }, + { "std", OP_D_IDX, 2, 0x6c, 5, 5, CLR_V_CHG_NZ, cpu6812 }, + { "std", OP_D_IDX_2, 4, 0x6c, 5, 5, CLR_V_CHG_NZ, cpu6812 }, + + { "stop", OP_NONE, 1, 0xcf, 2, 2, CHG_NONE, cpu6811 }, + { "stop", OP_NONE | OP_PAGE2,2, 0x3e, 2, 9, CHG_NONE, cpu6812 }, + + { "sts", OP_IND16, 3, 0xbf, 5, 5, CLR_V_CHG_NZ, cpu6811 }, + { "sts", OP_DIRECT, 2, 0x9f, 4, 4, CLR_V_CHG_NZ, cpu6811 }, + { "sts", OP_IX, 2, 0xaf, 5, 5, CLR_V_CHG_NZ, cpu6811 }, + { "sts", OP_IY | OP_PAGE2, 3, 0xaf, 6, 6, CLR_V_CHG_NZ, cpu6811 }, + { "sts", OP_DIRECT, 2, 0x5f, 2, 2, CLR_V_CHG_NZ, cpu6812 }, + { "sts", OP_IND16, 3, 0x7f, 3, 3, CLR_V_CHG_NZ, cpu6812 }, + { "sts", OP_IDX, 2, 0x6f, 2, 2, CLR_V_CHG_NZ, cpu6812 }, + { "sts", OP_IDX_1, 3, 0x6f, 3, 3, CLR_V_CHG_NZ, cpu6812 }, + { "sts", OP_IDX_2, 4, 0x6f, 3, 3, CLR_V_CHG_NZ, cpu6812 }, + { "sts", OP_D_IDX, 2, 0x6f, 5, 5, CLR_V_CHG_NZ, cpu6812 }, + { "sts", OP_D_IDX_2, 4, 0x6f, 5, 5, CLR_V_CHG_NZ, cpu6812 }, + + { "stx", OP_IND16, 3, 0xff, 5, 5, CLR_V_CHG_NZ, cpu6811 }, + { "stx", OP_DIRECT, 2, 0xdf, 4, 4, CLR_V_CHG_NZ, cpu6811 }, + { "stx", OP_IX, 2, 0xef, 5, 5, CLR_V_CHG_NZ, cpu6811 }, + { "stx", OP_IY | OP_PAGE4, 3, 0xef, 6, 6, CLR_V_CHG_NZ, cpu6811 }, + { "stx", OP_DIRECT, 2, 0x5e, 2, 2, CLR_V_CHG_NZ, cpu6812 }, + { "stx", OP_IND16, 3, 0x7e, 3, 3, CLR_V_CHG_NZ, cpu6812 }, + { "stx", OP_IDX, 2, 0x6e, 2, 2, CLR_V_CHG_NZ, cpu6812 }, + { "stx", OP_IDX_1, 3, 0x6e, 3, 3, CLR_V_CHG_NZ, cpu6812 }, + { "stx", OP_IDX_2, 4, 0x6e, 3, 3, CLR_V_CHG_NZ, cpu6812 }, + { "stx", OP_D_IDX, 2, 0x6e, 5, 5, CLR_V_CHG_NZ, cpu6812 }, + { "stx", OP_D_IDX_2, 4, 0x6e, 5, 5, CLR_V_CHG_NZ, cpu6812 }, + + { "sty", OP_IND16 | OP_PAGE2, 4, 0xff, 6, 6, CLR_V_CHG_NZ, cpu6811 }, + { "sty", OP_DIRECT | OP_PAGE2, 3, 0xdf, 5, 5, CLR_V_CHG_NZ, cpu6811 }, + { "sty", OP_IY | OP_PAGE2, 3, 0xef, 6, 6, CLR_V_CHG_NZ, cpu6811 }, + { "sty", OP_IX | OP_PAGE3, 3, 0xef, 6, 6, CLR_V_CHG_NZ, cpu6811 }, + { "sty", OP_DIRECT, 2, 0x5d, 2, 2, CLR_V_CHG_NZ, cpu6812 }, + { "sty", OP_IND16, 3, 0x7d, 3, 3, CLR_V_CHG_NZ, cpu6812 }, + { "sty", OP_IDX, 2, 0x6d, 2, 2, CLR_V_CHG_NZ, cpu6812 }, + { "sty", OP_IDX_1, 3, 0x6d, 3, 3, CLR_V_CHG_NZ, cpu6812 }, + { "sty", OP_IDX_2, 4, 0x6d, 3, 3, CLR_V_CHG_NZ, cpu6812 }, + { "sty", OP_D_IDX, 2, 0x6d, 5, 5, CLR_V_CHG_NZ, cpu6812 }, + { "sty", OP_D_IDX_2, 4, 0x6d, 5, 5, CLR_V_CHG_NZ, cpu6812 }, + + { "suba", OP_IMM8, 2, 0x80, 1, 1, CHG_NZVC, cpu6811|cpu6812 }, + { "suba", OP_DIRECT, 2, 0x90, 3, 3, CHG_NZVC, cpu6811|cpu6812 }, + { "suba", OP_IND16, 3, 0xb0, 3, 3, CHG_NZVC, cpu6811|cpu6812 }, + { "suba", OP_IX, 2, 0xa0, 4, 4, CHG_NZVC, cpu6811 }, + { "suba", OP_IY | OP_PAGE2, 3, 0xa0, 5, 5, CHG_NZVC, cpu6811 }, + { "suba", OP_IDX, 2, 0xa0, 3, 3, CHG_NZVC, cpu6812 }, + { "suba", OP_IDX_1, 3, 0xa0, 3, 3, CHG_NZVC, cpu6812 }, + { "suba", OP_IDX_2, 4, 0xa0, 4, 4, CHG_NZVC, cpu6812 }, + { "suba", OP_D_IDX, 2, 0xa0, 6, 6, CHG_NZVC, cpu6812 }, + { "suba", OP_D_IDX_2, 4, 0xa0, 6, 6, CHG_NZVC, cpu6812 }, + + { "subb", OP_IMM8, 2, 0xc0, 1, 1, CHG_NZVC, cpu6811|cpu6812 }, + { "subb", OP_DIRECT, 2, 0xd0, 3, 3, CHG_NZVC, cpu6811|cpu6812 }, + { "subb", OP_IND16, 3, 0xf0, 3, 3, CHG_NZVC, cpu6811|cpu6812 }, + { "subb", OP_IX, 2, 0xe0, 4, 4, CHG_NZVC, cpu6811 }, + { "subb", OP_IY | OP_PAGE2, 3, 0xe0, 5, 5, CHG_NZVC, cpu6811 }, + { "subb", OP_IDX, 2, 0xe0, 3, 3, CHG_NZVC, cpu6812 }, + { "subb", OP_IDX_1, 3, 0xe0, 3, 3, CHG_NZVC, cpu6812 }, + { "subb", OP_IDX_2, 4, 0xe0, 4, 4, CHG_NZVC, cpu6812 }, + { "subb", OP_D_IDX, 2, 0xe0, 6, 6, CHG_NZVC, cpu6812 }, + { "subb", OP_D_IDX_2, 4, 0xe0, 6, 6, CHG_NZVC, cpu6812 }, + + { "subd", OP_IMM16, 3, 0x83, 2, 2, CHG_NZVC, cpu6811|cpu6812 }, + { "subd", OP_DIRECT, 2, 0x93, 3, 3, CHG_NZVC, cpu6811|cpu6812 }, + { "subd", OP_IND16, 3, 0xb3, 3, 3, CHG_NZVC, cpu6811|cpu6812 }, + { "subd", OP_IX, 2, 0xa3, 6, 6, CHG_NZVC, cpu6811 }, + { "subd", OP_IY | OP_PAGE2, 3, 0xa3, 7, 7, CHG_NZVC, cpu6811 }, + { "subd", OP_IDX, 2, 0xa3, 3, 3, CHG_NZVC, cpu6812 }, + { "subd", OP_IDX_1, 3, 0xa3, 3, 3, CHG_NZVC, cpu6812 }, + { "subd", OP_IDX_2, 4, 0xa3, 4, 4, CHG_NZVC, cpu6812 }, + { "subd", OP_D_IDX, 2, 0xa3, 6, 6, CHG_NZVC, cpu6812 }, + { "subd", OP_D_IDX_2, 4, 0xa3, 6, 6, CHG_NZVC, cpu6812 }, + + { "swi", OP_NONE, 1, 0x3f, 9, 9, CHG_NONE, cpu6811|cpu6812 }, + + { "tab", OP_NONE, 1, 0x16, 2, 2, CLR_V_CHG_NZ, cpu6811 }, + { "tab", OP_NONE | OP_PAGE2,2, 0x0e, 2, 2, CLR_V_CHG_NZ, cpu6812 }, + + { "tap", OP_NONE, 1, 0x06, 2, 2, CHG_ALL, cpu6811 }, + + { "tba", OP_NONE, 1, 0x17, 2, 2, CLR_V_CHG_NZ, cpu6811 }, + { "tba", OP_NONE | OP_PAGE2,2, 0x0f, 2, 2, CLR_V_CHG_NZ, cpu6812 }, + + { "test", OP_NONE, 1, 0x00, 5, _M, CHG_NONE, cpu6811 }, + + { "tpa", OP_NONE, 1, 0x07, 2, 2, CHG_NONE, cpu6811 }, + + { "tbeq", OP_TBEQ_MARKER + | OP_REG | OP_JUMP_REL, 3, 0x04, 3, 3, CHG_NONE, cpu6812 }, + + { "tbl", OP_IDX | OP_PAGE2, 3, 0x3d, 8, 8, CHG_NZC, cpu6812 }, + + { "tbne", OP_TBNE_MARKER + | OP_REG | OP_JUMP_REL, 3, 0x04, 3, 3, CHG_NONE, cpu6812 }, + + { "tfr", OP_TFR_MARKER + | OP_REG_1 | OP_REG_2, 2, 0xb7, 1, 1, CHG_NONE, cpu6812 }, + + { "trap", OP_IMM8 | OP_TRAP_ID, 2, 0x18, 11, 11, SET_I, cpu6812 }, + + { "tst", OP_IND16, 3, 0x7d, 6, 6, CLR_VC_CHG_NZ, cpu6811 }, + { "tst", OP_IX, 2, 0x6d, 6, 6, CLR_VC_CHG_NZ, cpu6811 }, + { "tst", OP_IY | OP_PAGE2, 3, 0x6d, 7, 7, CLR_VC_CHG_NZ, cpu6811 }, + { "tst", OP_IND16, 3, 0xf7, 3, 3, CLR_VC_CHG_NZ, cpu6812 }, + { "tst", OP_IDX, 2, 0xe7, 3, 3, CLR_VC_CHG_NZ, cpu6812 }, + { "tst", OP_IDX_1, 3, 0xe7, 3, 3, CLR_VC_CHG_NZ, cpu6812 }, + { "tst", OP_IDX_2, 4, 0xe7, 4, 4, CLR_VC_CHG_NZ, cpu6812 }, + { "tst", OP_D_IDX, 2, 0xe7, 6, 6, CLR_VC_CHG_NZ, cpu6812 }, + { "tst", OP_D_IDX_2, 4, 0xe7, 6, 6, CLR_VC_CHG_NZ, cpu6812 }, + + { "tsta", OP_NONE, 1, 0x4d, 2, 2, CLR_VC_CHG_NZ, cpu6811 }, + { "tsta", OP_NONE, 1, 0x97, 1, 1, CLR_VC_CHG_NZ, cpu6812 }, + { "tstb", OP_NONE, 1, 0x5d, 2, 2, CLR_VC_CHG_NZ, cpu6811 }, + { "tstb", OP_NONE, 1, 0xd7, 1, 1, CLR_VC_CHG_NZ, cpu6812 }, + + { "tsx", OP_NONE, 1, 0x30, 3, 3, CHG_NONE, cpu6811 }, + { "tsy", OP_NONE | OP_PAGE2,2, 0x30, 4, 4, CHG_NONE, cpu6811 }, + { "txs", OP_NONE, 1, 0x35, 3, 3, CHG_NONE, cpu6811 }, + { "tys", OP_NONE | OP_PAGE2,2, 0x35, 4, 4, CHG_NONE, cpu6811 }, + + { "wai", OP_NONE, 1, 0x3e, 5, _M, CHG_NONE, cpu6811|cpu6812 }, + + { "wav", OP_NONE | OP_PAGE2, 2, 0x3c, 8, _M, SET_Z_CHG_HNVC, cpu6812 }, + + { "xgdx", OP_NONE, 1, 0x8f, 3, 3, CHG_NONE, cpu6811 }, + { "xgdy", OP_NONE | OP_PAGE2,2, 0x8f, 4, 4, CHG_NONE, cpu6811 } +}; + +const int m68hc11_num_opcodes = TABLE_SIZE (m68hc11_opcodes); + +/* The following alias table provides source compatibility to + move from 68HC11 assembly to 68HC12. */ +const struct m68hc12_opcode_alias m68hc12_alias[] = { + { "abx", "leax b,x", 2, 0x1a, 0xe5 }, + { "aby", "leay b,y", 2, 0x19, 0xed }, + { "clc", "andcc #$fe", 2, 0x10, 0xfe }, + { "cli", "andcc #$ef", 2, 0x10, 0xef }, + { "clv", "andcc #$fd", 2, 0x10, 0xfd }, + { "des", "leas -1,sp", 2, 0x1b, 0x9f }, + { "ins", "leas 1,sp", 2, 0x1b, 0x81 }, + { "sec", "orcc #$01", 2, 0x14, 0x01 }, + { "sei", "orcc #$10", 2, 0x14, 0x10 }, + { "sev", "orcc #$02", 2, 0x14, 0x02 }, + { "tap", "tfr a,ccr", 2, 0xb7, 0x02 }, + { "tpa", "tfr ccr,a", 2, 0xb7, 0x20 }, + { "tsx", "tfr sp,x", 2, 0xb7, 0x75 }, + { "tsy", "tfr sp,y", 2, 0xb7, 0x76 }, + { "txs", "tfr x,sp", 2, 0xb7, 0x57 }, + { "tys", "tfr y,sp", 2, 0xb7, 0x67 }, + { "xgdx","exg d,x", 2, 0xb7, 0xc5 }, + { "xgdy","exg d,y", 2, 0xb7, 0xc6 } +}; +const int m68hc12_num_alias = TABLE_SIZE (m68hc12_alias); diff --git a/opcodes/po/POTFILES.in b/opcodes/po/POTFILES.in index 361d98bae3e..d384c75d2d9 100644 --- a/opcodes/po/POTFILES.in +++ b/opcodes/po/POTFILES.in @@ -54,6 +54,8 @@ m32r-ibld.c m32r-opc.c m32r-opc.h m32r-opinst.c +m68hc11-dis.c +m68hc11-opc.c m68k-dis.c m68k-opc.c m88k-dis.c diff --git a/opcodes/po/opcodes.pot b/opcodes/po/opcodes.pot index 8bc5cee43a8..a65c70aa751 100644 --- a/opcodes/po/opcodes.pot +++ b/opcodes/po/opcodes.pot @@ -6,7 +6,7 @@ msgid "" msgstr "" "Project-Id-Version: PACKAGE VERSION\n" -"POT-Creation-Date: 2000-05-30 11:33-0700\n" +"POT-Creation-Date: 2000-06-18 17:38-0700\n" "PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n" "Last-Translator: FULL NAME <EMAIL@ADDRESS>\n" "Language-Team: LANGUAGE <LL@li.org>\n" @@ -69,6 +69,19 @@ msgid "" "the -M switch:\n" msgstr "" +#: avr-dis.c:106 +msgid " unknown register " +msgstr "" + +#: avr-dis.c:168 +msgid "Internal disassembler error" +msgstr "" + +#: avr-dis.c:208 +#, c-format +msgid "unknown constraint `%c'" +msgstr "" + #: cgen-asm.c:224 msgid "unrecognized keyword/register name" msgstr "" @@ -171,12 +184,12 @@ msgstr "" msgid "Unrecognized field %d while setting vma operand.\n" msgstr "" -#: h8300-dis.c:405 +#: h8300-dis.c:382 #, c-format msgid "Hmmmm %x" msgstr "" -#: h8300-dis.c:417 +#: h8300-dis.c:393 #, c-format msgid "Don't understand %x \n" msgstr "" |