diff options
| -rw-r--r-- | sim/bfin/ChangeLog | 10 | ||||
| -rwxr-xr-x | sim/bfin/configure | 1 | ||||
| -rw-r--r-- | sim/bfin/configure.ac | 1 | ||||
| -rw-r--r-- | sim/bfin/dv-bfin_gpio2.c | 284 | ||||
| -rw-r--r-- | sim/bfin/dv-bfin_gpio2.h | 25 | ||||
| -rw-r--r-- | sim/bfin/machs.c | 31 | ||||
| -rw-r--r-- | sim/bfin/machs.h | 1 |
7 files changed, 352 insertions, 1 deletions
diff --git a/sim/bfin/ChangeLog b/sim/bfin/ChangeLog index 8134269e06c..75cbf6304be 100644 --- a/sim/bfin/ChangeLog +++ b/sim/bfin/ChangeLog @@ -1,3 +1,13 @@ +2012-04-09 Mike Frysinger <vapier@gentoo.org> + + * configure.ac (SIM_AC_OPTION_HARDWARE): Add bfin_gpio2. + * configure: Regenerate. + * dv-bfin_gpio2.c, dv-bfin_gpio2.h: New device model. + * machs.c (bf54x_mem): Delete GPIO mem stub. + (bf542_dev): Add GPIO register blocks. + (bf544_dev, bf547_dev): Likewise. + * machs.h (BFIN_MMR_GPIO2_SIZE): Define. + 2012-04-09 Robin Getz <robin.getz@analog.com> * bfin-sim.c (decode_dsp32shift_0): Extract the sign for ASHIFT diff --git a/sim/bfin/configure b/sim/bfin/configure index 473394b94fb..3aadc21b443 100755 --- a/sim/bfin/configure +++ b/sim/bfin/configure @@ -5369,6 +5369,7 @@ hardware="$hardware \ bfin_eppi \ bfin_evt \ bfin_gpio \ + bfin_gpio2 \ bfin_gptimer \ bfin_jtag \ bfin_mmu \ diff --git a/sim/bfin/configure.ac b/sim/bfin/configure.ac index cda3ac9ecde..5cae416d1ea 100644 --- a/sim/bfin/configure.ac +++ b/sim/bfin/configure.ac @@ -24,6 +24,7 @@ SIM_AC_OPTION_HARDWARE(yes,,\ bfin_eppi \ bfin_evt \ bfin_gpio \ + bfin_gpio2 \ bfin_gptimer \ bfin_jtag \ bfin_mmu \ diff --git a/sim/bfin/dv-bfin_gpio2.c b/sim/bfin/dv-bfin_gpio2.c new file mode 100644 index 00000000000..0e8787e51dc --- /dev/null +++ b/sim/bfin/dv-bfin_gpio2.c @@ -0,0 +1,284 @@ +/* Blackfin General Purpose Ports (GPIO) model + For "new style" GPIOs on BF54x parts. + + Copyright (C) 2010-2012 Free Software Foundation, Inc. + Contributed by Analog Devices, Inc. and Mike Frysinger. + + This file is part of simulators. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see <http://www.gnu.org/licenses/>. */ + +#include "config.h" + +#include "sim-main.h" +#include "devices.h" +#include "dv-bfin_gpio2.h" + +struct bfin_gpio +{ + bu32 base; + + /* Only accessed indirectly via dir_{set,clear}. */ + bu16 dir; + + /* Make sure hardware MMRs are aligned. */ + bu16 _pad; + + /* Order after here is important -- matches hardware MMR layout. */ + bu16 BFIN_MMR_16(fer); + bu16 BFIN_MMR_16(data); + bu16 BFIN_MMR_16(set); + bu16 BFIN_MMR_16(clear); + bu16 BFIN_MMR_16(dir_set); + bu16 BFIN_MMR_16(dir_clear); + bu16 BFIN_MMR_16(inen); + bu32 mux; +}; +#define mmr_base() offsetof(struct bfin_gpio, fer) +#define mmr_offset(mmr) (offsetof(struct bfin_gpio, mmr) - mmr_base()) + +static const char * const mmr_names[] = +{ + "PORTIO_FER", "PORTIO", "PORTIO_SET", "PORTIO_CLEAR", "PORTIO_DIR_SET", + "PORTIO_DIR_CLEAR", "PORTIO_INEN", "PORTIO_MUX", +}; +#define mmr_name(off) mmr_names[(off) / 4] + +static unsigned +bfin_gpio_io_write_buffer (struct hw *me, const void *source, int space, + address_word addr, unsigned nr_bytes) +{ + struct bfin_gpio *port = hw_data (me); + bu32 mmr_off; + bu32 value; + bu16 *value16p; + bu32 *value32p; + void *valuep; + + if (nr_bytes == 4) + value = dv_load_4 (source); + else + value = dv_load_2 (source); + mmr_off = addr - port->base; + valuep = (void *)((unsigned long)port + mmr_base() + mmr_off); + value16p = valuep; + value32p = valuep; + + HW_TRACE_WRITE (); + + if (mmr_off == mmr_offset (mux)) + dv_bfin_mmr_require_32 (me, addr, nr_bytes, true); + else + dv_bfin_mmr_require_16 (me, addr, nr_bytes, true); + + switch (mmr_off) + { + case mmr_offset(fer): + case mmr_offset(data): + case mmr_offset(inen): + *value16p = value; + break; + case mmr_offset(clear): + /* We want to clear the related data MMR. */ + dv_w1c_2 (&port->data, value, -1); + break; + case mmr_offset(set): + /* We want to set the related data MMR. */ + port->data |= value; + break; + case mmr_offset(dir_clear): + dv_w1c_2 (&port->dir, value, -1); + break; + case mmr_offset(dir_set): + port->dir |= value; + break; + case mmr_offset(mux): + *value32p = value; + break; + default: + dv_bfin_mmr_invalid (me, addr, nr_bytes, true); + break; + } + + /* If tweaking output pins, make sure we send updated port info. */ + switch (mmr_off) + { + case mmr_offset(data): + case mmr_offset(set): + case mmr_offset(clear): + case mmr_offset(dir_set): + { + int i; + bu32 bit; + + for (i = 0; i < 16; ++i) + { + bit = (1 << i); + + if (!(port->inen & bit)) + hw_port_event (me, i, !!(port->data & bit)); + } + + break; + } + } + + return nr_bytes; +} + +static unsigned +bfin_gpio_io_read_buffer (struct hw *me, void *dest, int space, + address_word addr, unsigned nr_bytes) +{ + struct bfin_gpio *port = hw_data (me); + bu32 mmr_off; + bu16 *value16p; + bu32 *value32p; + void *valuep; + + mmr_off = addr - port->base; + valuep = (void *)((unsigned long)port + mmr_base() + mmr_off); + value16p = valuep; + value32p = valuep; + + HW_TRACE_READ (); + + if (mmr_off == mmr_offset (mux)) + dv_bfin_mmr_require_32 (me, addr, nr_bytes, false); + else + dv_bfin_mmr_require_16 (me, addr, nr_bytes, false); + + switch (mmr_off) + { + case mmr_offset(data): + case mmr_offset(clear): + case mmr_offset(set): + dv_store_2 (dest, port->data); + break; + case mmr_offset(dir_clear): + case mmr_offset(dir_set): + dv_store_2 (dest, port->dir); + break; + case mmr_offset(fer): + case mmr_offset(inen): + dv_store_2 (dest, *value16p); + break; + case mmr_offset(mux): + dv_store_4 (dest, *value32p); + break; + default: + dv_bfin_mmr_invalid (me, addr, nr_bytes, false); + break; + } + + return nr_bytes; +} + +static const struct hw_port_descriptor bfin_gpio_ports[] = +{ + { "p0", 0, 0, bidirect_port, }, + { "p1", 1, 0, bidirect_port, }, + { "p2", 2, 0, bidirect_port, }, + { "p3", 3, 0, bidirect_port, }, + { "p4", 4, 0, bidirect_port, }, + { "p5", 5, 0, bidirect_port, }, + { "p6", 6, 0, bidirect_port, }, + { "p7", 7, 0, bidirect_port, }, + { "p8", 8, 0, bidirect_port, }, + { "p9", 9, 0, bidirect_port, }, + { "p10", 10, 0, bidirect_port, }, + { "p11", 11, 0, bidirect_port, }, + { "p12", 12, 0, bidirect_port, }, + { "p13", 13, 0, bidirect_port, }, + { "p14", 14, 0, bidirect_port, }, + { "p15", 15, 0, bidirect_port, }, + { NULL, 0, 0, 0, }, +}; + +static void +bfin_gpio_port_event (struct hw *me, int my_port, struct hw *source, + int source_port, int level) +{ + struct bfin_gpio *port = hw_data (me); + bu32 bit = (1 << my_port); + + /* Normalize the level value. A simulated device can send any value + it likes to us, but in reality we only care about 0 and 1. This + lets us assume only those two values below. */ + level = !!level; + + HW_TRACE ((me, "pin %i set to %i", my_port, level)); + + /* Only screw with state if this pin is set as an input, and the + input is actually enabled, and it isn't in peripheral mode. */ + if ((port->dir & bit) || !(port->inen & bit) || !(port->fer & bit)) + { + HW_TRACE ((me, "ignoring level due to DIR=%i INEN=%i FER=%i", + !!(port->dir & bit), !!(port->inen & bit), + !!(port->fer & bit))); + return; + } + + hw_port_event (me, my_port, level); +} + +static void +attach_bfin_gpio_regs (struct hw *me, struct bfin_gpio *port) +{ + address_word attach_address; + int attach_space; + unsigned attach_size; + reg_property_spec reg; + + if (hw_find_property (me, "reg") == NULL) + hw_abort (me, "Missing \"reg\" property"); + + if (!hw_find_reg_array_property (me, "reg", 0, ®)) + hw_abort (me, "\"reg\" property must contain three addr/size entries"); + + hw_unit_address_to_attach_address (hw_parent (me), + ®.address, + &attach_space, &attach_address, me); + hw_unit_size_to_attach_size (hw_parent (me), ®.size, &attach_size, me); + + if (attach_size != BFIN_MMR_GPIO2_SIZE) + hw_abort (me, "\"reg\" size must be %#x", BFIN_MMR_GPIO2_SIZE); + + hw_attach_address (hw_parent (me), + 0, attach_space, attach_address, attach_size, me); + + port->base = attach_address; +} + +static void +bfin_gpio_finish (struct hw *me) +{ + struct bfin_gpio *port; + + port = HW_ZALLOC (me, struct bfin_gpio); + + set_hw_data (me, port); + set_hw_io_read_buffer (me, bfin_gpio_io_read_buffer); + set_hw_io_write_buffer (me, bfin_gpio_io_write_buffer); + set_hw_ports (me, bfin_gpio_ports); + set_hw_port_event (me, bfin_gpio_port_event); + + attach_bfin_gpio_regs (me, port); +} + +const struct hw_descriptor dv_bfin_gpio2_descriptor[] = +{ + {"bfin_gpio2", bfin_gpio_finish,}, + {NULL, NULL}, +}; diff --git a/sim/bfin/dv-bfin_gpio2.h b/sim/bfin/dv-bfin_gpio2.h new file mode 100644 index 00000000000..7e9e94e3138 --- /dev/null +++ b/sim/bfin/dv-bfin_gpio2.h @@ -0,0 +1,25 @@ +/* Blackfin General Purpose Ports (GPIO) model + For "new style" GPIOs on BF54x parts. + + Copyright (C) 2010-2012 Free Software Foundation, Inc. + Contributed by Analog Devices, Inc. and Mike Frysinger. + + This file is part of simulators. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see <http://www.gnu.org/licenses/>. */ + +#ifndef DV_BFIN_GPIO2_H +#define DV_BFIN_GPIO2_H + +#endif diff --git a/sim/bfin/machs.c b/sim/bfin/machs.c index 393a7b89fba..5267cfa6452 100644 --- a/sim/bfin/machs.c +++ b/sim/bfin/machs.c @@ -885,7 +885,6 @@ static const struct bfin_memory_layout bf54x_mem[] = { LAYOUT (0xFFC00800, 0x60, read_write), /* SPORT0 stub XXX: not on BF542/4 */ LAYOUT (0xFFC00900, 0x60, read_write), /* SPORT1 stub */ - LAYOUT (0xFFC01400, 0x200, read_write), /* PORT/GPIO stub */ LAYOUT (0xFFC02500, 0x60, read_write), /* SPORT2 stub */ LAYOUT (0xFFC02600, 0x60, read_write), /* SPORT3 stub */ LAYOUT (0xFFC03800, 0x70, read_write), /* ATAPI stub */ @@ -915,6 +914,16 @@ static const struct bfin_dev_layout bf542_dev[] = DEVICE (0xFFC00A00, BF54X_MMR_EBIU_AMC_SIZE, "bfin_ebiu_amc"), DEVICE (0xFFC00A20, BFIN_MMR_EBIU_DDRC_SIZE, "bfin_ebiu_ddrc"), _DEVICE (0xFFC01300, BFIN_MMR_EPPI_SIZE, "bfin_eppi@1", 1), + DEVICE (0xFFC014C0, BFIN_MMR_GPIO2_SIZE, "bfin_gpio2@0"), + DEVICE (0xFFC014E0, BFIN_MMR_GPIO2_SIZE, "bfin_gpio2@1"), + DEVICE (0xFFC01500, BFIN_MMR_GPIO2_SIZE, "bfin_gpio2@2"), + DEVICE (0xFFC01520, BFIN_MMR_GPIO2_SIZE, "bfin_gpio2@3"), + DEVICE (0xFFC01540, BFIN_MMR_GPIO2_SIZE, "bfin_gpio2@4"), + DEVICE (0xFFC01560, BFIN_MMR_GPIO2_SIZE, "bfin_gpio2@5"), + DEVICE (0xFFC01580, BFIN_MMR_GPIO2_SIZE, "bfin_gpio2@6"), + DEVICE (0xFFC015A0, BFIN_MMR_GPIO2_SIZE, "bfin_gpio2@7"), + DEVICE (0xFFC015C0, BFIN_MMR_GPIO2_SIZE, "bfin_gpio2@8"), + DEVICE (0xFFC015E0, BFIN_MMR_GPIO2_SIZE, "bfin_gpio2@9"), DEVICE (0xFFC01600, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@0"), DEVICE (0xFFC01610, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@1"), DEVICE (0xFFC01620, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@2"), @@ -945,6 +954,16 @@ static const struct bfin_dev_layout bf544_dev[] = DEVICE (0xFFC00A20, BFIN_MMR_EBIU_DDRC_SIZE, "bfin_ebiu_ddrc"), _DEVICE (0xFFC01000, BFIN_MMR_EPPI_SIZE, "bfin_eppi@0", 1), _DEVICE (0xFFC01300, BFIN_MMR_EPPI_SIZE, "bfin_eppi@1", 1), + DEVICE (0xFFC014C0, BFIN_MMR_GPIO2_SIZE, "bfin_gpio2@0"), + DEVICE (0xFFC014E0, BFIN_MMR_GPIO2_SIZE, "bfin_gpio2@1"), + DEVICE (0xFFC01500, BFIN_MMR_GPIO2_SIZE, "bfin_gpio2@2"), + DEVICE (0xFFC01520, BFIN_MMR_GPIO2_SIZE, "bfin_gpio2@3"), + DEVICE (0xFFC01540, BFIN_MMR_GPIO2_SIZE, "bfin_gpio2@4"), + DEVICE (0xFFC01560, BFIN_MMR_GPIO2_SIZE, "bfin_gpio2@5"), + DEVICE (0xFFC01580, BFIN_MMR_GPIO2_SIZE, "bfin_gpio2@6"), + DEVICE (0xFFC015A0, BFIN_MMR_GPIO2_SIZE, "bfin_gpio2@7"), + DEVICE (0xFFC015C0, BFIN_MMR_GPIO2_SIZE, "bfin_gpio2@8"), + DEVICE (0xFFC015E0, BFIN_MMR_GPIO2_SIZE, "bfin_gpio2@9"), DEVICE (0xFFC01600, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@0"), DEVICE (0xFFC01610, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@1"), DEVICE (0xFFC01620, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@2"), @@ -976,6 +995,16 @@ static const struct bfin_dev_layout bf547_dev[] = DEVICE (0xFFC00A20, BFIN_MMR_EBIU_DDRC_SIZE, "bfin_ebiu_ddrc"), _DEVICE (0xFFC01000, BFIN_MMR_EPPI_SIZE, "bfin_eppi@0", 1), _DEVICE (0xFFC01300, BFIN_MMR_EPPI_SIZE, "bfin_eppi@1", 1), + DEVICE (0xFFC014C0, BFIN_MMR_GPIO2_SIZE, "bfin_gpio2@0"), + DEVICE (0xFFC014E0, BFIN_MMR_GPIO2_SIZE, "bfin_gpio2@1"), + DEVICE (0xFFC01500, BFIN_MMR_GPIO2_SIZE, "bfin_gpio2@2"), + DEVICE (0xFFC01520, BFIN_MMR_GPIO2_SIZE, "bfin_gpio2@3"), + DEVICE (0xFFC01540, BFIN_MMR_GPIO2_SIZE, "bfin_gpio2@4"), + DEVICE (0xFFC01560, BFIN_MMR_GPIO2_SIZE, "bfin_gpio2@5"), + DEVICE (0xFFC01580, BFIN_MMR_GPIO2_SIZE, "bfin_gpio2@6"), + DEVICE (0xFFC015A0, BFIN_MMR_GPIO2_SIZE, "bfin_gpio2@7"), + DEVICE (0xFFC015C0, BFIN_MMR_GPIO2_SIZE, "bfin_gpio2@8"), + DEVICE (0xFFC015E0, BFIN_MMR_GPIO2_SIZE, "bfin_gpio2@9"), DEVICE (0xFFC01600, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@0"), DEVICE (0xFFC01610, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@1"), DEVICE (0xFFC01620, BFIN_MMR_GPTIMER_SIZE, "bfin_gptimer@2"), diff --git a/sim/bfin/machs.h b/sim/bfin/machs.h index 13388271984..e37d2c7ea4d 100644 --- a/sim/bfin/machs.h +++ b/sim/bfin/machs.h @@ -82,6 +82,7 @@ enum { #define BFIN_MMR_EMAC_SIZE 0x200 #define BFIN_MMR_EPPI_SIZE 0x40 #define BFIN_MMR_GPIO_SIZE (17 * 4) +#define BFIN_MMR_GPIO2_SIZE (8 * 4) #define BFIN_MMR_GPTIMER_SIZE (4 * 4) #define BFIN_MMR_NFC_SIZE 0x50 /* XXX: Not exactly true; it's two sets of 4 regs near each other: |