diff options
| -rw-r--r-- | include/opcode/ChangeLog | 4 | ||||
| -rw-r--r-- | include/opcode/aarch64.h | 2 | ||||
| -rw-r--r-- | opcodes/ChangeLog | 13 | ||||
| -rw-r--r-- | opcodes/aarch64-asm.c | 6 | ||||
| -rw-r--r-- | opcodes/aarch64-dis.c | 1 | ||||
| -rw-r--r-- | opcodes/aarch64-opc.c | 10 | ||||
| -rw-r--r-- | opcodes/aarch64-tbl.h | 8 |
7 files changed, 32 insertions, 12 deletions
diff --git a/include/opcode/ChangeLog b/include/opcode/ChangeLog index f8b25c60d10..85a1a8f3033 100644 --- a/include/opcode/ChangeLog +++ b/include/opcode/ChangeLog @@ -1,3 +1,7 @@ +2013-01-17 Yufeng Zhang <yufeng.zhang@arm.com> + + * aarch64.h (aarch64_op): Remove OP_V_MOVI_B. + 2013-01-10 Peter Bergner <bergner@vnet.ibm.com> * ppc.h (PPC_OPCODE_POWER8): New define. diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h index 3a26199a132..9005c8cdd01 100644 --- a/include/opcode/aarch64.h +++ b/include/opcode/aarch64.h @@ -409,8 +409,6 @@ enum aarch64_op OP_UXTH, OP_UXTW, - OP_V_MOVI_B, - OP_CINC, OP_CINV, OP_CNEG, diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 45f3e326b7a..c593d9dbd40 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,16 @@ +2013-01-17 Yufeng Zhang <yufeng.zhang@arm.com> + + * aarch64-asm.c (aarch64_ins_advsimd_imm_modified): Handle 8-bit MOVI. + * aarch64-dis.c (aarch64_ext_advsimd_imm_modified): Likewise. + * aarch64-opc.c (operand_general_constraint_met_p): For + AARCH64_MOD_LSL, move the range check on the shift amount before the + alignment check; change to call set_sft_amount_out_of_range_error + instead of set_imm_out_of_range_error. + * aarch64-tbl.h (QL_SIMD_IMM_B): Replace NIL with LSL. + (aarch64_opcode_table): Remove the OP enumerator from the asimdimm + 8-bit MOVI entry; change the 2nd operand from SIMD_IMM to + SIMD_IMM_SFT. + 2013-01-16 H.J. Lu <hongjiu.lu@intel.com> * i386-gen.c (operand_type_init): Add OPERAND_TYPE_IMM32_64. diff --git a/opcodes/aarch64-asm.c b/opcodes/aarch64-asm.c index 3a6e7b11d98..4c1c5216b76 100644 --- a/opcodes/aarch64-asm.c +++ b/opcodes/aarch64-asm.c @@ -382,7 +382,11 @@ aarch64_ins_advsimd_imm_modified (const aarch64_operand *self ATTRIBUTE_UNUSED, { /* AARCH64_MOD_LSL: shift zeros. */ int esize = aarch64_get_qualifier_esize (opnd0_qualifier); - assert (esize == 4 || esize == 2); + assert (esize == 4 || esize == 2 || esize == 1); + /* For 8-bit move immediate, the optional LSL #0 does not require + encoding. */ + if (esize == 1) + return NULL; amount >>= 3; if (esize == 4) gen_sub_field (FLD_cmode, 1, 2, &field); /* per word */ diff --git a/opcodes/aarch64-dis.c b/opcodes/aarch64-dis.c index 84b7b0a3eb8..bbd5a3e8a46 100644 --- a/opcodes/aarch64-dis.c +++ b/opcodes/aarch64-dis.c @@ -642,6 +642,7 @@ aarch64_ext_advsimd_imm_modified (const aarch64_operand *self ATTRIBUTE_UNUSED, { case 4: gen_sub_field (FLD_cmode, 1, 2, &field); break; /* per word */ case 2: gen_sub_field (FLD_cmode, 1, 1, &field); break; /* per half */ + case 1: gen_sub_field (FLD_cmode, 1, 0, &field); break; /* per byte */ default: assert (0); return 0; } /* 00: 0; 01: 8; 10:16; 11:24. */ diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c index 72ecf5b61e5..4bcb9eafbc1 100644 --- a/opcodes/aarch64-opc.c +++ b/opcodes/aarch64-opc.c @@ -1745,15 +1745,15 @@ operand_general_constraint_met_p (const aarch64_opnd_info *opnds, int idx, { case AARCH64_MOD_LSL: size = aarch64_get_qualifier_esize (opnds[0].qualifier); - if (!value_aligned_p (opnd->shifter.amount, 8)) + if (!value_in_range_p (opnd->shifter.amount, 0, (size - 1) * 8)) { - set_unaligned_error (mismatch_detail, idx, 8); + set_sft_amount_out_of_range_error (mismatch_detail, idx, 0, + (size - 1) * 8); return 0; } - if (!value_in_range_p (opnd->shifter.amount, 0, (size - 1) * 8)) + if (!value_aligned_p (opnd->shifter.amount, 8)) { - set_imm_out_of_range_error (mismatch_detail, idx, 0, - (size - 1) * 8); + set_unaligned_error (mismatch_detail, idx, 8); return 0; } break; diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h index fd38a9d9f20..e2906f8312e 100644 --- a/opcodes/aarch64-tbl.h +++ b/opcodes/aarch64-tbl.h @@ -1171,11 +1171,11 @@ QLF2(V_4S, NIL), \ } -/* e.g. MOVI <Vd>.8B, #<imm8>. */ +/* e.g. MOVI <Vd>.8B, #<imm8> {, LSL #<amount>}. */ #define QL_SIMD_IMM_B \ { \ - QLF2(V_8B, NIL), \ - QLF2(V_16B, NIL), \ + QLF2(V_8B, LSL), \ + QLF2(V_16B, LSL), \ } /* e.g. MOVI <Dd>, #<imm>. */ #define QL_SIMD_IMM_D \ @@ -1341,7 +1341,7 @@ struct aarch64_opcode aarch64_opcode_table[] = {"movi", 0xf008400, 0xbff8dc00, asimdimm, 0, SIMD, OP2 (Vd, SIMD_IMM_SFT), QL_SIMD_IMM_S0H, F_SIZEQ}, {"orr", 0xf009400, 0xbff8dc00, asimdimm, 0, SIMD, OP2 (Vd, SIMD_IMM_SFT), QL_SIMD_IMM_S0H, F_SIZEQ}, {"movi", 0xf00c400, 0xbff8ec00, asimdimm, 0, SIMD, OP2 (Vd, SIMD_IMM_SFT), QL_SIMD_IMM_S1W, F_SIZEQ}, - {"movi", 0xf00e400, 0xbff8fc00, asimdimm, OP_V_MOVI_B, SIMD, OP2 (Vd, SIMD_IMM), QL_SIMD_IMM_B, F_SIZEQ}, + {"movi", 0xf00e400, 0xbff8fc00, asimdimm, 0, SIMD, OP2 (Vd, SIMD_IMM_SFT), QL_SIMD_IMM_B, F_SIZEQ}, {"fmov", 0xf00f400, 0xbff8fc00, asimdimm, 0, SIMD, OP2 (Vd, SIMD_FPIMM), QL_SIMD_IMM_S, F_SIZEQ}, {"mvni", 0x2f000400, 0xbff89c00, asimdimm, 0, SIMD, OP2 (Vd, SIMD_IMM_SFT), QL_SIMD_IMM_S0W, F_SIZEQ}, {"bic", 0x2f001400, 0xbff89c00, asimdimm, 0, SIMD, OP2 (Vd, SIMD_IMM_SFT), QL_SIMD_IMM_S0W, F_SIZEQ}, |