diff options
| -rw-r--r-- | include/opcode/ChangeLog | 27 | ||||
| -rw-r--r-- | include/opcode/mips.h | 55 | ||||
| -rw-r--r-- | opcodes/ChangeLog | 14 | ||||
| -rw-r--r-- | opcodes/micromips-opc.c | 57 | ||||
| -rw-r--r-- | opcodes/mips-dis.c | 17 | ||||
| -rw-r--r-- | opcodes/mips-opc.c | 57 |
6 files changed, 218 insertions, 9 deletions
diff --git a/include/opcode/ChangeLog b/include/opcode/ChangeLog index ecf4b113d64..4daf47bc094 100644 --- a/include/opcode/ChangeLog +++ b/include/opcode/ChangeLog @@ -1,3 +1,30 @@ +2013-06-17 Catherine Moore <clm@codesourcery.com> + Maciej W. Rozycki <macro@codesourcery.com> + Chao-Ying Fu <fu@mips.com> + + * mips.h (OP_SH_EVAOFFSET): Define. + (OP_MASK_EVAOFFSET): Define. + (INSN_ASE_MASK): Delete. + (ASE_EVA): Define. + (M_CACHEE_AB, M_CACHEE_OB): New. + (M_LBE_OB, M_LBE_AB): New. + (M_LBUE_OB, M_LBUE_AB): New. + (M_LHE_OB, M_LHE_AB): New. + (M_LHUE_OB, M_LHUE_AB): New. + (M_LLE_AB, M_LLE_OB): New. + (M_LWE_OB, M_LWE_AB): New. + (M_LWLE_AB, M_LWLE_OB): New. + (M_LWRE_AB, M_LWRE_OB): New. + (M_PREFE_AB, M_PREFE_OB): New. + (M_SCE_AB, M_SCE_OB): New. + (M_SBE_OB, M_SBE_AB): New. + (M_SHE_OB, M_SHE_AB): New. + (M_SWE_OB, M_SWE_AB): New. + (M_SWLE_AB, M_SWLE_OB): New. + (M_SWRE_AB, M_SWRE_OB): New. + (MICROMIPSOP_SH_EVAOFFSET): Define. + (MICROMIPSOP_MASK_EVAOFFSET): Define. + 2013-06-12 Sandra Loosemore <sandra@codesourcery.com> * nios2.h (OP_MATCH_ERET): Correct eret encoding. diff --git a/include/opcode/mips.h b/include/opcode/mips.h index 0bb9c11870d..9d241e847a6 100644 --- a/include/opcode/mips.h +++ b/include/opcode/mips.h @@ -330,6 +330,10 @@ #define OP_MASK_IMMY 0 #define OP_SH_IMMY 0 +/* Enhanced VA Scheme */ +#define OP_SH_EVAOFFSET 7 +#define OP_MASK_EVAOFFSET 0x1ff + /* This structure holds information for a particular instruction. */ struct mips_opcode @@ -521,6 +525,9 @@ struct mips_opcode "+z" 5-bit rz register (OP_*_RZ) "+Z" 5-bit fz register (OP_*_FZ) + Enhanced VA Scheme: + "+j" 9-bit signed offset in bit 7 (OP_*_EVAOFFSET) + Other: "()" parens surrounding optional value "," separates operands @@ -537,7 +544,7 @@ struct mips_opcode following), for quick reference when adding more: "1234" "ABCDEFGHIJPQSTXZ" - "abcpstxz" + "abcjpstxz" */ /* These are the bits which may be set in the pinfo field of an @@ -733,9 +740,6 @@ static const unsigned int mips_isa_table[] = #define INSN_OCTEONP 0x00000200 #define INSN_OCTEON2 0x00000100 -/* Masks used for MIPS-defined ASEs. */ -#define INSN_ASE_MASK 0x3c00f0d0 - /* MIPS R5900 instruction */ #define INSN_5900 0x00004000 @@ -774,6 +778,8 @@ static const unsigned int mips_isa_table[] = #define ASE_DSP64 0x00000002 /* DSP R2 ASE */ #define ASE_DSPR2 0x00000004 +/* Enhanced VA Scheme */ +#define ASE_EVA 0x00000008 /* MCU (MicroController) ASE */ #define ASE_MCU 0x00000010 /* MDMX ASE */ @@ -1020,6 +1026,8 @@ enum M_BNEL_I, M_CACHE_AB, M_CACHE_OB, + M_CACHEE_AB, + M_CACHEE_OB, M_DABS, M_DADD_I, M_DADDU_I, @@ -1061,8 +1069,12 @@ enum M_LA_AB, M_LB_A, M_LB_AB, + M_LBE_OB, + M_LBE_AB, M_LBU_A, M_LBU_AB, + M_LBUE_OB, + M_LBUE_AB, M_LCA_AB, M_LD_A, M_LD_OB, @@ -1082,8 +1094,12 @@ enum M_LDR_OB, M_LH_A, M_LH_AB, + M_LHE_OB, + M_LHE_AB, M_LHU_A, M_LHU_AB, + M_LHUE_OB, + M_LHUE_AB, M_LI, M_LI_D, M_LI_DD, @@ -1093,10 +1109,14 @@ enum M_LL_OB, M_LLD_AB, M_LLD_OB, + M_LLE_AB, + M_LLE_OB, M_LQ_AB, M_LS_A, M_LW_A, M_LW_AB, + M_LWE_OB, + M_LWE_AB, M_LWC0_A, M_LWC0_AB, M_LWC1_A, @@ -1109,6 +1129,8 @@ enum M_LWL_A, M_LWL_AB, M_LWL_OB, + M_LWLE_AB, + M_LWLE_OB, M_LWM_AB, M_LWM_OB, M_LWP_AB, @@ -1116,6 +1138,8 @@ enum M_LWR_A, M_LWR_AB, M_LWR_OB, + M_LWRE_AB, + M_LWRE_OB, M_LWU_AB, M_LWU_OB, M_MSGSND, @@ -1134,6 +1158,8 @@ enum M_OR_I, M_PREF_AB, M_PREF_OB, + M_PREFE_AB, + M_PREFE_OB, M_REM_3, M_REM_3I, M_REMU_3, @@ -1158,6 +1184,8 @@ enum M_SC_OB, M_SCD_AB, M_SCD_OB, + M_SCE_AB, + M_SCE_OB, M_SD_A, M_SD_OB, M_SD_AB, @@ -1194,11 +1222,17 @@ enum M_SNE_I, M_SB_A, M_SB_AB, + M_SBE_OB, + M_SBE_AB, M_SH_A, M_SH_AB, + M_SHE_OB, + M_SHE_AB, M_SQ_AB, M_SW_A, M_SW_AB, + M_SWE_OB, + M_SWE_AB, M_SWC0_A, M_SWC0_AB, M_SWC1_A, @@ -1211,6 +1245,8 @@ enum M_SWL_A, M_SWL_AB, M_SWL_OB, + M_SWLE_AB, + M_SWLE_OB, M_SWM_AB, M_SWM_OB, M_SWP_AB, @@ -1218,6 +1254,8 @@ enum M_SWR_A, M_SWR_AB, M_SWR_OB, + M_SWRE_AB, + M_SWRE_OB, M_SUB_I, M_SUBU_I, M_SUBU_I_2, @@ -1638,6 +1676,10 @@ extern const int bfd_mips16_num_opcodes; #define MICROMIPSOP_SH_FZ 0 #define MICROMIPSOP_MASK_FZ 0 +/* microMIPS Enhanced VA Scheme */ +#define MICROMIPSOP_SH_EVAOFFSET 0 +#define MICROMIPSOP_MASK_EVAOFFSET 0x1ff + /* These are the characters which may appears in the args field of a microMIPS instruction. They appear in the order in which the fields appear when the instruction is used. Commas and parentheses in the args @@ -1795,6 +1837,9 @@ extern const int bfd_mips16_num_opcodes; "@" 10-bit signed immediate (MICROMIPSOP_*_IMM10) "^" 5-bit unsigned immediate (MICROMIPSOP_*_RD) + microMIPS Enhanced VA Scheme: + "+j" 9-bit signed offset in bit 0 (OP_*_EVAOFFSET) + Other: "()" parens surrounding optional value "," separates operands @@ -1809,7 +1854,7 @@ extern const int bfd_mips16_num_opcodes; Extension character sequences used so far ("+" followed by the following), for quick reference when adding more: - "" + "j" "" "ABCDEFGHI" "" diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 79d289a0606..d1b106eb4f2 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,17 @@ +2013-06-17 Catherine Moore <clm@codesourcery.com> + Maciej W. Rozycki <macro@codesourcery.com> + Chao-Ying Fu <fu@mips.com> + + * micromips-opc.c (EVA): Define. + (TLBINV): Define. + (micromips_opcodes): Add EVA opcodes. + * mips-dis.c (mips_arch_choices): Update for ASE_EVA. + (print_insn_args): Handle EVA offsets. + (print_insn_micromips): Likewise. + * mips-opc.c (EVA): Define. + (TLBINV): Define. + (mips_builtin_opcodes): Add EVA opcodes. + 2013-06-17 Alan Modra <amodra@gmail.com> * Makefile.am (mips-opc.lo): Add rules to create automatic diff --git a/opcodes/micromips-opc.c b/opcodes/micromips-opc.c index 605384c4231..34e7b124f64 100644 --- a/opcodes/micromips-opc.c +++ b/opcodes/micromips-opc.c @@ -110,6 +110,12 @@ /* MIPS MCU (MicroController) ASE support. */ #define MC ASE_MCU +/* MIPS Enhanced VA Scheme. */ +#define EVA ASE_EVA + +/* TLB invalidate instruction support. */ +#define TLBINV ASE_EVA + /* MIPS Virtualization ASE. */ #define IVIRT ASE_VIRT #define IVIRT64 ASE_VIRT64 @@ -955,6 +961,8 @@ const struct mips_opcode micromips_opcodes[] = {"tgeu", "s,t,|", 0x0000043c, 0xfc000fff, RD_s|RD_t|TRAP, 0, I1 }, {"tgeu", "s,j", 0x41600000, 0xffe00000, RD_s|TRAP, 0, I1 }, /* tgeiu */ {"tgeu", "s,I", 0, (int) M_TGEU_I, INSN_MACRO, 0, I1 }, +{"tlbinv", "", 0x0000437c, 0xffffffff, INSN_TLB, 0, 0, TLBINV }, +{"tlbinvf", "", 0x0000537c, 0xffffffff, INSN_TLB, 0, 0, TLBINV }, {"tlbginv", "", 0x0000417c, 0xffffffff, INSN_TLB, 0, 0, IVIRT }, {"tlbginvf","", 0x0000517c, 0xffffffff, INSN_TLB, 0, 0, IVIRT }, {"tlbgp", "", 0x0000017c, 0xffffffff, INSN_TLB, 0, 0, IVIRT }, @@ -1007,6 +1015,55 @@ const struct mips_opcode micromips_opcodes[] = {"xor", "d,v,t", 0x00000310, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1 }, {"xor", "t,r,I", 0, (int) M_XOR_I, INSN_MACRO, 0, I1 }, {"xori", "t,r,i", 0x70000000, 0xfc000000, WR_t|RD_s, 0, I1 }, +/* microMIPS Enhanced VA Scheme */ +{"lbue", "t,+j(b)", 0x60006000, 0xfc00fe00, RD_b|WR_t, 0, 0, EVA }, +{"lbue", "t,o(b)", 0, (int) M_LBUE_OB, INSN_MACRO, 0, 0, EVA }, +{"lbue", "t,A(b)", 0, (int) M_LBUE_AB, INSN_MACRO, 0, 0, EVA }, +{"lhue", "t,+j(b)", 0x60006200, 0xfc00fe00, RD_b|WR_t, 0, 0, EVA }, +{"lhue", "t,o(b)", 0, (int) M_LHUE_OB, INSN_MACRO, 0, 0, EVA }, +{"lhue", "t,A(b)", 0, (int) M_LHUE_AB, INSN_MACRO, 0, 0, EVA }, +{"lbe", "t,+j(b)", 0x60006800, 0xfc00fe00, RD_b|WR_t, 0, 0, EVA }, +{"lbe", "t,o(b)", 0, (int) M_LBE_OB, INSN_MACRO, 0, 0, EVA }, +{"lbe", "t,A(b)", 0, (int) M_LBE_AB, INSN_MACRO, 0, 0, EVA }, +{"lhe", "t,+j(b)", 0x60006a00, 0xfc00fe00, RD_b|WR_t, 0, 0, EVA }, +{"lhe", "t,o(b)", 0, (int) M_LHE_OB, INSN_MACRO, 0, 0, EVA }, +{"lhe", "t,A(b)", 0, (int) M_LHE_AB, INSN_MACRO, 0, 0, EVA }, +{"lle", "t,+j(b)", 0x60006c00, 0xfc00fe00, RD_b|WR_t, 0, 0, EVA }, +{"lle", "t,o(b)", 0, (int) M_LLE_OB, INSN_MACRO, 0, 0, EVA }, +{"lle", "t,A(b)", 0, (int) M_LLE_AB, INSN_MACRO, 0, 0, EVA }, +{"lwe", "t,+j(b)", 0x60006e00, 0xfc00fe00, RD_b|WR_t, 0, 0, EVA }, +{"lwe", "t,o(b)", 0, (int) M_LWE_OB, INSN_MACRO, 0, 0, EVA }, +{"lwe", "t,A(b)", 0, (int) M_LWE_AB, INSN_MACRO, 0, 0, EVA }, +{"lwle", "t,+j(b)", 0x60006400, 0xfc00fe00, RD_b|WR_t, 0, 0, EVA }, +{"lwle", "t,o(b)", 0, (int) M_LWLE_OB, INSN_MACRO, 0, 0, EVA }, +{"lwle", "t,A(b)", 0, (int) M_LWLE_AB, INSN_MACRO, 0, 0, EVA }, +{"lwre", "t,+j(b)", 0x60006600, 0xfc00fe00, RD_b|WR_t, 0, 0, EVA }, +{"lwre", "t,o(b)", 0, (int) M_LWRE_OB, INSN_MACRO, 0, 0, EVA }, +{"lwre", "t,A(b)", 0, (int) M_LWRE_AB, INSN_MACRO, 0, 0, EVA }, +{"sbe", "t,+j(b)", 0x6000a800, 0xfc00fe00, SM|RD_b|WR_t, 0, 0, EVA }, +{"sbe", "t,o(b)", 0, (int) M_SBE_OB, INSN_MACRO, 0, 0, EVA }, +{"sbe", "t,A(b)", 0, (int) M_SBE_AB, INSN_MACRO, 0, 0, EVA }, +{"sce", "t,+j(b)", 0x6000ac00, 0xfc00fe00, SM|RD_t|WR_t|RD_b, 0, 0, EVA }, +{"sce", "t,o(b)", 0, (int) M_SCE_OB, INSN_MACRO, 0, 0, EVA }, +{"sce", "t,A(b)", 0, (int) M_SCE_AB, INSN_MACRO, 0, 0, EVA }, +{"she", "t,+j(b)", 0x6000aa00, 0xfc00fe00, SM|RD_b|WR_t, 0, 0, EVA }, +{"she", "t,o(b)", 0, (int) M_SHE_OB, INSN_MACRO, 0, 0, EVA }, +{"she", "t,A(b)", 0, (int) M_SHE_AB, INSN_MACRO, 0, 0, EVA }, +{"swe", "t,+j(b)", 0x6000ae00, 0xfc00fe00, SM|RD_b|WR_t, 0, 0, EVA }, +{"swe", "t,o(b)", 0, (int) M_SWE_OB, INSN_MACRO, 0, 0, EVA }, +{"swe", "t,A(b)", 0, (int) M_SWE_AB, INSN_MACRO, 0, 0, EVA }, +{"swle", "t,+j(b)", 0x6000a000, 0xfc00fe00, SM|RD_b|WR_t, 0, 0, EVA }, +{"swle", "t,o(b)", 0, (int) M_SWLE_OB, INSN_MACRO, 0, 0, EVA }, +{"swle", "t,A(b)", 0, (int) M_SWLE_AB, INSN_MACRO, 0, 0, EVA }, +{"swre", "t,+j(b)", 0x6000a200, 0xfc00fe00, SM|RD_b|WR_t, 0, 0, EVA }, +{"swre", "t,o(b)", 0, (int) M_SWRE_OB, INSN_MACRO, 0, 0, EVA }, +{"swre", "t,A(b)", 0, (int) M_SWRE_AB, INSN_MACRO, 0, 0, EVA }, +{"cachee", "k,+j(b)", 0x6000a600, 0xfc00fe00, RD_b, 0, 0, EVA }, +{"cachee", "k,o(b)", 0, (int) M_CACHEE_OB,INSN_MACRO, 0, 0, EVA }, +{"cachee", "k,A(b)", 0, (int) M_CACHEE_AB,INSN_MACRO, 0, 0, EVA }, +{"prefe", "k,+j(b)", 0x6000a400, 0xfc00fe00, RD_b, 0, 0, EVA }, +{"prefe", "k,o(b)", 0, (int) M_PREFE_OB, INSN_MACRO, 0, 0, EVA }, +{"prefe", "k,A(b)", 0, (int) M_PREFE_AB, INSN_MACRO, 0, 0, EVA }, /* MIPS DSP ASE. */ {"absq_s.ph", "t,s", 0x0000113c, 0xfc00ffff, WR_t|RD_s, 0, 0, D32 }, {"absq_s.w", "t,s", 0x0000213c, 0xfc00ffff, WR_t|RD_s, 0, 0, D32 }, diff --git a/opcodes/mips-dis.c b/opcodes/mips-dis.c index bf1ef40b883..db8dac40491 100644 --- a/opcodes/mips-dis.c +++ b/opcodes/mips-dis.c @@ -591,8 +591,8 @@ const struct mips_arch_choice mips_arch_choices[] = { "mips32r2", 1, bfd_mach_mipsisa32r2, CPU_MIPS32R2, ISA_MIPS32R2, - (ASE_SMARTMIPS | ASE_DSP | ASE_DSPR2 | ASE_MIPS3D | ASE_MT - | ASE_MCU | ASE_VIRT), + (ASE_SMARTMIPS | ASE_DSP | ASE_DSPR2 | ASE_EVA | ASE_MIPS3D + | ASE_MT | ASE_MCU | ASE_VIRT), mips_cp0_names_mips3264r2, mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2), mips_hwr_names_mips3264r2 }, @@ -606,8 +606,8 @@ const struct mips_arch_choice mips_arch_choices[] = { "mips64r2", 1, bfd_mach_mipsisa64r2, CPU_MIPS64R2, ISA_MIPS64R2, - (ASE_MIPS3D | ASE_DSP | ASE_DSPR2 | ASE_DSP64 | ASE_MT | ASE_MDMX - | ASE_MCU | ASE_VIRT | ASE_VIRT64), + (ASE_MIPS3D | ASE_DSP | ASE_DSPR2 | ASE_DSP64 | ASE_EVA | ASE_MT + | ASE_MDMX | ASE_MCU | ASE_VIRT | ASE_VIRT64), mips_cp0_names_mips3264r2, mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2), mips_hwr_names_mips3264r2 }, @@ -1152,6 +1152,10 @@ print_insn_args (const char *d, infprintf (is, "%s", mips_fpr_names[GET_OP (l, FZ)]); break; + case 'j': /* 9-bit signed offset in bit 7. */ + infprintf (is, "%d", GET_OP_S (l, EVAOFFSET)); + break; + default: /* xgettext:c-format */ infprintf (is, @@ -2659,6 +2663,11 @@ print_insn_micromips (bfd_vma memaddr, struct disassemble_info *info) infprintf (is, "0x%x", msbd + 1); break; + case 'j': /* 9-bit signed offset in bit 0. */ + delta = GET_OP_S (insn, EVAOFFSET); + infprintf (is, "%d", delta); + break; + default: /* xgettext:c-format */ infprintf (is, diff --git a/opcodes/mips-opc.c b/opcodes/mips-opc.c index fcfa020cda0..d12701b8fbd 100644 --- a/opcodes/mips-opc.c +++ b/opcodes/mips-opc.c @@ -194,6 +194,12 @@ /* MIPS MCU (MicroController) ASE support. */ #define MC ASE_MCU +/* MIPS Enhanced VA Scheme. */ +#define EVA ASE_EVA + +/* TLB invalidate instruction support. */ +#define TLBINV ASE_EVA + /* The order of overloaded instructions matters. Label arguments and register arguments look the same. Instructions that can have either for arguments must apear in the correct order in this table for the @@ -1640,6 +1646,8 @@ const struct mips_opcode mips_builtin_opcodes[] = {"tgeu", "s,t,q", 0x00000031, 0xfc00003f, RD_s|RD_t|TRAP, 0, I2 }, {"tgeu", "s,j", 0x04090000, 0xfc1f0000, RD_s|TRAP, 0, I2 }, /* tgeiu */ {"tgeu", "s,I", 0, (int) M_TGEU_I, INSN_MACRO, 0, I2 }, +{"tlbinv", "", 0x42000003, 0xffffffff, INSN_TLB, 0, 0, TLBINV }, +{"tlbinvf", "", 0x42000004, 0xffffffff, INSN_TLB, 0, 0, TLBINV }, {"tlbp", "", 0x42000008, 0xffffffff, INSN_TLB, 0, I1 }, {"tlbr", "", 0x42000001, 0xffffffff, INSN_TLB, 0, I1 }, {"tlbwi", "", 0x42000002, 0xffffffff, INSN_TLB, 0, I1 }, @@ -2296,6 +2304,55 @@ const struct mips_opcode mips_builtin_opcodes[] = {"punpcklwd", "D,S,T", 0x4b80000b, 0xffe0003f, RD_S|RD_T|WR_D|FP_D, 0, IL2F|IL3A }, {"sequ", "S,T", 0x46800032, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, IL2E }, {"sequ", "S,T", 0x4b80000c, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, IL2F|IL3A }, +/* MIPS Enhanced VA Scheme */ +{"lbue", "t,+j(b)", 0x7c000028, 0xfc00007f, LDD|RD_b|WR_t, 0, 0, EVA }, +{"lbue", "t,o(b)", 0, (int) M_LBUE_OB, INSN_MACRO, 0, 0, EVA }, +{"lbue", "t,A(b)", 0, (int) M_LBUE_AB, INSN_MACRO, 0, 0, EVA }, +{"lhue", "t,+j(b)", 0x7c000029, 0xfc00007f, LDD|RD_b|WR_t, 0, 0, EVA }, +{"lhue", "t,o(b)", 0, (int) M_LHUE_OB, INSN_MACRO, 0, 0, EVA }, +{"lhue", "t,A(b)", 0, (int) M_LHUE_AB, INSN_MACRO, 0, 0, EVA }, +{"lbe", "t,+j(b)", 0x7c00002c, 0xfc00007f, LDD|RD_b|WR_t, 0, 0, EVA }, +{"lbe", "t,o(b)", 0, (int) M_LBE_OB, INSN_MACRO, 0, 0, EVA }, +{"lbe", "t,A(b)", 0, (int) M_LBE_AB, INSN_MACRO, 0, 0, EVA }, +{"lhe", "t,+j(b)", 0x7c00002d, 0xfc00007f, LDD|RD_b|WR_t, 0, 0, EVA }, +{"lhe", "t,o(b)", 0, (int) M_LHE_OB, INSN_MACRO, 0, 0, EVA }, +{"lhe", "t,A(b)", 0, (int) M_LHE_AB, INSN_MACRO, 0, 0, EVA }, +{"lle", "t,+j(b)", 0x7c00002e, 0xfc00007f, LDD|RD_b|WR_t, 0, 0, EVA }, +{"lle", "t,o(b)", 0, (int) M_LLE_OB, INSN_MACRO, 0, 0, EVA }, +{"lle", "t,A(b)", 0, (int) M_LLE_AB, INSN_MACRO, 0, 0, EVA }, +{"lwe", "t,+j(b)", 0x7c00002f, 0xfc00007f, LDD|RD_b|WR_t, 0, 0, EVA }, +{"lwe", "t,o(b)", 0, (int) M_LWE_OB, INSN_MACRO, 0, 0, EVA }, +{"lwe", "t,A(b)", 0, (int) M_LWE_AB, INSN_MACRO, 0, 0, EVA }, +{"lwle", "t,+j(b)", 0x7c000019, 0xfc00007f, LDD|RD_b|WR_t, 0, 0, EVA }, +{"lwle", "t,o(b)", 0, (int) M_LWLE_OB, INSN_MACRO, 0, 0, EVA }, +{"lwle", "t,A(b)", 0, (int) M_LWLE_AB, INSN_MACRO, 0, 0, EVA }, +{"lwre", "t,+j(b)", 0x7c00001a, 0xfc00007f, LDD|RD_b|WR_t, 0, 0, EVA }, +{"lwre", "t,o(b)", 0, (int) M_LWRE_OB, INSN_MACRO, 0, 0, EVA }, +{"lwre", "t,A(b)", 0, (int) M_LWRE_AB, INSN_MACRO, 0, 0, EVA }, +{"sbe", "t,+j(b)", 0x7c00001c, 0xfc00007f, SM|RD_t|RD_b, 0, 0, EVA }, +{"sbe", "t,o(b)", 0, (int) M_SBE_OB, INSN_MACRO, 0, 0, EVA }, +{"sbe", "t,A(b)", 0, (int) M_SBE_AB, INSN_MACRO, 0, 0, EVA }, +{"sce", "t,+j(b)", 0x7c00001e, 0xfc00007f, SM|RD_t|WR_t|RD_b, 0, 0, EVA }, +{"sce", "t,o(b)", 0, (int) M_SCE_OB, INSN_MACRO, 0, 0, EVA }, +{"sce", "t,A(b)", 0, (int) M_SCE_AB, INSN_MACRO, 0, 0, EVA }, +{"she", "t,+j(b)", 0x7c00001d, 0xfc00007f, SM|RD_t|RD_b, 0, 0, EVA }, +{"she", "t,o(b)", 0, (int) M_SHE_OB, INSN_MACRO, 0, 0, EVA }, +{"she", "t,A(b)", 0, (int) M_SHE_AB, INSN_MACRO, 0, 0, EVA }, +{"swe", "t,+j(b)", 0x7c00001f, 0xfc00007f, SM|RD_t|RD_b, 0, 0, EVA }, +{"swe", "t,o(b)", 0, (int) M_SWE_OB, INSN_MACRO, 0, 0, EVA }, +{"swe", "t,A(b)", 0, (int) M_SWE_AB, INSN_MACRO, 0, 0, EVA }, +{"swle", "t,+j(b)", 0x7c000021, 0xfc00007f, SM|RD_t|RD_b, 0, 0, EVA }, +{"swle", "t,o(b)", 0, (int) M_SWLE_OB, INSN_MACRO, 0, 0, EVA }, +{"swle", "t,A(b)", 0, (int) M_SWLE_AB, INSN_MACRO, 0, 0, EVA }, +{"swre", "t,+j(b)", 0x7c000022, 0xfc00007f, SM|RD_t|RD_b, 0, 0, EVA }, +{"swre", "t,o(b)", 0, (int) M_SWRE_OB, INSN_MACRO, 0, 0, EVA }, +{"swre", "t,A(b)", 0, (int) M_SWRE_AB, INSN_MACRO, 0, 0, EVA }, +{"cachee", "k,+j(b)", 0x7c00001b, 0xfc00007f, RD_b, 0, 0, EVA }, +{"cachee", "k,o(b)", 0, (int) M_CACHEE_OB,INSN_MACRO, 0, 0, EVA }, +{"cachee", "k,A(b)", 0, (int) M_CACHEE_AB,INSN_MACRO, 0, 0, EVA }, +{"prefe", "k,+j(b)", 0x7c000023, 0xfc00007f, RD_b, 0, 0, EVA }, +{"prefe", "k,o(b)", 0, (int) M_PREFE_OB, INSN_MACRO, 0, 0, EVA }, +{"prefe", "k,A(b)", 0, (int) M_PREFE_AB, INSN_MACRO, 0, 0, EVA }, /* No hazard protection on coprocessor instructions--they shouldn't change the state of the processor and if they do it's up to the user to put in nops as necessary. These are at the end so that the |