diff options
38 files changed, 15807 insertions, 1187 deletions
diff --git a/bfd/ChangeLog b/bfd/ChangeLog index 9ae63911a38..7e81552e198 100644 --- a/bfd/ChangeLog +++ b/bfd/ChangeLog @@ -1,3 +1,30 @@ +2011-10-25 Joern Rennecke <joern.rennecke@embecosm.com> + + * Makefile.am (ALL_MACHINES): Add cpu-epiphany.lo. + (ALL_MACHINES_CFILES): Add cpu-epiphany.c. + (BFD32_BACKENDS): Add elf32-epiphany.lo. + (BFD32_BACKENDS_CFILES): Add elf32-epiphany.c. + * archures.c (bfd_arch_epiphany): Add. + (bfd_mach_epiphany16, bfd_mach_epiphany32): Define. + (bfd_epiphany_arch): Declare. + (bfd_archures_list): Add &bfd_epiphany_arch. + * config.bfd (epiphany-*-elf): New target case. + * configure.in (bfd_elf32_epiphany_vec): New target vector case. + * reloc.c (BFD_RELOC_EPIPHANY_SIMM8): New relocation. + (BFD_RELOC_EPIPHANY_SIMM24, BFD_RELOC_EPIPHANY_HIGH): Likewise. + (BFD_RELOC_EPIPHANY_LOW, BFD_RELOC_EPIPHANY_SIMM11): Likewise. + (BFD_RELOC_EPIPHANY_IMM11, BFD_RELOC_EPIPHANY_IMM8): Likewise. + * targets.c (bfd_elf32_epiphany_vec): Declare. + (_bfd_target_vector): Add bfd_elf32_epiphany_vec. + * Makefile.in: Regenerate. + * bfd-in2.h: Regenerate. + * configure: Regenerate. + * libbfd.h: Regenerate. + * po/SRC-POTFILES.in: Regenerate. + * po/bfd.pot: Regenerate. + * cpu-epiphany.c: New file. + * elf32-epiphany.c: New file. + 2011-10-24 Maciej W. Rozycki <macro@codesourcery.com> * elfxx-mips.c (_bfd_mips_elf_symbol_processing): Remove diff --git a/bfd/Makefile.am b/bfd/Makefile.am index 8610d5e361f..46e94a5b30d 100644 --- a/bfd/Makefile.am +++ b/bfd/Makefile.am @@ -83,6 +83,7 @@ ALL_MACHINES = \ cpu-d10v.lo \ cpu-d30v.lo \ cpu-dlx.lo \ + cpu-epiphany.lo \ cpu-fr30.lo \ cpu-frv.lo \ cpu-h8300.lo \ @@ -158,6 +159,7 @@ ALL_MACHINES_CFILES = \ cpu-d10v.c \ cpu-d30v.c \ cpu-dlx.c \ + cpu-epiphany.c \ cpu-fr30.c \ cpu-frv.c \ cpu-h8300.c \ @@ -286,6 +288,7 @@ BFD32_BACKENDS = \ elf32-d10v.lo \ elf32-d30v.lo \ elf32-dlx.lo \ + elf32-epiphany.lo \ elf32-fr30.lo \ elf32-frv.lo \ elf32-gen.lo \ @@ -470,6 +473,7 @@ BFD32_BACKENDS_CFILES = \ elf32-d10v.c \ elf32-d30v.c \ elf32-dlx.c \ + elf32-epiphany.c \ elf32-fr30.c \ elf32-frv.c \ elf32-gen.c \ diff --git a/bfd/Makefile.in b/bfd/Makefile.in index 34196aa9b8e..12ec3ee0ba2 100644 --- a/bfd/Makefile.in +++ b/bfd/Makefile.in @@ -382,6 +382,7 @@ ALL_MACHINES = \ cpu-d10v.lo \ cpu-d30v.lo \ cpu-dlx.lo \ + cpu-epiphany.lo \ cpu-fr30.lo \ cpu-frv.lo \ cpu-h8300.lo \ @@ -457,6 +458,7 @@ ALL_MACHINES_CFILES = \ cpu-d10v.c \ cpu-d30v.c \ cpu-dlx.c \ + cpu-epiphany.c \ cpu-fr30.c \ cpu-frv.c \ cpu-h8300.c \ @@ -586,6 +588,7 @@ BFD32_BACKENDS = \ elf32-d10v.lo \ elf32-d30v.lo \ elf32-dlx.lo \ + elf32-epiphany.lo \ elf32-fr30.lo \ elf32-frv.lo \ elf32-gen.lo \ @@ -770,6 +773,7 @@ BFD32_BACKENDS_CFILES = \ elf32-d10v.c \ elf32-d30v.c \ elf32-dlx.c \ + elf32-epiphany.c \ elf32-fr30.c \ elf32-frv.c \ elf32-gen.c \ @@ -1260,6 +1264,7 @@ distclean-compile: @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cpu-d10v.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cpu-d30v.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cpu-dlx.Plo@am__quote@ +@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cpu-epiphany.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cpu-fr30.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cpu-frv.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cpu-h8300.Plo@am__quote@ @@ -1346,6 +1351,7 @@ distclean-compile: @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf32-d10v.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf32-d30v.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf32-dlx.Plo@am__quote@ +@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf32-epiphany.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf32-fr30.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf32-frv.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf32-gen.Plo@am__quote@ diff --git a/bfd/archures.c b/bfd/archures.c index 44850e75dc5..9781f1eec18 100644 --- a/bfd/archures.c +++ b/bfd/archures.c @@ -365,6 +365,9 @@ DESCRIPTION . bfd_arch_iq2000, {* Vitesse IQ2000. *} .#define bfd_mach_iq2000 1 .#define bfd_mach_iq10 2 +. bfd_arch_epiphany, {* Adapteva EPIPHANY *} +.#define bfd_mach_epiphany16 1 +.#define bfd_mach_epiphany32 2 . bfd_arch_mt, .#define bfd_mach_ms1 1 .#define bfd_mach_mrisc2 2 @@ -496,6 +499,7 @@ extern const bfd_arch_info_type bfd_crx_arch; extern const bfd_arch_info_type bfd_d10v_arch; extern const bfd_arch_info_type bfd_d30v_arch; extern const bfd_arch_info_type bfd_dlx_arch; +extern const bfd_arch_info_type bfd_epiphany_arch; extern const bfd_arch_info_type bfd_fr30_arch; extern const bfd_arch_info_type bfd_frv_arch; extern const bfd_arch_info_type bfd_h8300_arch; @@ -576,6 +580,7 @@ static const bfd_arch_info_type * const bfd_archures_list[] = &bfd_d10v_arch, &bfd_d30v_arch, &bfd_dlx_arch, + &bfd_epiphany_arch, &bfd_fr30_arch, &bfd_frv_arch, &bfd_h8300_arch, diff --git a/bfd/bfd-in2.h b/bfd/bfd-in2.h index 91f3531a628..f48d2d40eb3 100644 --- a/bfd/bfd-in2.h +++ b/bfd/bfd-in2.h @@ -2071,6 +2071,9 @@ enum bfd_architecture bfd_arch_iq2000, /* Vitesse IQ2000. */ #define bfd_mach_iq2000 1 #define bfd_mach_iq10 2 + bfd_arch_epiphany, /* Adapteva EPIPHANY */ +#define bfd_mach_epiphany16 1 +#define bfd_mach_epiphany32 2 bfd_arch_mt, #define bfd_mach_ms1 1 #define bfd_mach_mrisc2 2 @@ -5023,6 +5026,27 @@ the dynamic object into the runtime process image. */ BFD_RELOC_TILEGX_TLS_DTPMOD32, BFD_RELOC_TILEGX_TLS_DTPOFF32, BFD_RELOC_TILEGX_TLS_TPOFF32, + +/* Adapteva EPIPHANY - 8 bit signed pc-relative displacement */ + BFD_RELOC_EPIPHANY_SIMM8, + +/* Adapteva EPIPHANY - 24 bit signed pc-relative displacement */ + BFD_RELOC_EPIPHANY_SIMM24, + +/* Adapteva EPIPHANY - 16 most-significant bits of absolute address */ + BFD_RELOC_EPIPHANY_HIGH, + +/* Adapteva EPIPHANY - 16 least-significant bits of absolute address */ + BFD_RELOC_EPIPHANY_LOW, + +/* Adapteva EPIPHANY - 11 bit signed number - add/sub immediate */ + BFD_RELOC_EPIPHANY_SIMM11, + +/* Adapteva EPIPHANY - 11 bit sign-magnitude number (ld/st displacement) */ + BFD_RELOC_EPIPHANY_IMM11, + +/* Adapteva EPIPHANY - 8 bit immediate for 16 bit mov instruction. */ + BFD_RELOC_EPIPHANY_IMM8, BFD_RELOC_UNUSED }; typedef enum bfd_reloc_code_real bfd_reloc_code_real_type; reloc_howto_type *bfd_reloc_type_lookup diff --git a/bfd/config.bfd b/bfd/config.bfd index 3b9872a2a4d..1e86dd48fdb 100644 --- a/bfd/config.bfd +++ b/bfd/config.bfd @@ -361,6 +361,10 @@ case "${targ}" in targ_defvec=bfd_elf32_d30v_vec ;; + epiphany-*-elf) + targ_defvec=bfd_elf32_epiphany_vec + ;; + fido-*-elf* ) targ_defvec=bfd_elf32_m68k_vec targ_selvecs="m68kcoff_vec ieee_vec" diff --git a/bfd/configure b/bfd/configure index 96a8f758613..e6a3a5ab2ca 100755 --- a/bfd/configure +++ b/bfd/configure @@ -15199,6 +15199,7 @@ do bfd_elf32_d10v_vec) tb="$tb elf32-d10v.lo elf32.lo $elf" ;; bfd_elf32_d30v_vec) tb="$tb elf32-d30v.lo elf32.lo $elf" ;; bfd_elf32_dlx_big_vec) tb="$tb elf32-dlx.lo elf32.lo $elf" ;; + bfd_elf32_epiphany_vec) tb="$tb elf32-epiphany.lo elf32.lo $elf" ;; bfd_elf32_fr30_vec) tb="$tb elf32-fr30.lo elf32.lo $elf" ;; bfd_elf32_frv_vec) tb="$tb elf32-frv.lo elf32.lo $elf" ;; bfd_elf32_frvfdpic_vec) tb="$tb elf32-frv.lo elf32.lo $elf" ;; diff --git a/bfd/configure.in b/bfd/configure.in index 2088d62e616..f6d3693aa1b 100644 --- a/bfd/configure.in +++ b/bfd/configure.in @@ -698,6 +698,7 @@ do bfd_elf32_d10v_vec) tb="$tb elf32-d10v.lo elf32.lo $elf" ;; bfd_elf32_d30v_vec) tb="$tb elf32-d30v.lo elf32.lo $elf" ;; bfd_elf32_dlx_big_vec) tb="$tb elf32-dlx.lo elf32.lo $elf" ;; + bfd_elf32_epiphany_vec) tb="$tb elf32-epiphany.lo elf32.lo $elf" ;; bfd_elf32_fr30_vec) tb="$tb elf32-fr30.lo elf32.lo $elf" ;; bfd_elf32_frv_vec) tb="$tb elf32-frv.lo elf32.lo $elf" ;; bfd_elf32_frvfdpic_vec) tb="$tb elf32-frv.lo elf32.lo $elf" ;; diff --git a/bfd/cpu-epiphany.c b/bfd/cpu-epiphany.c new file mode 100644 index 00000000000..54f9580c888 --- /dev/null +++ b/bfd/cpu-epiphany.c @@ -0,0 +1,56 @@ +/* BFD support for the Adapteva EPIPHANY processor. + Copyright 2011 Free Software Foundation, Inc. + Contributed by Embecosm on behalf of Adapteva, Inc. + + This file is part of BFD, the Binary File Descriptor library. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +#include "sysdep.h" +#include "bfd.h" +#include "libbfd.h" + +const bfd_arch_info_type bfd_epiphany16_arch = +{ + 32, /* Bits per word */ + 32, /* Bits per address. */ + 8, /* Bits per byte. */ + bfd_arch_epiphany, /* Architecture. */ + bfd_mach_epiphany16, /* Machine. */ + "epiphany", /* Architecture name. */ + "epiphany16", /* Machine name. */ + 1, /* Section align power. */ + FALSE, /* The default ? */ + bfd_default_compatible, /* Architecture comparison fn. */ + bfd_default_scan, /* String to architecture convert fn. */ + NULL /* Next in list. */ +}; + +const bfd_arch_info_type bfd_epiphany_arch = +{ + 32, /* Bits per word - not really true. */ + 32, /* Bits per address. */ + 8, /* Bits per byte. */ + bfd_arch_epiphany, /* Architecture. */ + bfd_mach_epiphany32, /* Machine. */ + "epiphany", /* Architecture name. */ + "epiphany32", /* Machine name. */ + 2, /* Section align power. */ + TRUE, /* The default ? */ + bfd_default_compatible, /* Architecture comparison fn. */ + bfd_default_scan, /* String to architecture convert fn. */ + & bfd_epiphany16_arch /* Next in list. */ +}; diff --git a/bfd/elf32-epiphany.c b/bfd/elf32-epiphany.c new file mode 100644 index 00000000000..08f3be1798c --- /dev/null +++ b/bfd/elf32-epiphany.c @@ -0,0 +1,608 @@ +/* Adapteva epiphany specific support for 32-bit ELF + Copyright 2011 + Free Software Foundation, Inc. + Contributed by Embecosm on behalf of Adapteva, Inc. + + This file is part of BFD, the Binary File Descriptor library. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +#include "sysdep.h" +#include "bfd.h" +#include "libbfd.h" +#include "elf-bfd.h" +#include "elf/epiphany.h" +#include "libiberty.h" + +/* Struct used to pass miscellaneous paramaters which + helps to avoid overly long parameter lists. */ +struct misc +{ + Elf_Internal_Shdr * symtab_hdr; + Elf_Internal_Rela * irelbase; + bfd_byte * contents; + Elf_Internal_Sym * isymbuf; +}; + +struct epiphany_opcode +{ + unsigned short opcode; + unsigned short mask; +}; + +static bfd_boolean epiphany_relaxed = FALSE; + +/* Relocation tables. */ +static reloc_howto_type epiphany_elf_howto_table [] = +{ +#define AHOW(t,rs,s,bs,pr,bp,co,name,sm,dm) \ + HOWTO(t, /* type */ \ + rs, /* rightshift */ \ + s, /* size (0 = byte, 1 = short, 2 = long) */ \ + bs, /* bitsize */ \ + pr, /* pc_relative */ \ + bp, /* bitpos */ \ + co, /* complain_on_overflow */ \ + bfd_elf_generic_reloc,/* special_function */ \ + name, /* name */ \ + FALSE, /* partial_inplace */ \ + sm, /* src_mask */ \ + dm, /* dst_mask */ \ + pr) /* pcrel_offset */ + + /* This reloc does nothing. */ + AHOW (R_EPIPHANY_NONE, 0, 0,32, FALSE, 0, complain_overflow_dont, "R_EPIPHANY_NONE", 0, 0), + + /* 8 bit absolute (not likely) */ + AHOW (R_EPIPHANY_8, 0, 0, 8, FALSE, 0, complain_overflow_bitfield, "R_EPIPHANY_8", 0x000000ff, 0x000000ff), + /* 16 bit absolute */ + AHOW (R_EPIPHANY_16, 0, 1,16, FALSE, 0, complain_overflow_bitfield, "R_EPIPHANY_16", 0x0000ffff, 0x00ff1fe0), + /* A 32 bit absolute relocation. */ + AHOW (R_EPIPHANY_32, 0, 2,32, FALSE, 0, complain_overflow_dont, "R_EPIPHANY_32", 0xffffffff, 0xffffffff), + + /* 8 bit relative relocation */ + HOWTO ( R_EPIPHANY_8_PCREL, 0, 0, 8, TRUE, 0, complain_overflow_bitfield, bfd_elf_generic_reloc, "R_EPIPHANY_8_PCREL", FALSE, 0x000000ff, 0x000000ff, FALSE), + /* 16 bit relative relocation */ + HOWTO ( R_EPIPHANY_16_PCREL, 0, 1, 16, TRUE, 0, complain_overflow_bitfield, bfd_elf_generic_reloc, "R_EPIPHANY_8_PCREL", FALSE, 0x000000ff, 0x000000ff, FALSE), + /* 32 bit relative relocation */ + HOWTO ( R_EPIPHANY_32_PCREL, 0, 2, 32, TRUE, 0, complain_overflow_bitfield, bfd_elf_generic_reloc, "R_EPIPHANY_8_PCREL", FALSE, 0x000000ff, 0x000000ff, FALSE), + + /* 8 bit pc-relative relocation */ + AHOW (R_EPIPHANY_SIMM8, 1, 0, 8, TRUE, 8, complain_overflow_signed, "R_EPIPHANY_SIMM8", 0x000000ff, 0x0000ff00), + /* 24 bit pc-relative relocation */ + AHOW (R_EPIPHANY_SIMM24, 1, 2,24, TRUE, 8, complain_overflow_signed, "R_EPIPHANY_SIMM24", 0x00ffffff, 0xffffff00), + + /* %HIGH(EA) */ + AHOW (R_EPIPHANY_HIGH, 0, 2,16, FALSE, 0, complain_overflow_dont, "R_EPIPHANY_HIGH", 0x0ff01fe0, 0x0ff01fe0), + + /* %LOW(EA) */ + AHOW (R_EPIPHANY_LOW, 0, 2,16, FALSE, 0, complain_overflow_dont, "R_EPIPHANY_LOW", 0x0ff01fe0, 0x0ff01fe0), + + /* simm11 */ + AHOW (R_EPIPHANY_SIMM11, 0, 2,11, FALSE, 0, complain_overflow_bitfield, "R_EPIPHANY_SIMM11", 0x00ff0380, 0x00ff0380), + /* imm12 - sign-magnitude */ + AHOW (R_EPIPHANY_IMM11, 0, 2,11, FALSE, 0, complain_overflow_bitfield, "R_EPIPHANY_IMM12", 0x00ff0380, 0x00ff0380), + /* imm8 */ + AHOW (R_EPIPHANY_IMM8, 0, 1, 8, FALSE, 8, complain_overflow_signed, "R_EPIPHANY_IMM8", 0x0000ff00, 0x0000ff00) + + +}; +#undef AHOW + +/* Map BFD reloc types to EPIPHANY ELF reloc types. */ + +static reloc_howto_type * +epiphany_reloc_type_lookup (bfd * abfd ATTRIBUTE_UNUSED, + bfd_reloc_code_real_type code) +{ + /* Note that the epiphany_elf_howto_table is indxed by the R_ + constants. Thus, the order that the howto records appear in the + table *must* match the order of the relocation types defined in + include/elf/epiphany.h. */ + + switch (code) + { + case BFD_RELOC_NONE: + return &epiphany_elf_howto_table[ (int) R_EPIPHANY_NONE]; + + case BFD_RELOC_EPIPHANY_SIMM8: + return &epiphany_elf_howto_table[ (int) R_EPIPHANY_SIMM8]; + case BFD_RELOC_EPIPHANY_SIMM24: + return &epiphany_elf_howto_table[ (int) R_EPIPHANY_SIMM24]; + + case BFD_RELOC_8_PCREL: + return &epiphany_elf_howto_table[ (int) R_EPIPHANY_8_PCREL]; + case BFD_RELOC_16_PCREL: + return &epiphany_elf_howto_table[ (int) R_EPIPHANY_16_PCREL]; + case BFD_RELOC_32_PCREL: + return &epiphany_elf_howto_table[ (int) R_EPIPHANY_32_PCREL]; + + case BFD_RELOC_8: + return &epiphany_elf_howto_table[ (int) R_EPIPHANY_8]; + case BFD_RELOC_16: + return &epiphany_elf_howto_table[ (int) R_EPIPHANY_16]; + case BFD_RELOC_32: + return &epiphany_elf_howto_table[ (int) R_EPIPHANY_32]; + + case BFD_RELOC_EPIPHANY_HIGH: + return & epiphany_elf_howto_table[ (int) R_EPIPHANY_HIGH]; + case BFD_RELOC_EPIPHANY_LOW: + return & epiphany_elf_howto_table[ (int) R_EPIPHANY_LOW]; + + case BFD_RELOC_EPIPHANY_SIMM11: + return & epiphany_elf_howto_table[ (int) R_EPIPHANY_SIMM11]; + case BFD_RELOC_EPIPHANY_IMM11: + return & epiphany_elf_howto_table[ (int) R_EPIPHANY_IMM11]; + + case BFD_RELOC_EPIPHANY_IMM8: + return & epiphany_elf_howto_table[ (int) R_EPIPHANY_IMM8]; + + default: + /* Pacify gcc -Wall. */ + return NULL; + } + return NULL; +} + +static reloc_howto_type * +epiphany_reloc_name_lookup (bfd *abfd ATTRIBUTE_UNUSED, const char *r_name) +{ + unsigned int i; + + for (i = 0; i < ARRAY_SIZE (epiphany_elf_howto_table); i++) + if (epiphany_elf_howto_table[i].name != NULL + && strcasecmp (epiphany_elf_howto_table[i].name, r_name) == 0) + return &epiphany_elf_howto_table[i]; + + return NULL; +} + +#define PAGENO(ABSADDR) ((ABSADDR) & 0xFFFFC000) +#define BASEADDR(SEC) ((SEC)->output_section->vma + (SEC)->output_offset) + +/* This function handles relaxing for the epiphany. + Dummy placeholder for future optimizations. */ + +static bfd_boolean +epiphany_elf_relax_section (bfd *abfd, asection *sec, + struct bfd_link_info *link_info, + bfd_boolean *again) +{ + Elf_Internal_Shdr *symtab_hdr; + Elf_Internal_Rela *internal_relocs; + bfd_byte *contents = NULL; + Elf_Internal_Sym *isymbuf = NULL; + static asection * first_section = NULL; + static unsigned long search_addr; + static unsigned long page_start = 0; + static unsigned long page_end = 0; + static unsigned int pass = 0; + static bfd_boolean new_pass = FALSE; + static bfd_boolean changed = FALSE; + struct misc misc ATTRIBUTE_UNUSED; + asection *stab; + + /* Assume nothing changes. */ + *again = FALSE; + + if (first_section == NULL) + { + epiphany_relaxed = TRUE; + first_section = sec; + } + + if (first_section == sec) + { + pass++; + new_pass = TRUE; + } + + /* We don't have to do anything for a relocatable link, + if this section does not have relocs, or if this is + not a code section. */ + if (link_info->relocatable + || (sec->flags & SEC_RELOC) == 0 + || sec->reloc_count == 0 + || (sec->flags & SEC_CODE) == 0) + return TRUE; + + symtab_hdr = &elf_tdata (abfd)->symtab_hdr; + + internal_relocs = _bfd_elf_link_read_relocs (abfd, sec, NULL, NULL, + link_info->keep_memory); + if (internal_relocs == NULL) + goto error_return; + + /* Make sure the stac.rela stuff gets read in. */ + stab = bfd_get_section_by_name (abfd, ".stab"); + + if (stab) + { + /* So stab does exits. */ + Elf_Internal_Rela * irelbase ATTRIBUTE_UNUSED; + + irelbase = _bfd_elf_link_read_relocs (abfd, stab, NULL, NULL, + link_info->keep_memory); + } + + /* Get section contents cached copy if it exists. */ + if (contents == NULL) + { + /* Get cached copy if it exists. */ + if (elf_section_data (sec)->this_hdr.contents != NULL) + contents = elf_section_data (sec)->this_hdr.contents; + else + { + /* Go get them off disk. */ + if (!bfd_malloc_and_get_section (abfd, sec, &contents)) + goto error_return; + } + } + + /* Read this BFD's symbols cached copy if it exists. */ + if (isymbuf == NULL && symtab_hdr->sh_info != 0) + { + isymbuf = (Elf_Internal_Sym *) symtab_hdr->contents; + if (isymbuf == NULL) + isymbuf = bfd_elf_get_elf_syms (abfd, symtab_hdr, + symtab_hdr->sh_info, 0, + NULL, NULL, NULL); + if (isymbuf == NULL) + goto error_return; + } + + misc.symtab_hdr = symtab_hdr; + misc.isymbuf = isymbuf; + misc.irelbase = internal_relocs; + misc.contents = contents; + + /* This is where all the relaxation actually get done. */ + if ((pass == 1) || (new_pass && !changed)) + { + /* On the first pass we simply search for the lowest page that + we havn't relaxed yet. Note that the pass count is reset + each time a page is complete in order to move on to the next page. + If we can't find any more pages then we are finished. */ + if (new_pass) + { + pass = 1; + new_pass = FALSE; + changed = TRUE; /* Pre-initialize to break out of pass 1. */ + search_addr = 0xFFFFFFFF; + } + + if ((BASEADDR (sec) + sec->size < search_addr) + && (BASEADDR (sec) + sec->size > page_end)) + { + if (BASEADDR (sec) <= page_end) + search_addr = page_end + 1; + else + search_addr = BASEADDR (sec); + + /* Found a page => more work to do. */ + *again = TRUE; + } + } + else + { + if (new_pass) + { + new_pass = FALSE; + changed = FALSE; + page_start = PAGENO (search_addr); + page_end = page_start | 0x00003FFF; + } + + /* Only process sections in range. */ + if ((BASEADDR (sec) + sec->size >= page_start) + && (BASEADDR (sec) <= page_end)) + { +#if 0 + if (!epiphany_elf_relax_section_page (abfd, sec, &changed, &misc, + page_start, page_end)) +#endif + return FALSE; + } + *again = TRUE; + } + + /* Perform some house keeping after relaxing the section. */ + + if (isymbuf != NULL + && symtab_hdr->contents != (unsigned char *) isymbuf) + { + if (! link_info->keep_memory) + free (isymbuf); + else + symtab_hdr->contents = (unsigned char *) isymbuf; + } + + if (contents != NULL + && elf_section_data (sec)->this_hdr.contents != contents) + { + if (! link_info->keep_memory) + free (contents); + else + { + /* Cache the section contents for elf_link_input_bfd. */ + elf_section_data (sec)->this_hdr.contents = contents; + } + } + + if (internal_relocs != NULL + && elf_section_data (sec)->relocs != internal_relocs) + free (internal_relocs); + + return TRUE; + + error_return: + if (isymbuf != NULL + && symtab_hdr->contents != (unsigned char *) isymbuf) + free (isymbuf); + if (contents != NULL + && elf_section_data (sec)->this_hdr.contents != contents) + free (contents); + if (internal_relocs != NULL + && elf_section_data (sec)->relocs != internal_relocs) + free (internal_relocs); + return FALSE; +} + +/* Set the howto pointer for a EPIPHANY ELF reloc. */ + +static void +epiphany_info_to_howto_rela (bfd * abfd ATTRIBUTE_UNUSED, + arelent * cache_ptr, + Elf_Internal_Rela * dst) +{ + unsigned int r_type; + + r_type = ELF32_R_TYPE (dst->r_info); + cache_ptr->howto = & epiphany_elf_howto_table [r_type]; +} + +/* Perform a single relocation. + By default we use the standard BFD routines. */ + +static bfd_reloc_status_type +epiphany_final_link_relocate (reloc_howto_type * howto, + bfd * input_bfd, + asection * input_section, + bfd_byte * contents, + Elf_Internal_Rela * rel, + bfd_vma relocation) +{ + switch (howto->type) + { + /* Handle 16 bit immediates. */ + case R_EPIPHANY_HIGH: + relocation += rel->r_addend; + relocation >>= 16; + goto common; + + case R_EPIPHANY_LOW: + relocation += rel->r_addend; + common: + relocation = ((relocation & 0xff00L) << 12) + | ((relocation & 0x00ffL) << 5); + /* Sanity check the address. */ + if (rel->r_offset > bfd_get_section_limit (input_bfd, input_section)) + return bfd_reloc_outofrange; + + return _bfd_relocate_contents (howto, input_bfd, relocation, + contents + rel->r_offset); + + case R_EPIPHANY_SIMM11: + relocation += rel->r_addend; + /* Check signed overflow. */ + if ((int)relocation > 1023 || (int)relocation < -1024) + return bfd_reloc_outofrange; + goto disp11; + + case R_EPIPHANY_IMM11: + relocation += rel->r_addend; + if ((unsigned int) relocation > 0x7ff) + return bfd_reloc_outofrange; + disp11: + relocation = ((relocation & 7) << 5) + || ((relocation & 0x7f8 ) << 13); + return _bfd_relocate_contents (howto, input_bfd, relocation, + contents + rel->r_offset); + + /* Pass others through. */ + default: + break; + } + + /* Only install relocation if above tests did not disqualify it. */ + return _bfd_final_link_relocate (howto, input_bfd, input_section, + contents, rel->r_offset, + relocation, rel->r_addend); +} + +/* Relocate an EPIPHANY ELF section. + + The RELOCATE_SECTION function is called by the new ELF backend linker + to handle the relocations for a section. + + The relocs are always passed as Rela structures; if the section + actually uses Rel structures, the r_addend field will always be + zero. + + This function is responsible for adjusting the section contents as + necessary, and (if using Rela relocs and generating a relocatable + output file) adjusting the reloc addend as necessary. + + This function does not have to worry about setting the reloc + address or the reloc symbol index. + + LOCAL_SYMS is a pointer to the swapped in local symbols. + + LOCAL_SECTIONS is an array giving the section in the input file + corresponding to the st_shndx field of each local symbol. + + The global hash table entry for the global symbols can be found + via elf_sym_hashes (input_bfd). + + When generating relocatable output, this function must handle + STB_LOCAL/STT_SECTION symbols specially. The output symbol is + going to be the section symbol corresponding to the output + section, which means that the addend must be adjusted + accordingly. */ + +static bfd_boolean +epiphany_elf_relocate_section (bfd *output_bfd ATTRIBUTE_UNUSED, + struct bfd_link_info *info, + bfd *input_bfd, + asection *input_section, + bfd_byte *contents, + Elf_Internal_Rela *relocs, + Elf_Internal_Sym *local_syms, + asection **local_sections) +{ + Elf_Internal_Shdr *symtab_hdr; + struct elf_link_hash_entry **sym_hashes; + Elf_Internal_Rela *rel; + Elf_Internal_Rela *relend; + + symtab_hdr = & elf_tdata (input_bfd)->symtab_hdr; + sym_hashes = elf_sym_hashes (input_bfd); + relend = relocs + input_section->reloc_count; + + for (rel = relocs; rel < relend; rel ++) + { + reloc_howto_type * howto; + unsigned long r_symndx; + Elf_Internal_Sym * sym; + asection * sec; + struct elf_link_hash_entry * h; + bfd_vma relocation; + bfd_reloc_status_type r; + const char * name = NULL; + int r_type ATTRIBUTE_UNUSED; + + r_type = ELF32_R_TYPE (rel->r_info); + r_symndx = ELF32_R_SYM (rel->r_info); + howto = epiphany_elf_howto_table + ELF32_R_TYPE (rel->r_info); + h = NULL; + sym = NULL; + sec = NULL; + + if (r_symndx < symtab_hdr->sh_info) + { + sym = local_syms + r_symndx; + sec = local_sections [r_symndx]; + relocation = BASEADDR (sec) + sym->st_value; + + name = bfd_elf_string_from_elf_section + (input_bfd, symtab_hdr->sh_link, sym->st_name); + name = (name == NULL) ? bfd_section_name (input_bfd, sec) : name; + } + else + { + bfd_boolean warned ATTRIBUTE_UNUSED; + bfd_boolean unresolved_reloc ATTRIBUTE_UNUSED; + + RELOC_FOR_GLOBAL_SYMBOL (info, input_bfd, input_section, rel, + r_symndx, symtab_hdr, sym_hashes, + h, sec, relocation, + unresolved_reloc, warned); + + name = h->root.root.string; + } + + if (sec != NULL && elf_discarded_section (sec)) + RELOC_AGAINST_DISCARDED_SECTION (info, input_bfd, input_section, + rel, relend, howto, contents); + + if (info->relocatable) + continue; + + /* Finally, the sole EPIPHANY-specific part. */ + r = epiphany_final_link_relocate (howto, input_bfd, input_section, + contents, rel, relocation); + + if (r != bfd_reloc_ok) + { + const char * msg = NULL; + + switch (r) + { + case bfd_reloc_overflow: + r = info->callbacks->reloc_overflow + (info, (h ? &h->root : NULL), name, howto->name, + (bfd_vma) 0, input_bfd, input_section, rel->r_offset); + break; + + case bfd_reloc_undefined: + r = info->callbacks->undefined_symbol + (info, name, input_bfd, input_section, rel->r_offset, TRUE); + break; + + case bfd_reloc_outofrange: + msg = _("internal error: out of range error"); + break; + + /* This is how epiphany_final_link_relocate tells us of a + non-kosher reference between insn & data address spaces. */ + case bfd_reloc_notsupported: + if (sym != NULL) /* Only if it's not an unresolved symbol. */ + msg = _("unsupported relocation between data/insn address spaces"); + break; + + case bfd_reloc_dangerous: + msg = _("internal error: dangerous relocation"); + break; + + default: + msg = _("internal error: unknown error"); + break; + } + + if (msg) + r = info->callbacks->warning + (info, msg, name, input_bfd, input_section, rel->r_offset); + + if (! r) + return FALSE; + } + } + + return TRUE; +} + +/* We only have a little-endian target. */ +#define TARGET_LITTLE_SYM bfd_elf32_epiphany_vec +#define TARGET_LITTLE_NAME "elf32-epiphany" + +#define ELF_ARCH bfd_arch_epiphany +#define ELF_MACHINE_CODE EM_ADAPTEVA_EPIPHANY + +#define ELF_MAXPAGESIZE 0x8000 /* No pages on the EPIPHANY. */ + +#define elf_info_to_howto_rel NULL +#define elf_info_to_howto epiphany_info_to_howto_rela + +#define elf_backend_can_gc_sections 1 +#define elf_backend_rela_normal 1 +#define elf_backend_relocate_section epiphany_elf_relocate_section + +#define elf_symbol_leading_char '_' +#define bfd_elf32_bfd_reloc_type_lookup epiphany_reloc_type_lookup +#define bfd_elf32_bfd_reloc_name_lookup epiphany_reloc_name_lookup +#define bfd_elf32_bfd_relax_section epiphany_elf_relax_section + +#include "elf32-target.h" diff --git a/bfd/libbfd.h b/bfd/libbfd.h index c2b119d3613..ab3e6792984 100644 --- a/bfd/libbfd.h +++ b/bfd/libbfd.h @@ -2476,6 +2476,13 @@ static const char *const bfd_reloc_code_real_names[] = { "@@uninitialized@@", "BFD_RELOC_TILEGX_TLS_DTPMOD32", "BFD_RELOC_TILEGX_TLS_DTPOFF32", "BFD_RELOC_TILEGX_TLS_TPOFF32", + "BFD_RELOC_EPIPHANY_SIMM8", + "BFD_RELOC_EPIPHANY_SIMM24", + "BFD_RELOC_EPIPHANY_HIGH", + "BFD_RELOC_EPIPHANY_LOW", + "BFD_RELOC_EPIPHANY_SIMM11", + "BFD_RELOC_EPIPHANY_IMM11", + "BFD_RELOC_EPIPHANY_IMM8", "@@overflow: BFD_RELOC_UNUSED@@", }; #endif diff --git a/bfd/po/SRC-POTFILES.in b/bfd/po/SRC-POTFILES.in index a30fa3caeae..71546889e72 100644 --- a/bfd/po/SRC-POTFILES.in +++ b/bfd/po/SRC-POTFILES.in @@ -73,6 +73,7 @@ cpu-crx.c cpu-d10v.c cpu-d30v.c cpu-dlx.c +cpu-epiphany.c cpu-fr30.c cpu-frv.c cpu-h8300.c @@ -85,6 +86,7 @@ cpu-i960.c cpu-ia64.c cpu-ip2k.c cpu-iq2000.c +cpu-k1om.c cpu-l1om.c cpu-lm32.c cpu-m10200.c @@ -161,6 +163,7 @@ elf32-crx.c elf32-d10v.c elf32-d30v.c elf32-dlx.c +elf32-epiphany.c elf32-fr30.c elf32-frv.c elf32-gen.c diff --git a/bfd/po/bfd.pot b/bfd/po/bfd.pot index 38ce82fb1a7..b7d5a1eca6c 100644 --- a/bfd/po/bfd.pot +++ b/bfd/po/bfd.pot @@ -8,7 +8,7 @@ msgid "" msgstr "" "Project-Id-Version: PACKAGE VERSION\n" "Report-Msgid-Bugs-To: bug-binutils@gnu.org\n" -"POT-Creation-Date: 2011-06-02 14:25+0100\n" +"POT-Creation-Date: 2011-10-25 11:58+0100\n" "PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n" "Last-Translator: FULL NAME <EMAIL@ADDRESS>\n" "Language-Team: LANGUAGE <LL@li.org>\n" @@ -45,28 +45,28 @@ msgid "" "%s: can not represent section for symbol `%s' in a.out object file format" msgstr "" -#: aoutx.h:1579 vms-alpha.c:7668 +#: aoutx.h:1579 vms-alpha.c:7671 msgid "*unknown*" msgstr "" -#: aoutx.h:4017 aoutx.h:4343 +#: aoutx.h:4018 aoutx.h:4344 msgid "%P: %B: unexpected relocation type\n" msgstr "" -#: aoutx.h:5374 +#: aoutx.h:5375 #, c-format msgid "%s: relocatable link from %s to %s not supported" msgstr "" -#: archive.c:2194 +#: archive.c:2203 msgid "Warning: writing archive was slow: rewriting timestamp\n" msgstr "" -#: archive.c:2482 +#: archive.c:2491 msgid "Reading archive file mod timestamp" msgstr "" -#: archive.c:2506 +#: archive.c:2515 msgid "Writing updated armap timestamp" msgstr "" @@ -189,13 +189,13 @@ msgstr "" msgid "Warning: Writing section `%s' to huge (ie negative) file offset 0x%lx." msgstr "" -#: bout.c:1146 elf-m10300.c:2075 elf32-avr.c:1654 elf32-frv.c:5731 -#: elfxx-sparc.c:2796 reloc.c:5677 reloc16.c:162 elf32-ia64.c:360 +#: bout.c:1146 elf-m10300.c:2063 elf32-avr.c:1654 elf32-frv.c:5734 +#: elfxx-sparc.c:2802 reloc.c:6115 reloc16.c:162 elf32-ia64.c:360 #: elf64-ia64.c:360 msgid "%P%F: --relax and -r may not be used together\n" msgstr "" -#: cache.c:226 +#: cache.c:227 msgid "reopening %B: %s\n" msgstr "" @@ -225,8 +225,8 @@ msgstr "" msgid "%B: unsupported relocation: ALPHA_R_GPRELLOW" msgstr "" -#: coff-alpha.c:1575 elf32-m32r.c:2493 elf64-alpha.c:4079 elf64-alpha.c:4228 -#: elf32-ia64.c:3845 elf64-ia64.c:3845 +#: coff-alpha.c:1575 elf32-m32r.c:2484 elf64-alpha.c:4074 elf64-alpha.c:4224 +#: elf32-ia64.c:3839 elf64-ia64.c:3839 msgid "%B: unknown relocation type %d" msgstr "" @@ -240,7 +240,7 @@ msgstr "" msgid "%B: unable to find ARM glue '%s' for `%s'" msgstr "" -#: coff-arm.c:1369 elf32-arm.c:6980 +#: coff-arm.c:1369 elf32-arm.c:7023 #, c-format msgid "" "%B(%s): warning: interworking not enabled.\n" @@ -268,14 +268,14 @@ msgstr "" msgid "error: %B is compiled for APCS-%d, whereas %B is compiled for APCS-%d" msgstr "" -#: coff-arm.c:2226 elf32-arm.c:15580 +#: coff-arm.c:2226 elf32-arm.c:15621 #, c-format msgid "" "error: %B passes floats in float registers, whereas %B passes them in " "integer registers" msgstr "" -#: coff-arm.c:2229 elf32-arm.c:15584 +#: coff-arm.c:2229 elf32-arm.c:15625 #, c-format msgid "" "error: %B passes floats in integer registers, whereas %B passes them in " @@ -296,12 +296,12 @@ msgid "" "position independent" msgstr "" -#: coff-arm.c:2274 elf32-arm.c:15649 +#: coff-arm.c:2274 elf32-arm.c:15690 #, c-format msgid "Warning: %B supports interworking, whereas %B does not" msgstr "" -#: coff-arm.c:2277 elf32-arm.c:15655 +#: coff-arm.c:2277 elf32-arm.c:15696 #, c-format msgid "Warning: %B does not support interworking, whereas %B does" msgstr "" @@ -311,7 +311,7 @@ msgstr "" msgid "private flags = %x:" msgstr "" -#: coff-arm.c:2309 elf32-arm.c:11752 +#: coff-arm.c:2309 elf32-arm.c:11806 #, c-format msgid " [floats passed in float registers]" msgstr "" @@ -321,7 +321,7 @@ msgstr "" msgid " [floats passed in integer registers]" msgstr "" -#: coff-arm.c:2314 elf32-arm.c:11755 +#: coff-arm.c:2314 elf32-arm.c:11809 #, c-format msgid " [position independent]" msgstr "" @@ -346,14 +346,14 @@ msgstr "" msgid " [interworking not supported]" msgstr "" -#: coff-arm.c:2370 elf32-arm.c:10787 +#: coff-arm.c:2370 elf32-arm.c:10841 #, c-format msgid "" "Warning: Not setting interworking flag of %B since it has already been " "specified as non-interworking" msgstr "" -#: coff-arm.c:2374 elf32-arm.c:10791 +#: coff-arm.c:2374 elf32-arm.c:10845 #, c-format msgid "Warning: Clearing the interworking flag of %B due to outside request" msgstr "" @@ -368,20 +368,20 @@ msgstr "" msgid "relocation `%s' not yet implemented" msgstr "" -#: coff-i860.c:605 coff-tic54x.c:398 coffcode.h:5192 +#: coff-i860.c:605 coff-tic54x.c:398 coffcode.h:5198 msgid "%B: warning: illegal symbol index %ld in relocs" msgstr "" -#: coff-i960.c:143 coff-i960.c:506 +#: coff-i960.c:144 coff-i960.c:507 msgid "uncertain calling convention for non-COFF symbol" msgstr "" -#: coff-m68k.c:506 elf32-bfin.c:5689 elf32-cr16.c:2897 elf32-m68k.c:4677 +#: coff-m68k.c:506 elf32-bfin.c:5690 elf32-cr16.c:2897 elf32-m68k.c:4677 msgid "unsupported reloc type" msgstr "" -#: coff-mips.c:688 elf32-mips.c:1014 elf32-score.c:430 elf32-score7.c:330 -#: elf64-mips.c:2019 elfn32-mips.c:1832 +#: coff-mips.c:688 elf32-mips.c:1516 elf32-score.c:431 elf32-score7.c:330 +#: elf64-mips.c:2618 elfn32-mips.c:2431 msgid "GP relative relocation when _gp not defined" msgstr "" @@ -389,17 +389,17 @@ msgstr "" msgid "Unrecognized reloc" msgstr "" -#: coff-rs6000.c:2676 +#: coff-rs6000.c:2720 #, c-format msgid "%s: unsupported relocation type 0x%02x" msgstr "" -#: coff-rs6000.c:2761 +#: coff-rs6000.c:2805 #, c-format msgid "%s: TOC reloc at 0x%x to symbol `%s' with no TOC entry" msgstr "" -#: coff-rs6000.c:3512 coff64-rs6000.c:2111 +#: coff-rs6000.c:3556 coff64-rs6000.c:2111 msgid "%B: symbol `%s' has unrecognized smclas %d" msgstr "" @@ -423,76 +423,80 @@ msgstr "" msgid "ignoring reloc %s\n" msgstr "" -#: coffcode.h:991 +#: coffcode.h:997 msgid "%B: warning: COMDAT symbol '%s' does not match section name '%s'" msgstr "" #. Generate a warning message rather using the 'unhandled' #. variable as this will allow some .sys files generate by #. other toolchains to be processed. See bugzilla issue 196. -#: coffcode.h:1215 +#: coffcode.h:1221 msgid "" "%B: Warning: Ignoring section flag IMAGE_SCN_MEM_NOT_PAGED in section %s" msgstr "" -#: coffcode.h:1282 +#: coffcode.h:1288 msgid "%B (%s): Section flag %s (0x%x) ignored" msgstr "" -#: coffcode.h:2424 +#: coffcode.h:2430 #, c-format msgid "Unrecognized TI COFF target id '0x%x'" msgstr "" -#: coffcode.h:2738 +#: coffcode.h:2744 msgid "%B: reloc against a non-existant symbol index: %ld" msgstr "" -#: coffcode.h:3296 +#: coffcode.h:3302 msgid "%B: too many sections (%d)" msgstr "" -#: coffcode.h:3712 +#: coffcode.h:3718 msgid "%B: section %s: string table overflow at offset %ld" msgstr "" -#: coffcode.h:4517 +#: coffcode.h:4523 msgid "%B: warning: line number table read failed" msgstr "" -#: coffcode.h:4547 +#: coffcode.h:4553 msgid "%B: warning: illegal symbol index %ld in line numbers" msgstr "" -#: coffcode.h:4561 +#: coffcode.h:4567 msgid "%B: warning: duplicate line number information for `%s'" msgstr "" -#: coffcode.h:4961 +#: coffcode.h:4967 msgid "%B: Unrecognized storage class %d for %s symbol `%s'" msgstr "" -#: coffcode.h:5087 +#: coffcode.h:5093 msgid "warning: %B: local symbol `%s' has no section" msgstr "" -#: coffcode.h:5231 +#: coffcode.h:5237 msgid "%B: illegal relocation type %d at address 0x%lx" msgstr "" -#: coffgen.c:1578 +#: coffgen.c:1595 msgid "%B: bad string table size %lu" msgstr "" -#: cofflink.c:533 elflink.c:4353 +#: coffgen.c:2500 elflink.c:12689 linker.c:3122 +msgid "%F%P: already_linked_table: %E\n" +msgstr "" + +#: cofflink.c:533 elflink.c:4323 msgid "Warning: type of symbol `%s' changed from %d to %d in %B" msgstr "" -#: cofflink.c:2330 +#: cofflink.c:2329 msgid "%B: relocs in section `%A', but it has no contents" msgstr "" -#: cofflink.c:2392 elflink.c:9554 +#: cofflink.c:2391 elflink.c:9545 msgid "" "%X`%s' referenced in section `%A' of %B: defined in discarded section `%A' " "of %B\n" @@ -517,117 +521,117 @@ msgstr "" msgid "warning: unable to update contents of %s section in %s" msgstr "" -#: dwarf2.c:490 +#: dwarf2.c:496 #, c-format msgid "Dwarf Error: Can't find %s section." msgstr "" -#: dwarf2.c:518 +#: dwarf2.c:525 #, c-format msgid "Dwarf Error: Offset (%lu) greater than or equal to %s size (%lu)." msgstr "" -#: dwarf2.c:940 +#: dwarf2.c:949 #, c-format msgid "Dwarf Error: Invalid or unhandled FORM value: %u." msgstr "" -#: dwarf2.c:1191 +#: dwarf2.c:1200 msgid "Dwarf Error: mangled line number section (bad file number)." msgstr "" -#: dwarf2.c:1443 +#: dwarf2.c:1453 #, c-format msgid "Dwarf Error: Unhandled .debug_line version %d." msgstr "" -#: dwarf2.c:1465 +#: dwarf2.c:1475 msgid "Dwarf Error: Invalid maximum operations per instruction." msgstr "" -#: dwarf2.c:1652 +#: dwarf2.c:1662 msgid "Dwarf Error: mangled line number section." msgstr "" -#: dwarf2.c:1978 dwarf2.c:2098 dwarf2.c:2383 +#: dwarf2.c:1989 dwarf2.c:2109 dwarf2.c:2394 #, c-format msgid "Dwarf Error: Could not find abbrev number %u." msgstr "" -#: dwarf2.c:2344 +#: dwarf2.c:2355 #, c-format msgid "" "Dwarf Error: found dwarf version '%u', this reader only handles version 2, 3 " "and 4 information." msgstr "" -#: dwarf2.c:2351 +#: dwarf2.c:2362 #, c-format msgid "" "Dwarf Error: found address size '%u', this reader can not handle sizes " "greater than '%u'." msgstr "" -#: dwarf2.c:2374 +#: dwarf2.c:2385 #, c-format msgid "Dwarf Error: Bad abbrev number: %u." msgstr "" -#: ecoff.c:1237 +#: ecoff.c:1239 #, c-format msgid "Unknown basic type %d" msgstr "" -#: ecoff.c:1494 +#: ecoff.c:1496 #, c-format msgid "" "\n" " End+1 symbol: %ld" msgstr "" -#: ecoff.c:1501 ecoff.c:1504 +#: ecoff.c:1503 ecoff.c:1506 #, c-format msgid "" "\n" " First symbol: %ld" msgstr "" -#: ecoff.c:1516 +#: ecoff.c:1518 #, c-format msgid "" "\n" " End+1 symbol: %-7ld Type: %s" msgstr "" -#: ecoff.c:1523 +#: ecoff.c:1525 #, c-format msgid "" "\n" " Local symbol: %ld" msgstr "" -#: ecoff.c:1531 +#: ecoff.c:1533 #, c-format msgid "" "\n" " struct; End+1 symbol: %ld" msgstr "" -#: ecoff.c:1536 +#: ecoff.c:1538 #, c-format msgid "" "\n" " union; End+1 symbol: %ld" msgstr "" -#: ecoff.c:1541 +#: ecoff.c:1543 #, c-format msgid "" "\n" " enum; End+1 symbol: %ld" msgstr "" -#: ecoff.c:1547 +#: ecoff.c:1549 #, c-format msgid "" "\n" @@ -644,16 +648,16 @@ msgstr "" msgid "error: %B: Object tag '%d, %s' is incompatible with tag '%d, %s'" msgstr "" -#: elf-eh-frame.c:913 +#: elf-eh-frame.c:917 msgid "%P: error in %B(%A); no .eh_frame_hdr table will be created.\n" msgstr "" -#: elf-eh-frame.c:1165 +#: elf-eh-frame.c:1189 msgid "" "%P: fde encoding in %B(%A) prevents .eh_frame_hdr table being created.\n" msgstr "" -#: elf-eh-frame.c:1583 +#: elf-eh-frame.c:1605 msgid "%P: DW_EH_PE_datarel unspecified for this architecture.\n" msgstr "" @@ -664,74 +668,73 @@ msgid "" "pie\n" msgstr "" -#: elf-m10200.c:450 elf-m10300.c:1571 elf32-avr.c:1221 elf32-bfin.c:3209 -#: elf32-cr16.c:1482 elf32-cr16c.c:780 elf32-cris.c:2077 elf32-crx.c:922 -#: elf32-d10v.c:509 elf32-fr30.c:609 elf32-frv.c:4102 elf32-h8300.c:509 -#: elf32-i860.c:1211 elf32-ip2k.c:1468 elf32-iq2000.c:684 elf32-lm32.c:1168 -#: elf32-m32c.c:553 elf32-m32r.c:3111 elf32-m68hc1x.c:1138 elf32-mep.c:535 -#: elf32-microblaze.c:1231 elf32-moxie.c:282 elf32-msp430.c:486 elf32-mt.c:395 -#: elf32-openrisc.c:404 elf32-score.c:2731 elf32-score7.c:2540 -#: elf32-spu.c:5042 elf32-v850.c:2143 elf32-xstormy16.c:941 elf64-mmix.c:1522 +#: elf-m10200.c:450 elf-m10300.c:1563 elf32-avr.c:1221 elf32-bfin.c:3213 +#: elf32-cr16.c:1482 elf32-cr16c.c:780 elf32-cris.c:2081 elf32-crx.c:922 +#: elf32-d10v.c:509 elf32-epiphany.c:556 elf32-fr30.c:609 elf32-frv.c:4105 +#: elf32-h8300.c:509 elf32-i860.c:1211 elf32-ip2k.c:1468 elf32-iq2000.c:684 +#: elf32-lm32.c:1168 elf32-m32c.c:553 elf32-m32r.c:3106 elf32-m68hc1x.c:1138 +#: elf32-mep.c:535 elf32-microblaze.c:1231 elf32-moxie.c:282 +#: elf32-msp430.c:486 elf32-mt.c:395 elf32-openrisc.c:404 elf32-score.c:2729 +#: elf32-score7.c:2537 elf32-spu.c:5044 elf32-tilepro.c:3214 elf32-v850.c:2143 +#: elf32-xstormy16.c:935 elf64-mmix.c:1590 elfxx-tilegx.c:3577 msgid "internal error: out of range error" msgstr "" -#: elf-m10200.c:454 elf-m10300.c:1575 elf32-avr.c:1225 elf32-bfin.c:3213 -#: elf32-cr16.c:1486 elf32-cr16c.c:784 elf32-cris.c:2081 elf32-crx.c:926 -#: elf32-d10v.c:513 elf32-fr30.c:613 elf32-frv.c:4106 elf32-h8300.c:513 +#: elf-m10200.c:454 elf-m10300.c:1567 elf32-avr.c:1225 elf32-bfin.c:3217 +#: elf32-cr16.c:1486 elf32-cr16c.c:784 elf32-cris.c:2085 elf32-crx.c:926 +#: elf32-d10v.c:513 elf32-fr30.c:613 elf32-frv.c:4109 elf32-h8300.c:513 #: elf32-i860.c:1215 elf32-iq2000.c:688 elf32-lm32.c:1172 elf32-m32c.c:557 -#: elf32-m32r.c:3115 elf32-m68hc1x.c:1142 elf32-mep.c:539 +#: elf32-m32r.c:3110 elf32-m68hc1x.c:1142 elf32-mep.c:539 #: elf32-microblaze.c:1235 elf32-moxie.c:286 elf32-msp430.c:490 -#: elf32-openrisc.c:408 elf32-score.c:2735 elf32-score7.c:2544 -#: elf32-spu.c:5046 elf32-v850.c:2147 elf32-xstormy16.c:945 elf64-mmix.c:1526 -#: elfxx-mips.c:9193 +#: elf32-openrisc.c:408 elf32-score.c:2733 elf32-score7.c:2541 +#: elf32-spu.c:5048 elf32-tilepro.c:3218 elf32-v850.c:2147 +#: elf32-xstormy16.c:939 elf64-mmix.c:1594 elfxx-mips.c:9465 +#: elfxx-tilegx.c:3581 msgid "internal error: unsupported relocation error" msgstr "" #: elf-m10200.c:458 elf32-cr16.c:1490 elf32-cr16c.c:788 elf32-crx.c:930 -#: elf32-d10v.c:517 elf32-h8300.c:517 elf32-lm32.c:1176 elf32-m32r.c:3119 -#: elf32-m68hc1x.c:1146 elf32-microblaze.c:1239 elf32-score.c:2739 -#: elf32-score7.c:2548 elf32-spu.c:5050 +#: elf32-d10v.c:517 elf32-h8300.c:517 elf32-lm32.c:1176 elf32-m32r.c:3114 +#: elf32-m68hc1x.c:1146 elf32-microblaze.c:1239 elf32-score.c:2737 +#: elf32-score7.c:2545 elf32-spu.c:5052 msgid "internal error: dangerous error" msgstr "" -#: elf-m10200.c:462 elf-m10300.c:1591 elf32-avr.c:1233 elf32-bfin.c:3221 -#: elf32-cr16.c:1494 elf32-cr16c.c:792 elf32-cris.c:2089 elf32-crx.c:934 -#: elf32-d10v.c:521 elf32-fr30.c:621 elf32-frv.c:4114 elf32-h8300.c:521 -#: elf32-i860.c:1223 elf32-ip2k.c:1483 elf32-iq2000.c:696 elf32-lm32.c:1180 -#: elf32-m32c.c:565 elf32-m32r.c:3123 elf32-m68hc1x.c:1150 elf32-mep.c:547 -#: elf32-microblaze.c:1243 elf32-moxie.c:294 elf32-msp430.c:498 elf32-mt.c:403 -#: elf32-openrisc.c:416 elf32-score.c:2748 elf32-score7.c:2552 -#: elf32-spu.c:5054 elf32-v850.c:2167 elf32-xstormy16.c:953 elf64-mmix.c:1534 +#: elf-m10200.c:462 elf-m10300.c:1580 elf32-avr.c:1233 elf32-bfin.c:3225 +#: elf32-cr16.c:1494 elf32-cr16c.c:792 elf32-cris.c:2093 elf32-crx.c:934 +#: elf32-d10v.c:521 elf32-epiphany.c:571 elf32-fr30.c:621 elf32-frv.c:4117 +#: elf32-h8300.c:521 elf32-i860.c:1223 elf32-ip2k.c:1483 elf32-iq2000.c:696 +#: elf32-lm32.c:1180 elf32-m32c.c:565 elf32-m32r.c:3118 elf32-m68hc1x.c:1150 +#: elf32-mep.c:547 elf32-microblaze.c:1243 elf32-moxie.c:294 +#: elf32-msp430.c:498 elf32-mt.c:403 elf32-openrisc.c:416 elf32-score.c:2746 +#: elf32-score7.c:2549 elf32-spu.c:5056 elf32-tilepro.c:3226 elf32-v850.c:2167 +#: elf32-xstormy16.c:947 elf64-mmix.c:1602 elfxx-tilegx.c:3589 msgid "internal error: unknown error" msgstr "" -#: elf-m10300.c:1515 elf32-arm.c:10365 elf32-i386.c:4107 elf32-m32r.c:2604 -#: elf32-m68k.c:4156 elf32-s390.c:3010 elf32-sh.c:4223 elf32-xtensa.c:3067 -#: elf64-s390.c:2985 elf64-sh64.c:1636 elf64-x86-64.c:3882 elfxx-sparc.c:3807 +#: elf-m10300.c:1507 elf32-arm.c:10419 elf32-i386.c:4264 elf32-m32r.c:2599 +#: elf32-m68k.c:4156 elf32-s390.c:3003 elf32-sh.c:4218 elf32-tilepro.c:3117 +#: elf32-xtensa.c:3066 elf64-s390.c:2978 elf64-sh64.c:1640 elf64-x86-64.c:4110 +#: elfxx-sparc.c:3835 elfxx-tilegx.c:3500 msgid "%B(%A+0x%lx): unresolvable %s relocation against symbol `%s'" msgstr "" -#: elf-m10300.c:1580 +#: elf-m10300.c:1572 msgid "" "error: inappropriate relocation type for shared library (did you forget -" "fpic?)" msgstr "" -#: elf-m10300.c:1583 -msgid "" -"%B: error: taking the address of protected function '%s' cannot be done when " -"making a shared library" -msgstr "" - -#: elf-m10300.c:1586 +#: elf-m10300.c:1575 msgid "internal error: suspicious relocation type used in shared library" msgstr "" -#: elf-m10300.c:4384 elf32-arm.c:12743 elf32-cr16.c:2451 elf32-cris.c:3044 -#: elf32-hppa.c:1894 elf32-i370.c:503 elf32-i386.c:2043 elf32-lm32.c:1868 -#: elf32-m32r.c:1927 elf32-m68k.c:3252 elf32-s390.c:1652 elf32-sh.c:2931 -#: elf32-tic6x.c:2160 elf32-vax.c:1040 elf64-s390.c:1635 elf64-sh64.c:3377 -#: elf64-x86-64.c:1985 elfxx-sparc.c:2104 +#: elf-m10300.c:4372 elf32-arm.c:12800 elf32-cr16.c:2451 elf32-cris.c:3057 +#: elf32-hppa.c:1894 elf32-i370.c:503 elf32-i386.c:2182 elf32-lm32.c:1868 +#: elf32-m32r.c:1927 elf32-m68k.c:3253 elf32-s390.c:1652 elf32-sh.c:2931 +#: elf32-tic6x.c:2162 elf32-tilepro.c:1940 elf32-vax.c:1041 elf64-s390.c:1635 +#: elf64-sh64.c:3381 elf64-x86-64.c:2176 elfxx-sparc.c:2119 +#: elfxx-tilegx.c:2261 #, c-format msgid "dynamic variable `%s' is zero size" msgstr "" @@ -756,7 +759,7 @@ msgstr "" msgid "%B: no group info for section %A" msgstr "" -#: elf.c:737 elf.c:3121 elflink.c:10144 +#: elf.c:737 elf.c:3121 elflink.c:10135 msgid "%B: warning: sh_link not set for section `%A'" msgstr "" @@ -857,421 +860,423 @@ msgstr "" msgid "%B: section %A lma %#lx adjusted to %#lx" msgstr "" -#: elf.c:4774 +#: elf.c:4776 msgid "%B: section `%A' can't be allocated in segment %d" msgstr "" -#: elf.c:4822 +#: elf.c:4824 msgid "%B: warning: allocated section `%s' not in segment" msgstr "" -#: elf.c:5322 +#: elf.c:5324 msgid "%B: symbol `%s' required but not present" msgstr "" -#: elf.c:5660 +#: elf.c:5662 msgid "%B: warning: Empty loadable segment detected, is this intentional ?\n" msgstr "" -#: elf.c:6688 +#: elf.c:6692 #, c-format msgid "" "Unable to find equivalent output section for symbol '%s' from section '%s'" msgstr "" -#: elf.c:7684 +#: elf.c:7692 msgid "%B: unsupported relocation type %s" msgstr "" -#: elf32-arm.c:3590 +#: elf32-arm.c:3617 msgid "" "%B(%s): warning: interworking not enabled.\n" " first occurrence: %B: Thumb call to ARM" msgstr "" -#: elf32-arm.c:3637 +#: elf32-arm.c:3664 msgid "" "%B(%s): warning: interworking not enabled.\n" " first occurrence: %B: ARM call to Thumb" msgstr "" -#: elf32-arm.c:3849 elf32-arm.c:5286 +#: elf32-arm.c:3878 elf32-arm.c:5315 #, c-format msgid "%s: cannot create stub entry %s" msgstr "" -#: elf32-arm.c:5402 +#: elf32-arm.c:5431 #, c-format msgid "unable to find THUMB glue '%s' for '%s'" msgstr "" -#: elf32-arm.c:5438 +#: elf32-arm.c:5467 #, c-format msgid "unable to find ARM glue '%s' for '%s'" msgstr "" -#: elf32-arm.c:5964 +#: elf32-arm.c:6005 msgid "%B: BE8 images only valid in big-endian mode." msgstr "" #. Give a warning, but do as the user requests anyway. -#: elf32-arm.c:6194 +#: elf32-arm.c:6235 msgid "" "%B: warning: selected VFP11 erratum workaround is not necessary for target " "architecture" msgstr "" -#: elf32-arm.c:6738 elf32-arm.c:6758 +#: elf32-arm.c:6779 elf32-arm.c:6799 msgid "%B: unable to find VFP11 veneer `%s'" msgstr "" -#: elf32-arm.c:6806 +#: elf32-arm.c:6848 #, c-format msgid "Invalid TARGET2 relocation type '%s'." msgstr "" -#: elf32-arm.c:6890 +#: elf32-arm.c:6933 msgid "" "%B(%s): warning: interworking not enabled.\n" " first occurrence: %B: thumb call to arm" msgstr "" -#: elf32-arm.c:7674 +#: elf32-arm.c:7717 msgid "%B(%A+0x%lx):unexpected Thumb instruction '0x%x' in TLS trampoline" msgstr "" -#: elf32-arm.c:7713 +#: elf32-arm.c:7756 msgid "%B(%A+0x%lx):unexpected ARM instruction '0x%x' in TLS trampoline" msgstr "" -#: elf32-arm.c:8166 +#: elf32-arm.c:8209 msgid "\\%B: Warning: Arm BLX instruction targets Arm function '%s'." msgstr "" -#: elf32-arm.c:8575 +#: elf32-arm.c:8622 msgid "%B: Warning: Thumb BLX instruction targets thumb function '%s'." msgstr "" -#: elf32-arm.c:9408 +#: elf32-arm.c:9460 msgid "" "%B(%A+0x%lx):unexpected Thumb instruction '0x%x' referenced by TLS_GOTDESC" msgstr "" -#: elf32-arm.c:9431 +#: elf32-arm.c:9483 msgid "" "%B(%A+0x%lx):unexpected ARM instruction '0x%x' referenced by TLS_GOTDESC" msgstr "" -#: elf32-arm.c:9460 +#: elf32-arm.c:9512 msgid "%B(%A+0x%lx): R_ARM_TLS_LE32 relocation not permitted in shared object" msgstr "" -#: elf32-arm.c:9675 +#: elf32-arm.c:9727 msgid "" "%B(%A+0x%lx): Only ADD or SUB instructions are allowed for ALU group " "relocations" msgstr "" -#: elf32-arm.c:9715 elf32-arm.c:9802 elf32-arm.c:9885 elf32-arm.c:9970 +#: elf32-arm.c:9767 elf32-arm.c:9854 elf32-arm.c:9937 elf32-arm.c:10022 msgid "%B(%A+0x%lx): Overflow whilst splitting 0x%lx for group relocation %s" msgstr "" -#: elf32-arm.c:10209 elf32-sh.c:4112 elf64-sh64.c:1544 +#: elf32-arm.c:10261 elf32-sh.c:4103 elf64-sh64.c:1544 msgid "%B(%A+0x%lx): %s relocation against SEC_MERGE section" msgstr "" -#: elf32-arm.c:10320 elf32-m68k.c:4191 elf32-xtensa.c:2805 +#: elf32-arm.c:10372 elf32-m68k.c:4191 elf32-xtensa.c:2802 msgid "%B(%A+0x%lx): %s used with TLS symbol %s" msgstr "" -#: elf32-arm.c:10321 elf32-m68k.c:4192 elf32-xtensa.c:2806 +#: elf32-arm.c:10373 elf32-m68k.c:4192 elf32-xtensa.c:2803 msgid "%B(%A+0x%lx): %s used with non-TLS symbol %s" msgstr "" -#: elf32-arm.c:10399 elf32-tic6x.c:2751 +#: elf32-arm.c:10453 elf32-tic6x.c:2753 msgid "out of range" msgstr "" -#: elf32-arm.c:10403 elf32-tic6x.c:2755 +#: elf32-arm.c:10457 elf32-tic6x.c:2757 msgid "unsupported relocation" msgstr "" -#: elf32-arm.c:10411 elf32-tic6x.c:2763 +#: elf32-arm.c:10465 elf32-tic6x.c:2765 msgid "unknown error" msgstr "" -#: elf32-arm.c:10836 +#: elf32-arm.c:10890 msgid "" "Warning: Clearing the interworking flag of %B because non-interworking code " "in %B has been linked with it" msgstr "" -#: elf32-arm.c:10930 +#: elf32-arm.c:10984 msgid "%B: Unknown mandatory EABI object attribute %d" msgstr "" -#: elf32-arm.c:10938 +#: elf32-arm.c:10992 msgid "Warning: %B: Unknown EABI object attribute %d" msgstr "" -#: elf32-arm.c:11119 +#: elf32-arm.c:11173 msgid "error: %B: Unknown CPU architecture" msgstr "" -#: elf32-arm.c:11157 +#: elf32-arm.c:11211 msgid "error: %B: Conflicting CPU architectures %d/%d" msgstr "" -#: elf32-arm.c:11206 +#: elf32-arm.c:11260 msgid "" "Error: %B has both the current and legacy Tag_MPextension_use attributes" msgstr "" -#: elf32-arm.c:11231 +#: elf32-arm.c:11285 msgid "error: %B uses VFP register arguments, %B does not" msgstr "" -#: elf32-arm.c:11376 +#: elf32-arm.c:11430 msgid "error: %B: unable to merge virtualization attributes with %B" msgstr "" -#: elf32-arm.c:11402 +#: elf32-arm.c:11456 msgid "error: %B: Conflicting architecture profiles %c/%c" msgstr "" -#: elf32-arm.c:11503 +#: elf32-arm.c:11557 msgid "Warning: %B: Conflicting platform configuration" msgstr "" -#: elf32-arm.c:11512 +#: elf32-arm.c:11566 msgid "error: %B: Conflicting use of R9" msgstr "" -#: elf32-arm.c:11524 +#: elf32-arm.c:11578 msgid "error: %B: SB relative addressing conflicts with use of R9" msgstr "" -#: elf32-arm.c:11537 +#: elf32-arm.c:11591 msgid "" "warning: %B uses %u-byte wchar_t yet the output is to use %u-byte wchar_t; " "use of wchar_t values across objects may fail" msgstr "" -#: elf32-arm.c:11568 +#: elf32-arm.c:11622 msgid "" "warning: %B uses %s enums yet the output is to use %s enums; use of enum " "values across objects may fail" msgstr "" -#: elf32-arm.c:11580 +#: elf32-arm.c:11634 msgid "error: %B uses iWMMXt register arguments, %B does not" msgstr "" -#: elf32-arm.c:11597 +#: elf32-arm.c:11651 msgid "error: fp16 format mismatch between %B and %B" msgstr "" -#: elf32-arm.c:11621 +#: elf32-arm.c:11675 msgid "DIV usage mismatch between %B and %B" msgstr "" -#: elf32-arm.c:11640 +#: elf32-arm.c:11694 msgid "%B has has both the current and legacy Tag_MPextension_use attributes" msgstr "" #. Ignore init flag - it may not be set, despite the flags field #. containing valid data. #. Ignore init flag - it may not be set, despite the flags field containing valid data. -#: elf32-arm.c:11728 elf32-bfin.c:5075 elf32-cris.c:4162 elf32-m68hc1x.c:1282 -#: elf32-m68k.c:1235 elf32-score.c:3996 elf32-score7.c:3803 elf32-vax.c:528 -#: elfxx-mips.c:12857 +#: elf32-arm.c:11782 elf32-bfin.c:5079 elf32-cris.c:4169 elf32-m68hc1x.c:1282 +#: elf32-m68k.c:1236 elf32-score.c:3994 elf32-score7.c:3800 elf32-vax.c:529 +#: elfxx-mips.c:14103 #, c-format msgid "private flags = %lx:" msgstr "" -#: elf32-arm.c:11737 +#: elf32-arm.c:11791 #, c-format msgid " [interworking enabled]" msgstr "" -#: elf32-arm.c:11745 +#: elf32-arm.c:11799 #, c-format msgid " [VFP float format]" msgstr "" -#: elf32-arm.c:11747 +#: elf32-arm.c:11801 #, c-format msgid " [Maverick float format]" msgstr "" -#: elf32-arm.c:11749 +#: elf32-arm.c:11803 #, c-format msgid " [FPA float format]" msgstr "" -#: elf32-arm.c:11758 +#: elf32-arm.c:11812 #, c-format msgid " [new ABI]" msgstr "" -#: elf32-arm.c:11761 +#: elf32-arm.c:11815 #, c-format msgid " [old ABI]" msgstr "" -#: elf32-arm.c:11764 +#: elf32-arm.c:11818 #, c-format msgid " [software FP]" msgstr "" -#: elf32-arm.c:11773 +#: elf32-arm.c:11827 #, c-format msgid " [Version1 EABI]" msgstr "" -#: elf32-arm.c:11776 elf32-arm.c:11787 +#: elf32-arm.c:11830 elf32-arm.c:11841 #, c-format msgid " [sorted symbol table]" msgstr "" -#: elf32-arm.c:11778 elf32-arm.c:11789 +#: elf32-arm.c:11832 elf32-arm.c:11843 #, c-format msgid " [unsorted symbol table]" msgstr "" -#: elf32-arm.c:11784 +#: elf32-arm.c:11838 #, c-format msgid " [Version2 EABI]" msgstr "" -#: elf32-arm.c:11792 +#: elf32-arm.c:11846 #, c-format msgid " [dynamic symbols use segment index]" msgstr "" -#: elf32-arm.c:11795 +#: elf32-arm.c:11849 #, c-format msgid " [mapping symbols precede others]" msgstr "" -#: elf32-arm.c:11802 +#: elf32-arm.c:11856 #, c-format msgid " [Version3 EABI]" msgstr "" -#: elf32-arm.c:11806 +#: elf32-arm.c:11860 #, c-format msgid " [Version4 EABI]" msgstr "" -#: elf32-arm.c:11810 +#: elf32-arm.c:11864 #, c-format msgid " [Version5 EABI]" msgstr "" -#: elf32-arm.c:11813 +#: elf32-arm.c:11867 #, c-format msgid " [BE8]" msgstr "" -#: elf32-arm.c:11816 +#: elf32-arm.c:11870 #, c-format msgid " [LE8]" msgstr "" -#: elf32-arm.c:11822 +#: elf32-arm.c:11876 #, c-format msgid " <EABI version unrecognised>" msgstr "" -#: elf32-arm.c:11829 +#: elf32-arm.c:11883 #, c-format msgid " [relocatable executable]" msgstr "" -#: elf32-arm.c:11832 +#: elf32-arm.c:11886 #, c-format msgid " [has entry point]" msgstr "" -#: elf32-arm.c:11837 +#: elf32-arm.c:11891 #, c-format msgid "<Unrecognised flag bits set>" msgstr "" -#: elf32-arm.c:12135 elf32-i386.c:1323 elf32-s390.c:1000 elf32-tic6x.c:2827 -#: elf32-xtensa.c:1009 elf64-s390.c:960 elf64-x86-64.c:1172 elfxx-sparc.c:1370 +#: elf32-arm.c:12189 elf32-i386.c:1461 elf32-s390.c:1000 elf32-tic6x.c:2829 +#: elf32-tilepro.c:1336 elf32-xtensa.c:1009 elf64-s390.c:960 +#: elf64-x86-64.c:1364 elfxx-sparc.c:1371 elfxx-tilegx.c:1586 msgid "%B: bad symbol index: %d" msgstr "" -#: elf32-arm.c:12283 elf64-x86-64.c:1370 elf64-x86-64.c:1541 elfxx-mips.c:7949 +#: elf32-arm.c:12337 elf64-x86-64.c:1561 elf64-x86-64.c:1732 elfxx-mips.c:8223 msgid "" "%B: relocation %s against `%s' can not be used when making a shared object; " "recompile with -fPIC" msgstr "" -#: elf32-arm.c:13412 +#: elf32-arm.c:13460 #, c-format msgid "Errors encountered processing file %s" msgstr "" -#: elf32-arm.c:14795 +#: elf32-arm.c:14837 msgid "%B: error: Cortex-A8 erratum stub is allocated in unsafe location" msgstr "" #. There's not much we can do apart from complain if this #. happens. -#: elf32-arm.c:14822 +#: elf32-arm.c:14864 msgid "%B: error: Cortex-A8 erratum stub out of range (input file too large)" msgstr "" -#: elf32-arm.c:14916 elf32-arm.c:14938 +#: elf32-arm.c:14958 elf32-arm.c:14980 msgid "%B: error: VFP11 veneer out of range" msgstr "" -#: elf32-arm.c:15477 +#: elf32-arm.c:15518 msgid "error: %B is already in final BE8 format" msgstr "" -#: elf32-arm.c:15553 +#: elf32-arm.c:15594 msgid "" "error: Source object %B has EABI version %d, but target %B has EABI version " "%d" msgstr "" -#: elf32-arm.c:15569 +#: elf32-arm.c:15610 msgid "error: %B is compiled for APCS-%d, whereas target %B uses APCS-%d" msgstr "" -#: elf32-arm.c:15594 +#: elf32-arm.c:15635 msgid "error: %B uses VFP instructions, whereas %B does not" msgstr "" -#: elf32-arm.c:15598 +#: elf32-arm.c:15639 msgid "error: %B uses FPA instructions, whereas %B does not" msgstr "" -#: elf32-arm.c:15608 +#: elf32-arm.c:15649 msgid "error: %B uses Maverick instructions, whereas %B does not" msgstr "" -#: elf32-arm.c:15612 +#: elf32-arm.c:15653 msgid "error: %B does not use Maverick instructions, whereas %B does" msgstr "" -#: elf32-arm.c:15631 +#: elf32-arm.c:15672 msgid "error: %B uses software FP, whereas %B uses hardware FP" msgstr "" -#: elf32-arm.c:15635 +#: elf32-arm.c:15676 msgid "error: %B uses hardware FP, whereas %B uses software FP" msgstr "" -#: elf32-avr.c:1229 elf32-bfin.c:3217 elf32-cris.c:2085 elf32-fr30.c:617 -#: elf32-frv.c:4110 elf32-i860.c:1219 elf32-ip2k.c:1479 elf32-iq2000.c:692 -#: elf32-m32c.c:561 elf32-mep.c:543 elf32-moxie.c:290 elf32-msp430.c:494 -#: elf32-mt.c:399 elf32-openrisc.c:412 elf32-v850.c:2151 elf32-xstormy16.c:949 -#: elf64-mmix.c:1530 +#: elf32-avr.c:1229 elf32-bfin.c:3221 elf32-cris.c:2089 elf32-epiphany.c:567 +#: elf32-fr30.c:617 elf32-frv.c:4113 elf32-i860.c:1219 elf32-ip2k.c:1479 +#: elf32-iq2000.c:692 elf32-m32c.c:561 elf32-mep.c:543 elf32-moxie.c:290 +#: elf32-msp430.c:494 elf32-mt.c:399 elf32-openrisc.c:412 elf32-tilepro.c:3222 +#: elf32-v850.c:2151 elf32-xstormy16.c:943 elf64-mmix.c:1598 +#: elfxx-tilegx.c:3585 msgid "internal error: dangerous relocation" msgstr "" @@ -1283,181 +1288,181 @@ msgstr "" msgid "relocation should be even number" msgstr "" -#: elf32-bfin.c:1591 +#: elf32-bfin.c:1593 msgid "%B(%A+0x%lx): unresolvable relocation against symbol `%s'" msgstr "" -#: elf32-bfin.c:1624 elf32-i386.c:4150 elf32-m68k.c:4233 elf32-s390.c:3062 -#: elf64-s390.c:3037 elf64-x86-64.c:3923 +#: elf32-bfin.c:1626 elf32-i386.c:4307 elf32-m68k.c:4233 elf32-s390.c:3055 +#: elf64-s390.c:3030 elf64-x86-64.c:4151 msgid "%B(%A+0x%lx): reloc against `%s': error %d" msgstr "" -#: elf32-bfin.c:2723 +#: elf32-bfin.c:2725 msgid "%B: relocation at `%A+0x%x' references symbol `%s' with nonzero addend" msgstr "" -#: elf32-bfin.c:2737 +#: elf32-bfin.c:2741 msgid "relocation references symbol not defined in the module" msgstr "" -#: elf32-bfin.c:2834 +#: elf32-bfin.c:2838 msgid "R_BFIN_FUNCDESC references dynamic symbol with nonzero addend" msgstr "" -#: elf32-bfin.c:2875 elf32-bfin.c:2998 +#: elf32-bfin.c:2879 elf32-bfin.c:3002 msgid "cannot emit fixups in read-only section" msgstr "" -#: elf32-bfin.c:2906 elf32-bfin.c:3036 elf32-lm32.c:1103 elf32-sh.c:5021 +#: elf32-bfin.c:2910 elf32-bfin.c:3040 elf32-lm32.c:1103 elf32-sh.c:5016 msgid "cannot emit dynamic relocations in read-only section" msgstr "" -#: elf32-bfin.c:2956 +#: elf32-bfin.c:2960 msgid "R_BFIN_FUNCDESC_VALUE references dynamic symbol with nonzero addend" msgstr "" -#: elf32-bfin.c:3121 +#: elf32-bfin.c:3125 msgid "relocations between different segments are not supported" msgstr "" -#: elf32-bfin.c:3122 +#: elf32-bfin.c:3126 msgid "warning: relocation references a different segment" msgstr "" -#: elf32-bfin.c:4967 +#: elf32-bfin.c:4971 msgid "%B: unsupported relocation type %i" msgstr "" -#: elf32-bfin.c:5121 elf32-frv.c:6805 +#: elf32-bfin.c:5125 elf32-frv.c:6808 #, c-format msgid "%s: cannot link non-fdpic object file into fdpic executable" msgstr "" -#: elf32-bfin.c:5125 elf32-frv.c:6809 +#: elf32-bfin.c:5129 elf32-frv.c:6812 #, c-format msgid "%s: cannot link fdpic object file into non-fdpic executable" msgstr "" -#: elf32-bfin.c:5279 +#: elf32-bfin.c:5283 #, c-format msgid "*** check this relocation %s" msgstr "" -#: elf32-cris.c:1172 +#: elf32-cris.c:1176 msgid "%B, section %A: unresolvable relocation %s against symbol `%s'" msgstr "" -#: elf32-cris.c:1234 +#: elf32-cris.c:1238 msgid "%B, section %A: No PLT nor GOT for relocation %s against symbol `%s'" msgstr "" -#: elf32-cris.c:1236 +#: elf32-cris.c:1240 msgid "%B, section %A: No PLT for relocation %s against symbol `%s'" msgstr "" -#: elf32-cris.c:1242 elf32-cris.c:1375 elf32-cris.c:1635 elf32-cris.c:1718 -#: elf32-cris.c:1871 elf32-tic6x.c:2660 +#: elf32-cris.c:1246 elf32-cris.c:1379 elf32-cris.c:1639 elf32-cris.c:1722 +#: elf32-cris.c:1875 elf32-tic6x.c:2662 msgid "[whose name is lost]" msgstr "" -#: elf32-cris.c:1361 elf32-tic6x.c:2645 +#: elf32-cris.c:1365 elf32-tic6x.c:2647 msgid "" "%B, section %A: relocation %s with non-zero addend %d against local symbol" msgstr "" -#: elf32-cris.c:1369 elf32-cris.c:1712 elf32-cris.c:1865 elf32-tic6x.c:2653 +#: elf32-cris.c:1373 elf32-cris.c:1716 elf32-cris.c:1869 elf32-tic6x.c:2655 msgid "" "%B, section %A: relocation %s with non-zero addend %d against symbol `%s'" msgstr "" -#: elf32-cris.c:1395 +#: elf32-cris.c:1399 msgid "%B, section %A: relocation %s is not allowed for global symbol: `%s'" msgstr "" -#: elf32-cris.c:1411 +#: elf32-cris.c:1415 msgid "%B, section %A: relocation %s with no GOT created" msgstr "" #. We shouldn't get here for GCC-emitted code. -#: elf32-cris.c:1626 +#: elf32-cris.c:1630 msgid "" "%B, section %A: relocation %s has an undefined reference to `%s', perhaps a " "declaration mixup?" msgstr "" -#: elf32-cris.c:1998 +#: elf32-cris.c:2002 msgid "" "%B, section %A: relocation %s is not allowed for symbol: `%s' which is " "defined outside the program, perhaps a declaration mixup?" msgstr "" -#: elf32-cris.c:2051 +#: elf32-cris.c:2055 msgid "(too many global variables for -fpic: recompile with -fPIC)" msgstr "" -#: elf32-cris.c:2058 +#: elf32-cris.c:2062 msgid "" "(thread-local data too big for -fpic or -msmall-tls: recompile with -fPIC or " "-mno-small-tls)" msgstr "" -#: elf32-cris.c:3248 +#: elf32-cris.c:3261 msgid "" "%B, section %A:\n" " v10/v32 compatible object %s must not contain a PIC relocation" msgstr "" -#: elf32-cris.c:3353 +#: elf32-cris.c:3366 msgid "" "%B, section %A:\n" " relocation %s not valid in a shared object; typically an option mixup, " "recompile with -fPIC" msgstr "" -#: elf32-cris.c:3567 +#: elf32-cris.c:3580 msgid "" "%B, section %A:\n" " relocation %s should not be used in a shared object; recompile with -fPIC" msgstr "" -#: elf32-cris.c:3992 +#: elf32-cris.c:4002 msgid "" "%B, section `%A', to symbol `%s':\n" " relocation %s should not be used in a shared object; recompile with -fPIC" msgstr "" -#: elf32-cris.c:4111 +#: elf32-cris.c:4118 msgid "Unexpected machine number" msgstr "" -#: elf32-cris.c:4165 +#: elf32-cris.c:4172 #, c-format msgid " [symbols have a _ prefix]" msgstr "" -#: elf32-cris.c:4168 +#: elf32-cris.c:4175 #, c-format msgid " [v10 and v32]" msgstr "" -#: elf32-cris.c:4171 +#: elf32-cris.c:4178 #, c-format msgid " [v32]" msgstr "" -#: elf32-cris.c:4216 +#: elf32-cris.c:4223 msgid "%B: uses _-prefixed symbols, but writing file with non-prefixed symbols" msgstr "" -#: elf32-cris.c:4217 +#: elf32-cris.c:4224 msgid "%B: uses non-prefixed symbols, but writing file with _-prefixed symbols" msgstr "" -#: elf32-cris.c:4236 +#: elf32-cris.c:4243 msgid "%B contains CRIS v32 code, incompatible with previous objects" msgstr "" -#: elf32-cris.c:4238 +#: elf32-cris.c:4245 msgid "%B contains non-CRIS-v32 code, incompatible with previous objects" msgstr "" @@ -1471,6 +1476,11 @@ msgstr "" msgid "BFD Link Error: jump (PC rel26) to section (%s) not supported" msgstr "" +#. Only if it's not an unresolved symbol. +#: elf32-epiphany.c:563 elf32-ip2k.c:1475 +msgid "unsupported relocation between data/insn address spaces" +msgstr "" + #: elf32-frv.c:1509 elf32-frv.c:1658 msgid "relocation requires zero addend" msgstr "" @@ -1479,107 +1489,107 @@ msgstr "" msgid "%H: relocation to `%s+%v' may have caused the error above\n" msgstr "" -#: elf32-frv.c:2902 +#: elf32-frv.c:2905 msgid "%H: relocation references symbol not defined in the module\n" msgstr "" -#: elf32-frv.c:2978 +#: elf32-frv.c:2981 msgid "%H: R_FRV_GETTLSOFF not applied to a call instruction\n" msgstr "" -#: elf32-frv.c:3019 +#: elf32-frv.c:3022 msgid "%H: R_FRV_GOTTLSDESC12 not applied to an lddi instruction\n" msgstr "" -#: elf32-frv.c:3090 +#: elf32-frv.c:3093 msgid "%H: R_FRV_GOTTLSDESCHI not applied to a sethi instruction\n" msgstr "" -#: elf32-frv.c:3127 +#: elf32-frv.c:3130 msgid "%H: R_FRV_GOTTLSDESCLO not applied to a setlo or setlos instruction\n" msgstr "" -#: elf32-frv.c:3174 +#: elf32-frv.c:3177 msgid "%H: R_FRV_TLSDESC_RELAX not applied to an ldd instruction\n" msgstr "" -#: elf32-frv.c:3258 +#: elf32-frv.c:3261 msgid "%H: R_FRV_GETTLSOFF_RELAX not applied to a calll instruction\n" msgstr "" -#: elf32-frv.c:3312 +#: elf32-frv.c:3315 msgid "%H: R_FRV_GOTTLSOFF12 not applied to an ldi instruction\n" msgstr "" -#: elf32-frv.c:3342 +#: elf32-frv.c:3345 msgid "%H: R_FRV_GOTTLSOFFHI not applied to a sethi instruction\n" msgstr "" -#: elf32-frv.c:3371 +#: elf32-frv.c:3374 msgid "%H: R_FRV_GOTTLSOFFLO not applied to a setlo or setlos instruction\n" msgstr "" -#: elf32-frv.c:3401 +#: elf32-frv.c:3404 msgid "%H: R_FRV_TLSOFF_RELAX not applied to an ld instruction\n" msgstr "" -#: elf32-frv.c:3446 +#: elf32-frv.c:3449 msgid "%H: R_FRV_TLSMOFFHI not applied to a sethi instruction\n" msgstr "" -#: elf32-frv.c:3473 +#: elf32-frv.c:3476 msgid "R_FRV_TLSMOFFLO not applied to a setlo or setlos instruction\n" msgstr "" -#: elf32-frv.c:3594 +#: elf32-frv.c:3597 msgid "%H: R_FRV_FUNCDESC references dynamic symbol with nonzero addend\n" msgstr "" -#: elf32-frv.c:3635 elf32-frv.c:3757 +#: elf32-frv.c:3638 elf32-frv.c:3760 msgid "%H: cannot emit fixups in read-only section\n" msgstr "" -#: elf32-frv.c:3666 elf32-frv.c:3800 +#: elf32-frv.c:3669 elf32-frv.c:3803 msgid "%H: cannot emit dynamic relocations in read-only section\n" msgstr "" -#: elf32-frv.c:3715 +#: elf32-frv.c:3718 msgid "" "%H: R_FRV_FUNCDESC_VALUE references dynamic symbol with nonzero addend\n" msgstr "" -#: elf32-frv.c:3971 +#: elf32-frv.c:3974 msgid "%H: reloc against `%s' references a different segment\n" msgstr "" -#: elf32-frv.c:4121 +#: elf32-frv.c:4124 msgid "%H: reloc against `%s': %s\n" msgstr "" -#: elf32-frv.c:6397 +#: elf32-frv.c:6400 msgid "%B: unsupported relocation type %i\n" msgstr "" -#: elf32-frv.c:6719 +#: elf32-frv.c:6722 #, c-format msgid "" "%s: compiled with %s and linked with modules that use non-pic relocations" msgstr "" -#: elf32-frv.c:6772 elf32-iq2000.c:845 elf32-m32c.c:807 +#: elf32-frv.c:6775 elf32-iq2000.c:845 elf32-m32c.c:807 #, c-format msgid "%s: compiled with %s and linked with modules compiled with %s" msgstr "" -#: elf32-frv.c:6784 +#: elf32-frv.c:6787 #, c-format msgid "" "%s: uses different unknown e_flags (0x%lx) fields than previous modules (0x" "%lx)" msgstr "" -#: elf32-frv.c:6834 elf32-iq2000.c:882 elf32-m32c.c:843 elf32-mt.c:576 -#: elf32-rx.c:2937 +#: elf32-frv.c:6837 elf32-iq2000.c:882 elf32-m32c.c:843 elf32-mt.c:576 +#: elf32-rx.c:3001 #, c-format msgid "private flags = 0x%lx:" msgstr "" @@ -1588,7 +1598,7 @@ msgstr "" msgid "%B: Relocations in generic ELF (EM: %d)" msgstr "" -#: elf32-hppa.c:850 elf32-hppa.c:3610 +#: elf32-hppa.c:850 elf32-hppa.c:3598 msgid "%B(%A+0x%lx): cannot reach %s, recompile with -ffunction-sections" msgstr "" @@ -1598,85 +1608,87 @@ msgid "" "with -fPIC" msgstr "" -#: elf32-hppa.c:2803 +#: elf32-hppa.c:2791 msgid "%B: duplicate export stub %s" msgstr "" -#: elf32-hppa.c:3449 +#: elf32-hppa.c:3437 msgid "" "%B(%A+0x%lx): %s fixup for insn 0x%x is not supported in a non-shared link" msgstr "" -#: elf32-hppa.c:4296 +#: elf32-hppa.c:4284 msgid "%B(%A+0x%lx): cannot handle %s for %s" msgstr "" -#: elf32-hppa.c:4608 +#: elf32-hppa.c:4603 msgid ".got section not immediately after .plt section" msgstr "" #. Unknown relocation. -#: elf32-i386.c:372 elf32-m68k.c:383 elf32-ppc.c:1675 elf32-s390.c:379 -#: elf32-tic6x.c:2682 elf64-ppc.c:2285 elf64-s390.c:403 elf64-x86-64.c:243 +#: elf32-i386.c:373 elf32-m68k.c:384 elf32-ppc.c:1676 elf32-s390.c:379 +#: elf32-tic6x.c:2684 elf64-ppc.c:2300 elf64-s390.c:403 elf64-x86-64.c:265 msgid "%B: invalid relocation type %d" msgstr "" -#: elf32-i386.c:1266 elf64-x86-64.c:1116 +#: elf32-i386.c:1404 elf64-x86-64.c:1308 msgid "" "%B: TLS transition from %s to %s against `%s' at 0x%lx in section `%A' failed" msgstr "" -#: elf32-i386.c:1411 elf32-i386.c:3090 elf64-x86-64.c:1296 elf64-x86-64.c:2909 -#: elfxx-sparc.c:3077 +#: elf32-i386.c:1549 elf32-i386.c:3244 elf64-x86-64.c:1487 elf64-x86-64.c:3125 +#: elfxx-sparc.c:3083 msgid "%B: relocation %s against STT_GNU_IFUNC symbol `%s' isn't handled by %s" msgstr "" -#: elf32-i386.c:1573 elf32-s390.c:1182 elf32-sh.c:6367 elf32-xtensa.c:1182 -#: elf64-s390.c:1151 elfxx-sparc.c:1547 +#: elf32-i386.c:1711 elf32-s390.c:1182 elf32-sh.c:6362 elf32-tilepro.c:1434 +#: elf32-xtensa.c:1182 elf64-s390.c:1151 elfxx-sparc.c:1548 +#: elfxx-tilegx.c:1701 msgid "%B: `%s' accessed both as normal and thread local symbol" msgstr "" -#: elf32-i386.c:2405 elf64-x86-64.c:2320 +#: elf32-i386.c:2539 elf64-x86-64.c:2506 msgid "%P: %B: warning: relocation against `%s' in readonly section `%A'.\n" msgstr "" -#: elf32-i386.c:2496 elf64-x86-64.c:2407 +#: elf32-i386.c:2629 elf64-x86-64.c:2593 msgid "%P: %B: warning: relocation in readonly section `%A'.\n" msgstr "" -#: elf32-i386.c:2932 +#: elf32-i386.c:3086 elf32-tilepro.c:2557 elfxx-tilegx.c:2871 msgid "%B: unrecognized relocation (0x%x) in section `%A'" msgstr "" -#: elf32-i386.c:3339 elf64-x86-64.c:3295 +#: elf32-i386.c:3494 elf64-x86-64.c:3513 msgid "hidden symbol" msgstr "" -#: elf32-i386.c:3342 elf64-x86-64.c:3298 +#: elf32-i386.c:3497 elf64-x86-64.c:3516 msgid "internal symbol" msgstr "" -#: elf32-i386.c:3345 elf64-x86-64.c:3301 +#: elf32-i386.c:3500 elf64-x86-64.c:3519 msgid "protected symbol" msgstr "" -#: elf32-i386.c:3348 elf64-x86-64.c:3304 +#: elf32-i386.c:3503 elf64-x86-64.c:3522 msgid "symbol" msgstr "" -#: elf32-i386.c:3353 +#: elf32-i386.c:3508 msgid "" "%B: relocation R_386_GOTOFF against undefined %s `%s' can not be used when " "making a shared object" msgstr "" -#: elf32-i386.c:3363 +#: elf32-i386.c:3518 msgid "" "%B: relocation R_386_GOTOFF against protected function `%s' can not be used " "when making a shared object" msgstr "" -#: elf32-i386.c:4660 elf64-x86-64.c:4378 +#: elf32-i386.c:4839 elf32-tilepro.c:3467 elf64-x86-64.c:4609 +#: elfxx-tilegx.c:3847 #, c-format msgid "discarded output section: `%A'" msgstr "" @@ -1700,11 +1712,6 @@ msgstr "" msgid "ip2k linker: redundant page instruction at 0x%08lx (dest = 0x%08lx)." msgstr "" -#. Only if it's not an unresolved symbol. -#: elf32-ip2k.c:1475 -msgid "unsupported relocation between data/insn address spaces" -msgstr "" - #: elf32-iq2000.c:858 elf32-m32c.c:819 #, c-format msgid "%s: uses different e_flags (0x%lx) fields than previous modules (0x%lx)" @@ -1726,30 +1733,30 @@ msgstr "" msgid "SDA relocation when _SDA_BASE_ not defined" msgstr "" -#: elf32-m32r.c:3048 +#: elf32-m32r.c:3043 msgid "%B: The target (%s) of an %s relocation is in the wrong section (%A)" msgstr "" -#: elf32-m32r.c:3576 +#: elf32-m32r.c:3571 msgid "%B: Instruction set mismatch with previous modules" msgstr "" -#: elf32-m32r.c:3597 +#: elf32-m32r.c:3592 #, c-format msgid "private flags = %lx" msgstr "" -#: elf32-m32r.c:3602 +#: elf32-m32r.c:3597 #, c-format msgid ": m32r instructions" msgstr "" -#: elf32-m32r.c:3603 +#: elf32-m32r.c:3598 #, c-format msgid ": m32rx instructions" msgstr "" -#: elf32-m32r.c:3604 +#: elf32-m32r.c:3599 #, c-format msgid ": m32r2 instructions" msgstr "" @@ -1791,7 +1798,7 @@ msgstr "" msgid "%B: linking files compiled for HCS12 with others compiled for HC12" msgstr "" -#: elf32-m68hc1x.c:1257 elf32-ppc.c:4214 elf64-sparc.c:705 elfxx-mips.c:12719 +#: elf32-m68hc1x.c:1257 elf32-ppc.c:4227 elf64-sparc.c:706 elfxx-mips.c:13965 msgid "%B: uses different e_flags (0x%lx) fields than previous modules (0x%lx)" msgstr "" @@ -1840,19 +1847,19 @@ msgstr "" msgid " [memory=flat]" msgstr "" -#: elf32-m68k.c:1250 elf32-m68k.c:1251 vms-alpha.c:7311 vms-alpha.c:7326 +#: elf32-m68k.c:1251 elf32-m68k.c:1252 vms-alpha.c:7314 vms-alpha.c:7329 msgid "unknown" msgstr "" -#: elf32-m68k.c:1714 +#: elf32-m68k.c:1715 msgid "%B: GOT overflow: Number of relocations with 8-bit offset > %d" msgstr "" -#: elf32-m68k.c:1720 +#: elf32-m68k.c:1721 msgid "%B: GOT overflow: Number of relocations with 8- or 16-bit offset > %d" msgstr "" -#: elf32-m68k.c:3959 +#: elf32-m68k.c:3957 msgid "%B(%A+0x%lx): R_68K_TLS_LE32 relocation not permitted in shared object" msgstr "" @@ -1898,7 +1905,8 @@ msgstr "" msgid "%s: The target (%s) of an %s relocation is in the wrong section (%s)" msgstr "" -#: elf32-microblaze.c:1155 elfxx-sparc.c:3451 +#: elf32-microblaze.c:1155 elf32-tilepro.c:2891 elfxx-sparc.c:3457 +#: elfxx-tilegx.c:3230 msgid "%B: probably compiled without -fPIC?" msgstr "" @@ -1906,224 +1914,235 @@ msgstr "" msgid "%B: bad relocation section name `%s'" msgstr "" -#: elf32-mips.c:1045 elf64-mips.c:2084 elfn32-mips.c:1888 +#: elf32-mips.c:1549 elf64-mips.c:2683 elfn32-mips.c:2487 msgid "literal relocation occurs for an external symbol" msgstr "" -#: elf32-mips.c:1085 elf32-score.c:569 elf32-score7.c:469 elf64-mips.c:2127 -#: elfn32-mips.c:1929 +#: elf32-mips.c:1596 elf32-score.c:570 elf32-score7.c:469 elf64-mips.c:2726 +#: elfn32-mips.c:2528 msgid "32bits gp relative relocation occurs for an external symbol" msgstr "" -#: elf32-ppc.c:1740 +#: elf32-ppc.c:1741 #, c-format msgid "generic linker can't handle %s" msgstr "" -#: elf32-ppc.c:2183 +#: elf32-ppc.c:2184 msgid "corrupt %s section in %B" msgstr "" -#: elf32-ppc.c:2202 +#: elf32-ppc.c:2203 msgid "unable to read in %s section from %B" msgstr "" -#: elf32-ppc.c:2243 +#: elf32-ppc.c:2244 msgid "warning: unable to set size of %s section in %B" msgstr "" -#: elf32-ppc.c:2293 +#: elf32-ppc.c:2294 msgid "failed to allocate space for new APUinfo section." msgstr "" -#: elf32-ppc.c:2312 +#: elf32-ppc.c:2313 msgid "failed to compute new APUinfo section." msgstr "" -#: elf32-ppc.c:2315 +#: elf32-ppc.c:2316 msgid "failed to install new APUinfo section." msgstr "" -#: elf32-ppc.c:3343 +#: elf32-ppc.c:3356 msgid "%B: relocation %s cannot be used when making a shared object" msgstr "" #. It does not make sense to have a procedure linkage #. table entry for a local symbol. -#: elf32-ppc.c:3687 -msgid "%H: %s reloc against local symbol\n" +#: elf32-ppc.c:3700 +msgid "%P: %H: %s reloc against local symbol\n" msgstr "" -#: elf32-ppc.c:4026 elf32-ppc.c:4041 elfxx-mips.c:12423 elfxx-mips.c:12449 -#: elfxx-mips.c:12471 elfxx-mips.c:12497 +#: elf32-ppc.c:4039 elf32-ppc.c:4054 elfxx-mips.c:13651 elfxx-mips.c:13677 +#: elfxx-mips.c:13699 elfxx-mips.c:13725 msgid "Warning: %B uses hard float, %B uses soft float" msgstr "" -#: elf32-ppc.c:4029 elf32-ppc.c:4033 +#: elf32-ppc.c:4042 elf32-ppc.c:4046 msgid "" "Warning: %B uses double-precision hard float, %B uses single-precision hard " "float" msgstr "" -#: elf32-ppc.c:4037 +#: elf32-ppc.c:4050 msgid "Warning: %B uses soft float, %B uses single-precision hard float" msgstr "" -#: elf32-ppc.c:4044 elf32-ppc.c:4048 elfxx-mips.c:12403 elfxx-mips.c:12407 +#: elf32-ppc.c:4057 elf32-ppc.c:4061 elfxx-mips.c:13631 elfxx-mips.c:13635 msgid "Warning: %B uses unknown floating point ABI %d" msgstr "" -#: elf32-ppc.c:4090 elf32-ppc.c:4094 +#: elf32-ppc.c:4103 elf32-ppc.c:4107 msgid "Warning: %B uses unknown vector ABI %d" msgstr "" -#: elf32-ppc.c:4098 +#: elf32-ppc.c:4111 msgid "Warning: %B uses vector ABI \"%s\", %B uses \"%s\"" msgstr "" -#: elf32-ppc.c:4115 elf32-ppc.c:4118 +#: elf32-ppc.c:4128 elf32-ppc.c:4131 msgid "Warning: %B uses r3/r4 for small structure returns, %B uses memory" msgstr "" -#: elf32-ppc.c:4121 elf32-ppc.c:4125 +#: elf32-ppc.c:4134 elf32-ppc.c:4138 msgid "Warning: %B uses unknown small structure return convention %d" msgstr "" -#: elf32-ppc.c:4179 +#: elf32-ppc.c:4192 msgid "" "%B: compiled with -mrelocatable and linked with modules compiled normally" msgstr "" -#: elf32-ppc.c:4187 +#: elf32-ppc.c:4200 msgid "" "%B: compiled normally and linked with modules compiled with -mrelocatable" msgstr "" -#: elf32-ppc.c:4275 -msgid "Using bss-plt due to %B" +#: elf32-ppc.c:4309 +msgid "%P: bss-plt forced due to %B\n" +msgstr "" + +#: elf32-ppc.c:4312 +msgid "%P: bss-plt forced by profiling\n" msgstr "" #. Uh oh, we didn't find the expected call. We #. could just mark this symbol to exclude it #. from tls optimization but it's safer to skip #. the entire optimization. -#: elf32-ppc.c:4771 elf64-ppc.c:7778 +#: elf32-ppc.c:4809 elf64-ppc.c:7858 msgid "%H arg lost __tls_get_addr, TLS optimization disabled\n" msgstr "" -#: elf32-ppc.c:5006 elf64-ppc.c:6494 -#, c-format -msgid "dynamic variable `%s' is zero size\n" +#: elf32-ppc.c:5044 elf64-ppc.c:6528 +msgid "%P: dynamic variable `%s' is zero size\n" msgstr "" -#: elf32-ppc.c:7204 elf64-ppc.c:12431 -msgid "%B: unknown relocation type %d for symbol %s\n" +#: elf32-ppc.c:7263 elf64-ppc.c:12675 +msgid "%P: %B: unknown relocation type %d for symbol %s\n" msgstr "" -#: elf32-ppc.c:7465 -msgid "%H: non-zero addend on %s reloc against `%s'\n" +#: elf32-ppc.c:7524 +msgid "%P: %H: non-zero addend on %s reloc against `%s'\n" msgstr "" -#: elf32-ppc.c:7661 elf64-ppc.c:12936 -msgid "%H: relocation %s for indirect function %s unsupported\n" +#: elf32-ppc.c:7720 elf64-ppc.c:13181 +msgid "%P: %H: relocation %s for indirect function %s unsupported\n" msgstr "" -#: elf32-ppc.c:7889 elf32-ppc.c:7919 elf32-ppc.c:7966 +#: elf32-ppc.c:7948 elf32-ppc.c:7978 elf32-ppc.c:8025 msgid "" -"%B: the target (%s) of a %s relocation is in the wrong output section (%s)\n" +"%P: %B: the target (%s) of a %s relocation is in the wrong output section " +"(%s)\n" msgstr "" -#: elf32-ppc.c:8038 -msgid "%B: relocation %s is not yet supported for symbol %s\n" +#: elf32-ppc.c:8097 +msgid "%P: %B: relocation %s is not yet supported for symbol %s\n" msgstr "" -#: elf32-ppc.c:8097 elf64-ppc.c:13237 -msgid "%H: unresolvable %s relocation against symbol `%s'\n" +#: elf32-ppc.c:8158 elf64-ppc.c:13467 +msgid "%P: %H: unresolvable %s relocation against symbol `%s'\n" msgstr "" -#: elf32-ppc.c:8144 elf64-ppc.c:13282 -msgid "%H: %s reloc against `%s': error %d\n" +#: elf32-ppc.c:8205 elf64-ppc.c:13512 +msgid "%P: %H: %s reloc against `%s': error %d\n" msgstr "" -#: elf32-ppc.c:8635 -#, c-format -msgid "%s not defined in linker created %s\n" +#: elf32-ppc.c:8696 +msgid "%P: %s not defined in linker created %s\n" msgstr "" -#: elf32-rx.c:553 +#: elf32-rx.c:563 msgid "%B:%A: Warning: deprecated Red Hat reloc " msgstr "" -#: elf32-rx.c:1095 +#. Check for unsafe relocs in PID mode. These are any relocs where +#. an absolute address is being computed. There are special cases +#. for relocs against symbols that are known to be referenced in +#. crt0.o before the PID base address register has been initialised. +#: elf32-rx.c:581 +msgid "%B(%A): unsafe PID relocation %s at 0x%08lx (against %s in %s)" +msgstr "" + +#: elf32-rx.c:1157 msgid "Warning: RX_SYM reloc with an unknown symbol" msgstr "" -#: elf32-rx.c:1260 +#: elf32-rx.c:1324 msgid "%B(%A): error: call to undefined function '%s'" msgstr "" -#: elf32-rx.c:1274 +#: elf32-rx.c:1338 msgid "%B(%A): warning: unaligned access to symbol '%s' in the small data area" msgstr "" -#: elf32-rx.c:1278 +#: elf32-rx.c:1342 msgid "%B(%A): internal error: out of range error" msgstr "" -#: elf32-rx.c:1282 +#: elf32-rx.c:1346 msgid "%B(%A): internal error: unsupported relocation error" msgstr "" -#: elf32-rx.c:1286 +#: elf32-rx.c:1350 msgid "%B(%A): internal error: dangerous relocation" msgstr "" -#: elf32-rx.c:1290 +#: elf32-rx.c:1354 msgid "%B(%A): internal error: unknown error" msgstr "" -#: elf32-rx.c:2940 +#: elf32-rx.c:3004 #, c-format msgid " [64-bit doubles]" msgstr "" -#: elf32-rx.c:2942 +#: elf32-rx.c:3006 #, c-format msgid " [dsp]" msgstr "" -#: elf32-s390.c:2209 elf64-s390.c:2196 +#: elf32-s390.c:2200 elf64-s390.c:2187 msgid "%B(%A+0x%lx): invalid instruction for TLS relocation %s" msgstr "" -#: elf32-score.c:1522 elf32-score7.c:1382 elfxx-mips.c:3324 +#: elf32-score.c:1520 elf32-score7.c:1379 elfxx-mips.c:3435 msgid "not enough GOT space for local GOT entries" msgstr "" -#: elf32-score.c:2744 +#: elf32-score.c:2742 msgid "address not word align" msgstr "" -#: elf32-score.c:2829 elf32-score7.c:2634 +#: elf32-score.c:2827 elf32-score7.c:2631 #, c-format msgid "%s: Malformed reloc detected for section %s" msgstr "" -#: elf32-score.c:2880 elf32-score7.c:2685 +#: elf32-score.c:2878 elf32-score7.c:2682 msgid "%B: CALL15 reloc at 0x%lx not against global symbol" msgstr "" -#: elf32-score.c:3999 elf32-score7.c:3806 +#: elf32-score.c:3997 elf32-score7.c:3803 #, c-format msgid " [pic]" msgstr "" -#: elf32-score.c:4003 elf32-score7.c:3810 +#: elf32-score.c:4001 elf32-score7.c:3807 #, c-format msgid " [fix dep]" msgstr "" -#: elf32-score.c:4045 elf32-score7.c:3852 +#: elf32-score.c:4043 elf32-score7.c:3849 msgid "%B: warning: linking PIC files with non-PIC files" msgstr "" @@ -2171,76 +2190,76 @@ msgstr "" msgid "%B: 0x%lx: fatal: reloc overflow while relaxing" msgstr "" -#: elf32-sh.c:4057 elf64-sh64.c:1514 +#: elf32-sh.c:4048 elf64-sh64.c:1514 msgid "Unexpected STO_SH5_ISA32 on local symbol is not handled" msgstr "" -#: elf32-sh.c:4304 +#: elf32-sh.c:4299 msgid "%B: 0x%lx: fatal: unaligned branch target for relax-support relocation" msgstr "" -#: elf32-sh.c:4337 elf32-sh.c:4352 +#: elf32-sh.c:4332 elf32-sh.c:4347 msgid "%B: 0x%lx: fatal: unaligned %s relocation 0x%lx" msgstr "" -#: elf32-sh.c:4366 +#: elf32-sh.c:4361 msgid "%B: 0x%lx: fatal: R_SH_PSHA relocation %d not in range -32..32" msgstr "" -#: elf32-sh.c:4380 +#: elf32-sh.c:4375 msgid "%B: 0x%lx: fatal: R_SH_PSHL relocation %d not in range -32..32" msgstr "" -#: elf32-sh.c:4524 elf32-sh.c:4994 +#: elf32-sh.c:4519 elf32-sh.c:4989 msgid "%B(%A+0x%lx): cannot emit fixup to `%s' in read-only section" msgstr "" -#: elf32-sh.c:5101 +#: elf32-sh.c:5096 msgid "%B(%A+0x%lx): %s relocation against external symbol \"%s\"" msgstr "" -#: elf32-sh.c:5574 +#: elf32-sh.c:5569 #, c-format msgid "%X%C: relocation to \"%s\" references a different segment\n" msgstr "" -#: elf32-sh.c:5580 +#: elf32-sh.c:5575 #, c-format msgid "%C: warning: relocation to \"%s\" references a different segment\n" msgstr "" -#: elf32-sh.c:6358 elf32-sh.c:6441 +#: elf32-sh.c:6353 elf32-sh.c:6436 msgid "%B: `%s' accessed both as normal and FDPIC symbol" msgstr "" -#: elf32-sh.c:6363 elf32-sh.c:6445 +#: elf32-sh.c:6358 elf32-sh.c:6440 msgid "%B: `%s' accessed both as FDPIC and thread local symbol" msgstr "" -#: elf32-sh.c:6393 +#: elf32-sh.c:6388 msgid "%B: Function descriptor relocation with non-zero addend" msgstr "" -#: elf32-sh.c:6629 elf64-alpha.c:4648 +#: elf32-sh.c:6624 elf64-alpha.c:4652 msgid "%B: TLS local exec code cannot be linked into shared objects" msgstr "" -#: elf32-sh64.c:223 elf64-sh64.c:2314 +#: elf32-sh64.c:223 elf64-sh64.c:2318 #, c-format msgid "%s: compiled as 32-bit object and %s is 64-bit" msgstr "" -#: elf32-sh64.c:226 elf64-sh64.c:2317 +#: elf32-sh64.c:226 elf64-sh64.c:2321 #, c-format msgid "%s: compiled as 64-bit object and %s is 32-bit" msgstr "" -#: elf32-sh64.c:228 elf64-sh64.c:2319 +#: elf32-sh64.c:228 elf64-sh64.c:2323 #, c-format msgid "%s: object size does not match that of target %s" msgstr "" -#: elf32-sh64.c:451 elf64-sh64.c:2833 +#: elf32-sh64.c:451 elf64-sh64.c:2837 #, c-format msgid "%s: encountered datalabel symbol in input" msgstr "" @@ -2272,11 +2291,11 @@ msgstr "" msgid "%s: could not write out sorted .cranges entries" msgstr "" -#: elf32-sparc.c:89 +#: elf32-sparc.c:90 msgid "%B: compiled for a 64 bit system and target is 32 bit" msgstr "" -#: elf32-sparc.c:102 +#: elf32-sparc.c:103 msgid "%B: linking little endian files with big endian files" msgstr "" @@ -2408,7 +2427,7 @@ msgstr "" msgid "fatal error while creating .fixup" msgstr "" -#: elf32-spu.c:5006 +#: elf32-spu.c:5008 msgid "%B(%s+0x%lx): unresolvable %s relocation against symbol `%s'" msgstr "" @@ -2420,43 +2439,43 @@ msgstr "" msgid "warning: generating a shared library containing non-PID code" msgstr "" -#: elf32-tic6x.c:2539 +#: elf32-tic6x.c:2541 msgid "%B: SB-relative relocation but __c6xabi_DSBT_BASE not defined" msgstr "" -#: elf32-tic6x.c:2759 +#: elf32-tic6x.c:2761 msgid "dangerous relocation" msgstr "" -#: elf32-tic6x.c:3740 +#: elf32-tic6x.c:3733 msgid "%B: error: unknown mandatory EABI object attribute %d" msgstr "" -#: elf32-tic6x.c:3748 +#: elf32-tic6x.c:3741 msgid "%B: warning: unknown EABI object attribute %d" msgstr "" -#: elf32-tic6x.c:3860 elf32-tic6x.c:3868 +#: elf32-tic6x.c:3853 elf32-tic6x.c:3861 msgid "error: %B requires more stack alignment than %B preserves" msgstr "" -#: elf32-tic6x.c:3878 elf32-tic6x.c:3887 +#: elf32-tic6x.c:3871 elf32-tic6x.c:3880 msgid "error: unknown Tag_ABI_array_object_alignment value in %B" msgstr "" -#: elf32-tic6x.c:3896 elf32-tic6x.c:3905 +#: elf32-tic6x.c:3889 elf32-tic6x.c:3898 msgid "error: unknown Tag_ABI_array_object_align_expected value in %B" msgstr "" -#: elf32-tic6x.c:3913 elf32-tic6x.c:3920 +#: elf32-tic6x.c:3906 elf32-tic6x.c:3913 msgid "error: %B requires more array alignment than %B preserves" msgstr "" -#: elf32-tic6x.c:3942 +#: elf32-tic6x.c:3935 msgid "warning: %B and %B differ in wchar_t size" msgstr "" -#: elf32-tic6x.c:3960 +#: elf32-tic6x.c:3953 msgid "warning: %B and %B differ in whether code is compiled for DSBT" msgstr "" @@ -2540,44 +2559,44 @@ msgstr "" msgid "v850e2v3 architecture" msgstr "" -#: elf32-vax.c:531 +#: elf32-vax.c:532 #, c-format msgid " [nonpic]" msgstr "" -#: elf32-vax.c:534 +#: elf32-vax.c:535 #, c-format msgid " [d-float]" msgstr "" -#: elf32-vax.c:537 +#: elf32-vax.c:538 #, c-format msgid " [g-float]" msgstr "" -#: elf32-vax.c:654 +#: elf32-vax.c:655 #, c-format msgid "" "%s: warning: GOT addend of %ld to `%s' does not match previous GOT addend of " "%ld" msgstr "" -#: elf32-vax.c:1587 +#: elf32-vax.c:1585 #, c-format msgid "%s: warning: PLT addend of %d to `%s' from %s section ignored" msgstr "" -#: elf32-vax.c:1714 +#: elf32-vax.c:1712 #, c-format msgid "%s: warning: %s relocation against symbol `%s' from %s section" msgstr "" -#: elf32-vax.c:1720 +#: elf32-vax.c:1718 #, c-format msgid "%s: warning: %s relocation to 0x%x from %s section" msgstr "" -#: elf32-xstormy16.c:451 elf32-ia64.c:2342 elf64-ia64.c:2342 +#: elf32-xstormy16.c:451 elf32-ia64.c:2336 elf64-ia64.c:2336 msgid "non-zero addend in @fptr reloc" msgstr "" @@ -2585,50 +2604,50 @@ msgstr "" msgid "%B(%A): invalid property table" msgstr "" -#: elf32-xtensa.c:2780 +#: elf32-xtensa.c:2777 msgid "%B(%A+0x%lx): relocation offset out of range (size=0x%x)" msgstr "" -#: elf32-xtensa.c:2859 elf32-xtensa.c:2980 +#: elf32-xtensa.c:2856 elf32-xtensa.c:2977 msgid "dynamic relocation in read-only section" msgstr "" -#: elf32-xtensa.c:2956 +#: elf32-xtensa.c:2953 msgid "TLS relocation invalid without dynamic sections" msgstr "" -#: elf32-xtensa.c:3173 +#: elf32-xtensa.c:3172 msgid "internal inconsistency in size of .got.loc section" msgstr "" -#: elf32-xtensa.c:3486 +#: elf32-xtensa.c:3485 msgid "%B: incompatible machine type. Output is 0x%x. Input is 0x%x" msgstr "" -#: elf32-xtensa.c:4715 elf32-xtensa.c:4723 +#: elf32-xtensa.c:4714 elf32-xtensa.c:4722 msgid "Attempt to convert L32R/CALLX to CALL failed" msgstr "" -#: elf32-xtensa.c:6333 elf32-xtensa.c:6409 elf32-xtensa.c:7525 +#: elf32-xtensa.c:6332 elf32-xtensa.c:6408 elf32-xtensa.c:7524 msgid "" "%B(%A+0x%lx): could not decode instruction; possible configuration mismatch" msgstr "" -#: elf32-xtensa.c:7265 +#: elf32-xtensa.c:7264 msgid "" "%B(%A+0x%lx): could not decode instruction for XTENSA_ASM_SIMPLIFY " "relocation; possible configuration mismatch" msgstr "" -#: elf32-xtensa.c:9024 +#: elf32-xtensa.c:9023 msgid "invalid relocation address" msgstr "" -#: elf32-xtensa.c:9073 +#: elf32-xtensa.c:9072 msgid "overflow after relaxation" msgstr "" -#: elf32-xtensa.c:10205 +#: elf32-xtensa.c:10204 msgid "%B(%A+0x%lx): unexpected fix for %s relocation" msgstr "" @@ -2636,27 +2655,27 @@ msgstr "" msgid "GPDISP relocation did not find ldah and lda instructions" msgstr "" -#: elf64-alpha.c:2495 +#: elf64-alpha.c:2497 msgid "%B: .got subsegment exceeds 64K (size %d)" msgstr "" -#: elf64-alpha.c:4392 elf64-alpha.c:4404 +#: elf64-alpha.c:4387 elf64-alpha.c:4399 msgid "%B: gp-relative relocation against dynamic symbol %s" msgstr "" -#: elf64-alpha.c:4430 elf64-alpha.c:4565 +#: elf64-alpha.c:4425 elf64-alpha.c:4565 msgid "%B: pc-relative relocation against dynamic symbol %s" msgstr "" -#: elf64-alpha.c:4458 +#: elf64-alpha.c:4453 msgid "%B: change in gp: BRSGP %s" msgstr "" -#: elf64-alpha.c:4483 +#: elf64-alpha.c:4478 msgid "<unknown>" msgstr "" -#: elf64-alpha.c:4488 +#: elf64-alpha.c:4483 msgid "%B: !samegp reloc against symbol without .prologue: %s" msgstr "" @@ -2668,24 +2687,38 @@ msgstr "" msgid "%B: pc-relative relocation against undefined weak symbol %s" msgstr "" -#: elf64-alpha.c:4632 +#: elf64-alpha.c:4636 msgid "%B: dtp-relative relocation against dynamic symbol %s" msgstr "" -#: elf64-alpha.c:4655 +#: elf64-alpha.c:4659 msgid "%B: tp-relative relocation against dynamic symbol %s" msgstr "" -#: elf64-hppa.c:2094 +#: elf64-hppa.c:2083 #, c-format msgid "stub entry for %s cannot load .plt, dp offset = %ld" msgstr "" -#: elf64-hppa.c:3292 -msgid "%B(%A+0x%lx): cannot reach %s" +#: elf64-hppa.c:3275 +msgid "%B(%A+0x" +msgstr "" + +#: elf64-mmix.c:1034 +msgid "" +"invalid input relocation when producing non-ELF, non-mmo format output.\n" +" Please use the objcopy program to convert from ELF or mmo,\n" +" or assemble using \"-no-expand\" (for gcc, \"-Wa,-no-expand\"" +msgstr "" + +#: elf64-mmix.c:1218 +msgid "" +"invalid input relocation when producing non-ELF, non-mmo format output.\n" +" Please use the objcopy program to convert from ELF or mmo,\n" +" or compile using the gcc-option \"-mno-base-addresses\"." msgstr "" -#: elf64-mmix.c:1177 +#: elf64-mmix.c:1244 #, c-format msgid "" "%s: Internal inconsistency error for value for\n" @@ -2693,135 +2726,133 @@ msgid "" "%08lx\n" msgstr "" -#: elf64-mmix.c:1607 +#: elf64-mmix.c:1670 #, c-format msgid "" "%s: base-plus-offset relocation against register symbol: (unknown) in %s" msgstr "" -#: elf64-mmix.c:1612 +#: elf64-mmix.c:1675 #, c-format msgid "%s: base-plus-offset relocation against register symbol: %s in %s" msgstr "" -#: elf64-mmix.c:1656 +#: elf64-mmix.c:1719 #, c-format msgid "%s: register relocation against non-register symbol: (unknown) in %s" msgstr "" -#: elf64-mmix.c:1661 +#: elf64-mmix.c:1724 #, c-format msgid "%s: register relocation against non-register symbol: %s in %s" msgstr "" -#: elf64-mmix.c:1698 +#: elf64-mmix.c:1761 #, c-format msgid "%s: directive LOCAL valid only with a register or absolute value" msgstr "" -#: elf64-mmix.c:1726 +#: elf64-mmix.c:1789 #, c-format msgid "" "%s: LOCAL directive: Register $%ld is not a local register. First global " "register is $%ld." msgstr "" -#: elf64-mmix.c:2190 +#: elf64-mmix.c:2253 #, c-format msgid "" "%s: Error: multiple definition of `%s'; start of %s is set in a earlier " "linked file\n" msgstr "" -#: elf64-mmix.c:2248 +#: elf64-mmix.c:2311 msgid "Register section has contents\n" msgstr "" -#: elf64-mmix.c:2440 +#: elf64-mmix.c:2503 #, c-format msgid "" "Internal inconsistency: remaining %u != max %u.\n" " Please report this bug." msgstr "" -#: elf64-ppc.c:2744 libbfd.c:1012 -msgid "%B: compiled for a big endian system and target is little endian" -msgstr "" - -#: elf64-ppc.c:2747 libbfd.c:1014 -msgid "%B: compiled for a little endian system and target is big endian" +#: elf64-ppc.c:4185 +msgid "%P: %B: cannot create stub entry %s\n" msgstr "" -#: elf64-ppc.c:4160 -msgid "%B: cannot create stub entry %s\n" -msgstr "" - -#: elf64-ppc.c:6484 -#, c-format +#: elf64-ppc.c:6518 msgid "" -"copy reloc against `%s' requires lazy plt linking; avoid setting " +"%P: copy reloc against `%s' requires lazy plt linking; avoid setting " "LD_BIND_NOW=1 or upgrade gcc\n" msgstr "" -#: elf64-ppc.c:6912 -msgid "dynreloc miscount for %B, section %A\n" +#: elf64-ppc.c:6788 +msgid "%B: undefined symbol on R_PPC64_TOCSAVE relocation" +msgstr "" + +#: elf64-ppc.c:6992 +msgid "%P: dynreloc miscount for %B, section %A\n" msgstr "" -#: elf64-ppc.c:6996 +#: elf64-ppc.c:7076 msgid "%B: .opd is not a regular array of opd entries" msgstr "" -#: elf64-ppc.c:7005 +#: elf64-ppc.c:7085 msgid "%B: unexpected reloc type %u in .opd section" msgstr "" -#: elf64-ppc.c:7026 +#: elf64-ppc.c:7106 msgid "%B: undefined sym `%s' in .opd section" msgstr "" -#: elf64-ppc.c:7584 +#: elf64-ppc.c:7664 msgid "%H __tls_get_addr lost arg, TLS optimization disabled\n" msgstr "" -#: elf64-ppc.c:7929 elf64-ppc.c:8450 +#: elf64-ppc.c:8003 elf64-ppc.c:8564 #, c-format msgid "%s defined on removed toc entry" msgstr "" -#: elf64-ppc.c:9474 -#, c-format -msgid "cannot find opd entry toc for %s\n" +#: elf64-ppc.c:8521 +msgid "%P: %H: %s relocation references optimized away TOC entry\n" msgstr "" -#: elf64-ppc.c:9556 -#, c-format -msgid "long branch stub `%s' offset overflow\n" +#: elf64-ppc.c:9598 +msgid "%P: cannot find opd entry toc for %s\n" msgstr "" -#: elf64-ppc.c:9615 -#, c-format -msgid "can't find branch stub `%s'\n" +#: elf64-ppc.c:9680 +msgid "%P: long branch stub `%s' offset overflow\n" msgstr "" -#: elf64-ppc.c:9677 elf64-ppc.c:9819 -#, c-format -msgid "linkage table error against `%s'\n" +#: elf64-ppc.c:9739 +msgid "%P: can't find branch stub `%s'\n" msgstr "" -#: elf64-ppc.c:9993 -#, c-format -msgid "can't build branch stub `%s'\n" +#: elf64-ppc.c:9801 elf64-ppc.c:9943 +msgid "%P: linkage table error against `%s'\n" +msgstr "" + +#: elf64-ppc.c:10126 +msgid "%P: can't build branch stub `%s'\n" msgstr "" -#: elf64-ppc.c:10814 +#: elf64-ppc.c:10941 msgid "%B section %A exceeds stub group size" msgstr "" -#: elf64-ppc.c:11457 -msgid "stubs don't match calculated size\n" +#: elf64-ppc.c:11666 elf64-ppc.c:11699 +msgid "%P: %s offset too large for .eh_frame sdata4 encoding" msgstr "" -#: elf64-ppc.c:11469 +#: elf64-ppc.c:11744 +msgid "%P: stubs don't match calculated size\n" +msgstr "" + +#: elf64-ppc.c:11756 #, c-format msgid "" "linker stubs in %u group%s\n" @@ -2832,106 +2863,106 @@ msgid "" " plt call %lu" msgstr "" -#: elf64-ppc.c:11819 -msgid "%H: %s used with TLS symbol %s\n" +#: elf64-ppc.c:12042 +msgid "%P: %H: %s used with TLS symbol %s\n" msgstr "" -#: elf64-ppc.c:11820 -msgid "%H: %s used with non-TLS symbol %s\n" +#: elf64-ppc.c:12043 +msgid "%P: %H: %s used with non-TLS symbol %s\n" msgstr "" -#: elf64-ppc.c:12318 +#: elf64-ppc.c:12556 msgid "" -"%H: automatic multiple TOCs not supported using your crt files; recompile " -"with -mminimal-toc or upgrade gcc\n" +"%P: %H: automatic multiple TOCs not supported using your crt files; " +"recompile with -mminimal-toc or upgrade gcc\n" msgstr "" -#: elf64-ppc.c:12324 +#: elf64-ppc.c:12562 msgid "" -"%H: sibling call optimization to `%s' does not allow automatic multiple " +"%P: %H: sibling call optimization to `%s' does not allow automatic multiple " "TOCs; recompile with -mminimal-toc or -fno-optimize-sibling-calls, or make `" "%s' extern\n" msgstr "" -#: elf64-ppc.c:13041 -msgid "%B: relocation %s is not supported for symbol %s\n" +#: elf64-ppc.c:13286 +msgid "%P: %B: relocation %s is not supported for symbol %s\n" msgstr "" -#: elf64-ppc.c:13218 -msgid "%H: error: %s not a multiple of %u\n" +#: elf64-ppc.c:13446 +msgid "%P: %H: error: %s not a multiple of %u\n" msgstr "" -#: elf64-sh64.c:1682 +#: elf64-sh64.c:1686 #, c-format msgid "%s: error: unaligned relocation type %d at %08x reloc %08x\n" msgstr "" -#: elf64-sparc.c:445 +#: elf64-sparc.c:446 msgid "%B: Only registers %%g[2367] can be declared using STT_REGISTER" msgstr "" -#: elf64-sparc.c:465 +#: elf64-sparc.c:466 msgid "Register %%g%d used incompatibly: %s in %B, previously %s in %B" msgstr "" -#: elf64-sparc.c:488 +#: elf64-sparc.c:489 msgid "Symbol `%s' has differing types: REGISTER in %B, previously %s in %B" msgstr "" -#: elf64-sparc.c:533 +#: elf64-sparc.c:534 msgid "Symbol `%s' has differing types: %s in %B, previously REGISTER in %B" msgstr "" -#: elf64-sparc.c:686 +#: elf64-sparc.c:687 msgid "%B: linking UltraSPARC specific with HAL specific code" msgstr "" -#: elf64-x86-64.c:1236 +#: elf64-x86-64.c:1427 msgid "%B: relocation %s against symbol `%s' isn't supported in x32 mode" msgstr "" -#: elf64-x86-64.c:1465 +#: elf64-x86-64.c:1656 msgid "%B: '%s' accessed both as normal and thread local symbol" msgstr "" -#: elf64-x86-64.c:2934 +#: elf64-x86-64.c:3150 msgid "" "%B: relocation %s against STT_GNU_IFUNC symbol `%s' has non-zero addend: %d" msgstr "" -#: elf64-x86-64.c:3193 +#: elf64-x86-64.c:3411 msgid "" "%B: relocation R_X86_64_GOTOFF64 against protected function `%s' can not be " "used when making a shared object" msgstr "" -#: elf64-x86-64.c:3305 +#: elf64-x86-64.c:3523 msgid "; recompile with -fPIC" msgstr "" -#: elf64-x86-64.c:3310 +#: elf64-x86-64.c:3528 msgid "" "%B: relocation %s against %s `%s' can not be used when making a shared object" "%s" msgstr "" -#: elf64-x86-64.c:3312 +#: elf64-x86-64.c:3530 msgid "" "%B: relocation %s against undefined %s `%s' can not be used when making a " "shared object%s" msgstr "" -#: elfcode.h:827 +#: elfcode.h:767 #, c-format msgid "warning: %s has a corrupt string table index - ignoring" msgstr "" -#: elfcode.h:1237 +#: elfcode.h:1177 #, c-format msgid "%s: version count (%ld) does not match symbol count (%ld)" msgstr "" -#: elfcode.h:1491 +#: elfcode.h:1431 #, c-format msgid "%s(%s): relocation %d has invalid symbol index %ld" msgstr "" @@ -2940,377 +2971,387 @@ msgstr "" msgid "Warning: %B is truncated: expected core file size >= %lu, found: %lu." msgstr "" -#: elflink.c:1119 +#: elflink.c:1117 msgid "" "%s: TLS definition in %B section %A mismatches non-TLS definition in %B " "section %A" msgstr "" -#: elflink.c:1123 +#: elflink.c:1121 msgid "%s: TLS reference in %B mismatches non-TLS reference in %B" msgstr "" -#: elflink.c:1127 +#: elflink.c:1125 msgid "%s: TLS definition in %B section %A mismatches non-TLS reference in %B" msgstr "" -#: elflink.c:1131 +#: elflink.c:1129 msgid "%s: TLS reference in %B mismatches non-TLS definition in %B section %A" msgstr "" -#: elflink.c:1764 +#: elflink.c:1762 msgid "%B: unexpected redefinition of indirect versioned symbol `%s'" msgstr "" -#: elflink.c:2077 +#: elflink.c:2063 msgid "%B: version node not found for symbol %s" msgstr "" -#: elflink.c:2167 +#: elflink.c:2154 msgid "" "%B: bad reloc symbol index (0x%lx >= 0x%lx) for offset 0x%lx in section `%A'" msgstr "" -#: elflink.c:2178 +#: elflink.c:2165 msgid "" "%B: non-zero symbol index (0x%lx) for offset 0x%lx in section `%A' when the " "object file has no symbol table" msgstr "" -#: elflink.c:2368 +#: elflink.c:2355 msgid "%B: relocation size mismatch in %B section %A" msgstr "" -#: elflink.c:2663 +#: elflink.c:2639 #, c-format msgid "warning: type and size of dynamic symbol `%s' are not defined" msgstr "" -#: elflink.c:3421 +#: elflink.c:3391 msgid "%P: alternate ELF machine code found (%d) in %B, expecting %d\n" msgstr "" -#: elflink.c:4067 +#: elflink.c:4037 msgid "%B: %s: invalid version %u (max %d)" msgstr "" -#: elflink.c:4103 +#: elflink.c:4073 msgid "%B: %s: invalid needed version %d" msgstr "" -#: elflink.c:4299 +#: elflink.c:4269 msgid "" "Warning: alignment %u of common symbol `%s' in %B is greater than the " "alignment (%u) of its section %A" msgstr "" -#: elflink.c:4305 +#: elflink.c:4275 msgid "Warning: alignment %u of symbol `%s' in %B is smaller than %u in %B" msgstr "" -#: elflink.c:4320 +#: elflink.c:4290 msgid "Warning: size of symbol `%s' changed from %lu in %B to %lu in %B" msgstr "" -#: elflink.c:4489 +#: elflink.c:4463 msgid "%B: undefined reference to symbol '%s'" msgstr "" -#: elflink.c:4492 +#: elflink.c:4466 msgid "" "note: '%s' is defined in DSO %B so try adding it to the linker command line" msgstr "" -#: elflink.c:5795 +#: elflink.c:5781 #, c-format msgid "%s: undefined version: %s" msgstr "" -#: elflink.c:5863 +#: elflink.c:5849 msgid "%B: .preinit_array section is not allowed in DSO" msgstr "" -#: elflink.c:7617 +#: elflink.c:7604 #, c-format msgid "undefined %s reference in complex symbol: %s" msgstr "" -#: elflink.c:7771 +#: elflink.c:7758 #, c-format msgid "unknown operator '%c' in complex symbol" msgstr "" -#: elflink.c:8110 elflink.c:8127 elflink.c:8164 elflink.c:8181 +#: elflink.c:8097 elflink.c:8114 elflink.c:8151 elflink.c:8168 msgid "%B: Unable to sort relocs - they are in more than one size" msgstr "" -#: elflink.c:8141 elflink.c:8195 +#: elflink.c:8128 elflink.c:8182 msgid "%B: Unable to sort relocs - they are of an unknown size" msgstr "" -#: elflink.c:8246 +#: elflink.c:8233 msgid "Not enough memory to sort relocations" msgstr "" -#: elflink.c:8439 +#: elflink.c:8426 msgid "%B: Too many sections: %d (>= %d)" msgstr "" -#: elflink.c:8686 +#: elflink.c:8675 msgid "%B: internal symbol `%s' in %B is referenced by DSO" msgstr "" -#: elflink.c:8688 +#: elflink.c:8677 msgid "%B: hidden symbol `%s' in %B is referenced by DSO" msgstr "" -#: elflink.c:8690 +#: elflink.c:8679 msgid "%B: local symbol `%s' in %B is referenced by DSO" msgstr "" -#: elflink.c:8785 +#: elflink.c:8776 msgid "%B: could not find output section %A for input section %A" msgstr "" -#: elflink.c:8908 +#: elflink.c:8899 msgid "%B: protected symbol `%s' isn't defined" msgstr "" -#: elflink.c:8910 +#: elflink.c:8901 msgid "%B: internal symbol `%s' isn't defined" msgstr "" -#: elflink.c:8912 +#: elflink.c:8903 msgid "%B: hidden symbol `%s' isn't defined" msgstr "" -#: elflink.c:9441 +#: elflink.c:9432 msgid "error: %B: size of section %A is not multiple of address size" msgstr "" -#: elflink.c:9488 +#: elflink.c:9479 msgid "" "error: %B contains a reloc (0x%s) for section %A that references a non-" "existent global symbol" msgstr "" -#: elflink.c:10223 +#: elflink.c:10214 msgid "%A has both ordered [`%A' in %B] and unordered [`%A' in %B] sections" msgstr "" -#: elflink.c:10228 +#: elflink.c:10219 #, c-format msgid "%A has both ordered and unordered sections" msgstr "" -#: elflink.c:10793 +#: elflink.c:10784 msgid "%B: file class %s incompatible with %s" msgstr "" -#: elflink.c:11104 elflink.c:11148 +#: elflink.c:11093 elflink.c:11137 msgid "%B: could not find output section %s" msgstr "" -#: elflink.c:11109 +#: elflink.c:11098 #, c-format msgid "warning: %s section has zero size" msgstr "" -#: elflink.c:11214 -msgid "%P: warning: creating a DT_TEXTREL in a shared object.\n" -msgstr "" - -#: elflink.c:11401 -msgid "%P%X: can not read symbols: %E\n" +#: elflink.c:11143 +#, c-format +msgid "warning: section '%s' is being made into a note" msgstr "" -#: elflink.c:11750 -msgid "Removing unused section '%s' in file '%B'" +#: elflink.c:11212 +msgid "%P%X: read-only segment has dynamic relocations.\n" msgstr "" -#: elflink.c:11962 -msgid "Warning: gc-sections option ignored" +#: elflink.c:11215 +msgid "%P: warning: creating a DT_TEXTREL in a shared object.\n" msgstr "" -#: elflink.c:12511 -msgid "%B: ignoring duplicate section `%A'" +#: elflink.c:11402 +msgid "%P%X: can not read symbols: %E\n" msgstr "" -#: elflink.c:12518 elflink.c:12525 -msgid "%B: duplicate section `%A' has different size" +#: elflink.c:11792 +msgid "Removing unused section '%s' in file '%B'" msgstr "" -#: elflink.c:12533 elflink.c:12538 -msgid "%B: warning: could not read contents of section `%A'" +#: elflink.c:11998 +msgid "Warning: gc-sections option ignored" msgstr "" -#: elflink.c:12542 -msgid "%B: warning: duplicate section `%A' has different contents" +#: elflink.c:12277 +#, c-format +msgid "Unrecognized INPUT_SECTION_FLAG %s\n" msgstr "" -#: elflink.c:12643 linker.c:3086 -msgid "%F%P: already_linked_table: %E\n" +#: elfxx-mips.c:1234 +msgid "static procedure (no name)" msgstr "" -#: elfxx-mips.c:1221 -msgid "static procedure (no name)" +#: elfxx-mips.c:5259 +msgid "MIPS16 and microMIPS functions cannot call each other" msgstr "" -#: elfxx-mips.c:5628 +#: elfxx-mips.c:5856 msgid "" "%B: %A+0x%lx: Direct jumps between ISA modes are not allowed; consider " "recompiling with interlinking enabled." msgstr "" -#: elfxx-mips.c:6288 elfxx-mips.c:6511 +#: elfxx-mips.c:6519 elfxx-mips.c:6742 msgid "%B: Warning: bad `%s' option size %u smaller than its header" msgstr "" -#: elfxx-mips.c:7262 elfxx-mips.c:7387 +#: elfxx-mips.c:7495 elfxx-mips.c:7620 msgid "%B: Warning: cannot determine the target function for stub section `%s'" msgstr "" -#: elfxx-mips.c:7516 +#: elfxx-mips.c:7749 msgid "%B: Malformed reloc detected for section %s" msgstr "" -#: elfxx-mips.c:7556 +#: elfxx-mips.c:7801 msgid "%B: GOT reloc at 0x%lx not expected in executables" msgstr "" -#: elfxx-mips.c:7678 +#: elfxx-mips.c:7930 msgid "%B: CALL16 reloc at 0x%lx not against global symbol" msgstr "" -#: elfxx-mips.c:8372 +#: elfxx-mips.c:8645 #, c-format msgid "non-dynamic relocations refer to dynamic symbol %s" msgstr "" -#: elfxx-mips.c:9075 +#: elfxx-mips.c:9347 msgid "" "%B: Can't find matching LO16 reloc against `%s' for %s at 0x%lx in section `" "%A'" msgstr "" -#: elfxx-mips.c:9214 +#: elfxx-mips.c:9486 msgid "" "small-data section exceeds 64KB; lower small-data size limit (see option -G)" msgstr "" -#: elfxx-mips.c:12038 +#: elfxx-mips.c:9505 +msgid "JALX to a non-word-aligned address" +msgstr "" + +#: elfxx-mips.c:13266 #, c-format msgid "%s: illegal section name `%s'" msgstr "" -#: elfxx-mips.c:12417 elfxx-mips.c:12443 +#: elfxx-mips.c:13645 elfxx-mips.c:13671 msgid "Warning: %B uses -msingle-float, %B uses -mdouble-float" msgstr "" -#: elfxx-mips.c:12429 elfxx-mips.c:12485 +#: elfxx-mips.c:13657 elfxx-mips.c:13713 msgid "Warning: %B uses -msingle-float, %B uses -mips32r2 -mfp64" msgstr "" -#: elfxx-mips.c:12455 elfxx-mips.c:12491 +#: elfxx-mips.c:13683 elfxx-mips.c:13719 msgid "Warning: %B uses -mdouble-float, %B uses -mips32r2 -mfp64" msgstr "" -#: elfxx-mips.c:12533 +#: elfxx-mips.c:13761 msgid "%B: endianness incompatible with that of the selected emulation" msgstr "" -#: elfxx-mips.c:12544 +#: elfxx-mips.c:13772 msgid "%B: ABI is incompatible with that of the selected emulation" msgstr "" -#: elfxx-mips.c:12628 +#: elfxx-mips.c:13856 msgid "%B: warning: linking abicalls files with non-abicalls files" msgstr "" -#: elfxx-mips.c:12645 +#: elfxx-mips.c:13873 msgid "%B: linking 32-bit code with 64-bit code" msgstr "" -#: elfxx-mips.c:12673 +#: elfxx-mips.c:13901 msgid "%B: linking %s module with previous %s modules" msgstr "" -#: elfxx-mips.c:12696 +#: elfxx-mips.c:13924 msgid "%B: ABI mismatch: linking %s module with previous %s modules" msgstr "" -#: elfxx-mips.c:12860 +#: elfxx-mips.c:13948 +msgid "%B: ASE mismatch: linking %s module with previous %s modules" +msgstr "" + +#: elfxx-mips.c:14106 #, c-format msgid " [abi=O32]" msgstr "" -#: elfxx-mips.c:12862 +#: elfxx-mips.c:14108 #, c-format msgid " [abi=O64]" msgstr "" -#: elfxx-mips.c:12864 +#: elfxx-mips.c:14110 #, c-format msgid " [abi=EABI32]" msgstr "" -#: elfxx-mips.c:12866 +#: elfxx-mips.c:14112 #, c-format msgid " [abi=EABI64]" msgstr "" -#: elfxx-mips.c:12868 +#: elfxx-mips.c:14114 #, c-format msgid " [abi unknown]" msgstr "" -#: elfxx-mips.c:12870 +#: elfxx-mips.c:14116 #, c-format msgid " [abi=N32]" msgstr "" -#: elfxx-mips.c:12872 +#: elfxx-mips.c:14118 #, c-format msgid " [abi=64]" msgstr "" -#: elfxx-mips.c:12874 +#: elfxx-mips.c:14120 #, c-format msgid " [no abi set]" msgstr "" -#: elfxx-mips.c:12895 +#: elfxx-mips.c:14141 #, c-format msgid " [unknown ISA]" msgstr "" -#: elfxx-mips.c:12906 +#: elfxx-mips.c:14155 #, c-format msgid " [not 32bitmode]" msgstr "" -#: elfxx-sparc.c:595 +#: elfxx-sparc.c:596 #, c-format msgid "invalid relocation type %d" msgstr "" -#: i386linux.c:454 m68klinux.c:458 sparclinux.c:452 +#: elfxx-tilegx.c:3952 +msgid "%B: Cannot link together %s and %s objects." +msgstr "" + +#: i386linux.c:451 m68klinux.c:456 sparclinux.c:450 #, c-format msgid "Output file requires shared library `%s'\n" msgstr "" -#: i386linux.c:462 m68klinux.c:466 sparclinux.c:460 +#: i386linux.c:459 m68klinux.c:464 sparclinux.c:458 #, c-format msgid "Output file requires shared library `%s.so.%s'\n" msgstr "" -#: i386linux.c:651 i386linux.c:701 m68klinux.c:658 m68klinux.c:706 -#: sparclinux.c:650 sparclinux.c:700 +#: i386linux.c:648 i386linux.c:698 m68klinux.c:656 m68klinux.c:704 +#: sparclinux.c:648 sparclinux.c:698 #, c-format msgid "Symbol %s not defined for fixups\n" msgstr "" -#: i386linux.c:725 m68klinux.c:730 sparclinux.c:724 +#: i386linux.c:722 m68klinux.c:728 sparclinux.c:722 msgid "Warning: fixup count mismatch\n" msgstr "" @@ -3381,6 +3422,14 @@ msgstr "" msgid "%B: unable to get decompressed section %A" msgstr "" +#: libbfd.c:1012 +msgid "%B: compiled for a big endian system and target is little endian" +msgstr "" + +#: libbfd.c:1014 +msgid "%B: compiled for a little endian system and target is big endian" +msgstr "" + #: libbfd.c:1043 #, c-format msgid "Deprecated %s called at %s line %d in %s\n" @@ -3391,140 +3440,148 @@ msgstr "" msgid "Deprecated %s called\n" msgstr "" -#: linker.c:1859 +#: linker.c:1872 msgid "%B: indirect symbol `%s' to `%s' is a loop" msgstr "" -#: linker.c:2726 +#: linker.c:2736 #, c-format msgid "Attempt to do relocatable link with %s input and %s output" msgstr "" -#: linker.c:3053 -msgid "%B: warning: ignoring duplicate section `%A'\n" +#: linker.c:3021 +msgid "%B: ignoring duplicate section `%A'\n" msgstr "" -#: linker.c:3067 -msgid "%B: warning: duplicate section `%A' has different size\n" +#: linker.c:3030 linker.c:3039 +msgid "%B: duplicate section `%A' has different size\n" msgstr "" -#: mach-o.c:381 +#: linker.c:3047 linker.c:3052 +msgid "%B: could not read contents of section `%A'\n" +msgstr "" + +#: linker.c:3056 +msgid "%B: duplicate section `%A' has different contents\n" +msgstr "" + +#: mach-o.c:407 msgid "bfd_mach_o_canonicalize_symtab: unable to load symbols" msgstr "" -#: mach-o.c:1253 +#: mach-o.c:1301 #, c-format msgid "unable to write unknown load command 0x%lx" msgstr "" -#: mach-o.c:1654 +#: mach-o.c:1789 #, c-format msgid "bfd_mach_o_read_symtab_symbol: unable to read %d bytes at %lu" msgstr "" -#: mach-o.c:1671 +#: mach-o.c:1807 #, c-format -msgid "bfd_mach_o_read_symtab_symbol: symbol name out of range (%lu >= %lu)" +msgid "bfd_mach_o_read_symtab_symbol: name out of range (%lu >= %lu)" msgstr "" -#: mach-o.c:1756 +#: mach-o.c:1892 #, c-format msgid "" "bfd_mach_o_read_symtab_symbol: symbol \"%s\" specified invalid section %d " "(max %lu): setting to undefined" msgstr "" -#: mach-o.c:1764 +#: mach-o.c:1900 #, c-format msgid "" "bfd_mach_o_read_symtab_symbol: symbol \"%s\" is unsupported 'indirect' " "reference: setting to undefined" msgstr "" -#: mach-o.c:1770 +#: mach-o.c:1906 #, c-format msgid "" "bfd_mach_o_read_symtab_symbol: symbol \"%s\" specified invalid type field 0x" "%x: setting to undefined" msgstr "" -#: mach-o.c:1840 +#: mach-o.c:1979 msgid "bfd_mach_o_read_symtab_symbols: unable to allocate memory for symbols" msgstr "" -#: mach-o.c:1874 +#: mach-o.c:2014 #, c-format msgid "bfd_mach_o_read_dysymtab_symbol: unable to read %lu bytes at %lu" msgstr "" -#: mach-o.c:2556 +#: mach-o.c:2734 #, c-format msgid "unable to read unknown load command 0x%lx" msgstr "" -#: mach-o.c:2736 +#: mach-o.c:2915 #, c-format msgid "bfd_mach_o_scan: unknown architecture 0x%lx/0x%lx" msgstr "" -#: mach-o.c:2832 +#: mach-o.c:3011 #, c-format msgid "unknown header byte-order value 0x%lx" msgstr "" -#: mach-o.c:3402 +#: mach-o.c:3577 msgid "Mach-O header:\n" msgstr "" -#: mach-o.c:3403 +#: mach-o.c:3578 #, c-format msgid " magic : %08lx\n" msgstr "" -#: mach-o.c:3404 +#: mach-o.c:3579 #, c-format msgid " cputype : %08lx (%s)\n" msgstr "" -#: mach-o.c:3406 +#: mach-o.c:3581 #, c-format msgid " cpusubtype: %08lx\n" msgstr "" -#: mach-o.c:3407 +#: mach-o.c:3582 #, c-format msgid " filetype : %08lx (%s)\n" msgstr "" -#: mach-o.c:3410 +#: mach-o.c:3585 #, c-format msgid " ncmds : %08lx (%lu)\n" msgstr "" -#: mach-o.c:3411 +#: mach-o.c:3586 #, c-format msgid " sizeofcmds: %08lx\n" msgstr "" -#: mach-o.c:3412 +#: mach-o.c:3587 #, c-format msgid " flags : %08lx (" msgstr "" -#: mach-o.c:3414 vms-alpha.c:7671 +#: mach-o.c:3589 vms-alpha.c:7674 msgid ")\n" msgstr "" -#: mach-o.c:3415 +#: mach-o.c:3590 #, c-format msgid " reserved : %08x\n" msgstr "" -#: mach-o.c:3425 +#: mach-o.c:3600 msgid "Segments and Sections:\n" msgstr "" -#: mach-o.c:3426 +#: mach-o.c:3601 msgid " #: Segment name Section name Address\n" msgstr "" @@ -3705,7 +3762,7 @@ msgstr "" msgid "%B: bad pair/reflo after refhi\n" msgstr "" -#: pef.c:519 +#: pef.c:520 #, c-format msgid "bfd_pef_scan: unknown architecture 0x%lx" msgstr "" @@ -3741,21 +3798,21 @@ msgstr "" msgid "%B: Unrecognised import name type; %x" msgstr "" -#: peicode.h:1162 +#: peicode.h:1166 msgid "%B: Unrecognised machine type (0x%x) in Import Library Format archive" msgstr "" -#: peicode.h:1174 +#: peicode.h:1178 msgid "" "%B: Recognised but unhandled machine type (0x%x) in Import Library Format " "archive" msgstr "" -#: peicode.h:1192 +#: peicode.h:1196 msgid "%B: size field is zero in Import Library Format header" msgstr "" -#: peicode.h:1223 +#: peicode.h:1227 msgid "%B: string not null terminated in ILF object file." msgstr "" @@ -3808,6 +3865,10 @@ msgstr "" msgid "Partition[%d] length = 0x%.8lx (%ld)\n" msgstr "" +#: reloc.c:6160 +msgid "INPUT_SECTION_FLAGS are not supported.\n" +msgstr "" + #: rs6000-core.c:448 #, c-format msgid "%s: warning core file truncated" @@ -3909,1821 +3970,1825 @@ msgstr "" msgid "SEC_RELOC with no relocs in section %s" msgstr "" -#: vms-alpha.c:3822 vms-alpha.c:4053 +#: vms-alpha.c:3822 vms-alpha.c:4049 #, c-format msgid "Size error in section %s" msgstr "" -#: vms-alpha.c:3992 +#: vms-alpha.c:3991 msgid "Spurious ALPHA_R_BSR reloc" msgstr "" -#: vms-alpha.c:4040 +#: vms-alpha.c:4036 #, c-format msgid "Unhandled relocation %s" msgstr "" -#: vms-alpha.c:4330 +#: vms-alpha.c:4326 #, c-format msgid "unknown source command %d" msgstr "" -#: vms-alpha.c:4391 +#: vms-alpha.c:4387 msgid "DST__K_SET_LINUM_INCR not implemented" msgstr "" -#: vms-alpha.c:4397 +#: vms-alpha.c:4393 msgid "DST__K_SET_LINUM_INCR_W not implemented" msgstr "" -#: vms-alpha.c:4403 +#: vms-alpha.c:4399 msgid "DST__K_RESET_LINUM_INCR not implemented" msgstr "" -#: vms-alpha.c:4409 +#: vms-alpha.c:4405 msgid "DST__K_BEG_STMT_MODE not implemented" msgstr "" -#: vms-alpha.c:4415 +#: vms-alpha.c:4411 msgid "DST__K_END_STMT_MODE not implemented" msgstr "" -#: vms-alpha.c:4442 +#: vms-alpha.c:4438 msgid "DST__K_SET_PC not implemented" msgstr "" -#: vms-alpha.c:4448 +#: vms-alpha.c:4444 msgid "DST__K_SET_PC_W not implemented" msgstr "" -#: vms-alpha.c:4454 +#: vms-alpha.c:4450 msgid "DST__K_SET_PC_L not implemented" msgstr "" -#: vms-alpha.c:4460 +#: vms-alpha.c:4456 msgid "DST__K_SET_STMTNUM not implemented" msgstr "" -#: vms-alpha.c:4503 +#: vms-alpha.c:4499 #, c-format msgid "unknown line command %d" msgstr "" -#: vms-alpha.c:4957 vms-alpha.c:4974 vms-alpha.c:4988 vms-alpha.c:5003 -#: vms-alpha.c:5015 vms-alpha.c:5026 vms-alpha.c:5038 +#: vms-alpha.c:4953 vms-alpha.c:4970 vms-alpha.c:4984 vms-alpha.c:4999 +#: vms-alpha.c:5011 vms-alpha.c:5022 vms-alpha.c:5034 #, c-format msgid "Unknown reloc %s + %s" msgstr "" -#: vms-alpha.c:5093 +#: vms-alpha.c:5089 #, c-format msgid "Unknown reloc %s" msgstr "" -#: vms-alpha.c:5106 +#: vms-alpha.c:5102 msgid "Invalid section index in ETIR" msgstr "" -#: vms-alpha.c:5153 +#: vms-alpha.c:5109 +msgid "Relocation for non-REL psect" +msgstr "" + +#: vms-alpha.c:5156 #, c-format msgid "Unknown symbol in command %s" msgstr "" -#: vms-alpha.c:5668 +#: vms-alpha.c:5671 #, c-format msgid " EMH %u (len=%u): " msgstr "" -#: vms-alpha.c:5677 +#: vms-alpha.c:5680 #, c-format msgid "Module header\n" msgstr "" -#: vms-alpha.c:5678 +#: vms-alpha.c:5681 #, c-format msgid " structure level: %u\n" msgstr "" -#: vms-alpha.c:5679 +#: vms-alpha.c:5682 #, c-format msgid " max record size: %u\n" msgstr "" -#: vms-alpha.c:5682 +#: vms-alpha.c:5685 #, c-format msgid " module name : %.*s\n" msgstr "" -#: vms-alpha.c:5684 +#: vms-alpha.c:5687 #, c-format msgid " module version : %.*s\n" msgstr "" -#: vms-alpha.c:5686 +#: vms-alpha.c:5689 #, c-format msgid " compile date : %.17s\n" msgstr "" -#: vms-alpha.c:5691 +#: vms-alpha.c:5694 #, c-format msgid "Language Processor Name\n" msgstr "" -#: vms-alpha.c:5692 +#: vms-alpha.c:5695 #, c-format msgid " language name: %.*s\n" msgstr "" -#: vms-alpha.c:5699 +#: vms-alpha.c:5702 #, c-format msgid "Source Files Header\n" msgstr "" -#: vms-alpha.c:5700 +#: vms-alpha.c:5703 #, c-format msgid " file: %.*s\n" msgstr "" -#: vms-alpha.c:5707 +#: vms-alpha.c:5710 #, c-format msgid "Title Text Header\n" msgstr "" -#: vms-alpha.c:5708 +#: vms-alpha.c:5711 #, c-format msgid " title: %.*s\n" msgstr "" -#: vms-alpha.c:5715 +#: vms-alpha.c:5718 #, c-format msgid "Copyright Header\n" msgstr "" -#: vms-alpha.c:5716 +#: vms-alpha.c:5719 #, c-format msgid " copyright: %.*s\n" msgstr "" -#: vms-alpha.c:5722 +#: vms-alpha.c:5725 #, c-format msgid "unhandled emh subtype %u\n" msgstr "" -#: vms-alpha.c:5732 +#: vms-alpha.c:5735 #, c-format msgid " EEOM (len=%u):\n" msgstr "" -#: vms-alpha.c:5733 +#: vms-alpha.c:5736 #, c-format msgid " number of cond linkage pairs: %u\n" msgstr "" -#: vms-alpha.c:5735 +#: vms-alpha.c:5738 #, c-format msgid " completion code: %u\n" msgstr "" -#: vms-alpha.c:5739 +#: vms-alpha.c:5742 #, c-format msgid " transfer addr flags: 0x%02x\n" msgstr "" -#: vms-alpha.c:5740 +#: vms-alpha.c:5743 #, c-format msgid " transfer addr psect: %u\n" msgstr "" -#: vms-alpha.c:5742 +#: vms-alpha.c:5745 #, c-format msgid " transfer address : 0x%08x\n" msgstr "" -#: vms-alpha.c:5751 +#: vms-alpha.c:5754 msgid " WEAK" msgstr "" -#: vms-alpha.c:5753 +#: vms-alpha.c:5756 msgid " DEF" msgstr "" -#: vms-alpha.c:5755 +#: vms-alpha.c:5758 msgid " UNI" msgstr "" -#: vms-alpha.c:5757 vms-alpha.c:5778 +#: vms-alpha.c:5760 vms-alpha.c:5781 msgid " REL" msgstr "" -#: vms-alpha.c:5759 +#: vms-alpha.c:5762 msgid " COMM" msgstr "" -#: vms-alpha.c:5761 +#: vms-alpha.c:5764 msgid " VECEP" msgstr "" -#: vms-alpha.c:5763 +#: vms-alpha.c:5766 msgid " NORM" msgstr "" -#: vms-alpha.c:5765 +#: vms-alpha.c:5768 msgid " QVAL" msgstr "" -#: vms-alpha.c:5772 +#: vms-alpha.c:5775 msgid " PIC" msgstr "" -#: vms-alpha.c:5774 +#: vms-alpha.c:5777 msgid " LIB" msgstr "" -#: vms-alpha.c:5776 +#: vms-alpha.c:5779 msgid " OVR" msgstr "" -#: vms-alpha.c:5780 +#: vms-alpha.c:5783 msgid " GBL" msgstr "" -#: vms-alpha.c:5782 +#: vms-alpha.c:5785 msgid " SHR" msgstr "" -#: vms-alpha.c:5784 +#: vms-alpha.c:5787 msgid " EXE" msgstr "" -#: vms-alpha.c:5786 +#: vms-alpha.c:5789 msgid " RD" msgstr "" -#: vms-alpha.c:5788 +#: vms-alpha.c:5791 msgid " WRT" msgstr "" -#: vms-alpha.c:5790 +#: vms-alpha.c:5793 msgid " VEC" msgstr "" -#: vms-alpha.c:5792 +#: vms-alpha.c:5795 msgid " NOMOD" msgstr "" -#: vms-alpha.c:5794 +#: vms-alpha.c:5797 msgid " COM" msgstr "" -#: vms-alpha.c:5796 +#: vms-alpha.c:5799 msgid " 64B" msgstr "" -#: vms-alpha.c:5805 +#: vms-alpha.c:5808 #, c-format msgid " EGSD (len=%u):\n" msgstr "" -#: vms-alpha.c:5817 +#: vms-alpha.c:5820 #, c-format msgid " EGSD entry %2u (type: %u, len: %u): " msgstr "" -#: vms-alpha.c:5829 +#: vms-alpha.c:5832 #, c-format msgid "PSC - Program section definition\n" msgstr "" -#: vms-alpha.c:5830 vms-alpha.c:5847 +#: vms-alpha.c:5833 vms-alpha.c:5850 #, c-format msgid " alignment : 2**%u\n" msgstr "" -#: vms-alpha.c:5831 vms-alpha.c:5848 +#: vms-alpha.c:5834 vms-alpha.c:5851 #, c-format msgid " flags : 0x%04x" msgstr "" -#: vms-alpha.c:5835 +#: vms-alpha.c:5838 #, c-format msgid " alloc (len): %u (0x%08x)\n" msgstr "" -#: vms-alpha.c:5836 vms-alpha.c:5893 vms-alpha.c:5942 +#: vms-alpha.c:5839 vms-alpha.c:5896 vms-alpha.c:5945 #, c-format msgid " name : %.*s\n" msgstr "" -#: vms-alpha.c:5846 +#: vms-alpha.c:5849 #, c-format msgid "SPSC - Shared Image Program section def\n" msgstr "" -#: vms-alpha.c:5852 +#: vms-alpha.c:5855 #, c-format msgid " alloc (len) : %u (0x%08x)\n" msgstr "" -#: vms-alpha.c:5853 +#: vms-alpha.c:5856 #, c-format msgid " image offset : 0x%08x\n" msgstr "" -#: vms-alpha.c:5855 +#: vms-alpha.c:5858 #, c-format msgid " symvec offset : 0x%08x\n" msgstr "" -#: vms-alpha.c:5857 +#: vms-alpha.c:5860 #, c-format msgid " name : %.*s\n" msgstr "" -#: vms-alpha.c:5870 +#: vms-alpha.c:5873 #, c-format msgid "SYM - Global symbol definition\n" msgstr "" -#: vms-alpha.c:5871 vms-alpha.c:5931 vms-alpha.c:5952 vms-alpha.c:5971 +#: vms-alpha.c:5874 vms-alpha.c:5934 vms-alpha.c:5955 vms-alpha.c:5974 #, c-format msgid " flags: 0x%04x" msgstr "" -#: vms-alpha.c:5874 +#: vms-alpha.c:5877 #, c-format msgid " psect offset: 0x%08x\n" msgstr "" -#: vms-alpha.c:5878 +#: vms-alpha.c:5881 #, c-format msgid " code address: 0x%08x\n" msgstr "" -#: vms-alpha.c:5880 +#: vms-alpha.c:5883 #, c-format msgid " psect index for entry point : %u\n" msgstr "" -#: vms-alpha.c:5883 vms-alpha.c:5959 vms-alpha.c:5978 +#: vms-alpha.c:5886 vms-alpha.c:5962 vms-alpha.c:5981 #, c-format msgid " psect index : %u\n" msgstr "" -#: vms-alpha.c:5885 vms-alpha.c:5961 vms-alpha.c:5980 +#: vms-alpha.c:5888 vms-alpha.c:5964 vms-alpha.c:5983 #, c-format msgid " name : %.*s\n" msgstr "" -#: vms-alpha.c:5892 +#: vms-alpha.c:5895 #, c-format msgid "SYM - Global symbol reference\n" msgstr "" -#: vms-alpha.c:5904 +#: vms-alpha.c:5907 #, c-format msgid "IDC - Ident Consistency check\n" msgstr "" -#: vms-alpha.c:5905 +#: vms-alpha.c:5908 #, c-format msgid " flags : 0x%08x" msgstr "" -#: vms-alpha.c:5909 +#: vms-alpha.c:5912 #, c-format msgid " id match : %x\n" msgstr "" -#: vms-alpha.c:5911 +#: vms-alpha.c:5914 #, c-format msgid " error severity: %x\n" msgstr "" -#: vms-alpha.c:5914 +#: vms-alpha.c:5917 #, c-format msgid " entity name : %.*s\n" msgstr "" -#: vms-alpha.c:5916 +#: vms-alpha.c:5919 #, c-format msgid " object name : %.*s\n" msgstr "" -#: vms-alpha.c:5919 +#: vms-alpha.c:5922 #, c-format msgid " binary ident : 0x%08x\n" msgstr "" -#: vms-alpha.c:5922 +#: vms-alpha.c:5925 #, c-format msgid " ascii ident : %.*s\n" msgstr "" -#: vms-alpha.c:5930 +#: vms-alpha.c:5933 #, c-format msgid "SYMG - Universal symbol definition\n" msgstr "" -#: vms-alpha.c:5934 +#: vms-alpha.c:5937 #, c-format msgid " symbol vector offset: 0x%08x\n" msgstr "" -#: vms-alpha.c:5936 +#: vms-alpha.c:5939 #, c-format msgid " entry point: 0x%08x\n" msgstr "" -#: vms-alpha.c:5938 +#: vms-alpha.c:5941 #, c-format msgid " proc descr : 0x%08x\n" msgstr "" -#: vms-alpha.c:5940 +#: vms-alpha.c:5943 #, c-format msgid " psect index: %u\n" msgstr "" -#: vms-alpha.c:5951 +#: vms-alpha.c:5954 #, c-format msgid "SYMV - Vectored symbol definition\n" msgstr "" -#: vms-alpha.c:5955 +#: vms-alpha.c:5958 #, c-format msgid " vector : 0x%08x\n" msgstr "" -#: vms-alpha.c:5957 vms-alpha.c:5976 +#: vms-alpha.c:5960 vms-alpha.c:5979 #, c-format msgid " psect offset: %u\n" msgstr "" -#: vms-alpha.c:5970 +#: vms-alpha.c:5973 #, c-format msgid "SYMM - Global symbol definition with version\n" msgstr "" -#: vms-alpha.c:5974 +#: vms-alpha.c:5977 #, c-format msgid " version mask: 0x%08x\n" msgstr "" -#: vms-alpha.c:5985 +#: vms-alpha.c:5988 #, c-format msgid "unhandled egsd entry type %u\n" msgstr "" -#: vms-alpha.c:6019 +#: vms-alpha.c:6022 #, c-format msgid " linkage index: %u, replacement insn: 0x%08x\n" msgstr "" -#: vms-alpha.c:6022 +#: vms-alpha.c:6025 #, c-format msgid " psect idx 1: %u, offset 1: 0x%08x %08x\n" msgstr "" -#: vms-alpha.c:6026 +#: vms-alpha.c:6029 #, c-format msgid " psect idx 2: %u, offset 2: 0x%08x %08x\n" msgstr "" -#: vms-alpha.c:6031 +#: vms-alpha.c:6034 #, c-format msgid " psect idx 3: %u, offset 3: 0x%08x %08x\n" msgstr "" -#: vms-alpha.c:6036 +#: vms-alpha.c:6039 #, c-format msgid " global name: %.*s\n" msgstr "" -#: vms-alpha.c:6046 +#: vms-alpha.c:6049 #, c-format msgid " %s (len=%u+%u):\n" msgstr "" -#: vms-alpha.c:6061 +#: vms-alpha.c:6064 #, c-format msgid " (type: %3u, size: 4+%3u): " msgstr "" -#: vms-alpha.c:6065 +#: vms-alpha.c:6068 #, c-format msgid "STA_GBL (stack global) %.*s\n" msgstr "" -#: vms-alpha.c:6069 +#: vms-alpha.c:6072 #, c-format msgid "STA_LW (stack longword) 0x%08x\n" msgstr "" -#: vms-alpha.c:6073 +#: vms-alpha.c:6076 #, c-format msgid "STA_QW (stack quadword) 0x%08x %08x\n" msgstr "" -#: vms-alpha.c:6078 +#: vms-alpha.c:6081 #, c-format msgid "STA_PQ (stack psect base + offset)\n" msgstr "" -#: vms-alpha.c:6079 +#: vms-alpha.c:6082 #, c-format msgid " psect: %u, offset: 0x%08x %08x\n" msgstr "" -#: vms-alpha.c:6085 +#: vms-alpha.c:6088 #, c-format msgid "STA_LI (stack literal)\n" msgstr "" -#: vms-alpha.c:6088 +#: vms-alpha.c:6091 #, c-format msgid "STA_MOD (stack module)\n" msgstr "" -#: vms-alpha.c:6091 +#: vms-alpha.c:6094 #, c-format msgid "STA_CKARG (compare procedure argument)\n" msgstr "" -#: vms-alpha.c:6095 +#: vms-alpha.c:6098 #, c-format msgid "STO_B (store byte)\n" msgstr "" -#: vms-alpha.c:6098 +#: vms-alpha.c:6101 #, c-format msgid "STO_W (store word)\n" msgstr "" -#: vms-alpha.c:6101 +#: vms-alpha.c:6104 #, c-format msgid "STO_LW (store longword)\n" msgstr "" -#: vms-alpha.c:6104 +#: vms-alpha.c:6107 #, c-format msgid "STO_QW (store quadword)\n" msgstr "" -#: vms-alpha.c:6110 +#: vms-alpha.c:6113 #, c-format msgid "STO_IMMR (store immediate repeat) %u bytes\n" msgstr "" -#: vms-alpha.c:6117 +#: vms-alpha.c:6120 #, c-format msgid "STO_GBL (store global) %.*s\n" msgstr "" -#: vms-alpha.c:6121 +#: vms-alpha.c:6124 #, c-format msgid "STO_CA (store code address) %.*s\n" msgstr "" -#: vms-alpha.c:6125 +#: vms-alpha.c:6128 #, c-format msgid "STO_RB (store relative branch)\n" msgstr "" -#: vms-alpha.c:6128 +#: vms-alpha.c:6131 #, c-format msgid "STO_AB (store absolute branch)\n" msgstr "" -#: vms-alpha.c:6131 +#: vms-alpha.c:6134 #, c-format msgid "STO_OFF (store offset to psect)\n" msgstr "" -#: vms-alpha.c:6137 +#: vms-alpha.c:6140 #, c-format msgid "STO_IMM (store immediate) %u bytes\n" msgstr "" -#: vms-alpha.c:6144 +#: vms-alpha.c:6147 #, c-format msgid "STO_GBL_LW (store global longword) %.*s\n" msgstr "" -#: vms-alpha.c:6148 +#: vms-alpha.c:6151 #, c-format msgid "STO_OFF (store LP with procedure signature)\n" msgstr "" -#: vms-alpha.c:6151 +#: vms-alpha.c:6154 #, c-format msgid "STO_BR_GBL (store branch global) *todo*\n" msgstr "" -#: vms-alpha.c:6154 +#: vms-alpha.c:6157 #, c-format msgid "STO_BR_PS (store branch psect + offset) *todo*\n" msgstr "" -#: vms-alpha.c:6158 +#: vms-alpha.c:6161 #, c-format msgid "OPR_NOP (no-operation)\n" msgstr "" -#: vms-alpha.c:6161 +#: vms-alpha.c:6164 #, c-format msgid "OPR_ADD (add)\n" msgstr "" -#: vms-alpha.c:6164 +#: vms-alpha.c:6167 #, c-format msgid "OPR_SUB (substract)\n" msgstr "" -#: vms-alpha.c:6167 +#: vms-alpha.c:6170 #, c-format msgid "OPR_MUL (multiply)\n" msgstr "" -#: vms-alpha.c:6170 +#: vms-alpha.c:6173 #, c-format msgid "OPR_DIV (divide)\n" msgstr "" -#: vms-alpha.c:6173 +#: vms-alpha.c:6176 #, c-format msgid "OPR_AND (logical and)\n" msgstr "" -#: vms-alpha.c:6176 +#: vms-alpha.c:6179 #, c-format msgid "OPR_IOR (logical inclusive or)\n" msgstr "" -#: vms-alpha.c:6179 +#: vms-alpha.c:6182 #, c-format msgid "OPR_EOR (logical exclusive or)\n" msgstr "" -#: vms-alpha.c:6182 +#: vms-alpha.c:6185 #, c-format msgid "OPR_NEG (negate)\n" msgstr "" -#: vms-alpha.c:6185 +#: vms-alpha.c:6188 #, c-format msgid "OPR_COM (complement)\n" msgstr "" -#: vms-alpha.c:6188 +#: vms-alpha.c:6191 #, c-format msgid "OPR_INSV (insert field)\n" msgstr "" -#: vms-alpha.c:6191 +#: vms-alpha.c:6194 #, c-format msgid "OPR_ASH (arithmetic shift)\n" msgstr "" -#: vms-alpha.c:6194 +#: vms-alpha.c:6197 #, c-format msgid "OPR_USH (unsigned shift)\n" msgstr "" -#: vms-alpha.c:6197 +#: vms-alpha.c:6200 #, c-format msgid "OPR_ROT (rotate)\n" msgstr "" -#: vms-alpha.c:6200 +#: vms-alpha.c:6203 #, c-format msgid "OPR_SEL (select)\n" msgstr "" -#: vms-alpha.c:6203 +#: vms-alpha.c:6206 #, c-format msgid "OPR_REDEF (redefine symbol to curr location)\n" msgstr "" -#: vms-alpha.c:6206 +#: vms-alpha.c:6209 #, c-format msgid "OPR_REDEF (define a literal)\n" msgstr "" -#: vms-alpha.c:6210 +#: vms-alpha.c:6213 #, c-format msgid "STC_LP (store cond linkage pair)\n" msgstr "" -#: vms-alpha.c:6214 +#: vms-alpha.c:6217 #, c-format msgid "STC_LP_PSB (store cond linkage pair + signature)\n" msgstr "" -#: vms-alpha.c:6215 +#: vms-alpha.c:6218 #, c-format msgid " linkage index: %u, procedure: %.*s\n" msgstr "" -#: vms-alpha.c:6218 +#: vms-alpha.c:6221 #, c-format msgid " signature: %.*s\n" msgstr "" -#: vms-alpha.c:6221 +#: vms-alpha.c:6224 #, c-format msgid "STC_GBL (store cond global)\n" msgstr "" -#: vms-alpha.c:6222 +#: vms-alpha.c:6225 #, c-format msgid " linkage index: %u, global: %.*s\n" msgstr "" -#: vms-alpha.c:6226 +#: vms-alpha.c:6229 #, c-format msgid "STC_GCA (store cond code address)\n" msgstr "" -#: vms-alpha.c:6227 +#: vms-alpha.c:6230 #, c-format msgid " linkage index: %u, procedure name: %.*s\n" msgstr "" -#: vms-alpha.c:6231 +#: vms-alpha.c:6234 #, c-format msgid "STC_PS (store cond psect + offset)\n" msgstr "" -#: vms-alpha.c:6233 +#: vms-alpha.c:6236 #, c-format msgid " linkage index: %u, psect: %u, offset: 0x%08x %08x\n" msgstr "" -#: vms-alpha.c:6240 +#: vms-alpha.c:6243 #, c-format msgid "STC_NOP_GBL (store cond NOP at global addr)\n" msgstr "" -#: vms-alpha.c:6244 +#: vms-alpha.c:6247 #, c-format msgid "STC_NOP_PS (store cond NOP at psect + offset)\n" msgstr "" -#: vms-alpha.c:6248 +#: vms-alpha.c:6251 #, c-format msgid "STC_BSR_GBL (store cond BSR at global addr)\n" msgstr "" -#: vms-alpha.c:6252 +#: vms-alpha.c:6255 #, c-format msgid "STC_BSR_PS (store cond BSR at psect + offset)\n" msgstr "" -#: vms-alpha.c:6256 +#: vms-alpha.c:6259 #, c-format msgid "STC_LDA_GBL (store cond LDA at global addr)\n" msgstr "" -#: vms-alpha.c:6260 +#: vms-alpha.c:6263 #, c-format msgid "STC_LDA_PS (store cond LDA at psect + offset)\n" msgstr "" -#: vms-alpha.c:6264 +#: vms-alpha.c:6267 #, c-format msgid "STC_BOH_GBL (store cond BOH at global addr)\n" msgstr "" -#: vms-alpha.c:6268 +#: vms-alpha.c:6271 #, c-format msgid "STC_BOH_PS (store cond BOH at psect + offset)\n" msgstr "" -#: vms-alpha.c:6273 +#: vms-alpha.c:6276 #, c-format msgid "STC_NBH_GBL (store cond or hint at global addr)\n" msgstr "" -#: vms-alpha.c:6277 +#: vms-alpha.c:6280 #, c-format msgid "STC_NBH_PS (store cond or hint at psect + offset)\n" msgstr "" -#: vms-alpha.c:6281 +#: vms-alpha.c:6284 #, c-format msgid "CTL_SETRB (set relocation base)\n" msgstr "" -#: vms-alpha.c:6287 +#: vms-alpha.c:6290 #, c-format msgid "CTL_AUGRB (augment relocation base) %u\n" msgstr "" -#: vms-alpha.c:6291 +#: vms-alpha.c:6294 #, c-format msgid "CTL_DFLOC (define location)\n" msgstr "" -#: vms-alpha.c:6294 +#: vms-alpha.c:6297 #, c-format msgid "CTL_STLOC (set location)\n" msgstr "" -#: vms-alpha.c:6297 +#: vms-alpha.c:6300 #, c-format msgid "CTL_STKDL (stack defined location)\n" msgstr "" -#: vms-alpha.c:6300 vms-alpha.c:6714 +#: vms-alpha.c:6303 vms-alpha.c:6717 #, c-format msgid "*unhandled*\n" msgstr "" -#: vms-alpha.c:6330 vms-alpha.c:6369 +#: vms-alpha.c:6333 vms-alpha.c:6372 #, c-format msgid "cannot read GST record length\n" msgstr "" #. Ill-formed. -#: vms-alpha.c:6351 +#: vms-alpha.c:6354 #, c-format msgid "cannot find EMH in first GST record\n" msgstr "" -#: vms-alpha.c:6377 +#: vms-alpha.c:6380 #, c-format msgid "cannot read GST record header\n" msgstr "" -#: vms-alpha.c:6390 +#: vms-alpha.c:6393 #, c-format msgid " corrupted GST\n" msgstr "" -#: vms-alpha.c:6398 +#: vms-alpha.c:6401 #, c-format msgid "cannot read GST record\n" msgstr "" -#: vms-alpha.c:6427 +#: vms-alpha.c:6430 #, c-format msgid " unhandled EOBJ record type %u\n" msgstr "" -#: vms-alpha.c:6450 +#: vms-alpha.c:6453 #, c-format msgid " bitcount: %u, base addr: 0x%08x\n" msgstr "" -#: vms-alpha.c:6463 +#: vms-alpha.c:6466 #, c-format msgid " bitmap: 0x%08x (count: %u):\n" msgstr "" -#: vms-alpha.c:6470 +#: vms-alpha.c:6473 #, c-format msgid " %08x" msgstr "" -#: vms-alpha.c:6495 +#: vms-alpha.c:6498 #, c-format msgid " image %u (%u entries)\n" msgstr "" -#: vms-alpha.c:6500 +#: vms-alpha.c:6503 #, c-format msgid " offset: 0x%08x, val: 0x%08x\n" msgstr "" -#: vms-alpha.c:6521 +#: vms-alpha.c:6524 #, c-format msgid " image %u (%u entries), offsets:\n" msgstr "" -#: vms-alpha.c:6528 +#: vms-alpha.c:6531 #, c-format msgid " 0x%08x" msgstr "" #. 64 bits. -#: vms-alpha.c:6650 +#: vms-alpha.c:6653 #, c-format msgid "64 bits *unhandled*\n" msgstr "" -#: vms-alpha.c:6654 +#: vms-alpha.c:6657 #, c-format msgid "class: %u, dtype: %u, length: %u, pointer: 0x%08x\n" msgstr "" -#: vms-alpha.c:6665 +#: vms-alpha.c:6668 #, c-format msgid "non-contiguous array of %s\n" msgstr "" -#: vms-alpha.c:6669 +#: vms-alpha.c:6672 #, c-format msgid "dimct: %u, aflags: 0x%02x, digits: %u, scale: %u\n" msgstr "" -#: vms-alpha.c:6673 +#: vms-alpha.c:6676 #, c-format msgid "arsize: %u, a0: 0x%08x\n" msgstr "" -#: vms-alpha.c:6677 +#: vms-alpha.c:6680 #, c-format msgid "Strides:\n" msgstr "" -#: vms-alpha.c:6682 +#: vms-alpha.c:6685 #, c-format msgid "[%u]: %u\n" msgstr "" -#: vms-alpha.c:6687 +#: vms-alpha.c:6690 #, c-format msgid "Bounds:\n" msgstr "" -#: vms-alpha.c:6692 +#: vms-alpha.c:6695 #, c-format msgid "[%u]: Lower: %u, upper: %u\n" msgstr "" -#: vms-alpha.c:6704 +#: vms-alpha.c:6707 #, c-format msgid "unaligned bit-string of %s\n" msgstr "" -#: vms-alpha.c:6708 +#: vms-alpha.c:6711 #, c-format msgid "base: %u, pos: %u\n" msgstr "" -#: vms-alpha.c:6728 +#: vms-alpha.c:6731 #, c-format msgid "vflags: 0x%02x, value: 0x%08x " msgstr "" -#: vms-alpha.c:6734 +#: vms-alpha.c:6737 #, c-format msgid "(no value)\n" msgstr "" -#: vms-alpha.c:6737 +#: vms-alpha.c:6740 #, c-format msgid "(not active)\n" msgstr "" -#: vms-alpha.c:6740 +#: vms-alpha.c:6743 #, c-format msgid "(not allocated)\n" msgstr "" -#: vms-alpha.c:6743 +#: vms-alpha.c:6746 #, c-format msgid "(descriptor)\n" msgstr "" -#: vms-alpha.c:6747 +#: vms-alpha.c:6750 #, c-format msgid "(trailing value)\n" msgstr "" -#: vms-alpha.c:6750 +#: vms-alpha.c:6753 #, c-format msgid "(value spec follows)\n" msgstr "" -#: vms-alpha.c:6753 +#: vms-alpha.c:6756 #, c-format msgid "(at bit offset %u)\n" msgstr "" -#: vms-alpha.c:6756 +#: vms-alpha.c:6759 #, c-format msgid "(reg: %u, disp: %u, indir: %u, kind: " msgstr "" -#: vms-alpha.c:6763 +#: vms-alpha.c:6766 msgid "literal" msgstr "" -#: vms-alpha.c:6766 +#: vms-alpha.c:6769 msgid "address" msgstr "" -#: vms-alpha.c:6769 +#: vms-alpha.c:6772 msgid "desc" msgstr "" -#: vms-alpha.c:6772 +#: vms-alpha.c:6775 msgid "reg" msgstr "" -#: vms-alpha.c:6847 +#: vms-alpha.c:6850 #, c-format msgid "Debug symbol table:\n" msgstr "" -#: vms-alpha.c:6858 +#: vms-alpha.c:6861 #, c-format msgid "cannot read DST header\n" msgstr "" -#: vms-alpha.c:6863 +#: vms-alpha.c:6866 #, c-format msgid " type: %3u, len: %3u (at 0x%08x): " msgstr "" -#: vms-alpha.c:6877 +#: vms-alpha.c:6880 #, c-format msgid "cannot read DST symbol\n" msgstr "" -#: vms-alpha.c:6920 +#: vms-alpha.c:6923 #, c-format msgid "standard data: %s\n" msgstr "" -#: vms-alpha.c:6923 vms-alpha.c:7007 +#: vms-alpha.c:6926 vms-alpha.c:7010 #, c-format msgid " name: %.*s\n" msgstr "" -#: vms-alpha.c:6930 +#: vms-alpha.c:6933 #, c-format msgid "modbeg\n" msgstr "" -#: vms-alpha.c:6931 +#: vms-alpha.c:6934 #, c-format msgid " flags: %d, language: %u, major: %u, minor: %u\n" msgstr "" -#: vms-alpha.c:6937 vms-alpha.c:7203 +#: vms-alpha.c:6940 vms-alpha.c:7206 #, c-format msgid " module name: %.*s\n" msgstr "" -#: vms-alpha.c:6940 +#: vms-alpha.c:6943 #, c-format msgid " compiler : %.*s\n" msgstr "" -#: vms-alpha.c:6945 +#: vms-alpha.c:6948 #, c-format msgid "modend\n" msgstr "" -#: vms-alpha.c:6952 +#: vms-alpha.c:6955 msgid "rtnbeg\n" msgstr "" -#: vms-alpha.c:6953 +#: vms-alpha.c:6956 #, c-format msgid " flags: %u, address: 0x%08x, pd-address: 0x%08x\n" msgstr "" -#: vms-alpha.c:6958 +#: vms-alpha.c:6961 #, c-format msgid " routine name: %.*s\n" msgstr "" -#: vms-alpha.c:6966 +#: vms-alpha.c:6969 #, c-format msgid "rtnend: size 0x%08x\n" msgstr "" -#: vms-alpha.c:6974 +#: vms-alpha.c:6977 #, c-format msgid "prolog: bkpt address 0x%08x\n" msgstr "" -#: vms-alpha.c:6982 +#: vms-alpha.c:6985 #, c-format msgid "epilog: flags: %u, count: %u\n" msgstr "" -#: vms-alpha.c:6991 +#: vms-alpha.c:6994 #, c-format msgid "blkbeg: address: 0x%08x, name: %.*s\n" msgstr "" -#: vms-alpha.c:7000 +#: vms-alpha.c:7003 #, c-format msgid "blkend: size: 0x%08x\n" msgstr "" -#: vms-alpha.c:7006 +#: vms-alpha.c:7009 #, c-format msgid "typspec (len: %u)\n" msgstr "" -#: vms-alpha.c:7013 +#: vms-alpha.c:7016 #, c-format msgid "septyp, name: %.*s\n" msgstr "" -#: vms-alpha.c:7022 +#: vms-alpha.c:7025 #, c-format msgid "recbeg: name: %.*s\n" msgstr "" -#: vms-alpha.c:7029 +#: vms-alpha.c:7032 #, c-format msgid "recend\n" msgstr "" -#: vms-alpha.c:7032 +#: vms-alpha.c:7035 #, c-format msgid "enumbeg, len: %u, name: %.*s\n" msgstr "" -#: vms-alpha.c:7036 +#: vms-alpha.c:7039 #, c-format msgid "enumelt, name: %.*s\n" msgstr "" -#: vms-alpha.c:7040 +#: vms-alpha.c:7043 #, c-format msgid "enumend\n" msgstr "" -#: vms-alpha.c:7057 +#: vms-alpha.c:7060 #, c-format msgid "discontiguous range (nbr: %u)\n" msgstr "" -#: vms-alpha.c:7059 +#: vms-alpha.c:7062 #, c-format msgid " address: 0x%08x, size: %u\n" msgstr "" -#: vms-alpha.c:7069 +#: vms-alpha.c:7072 #, c-format msgid "line num (len: %u)\n" msgstr "" -#: vms-alpha.c:7086 +#: vms-alpha.c:7089 #, c-format msgid "delta_pc_w %u\n" msgstr "" -#: vms-alpha.c:7093 +#: vms-alpha.c:7096 #, c-format msgid "incr_linum(b): +%u\n" msgstr "" -#: vms-alpha.c:7099 +#: vms-alpha.c:7102 #, c-format msgid "incr_linum_w: +%u\n" msgstr "" -#: vms-alpha.c:7105 +#: vms-alpha.c:7108 #, c-format msgid "incr_linum_l: +%u\n" msgstr "" -#: vms-alpha.c:7111 +#: vms-alpha.c:7114 #, c-format msgid "set_line_num(w) %u\n" msgstr "" -#: vms-alpha.c:7116 +#: vms-alpha.c:7119 #, c-format msgid "set_line_num_b %u\n" msgstr "" -#: vms-alpha.c:7121 +#: vms-alpha.c:7124 #, c-format msgid "set_line_num_l %u\n" msgstr "" -#: vms-alpha.c:7126 +#: vms-alpha.c:7129 #, c-format msgid "set_abs_pc: 0x%08x\n" msgstr "" -#: vms-alpha.c:7130 +#: vms-alpha.c:7133 #, c-format msgid "delta_pc_l: +0x%08x\n" msgstr "" -#: vms-alpha.c:7135 +#: vms-alpha.c:7138 #, c-format msgid "term(b): 0x%02x" msgstr "" -#: vms-alpha.c:7137 +#: vms-alpha.c:7140 #, c-format msgid " pc: 0x%08x\n" msgstr "" -#: vms-alpha.c:7142 +#: vms-alpha.c:7145 #, c-format msgid "term_w: 0x%04x" msgstr "" -#: vms-alpha.c:7144 +#: vms-alpha.c:7147 #, c-format msgid " pc: 0x%08x\n" msgstr "" -#: vms-alpha.c:7150 +#: vms-alpha.c:7153 #, c-format msgid "delta pc +%-4d" msgstr "" -#: vms-alpha.c:7153 +#: vms-alpha.c:7156 #, c-format msgid " pc: 0x%08x line: %5u\n" msgstr "" -#: vms-alpha.c:7158 +#: vms-alpha.c:7161 #, c-format msgid " *unhandled* cmd %u\n" msgstr "" -#: vms-alpha.c:7173 +#: vms-alpha.c:7176 #, c-format msgid "source (len: %u)\n" msgstr "" -#: vms-alpha.c:7187 +#: vms-alpha.c:7190 #, c-format msgid " declfile: len: %u, flags: %u, fileid: %u\n" msgstr "" -#: vms-alpha.c:7191 +#: vms-alpha.c:7194 #, c-format msgid " rms: cdt: 0x%08x %08x, ebk: 0x%08x, ffb: 0x%04x, rfo: %u\n" msgstr "" -#: vms-alpha.c:7200 +#: vms-alpha.c:7203 #, c-format msgid " filename : %.*s\n" msgstr "" -#: vms-alpha.c:7209 +#: vms-alpha.c:7212 #, c-format msgid " setfile %u\n" msgstr "" -#: vms-alpha.c:7214 vms-alpha.c:7219 +#: vms-alpha.c:7217 vms-alpha.c:7222 #, c-format msgid " setrec %u\n" msgstr "" -#: vms-alpha.c:7224 vms-alpha.c:7229 +#: vms-alpha.c:7227 vms-alpha.c:7232 #, c-format msgid " setlnum %u\n" msgstr "" -#: vms-alpha.c:7234 vms-alpha.c:7239 +#: vms-alpha.c:7237 vms-alpha.c:7242 #, c-format msgid " deflines %u\n" msgstr "" -#: vms-alpha.c:7243 +#: vms-alpha.c:7246 #, c-format msgid " formfeed\n" msgstr "" -#: vms-alpha.c:7247 +#: vms-alpha.c:7250 #, c-format msgid " *unhandled* cmd %u\n" msgstr "" -#: vms-alpha.c:7259 +#: vms-alpha.c:7262 #, c-format msgid "*unhandled* dst type %u\n" msgstr "" -#: vms-alpha.c:7291 +#: vms-alpha.c:7294 #, c-format msgid "cannot read EIHD\n" msgstr "" -#: vms-alpha.c:7294 +#: vms-alpha.c:7297 #, c-format msgid "EIHD: (size: %u, nbr blocks: %u)\n" msgstr "" -#: vms-alpha.c:7297 +#: vms-alpha.c:7300 #, c-format msgid " majorid: %u, minorid: %u\n" msgstr "" -#: vms-alpha.c:7305 +#: vms-alpha.c:7308 msgid "executable" msgstr "" -#: vms-alpha.c:7308 +#: vms-alpha.c:7311 msgid "linkable image" msgstr "" -#: vms-alpha.c:7314 +#: vms-alpha.c:7317 #, c-format msgid " image type: %u (%s)" msgstr "" -#: vms-alpha.c:7320 +#: vms-alpha.c:7323 msgid "native" msgstr "" -#: vms-alpha.c:7323 +#: vms-alpha.c:7326 msgid "CLI" msgstr "" -#: vms-alpha.c:7329 +#: vms-alpha.c:7332 #, c-format msgid ", subtype: %u (%s)\n" msgstr "" -#: vms-alpha.c:7335 +#: vms-alpha.c:7338 #, c-format msgid " offsets: isd: %u, activ: %u, symdbg: %u, imgid: %u, patch: %u\n" msgstr "" -#: vms-alpha.c:7339 +#: vms-alpha.c:7342 #, c-format msgid " fixup info rva: " msgstr "" -#: vms-alpha.c:7341 +#: vms-alpha.c:7344 #, c-format msgid ", symbol vector rva: " msgstr "" -#: vms-alpha.c:7344 +#: vms-alpha.c:7347 #, c-format msgid "" "\n" " version array off: %u\n" msgstr "" -#: vms-alpha.c:7348 +#: vms-alpha.c:7351 #, c-format msgid " img I/O count: %u, nbr channels: %u, req pri: %08x%08x\n" msgstr "" -#: vms-alpha.c:7354 +#: vms-alpha.c:7357 #, c-format msgid " linker flags: %08x:" msgstr "" -#: vms-alpha.c:7384 +#: vms-alpha.c:7387 #, c-format msgid " ident: 0x%08x, sysver: 0x%08x, match ctrl: %u, symvect_size: %u\n" msgstr "" -#: vms-alpha.c:7390 +#: vms-alpha.c:7393 #, c-format msgid " BPAGE: %u" msgstr "" -#: vms-alpha.c:7396 +#: vms-alpha.c:7399 #, c-format msgid ", ext fixup offset: %u, no_opt psect off: %u" msgstr "" -#: vms-alpha.c:7399 +#: vms-alpha.c:7402 #, c-format msgid ", alias: %u\n" msgstr "" -#: vms-alpha.c:7407 +#: vms-alpha.c:7410 #, c-format msgid "system version array information:\n" msgstr "" -#: vms-alpha.c:7411 +#: vms-alpha.c:7414 #, c-format msgid "cannot read EIHVN header\n" msgstr "" -#: vms-alpha.c:7421 +#: vms-alpha.c:7424 #, c-format msgid "cannot read EIHVN version\n" msgstr "" -#: vms-alpha.c:7424 +#: vms-alpha.c:7427 #, c-format msgid " %02u " msgstr "" -#: vms-alpha.c:7428 +#: vms-alpha.c:7431 msgid "BASE_IMAGE " msgstr "" -#: vms-alpha.c:7431 +#: vms-alpha.c:7434 msgid "MEMORY_MANAGEMENT" msgstr "" -#: vms-alpha.c:7434 +#: vms-alpha.c:7437 msgid "IO " msgstr "" -#: vms-alpha.c:7437 +#: vms-alpha.c:7440 msgid "FILES_VOLUMES " msgstr "" -#: vms-alpha.c:7440 +#: vms-alpha.c:7443 msgid "PROCESS_SCHED " msgstr "" -#: vms-alpha.c:7443 +#: vms-alpha.c:7446 msgid "SYSGEN " msgstr "" -#: vms-alpha.c:7446 +#: vms-alpha.c:7449 msgid "CLUSTERS_LOCKMGR " msgstr "" -#: vms-alpha.c:7449 +#: vms-alpha.c:7452 msgid "LOGICAL_NAMES " msgstr "" -#: vms-alpha.c:7452 +#: vms-alpha.c:7455 msgid "SECURITY " msgstr "" -#: vms-alpha.c:7455 +#: vms-alpha.c:7458 msgid "IMAGE_ACTIVATOR " msgstr "" -#: vms-alpha.c:7458 +#: vms-alpha.c:7461 msgid "NETWORKS " msgstr "" -#: vms-alpha.c:7461 +#: vms-alpha.c:7464 msgid "COUNTERS " msgstr "" -#: vms-alpha.c:7464 +#: vms-alpha.c:7467 msgid "STABLE " msgstr "" -#: vms-alpha.c:7467 +#: vms-alpha.c:7470 msgid "MISC " msgstr "" -#: vms-alpha.c:7470 +#: vms-alpha.c:7473 msgid "CPU " msgstr "" -#: vms-alpha.c:7473 +#: vms-alpha.c:7476 msgid "VOLATILE " msgstr "" -#: vms-alpha.c:7476 +#: vms-alpha.c:7479 msgid "SHELL " msgstr "" -#: vms-alpha.c:7479 +#: vms-alpha.c:7482 msgid "POSIX " msgstr "" -#: vms-alpha.c:7482 +#: vms-alpha.c:7485 msgid "MULTI_PROCESSING " msgstr "" -#: vms-alpha.c:7485 +#: vms-alpha.c:7488 msgid "GALAXY " msgstr "" -#: vms-alpha.c:7488 +#: vms-alpha.c:7491 msgid "*unknown* " msgstr "" -#: vms-alpha.c:7491 +#: vms-alpha.c:7494 #, c-format msgid ": %u.%u\n" msgstr "" -#: vms-alpha.c:7504 vms-alpha.c:7763 +#: vms-alpha.c:7507 vms-alpha.c:7766 #, c-format msgid "cannot read EIHA\n" msgstr "" -#: vms-alpha.c:7507 +#: vms-alpha.c:7510 #, c-format msgid "Image activation: (size=%u)\n" msgstr "" -#: vms-alpha.c:7509 +#: vms-alpha.c:7512 #, c-format msgid " First address : 0x%08x 0x%08x\n" msgstr "" -#: vms-alpha.c:7512 +#: vms-alpha.c:7515 #, c-format msgid " Second address: 0x%08x 0x%08x\n" msgstr "" -#: vms-alpha.c:7515 +#: vms-alpha.c:7518 #, c-format msgid " Third address : 0x%08x 0x%08x\n" msgstr "" -#: vms-alpha.c:7518 +#: vms-alpha.c:7521 #, c-format msgid " Fourth address: 0x%08x 0x%08x\n" msgstr "" -#: vms-alpha.c:7521 +#: vms-alpha.c:7524 #, c-format msgid " Shared image : 0x%08x 0x%08x\n" msgstr "" -#: vms-alpha.c:7532 +#: vms-alpha.c:7535 #, c-format msgid "cannot read EIHI\n" msgstr "" -#: vms-alpha.c:7535 +#: vms-alpha.c:7538 #, c-format msgid "Image identification: (major: %u, minor: %u)\n" msgstr "" -#: vms-alpha.c:7538 +#: vms-alpha.c:7541 #, c-format msgid " image name : %.*s\n" msgstr "" -#: vms-alpha.c:7540 +#: vms-alpha.c:7543 #, c-format msgid " link time : %s\n" msgstr "" -#: vms-alpha.c:7542 +#: vms-alpha.c:7545 #, c-format msgid " image ident : %.*s\n" msgstr "" -#: vms-alpha.c:7544 +#: vms-alpha.c:7547 #, c-format msgid " linker ident : %.*s\n" msgstr "" -#: vms-alpha.c:7546 +#: vms-alpha.c:7549 #, c-format msgid " image build ident: %.*s\n" msgstr "" -#: vms-alpha.c:7556 +#: vms-alpha.c:7559 #, c-format msgid "cannot read EIHS\n" msgstr "" -#: vms-alpha.c:7559 +#: vms-alpha.c:7562 #, c-format msgid "Image symbol & debug table: (major: %u, minor: %u)\n" msgstr "" -#: vms-alpha.c:7564 +#: vms-alpha.c:7567 #, c-format msgid " debug symbol table : vbn: %u, size: %u (0x%x)\n" msgstr "" -#: vms-alpha.c:7568 +#: vms-alpha.c:7571 #, c-format msgid " global symbol table: vbn: %u, records: %u\n" msgstr "" -#: vms-alpha.c:7572 +#: vms-alpha.c:7575 #, c-format msgid " debug module table : vbn: %u, size: %u\n" msgstr "" -#: vms-alpha.c:7585 +#: vms-alpha.c:7588 #, c-format msgid "cannot read EISD\n" msgstr "" -#: vms-alpha.c:7595 +#: vms-alpha.c:7598 #, c-format msgid "" "Image section descriptor: (major: %u, minor: %u, size: %u, offset: %u)\n" msgstr "" -#: vms-alpha.c:7602 +#: vms-alpha.c:7605 #, c-format msgid " section: base: 0x%08x%08x size: 0x%08x\n" msgstr "" -#: vms-alpha.c:7607 +#: vms-alpha.c:7610 #, c-format msgid " flags: 0x%04x" msgstr "" -#: vms-alpha.c:7644 +#: vms-alpha.c:7647 #, c-format msgid " vbn: %u, pfc: %u, matchctl: %u type: %u (" msgstr "" -#: vms-alpha.c:7650 +#: vms-alpha.c:7653 msgid "NORMAL" msgstr "" -#: vms-alpha.c:7653 +#: vms-alpha.c:7656 msgid "SHRFXD" msgstr "" -#: vms-alpha.c:7656 +#: vms-alpha.c:7659 msgid "PRVFXD" msgstr "" -#: vms-alpha.c:7659 +#: vms-alpha.c:7662 msgid "SHRPIC" msgstr "" -#: vms-alpha.c:7662 +#: vms-alpha.c:7665 msgid "PRVPIC" msgstr "" -#: vms-alpha.c:7665 +#: vms-alpha.c:7668 msgid "USRSTACK" msgstr "" -#: vms-alpha.c:7673 +#: vms-alpha.c:7676 #, c-format msgid " ident: 0x%08x, name: %.*s\n" msgstr "" -#: vms-alpha.c:7683 +#: vms-alpha.c:7686 #, c-format msgid "cannot read DMT\n" msgstr "" -#: vms-alpha.c:7687 +#: vms-alpha.c:7690 #, c-format msgid "Debug module table:\n" msgstr "" -#: vms-alpha.c:7696 +#: vms-alpha.c:7699 #, c-format msgid "cannot read DMT header\n" msgstr "" -#: vms-alpha.c:7701 +#: vms-alpha.c:7704 #, c-format msgid " module offset: 0x%08x, size: 0x%08x, (%u psects)\n" msgstr "" -#: vms-alpha.c:7711 +#: vms-alpha.c:7714 #, c-format msgid "cannot read DMT psect\n" msgstr "" -#: vms-alpha.c:7714 +#: vms-alpha.c:7717 #, c-format msgid " psect start: 0x%08x, length: %u\n" msgstr "" -#: vms-alpha.c:7727 +#: vms-alpha.c:7730 #, c-format msgid "cannot read DST\n" msgstr "" -#: vms-alpha.c:7737 +#: vms-alpha.c:7740 #, c-format msgid "cannot read GST\n" msgstr "" -#: vms-alpha.c:7741 +#: vms-alpha.c:7744 #, c-format msgid "Global symbol table:\n" msgstr "" -#: vms-alpha.c:7769 +#: vms-alpha.c:7772 #, c-format msgid "Image activator fixup: (major: %u, minor: %u)\n" msgstr "" -#: vms-alpha.c:7772 +#: vms-alpha.c:7775 #, c-format msgid " iaflink : 0x%08x %08x\n" msgstr "" -#: vms-alpha.c:7775 +#: vms-alpha.c:7778 #, c-format msgid " fixuplnk: 0x%08x %08x\n" msgstr "" -#: vms-alpha.c:7778 +#: vms-alpha.c:7781 #, c-format msgid " size : %u\n" msgstr "" -#: vms-alpha.c:7780 +#: vms-alpha.c:7783 #, c-format msgid " flags: 0x%08x\n" msgstr "" -#: vms-alpha.c:7784 +#: vms-alpha.c:7787 #, c-format msgid " qrelfixoff: %5u, lrelfixoff: %5u\n" msgstr "" -#: vms-alpha.c:7788 +#: vms-alpha.c:7791 #, c-format msgid " qdotadroff: %5u, ldotadroff: %5u\n" msgstr "" -#: vms-alpha.c:7792 +#: vms-alpha.c:7795 #, c-format msgid " codeadroff: %5u, lpfixoff : %5u\n" msgstr "" -#: vms-alpha.c:7795 +#: vms-alpha.c:7798 #, c-format msgid " chgprtoff : %5u\n" msgstr "" -#: vms-alpha.c:7798 +#: vms-alpha.c:7801 #, c-format msgid " shlstoff : %5u, shrimgcnt : %5u\n" msgstr "" -#: vms-alpha.c:7800 +#: vms-alpha.c:7803 #, c-format msgid " shlextra : %5u, permctx : %5u\n" msgstr "" -#: vms-alpha.c:7803 +#: vms-alpha.c:7806 #, c-format msgid " base_va : 0x%08x\n" msgstr "" -#: vms-alpha.c:7805 +#: vms-alpha.c:7808 #, c-format msgid " lppsbfixoff: %5u\n" msgstr "" -#: vms-alpha.c:7813 +#: vms-alpha.c:7816 #, c-format msgid " Shareable images:\n" msgstr "" -#: vms-alpha.c:7817 +#: vms-alpha.c:7820 #, c-format msgid " %u: size: %u, flags: 0x%02x, name: %.*s\n" msgstr "" -#: vms-alpha.c:7824 +#: vms-alpha.c:7827 #, c-format msgid " quad-word relocation fixups:\n" msgstr "" -#: vms-alpha.c:7829 +#: vms-alpha.c:7832 #, c-format msgid " long-word relocation fixups:\n" msgstr "" -#: vms-alpha.c:7834 +#: vms-alpha.c:7837 #, c-format msgid " quad-word .address reference fixups:\n" msgstr "" -#: vms-alpha.c:7839 +#: vms-alpha.c:7842 #, c-format msgid " long-word .address reference fixups:\n" msgstr "" -#: vms-alpha.c:7844 +#: vms-alpha.c:7847 #, c-format msgid " Code Address Reference Fixups:\n" msgstr "" -#: vms-alpha.c:7849 +#: vms-alpha.c:7852 #, c-format msgid " Linkage Pairs Referece Fixups:\n" msgstr "" -#: vms-alpha.c:7858 +#: vms-alpha.c:7861 #, c-format msgid " Change Protection (%u entries):\n" msgstr "" -#: vms-alpha.c:7863 +#: vms-alpha.c:7866 #, c-format msgid " base: 0x%08x %08x, size: 0x%08x, prot: 0x%08x " msgstr "" #. FIXME: we do not yet support relocatable link. It is not obvious #. how to do it for debug infos. -#: vms-alpha.c:8694 +#: vms-alpha.c:8706 msgid "%P: relocatable link is not supported\n" msgstr "" -#: vms-alpha.c:8764 +#: vms-alpha.c:8776 msgid "%P: multiple entry points: in modules %B and %B\n" msgstr "" -#: vms-lib.c:1421 +#: vms-lib.c:1423 #, c-format msgid "could not open shared image '%s' from '%s'" msgstr "" @@ -5788,23 +5853,23 @@ msgstr "" msgid "warning: attempt to export undefined symbol `%s'" msgstr "" -#: xcofflink.c:3681 +#: xcofflink.c:3678 msgid "error: undefined symbol __rtinit" msgstr "" -#: xcofflink.c:4060 +#: xcofflink.c:4057 msgid "%B: loader reloc in unrecognized section `%s'" msgstr "" -#: xcofflink.c:4071 +#: xcofflink.c:4068 msgid "%B: `%s' in loader reloc but not loader sym" msgstr "" -#: xcofflink.c:4087 +#: xcofflink.c:4084 msgid "%B: loader reloc in read-only section %A" msgstr "" -#: xcofflink.c:5109 +#: xcofflink.c:5106 #, c-format msgid "TOC overflow: 0x%lx > 0x10000; try -mminimal-toc when compiling" msgstr "" @@ -5815,77 +5880,77 @@ msgid "" "branch." msgstr "" -#: elf32-ia64.c:2290 elf64-ia64.c:2290 +#: elf32-ia64.c:2284 elf64-ia64.c:2284 msgid "@pltoff reloc against local symbol" msgstr "" -#: elf32-ia64.c:3693 elf64-ia64.c:3693 +#: elf32-ia64.c:3687 elf64-ia64.c:3687 #, c-format msgid "%s: short data segment overflowed (0x%lx >= 0x400000)" msgstr "" -#: elf32-ia64.c:3704 elf64-ia64.c:3704 +#: elf32-ia64.c:3698 elf64-ia64.c:3698 #, c-format msgid "%s: __gp does not cover short data segment" msgstr "" -#: elf32-ia64.c:3971 elf64-ia64.c:3971 +#: elf32-ia64.c:3965 elf64-ia64.c:3965 msgid "%B: non-pic code with imm relocation against dynamic symbol `%s'" msgstr "" -#: elf32-ia64.c:4038 elf64-ia64.c:4038 +#: elf32-ia64.c:4032 elf64-ia64.c:4032 msgid "%B: @gprel relocation against dynamic symbol %s" msgstr "" -#: elf32-ia64.c:4101 elf64-ia64.c:4101 +#: elf32-ia64.c:4095 elf64-ia64.c:4095 msgid "%B: linking non-pic code in a position independent executable" msgstr "" -#: elf32-ia64.c:4238 elf64-ia64.c:4238 +#: elf32-ia64.c:4232 elf64-ia64.c:4232 msgid "%B: @internal branch to dynamic symbol %s" msgstr "" -#: elf32-ia64.c:4240 elf64-ia64.c:4240 +#: elf32-ia64.c:4234 elf64-ia64.c:4234 msgid "%B: speculation fixup to dynamic symbol %s" msgstr "" -#: elf32-ia64.c:4242 elf64-ia64.c:4242 +#: elf32-ia64.c:4236 elf64-ia64.c:4236 msgid "%B: @pcrel relocation against dynamic symbol %s" msgstr "" -#: elf32-ia64.c:4439 elf64-ia64.c:4439 +#: elf32-ia64.c:4433 elf64-ia64.c:4433 msgid "unsupported reloc" msgstr "" -#: elf32-ia64.c:4477 elf64-ia64.c:4477 +#: elf32-ia64.c:4471 elf64-ia64.c:4471 msgid "" "%B: missing TLS section for relocation %s against `%s' at 0x%lx in section `" "%A'." msgstr "" -#: elf32-ia64.c:4492 elf64-ia64.c:4492 +#: elf32-ia64.c:4486 elf64-ia64.c:4486 msgid "" "%B: Can't relax br (%s) to `%s' at 0x%lx in section `%A' with size 0x%lx (> " "0x1000000)." msgstr "" -#: elf32-ia64.c:4754 elf64-ia64.c:4754 +#: elf32-ia64.c:4748 elf64-ia64.c:4748 msgid "%B: linking trap-on-NULL-dereference with non-trapping files" msgstr "" -#: elf32-ia64.c:4763 elf64-ia64.c:4763 +#: elf32-ia64.c:4757 elf64-ia64.c:4757 msgid "%B: linking big-endian files with little-endian files" msgstr "" -#: elf32-ia64.c:4772 elf64-ia64.c:4772 +#: elf32-ia64.c:4766 elf64-ia64.c:4766 msgid "%B: linking 64-bit files with 32-bit files" msgstr "" -#: elf32-ia64.c:4781 elf64-ia64.c:4781 +#: elf32-ia64.c:4775 elf64-ia64.c:4775 msgid "%B: linking constant-gp files with non-constant-gp files" msgstr "" -#: elf32-ia64.c:4791 elf64-ia64.c:4791 +#: elf32-ia64.c:4785 elf64-ia64.c:4785 msgid "%B: linking auto-pic files with non-auto-pic files" msgstr "" diff --git a/bfd/reloc.c b/bfd/reloc.c index 6ac71489023..43296499369 100644 --- a/bfd/reloc.c +++ b/bfd/reloc.c @@ -5960,6 +5960,35 @@ ENUMX ENUMDOC Tilera TILE-Gx Relocations. +ENUM + BFD_RELOC_EPIPHANY_SIMM8 +ENUMDOC + Adapteva EPIPHANY - 8 bit signed pc-relative displacement +ENUM + BFD_RELOC_EPIPHANY_SIMM24 +ENUMDOC + Adapteva EPIPHANY - 24 bit signed pc-relative displacement +ENUM + BFD_RELOC_EPIPHANY_HIGH +ENUMDOC + Adapteva EPIPHANY - 16 most-significant bits of absolute address +ENUM + BFD_RELOC_EPIPHANY_LOW +ENUMDOC + Adapteva EPIPHANY - 16 least-significant bits of absolute address +ENUM + BFD_RELOC_EPIPHANY_SIMM11 +ENUMDOC + Adapteva EPIPHANY - 11 bit signed number - add/sub immediate +ENUM + BFD_RELOC_EPIPHANY_IMM11 +ENUMDOC + Adapteva EPIPHANY - 11 bit sign-magnitude number (ld/st displacement) +ENUM + BFD_RELOC_EPIPHANY_IMM8 +ENUMDOC + Adapteva EPIPHANY - 8 bit immediate for 16 bit mov instruction. + ENDSENUM BFD_RELOC_UNUSED diff --git a/bfd/targets.c b/bfd/targets.c index 46c2c9442e3..b6d8116f876 100644 --- a/bfd/targets.c +++ b/bfd/targets.c @@ -607,6 +607,7 @@ extern const bfd_target bfd_elf32_crx_vec; extern const bfd_target bfd_elf32_d10v_vec; extern const bfd_target bfd_elf32_d30v_vec; extern const bfd_target bfd_elf32_dlx_big_vec; +extern const bfd_target bfd_elf32_epiphany_vec; extern const bfd_target bfd_elf32_fr30_vec; extern const bfd_target bfd_elf32_frv_vec; extern const bfd_target bfd_elf32_frvfdpic_vec; @@ -968,6 +969,7 @@ static const bfd_target * const _bfd_target_vector[] = &bfd_elf32_d10v_vec, &bfd_elf32_d30v_vec, &bfd_elf32_dlx_big_vec, + &bfd_elf32_epiphany_vec, &bfd_elf32_fr30_vec, &bfd_elf32_frv_vec, &bfd_elf32_frvfdpic_vec, diff --git a/cpu/ChangeLog b/cpu/ChangeLog index 0ab89be9e28..857a81ea3e5 100644 --- a/cpu/ChangeLog +++ b/cpu/ChangeLog @@ -1,3 +1,8 @@ +2011-10-25 Joern Rennecke <joern.rennecke@embecosm.com> + + * cpu/epiphany.cpu: New file. + * cpu/epiphany.opc: New file. + 2011-08-22 Nick Clifton <nickc@redhat.com> * fr30.cpu: Newly contributed file. diff --git a/cpu/epiphany.cpu b/cpu/epiphany.cpu new file mode 100644 index 00000000000..8d4a57b55b8 --- /dev/null +++ b/cpu/epiphany.cpu @@ -0,0 +1,2935 @@ +; Adapteva EPIPHANY CPU description. -*- Scheme -*- +; Copyright 2011 +; Free Software Foundation, Inc. +; +; Contributed by Embecosm on behalf of Adapteva, Inc. +; This file is part of the GNU Binutils and of GDB. +; +; This program is free software; you can redistribute it and/or modify +; it under the terms of the GNU General Public License as published by +; the Free Software Foundation; either version 3 of the License, or +; (at your option) any later version. +; +; This program is distributed in the hope that it will be useful, +; but WITHOUT ANY WARRANTY; without even the implied warranty of +; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +; GNU General Public License for more details. +; +; You should have received a copy of the GNU General Public License +; along with this program; if not, write to the Free Software +; Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, +; MA 02110-1301, USA. + +(include "simplify.inc") + ; define-arch must appear first + +(define-arch + (name epiphany) ; name of cpu family + (comment "Adapteva, Inc. EPIPHANY family") + (default-alignment aligned) + (insn-lsb0? #t) + + ; - a 16/32 bit instruction machine (the default) + + (machs epiphany32) + (isas epiphany) + ) + + ; Attributes. + +(define-attr + (for insn) + (type boolean) + (name SHORT-INSN) + (comment "instruction is a 16 bit form") + ) + +;; 3 bit add/sub immediate forms - useful for relaxing into 11 bit form +(define-attr + (for insn) + (type boolean) + (name IMM3) + (comment "instruction has a 3 bit immediate form") + ) + +;; 8 bit mov immediate forms - useful for relaxing into 16 bit form +(define-attr + (for insn) + (type boolean) + (name IMM8) + (comment "instruction has a 8 bit immediate form") + ) + + ; Instruction set parameters. + +(define-isa + (name epiphany) + (comment "Adapteva, Inc. EPIPHANY32 ISA") + + (default-insn-word-bitsize 32) + (default-insn-bitsize 32) + (base-insn-bitsize 32) + (decode-assist (3 2 1 0)) ; CGEN can figure this out + (liw-insns 1) ; # instructions fetched at once + ) + + ; Cpu family definitions. + + +(define-cpu + ; cpu names must be distinct from the architecture name and machine names. + (name epiphanybf) + (comment "Adapteva, Inc. EPIPHANY Family") + (endian little) + (word-bitsize 32) + ) + +(define-cpu + (name epiphanymf) + (comment "Adapteva, Inc. EPIPHANY Family") + (endian little) + (word-bitsize 32) + ) + + +(define-mach + (name epiphany32) + (comment "Adapteva EPIPHANY") + (cpu epiphanybf) + ) + + + ; Model descriptions. + +(define-model + (name epiphany32) (comment "Adapteva EPIPHANY 32/16") (attrs) + (mach epiphany32) + + (unit u-exec "Execution Unit" () + 1 1 ; issue done + () ; state + () ; inputs + () ; outputs + () ; profile action (default) + ) + ) + + + + ; Instruction fields. + ; + ; Attributes: + ; XXX: what EPIPHANY attrs + ; PCREL-ADDR: pc relative value (for reloc and disassembly purposes) + ; ABS-ADDR: absolute address (for reloc and disassembly purposes?) + ; RESERVED: bits are not used to decode insn, must be all 0 + ; RELOC: there is a relocation associated with this field + +(define-attr + (for ifield operand) + (type boolean) + (name RELOC) + (comment "there is a reloc associated with this field (experiment)") + ) + +;; define the fields of the instruction. +;; name description ATTR MSB LEN +(dnf f-opc "primary opcode" () 3 4) +(dnf f-opc-4-1 "secondary opcode" () 4 1) +(dnf f-opc-6-3 "secondary opcode" () 6 3) ;; +(dnf f-opc-8-5 "tertiary opcode" () 8 5) ;; +(dnf f-opc-19-4 "additional opcode bits" () 19 4) +(dnf f-condcode "condition codes" () 7 4) +(dnf f-secondary-ccs "flag for secondary ccs" () 7 1) +(dnf f-shift "shift amount" () 9 5) +(dnf f-wordsize "load/store size" () 6 2) +(dnf f-store "load/store flag" () 4 1) ;; 0==load,1==store +(dnf f-opc-8-1 "opcode bits" () 8 1) +(dnf f-opc-31-32 "all opcode set" () 31 32) + +(df f-simm8 "branch displacement" (PCREL-ADDR RELOC) 15 8 INT + ((value pc) (sra SI (sub SI value pc) 1)) + ((value pc) (add SI (sll SI value 1) pc))) + +(df f-simm24 "branch displacement" (PCREL-ADDR RELOC) 31 24 INT + ((value pc) (sra SI (sub SI value pc) 1)) + ((value pc) (add SI (sll SI value 1) pc))) + +(df f-sdisp3 "signed immediate 3 bit" () 9 3 INT #f #f) + +(dnf f-disp3 "address offset" () 9 3) +(dnf f-disp8 "address offset" () 23 8) + +(dnf f-imm8 "move/add/sub imm8" () 12 8) +(dnf f-imm-27-8 "move/add/sub imm16" () 27 8) +(dnf f-addsubx "+/- index address" () 20 1) +(dnf f-subd "+/- displ address" () 24 1) +(dnf f-pm "post-modify immediate" () 25 1) + +(dnf f-rm "short rm" () 9 3) ;; RM +(dnf f-rn "short rn" () 12 3) ;; RN +(dnf f-rd "short rd" () 15 3) ;; RD + +(dnf f-rm-x "extension rm" () 25 3) ;; RM +(dnf f-rn-x "extension rn" () 28 3) ;; RN +(dnf f-rd-x "extension rd" () 31 3) ;; RD + +(dnf f-dc-9-1 "DC" (RESERVED) 9 1) + +(dnf f-sn "short sn" () 12 3) ;; SN +(dnf f-sd "short sd" () 15 3) ;; SD + +(dnf f-sn-x "extension sn" () 28 3) ;; SN +(dnf f-sd-x "extension sd" () 31 3) ;; SD + + + +(dnf f-dc-7-4 "movts zeros" () 7 4) +(dnf f-trap-swi-9-1 "trap or swi" () 9 1) +(dnf f-gien-gidis-9-1 "gien or gidis" () 9 1) + + +(dnf f-dc-15-3 "DC" (RESERVED) 15 3) +(dnf f-dc-15-7 "DC" (RESERVED) 15 7) +(dnf f-dc-15-6 "DC" () 15 6) +(dnf f-trap-num "trap number" () 15 6) + +(dnf f-dc-20-1 "DC" (RESERVED) 20 1) + +(dnf f-dc-21-1 "DC" (RESERVED) 21 1) +(dnf f-dc-21-2 "DC" (RESERVED) 21 2) + +(dnf f-dc-22-3 "DC" (RESERVED) 22 3) +(dnf f-dc-22-2 "DC" (RESERVED) 22 2) +(dnf f-dc-22-1 "DC" (RESERVED) 22 1) + +(dnf f-dc-25-6 "DC" (RESERVED) 25 6) +(dnf f-dc-25-4 "DC" (RESERVED) 25 4) +(dnf f-dc-25-2 "DC" (RESERVED) 25 2) +(dnf f-dc-25-1 "DC" (RESERVED) 25 1) + +(dnf f-dc-28-1 "DC" (RESERVED) 28 1) +(dnf f-dc-31-3 "DC" (RESERVED) 31 3) + +(dnmf f-disp11 "Unsigned offset for load/store" () UINT (f-disp3 f-disp8) + (sequence () + (set (ifield f-disp8) (and (srl (ifield f-disp11) 3) (const 255))) + (set (ifield f-disp3) (and (ifield f-disp11) 7))) + (sequence () + (set (ifield f-disp11) (or (sll (ifield f-disp8) 3) + (ifield f-disp3))) + ) + ) + + +(dnmf f-sdisp11 "Signed offset for load/store" () INT (f-disp3 f-disp8) + (sequence () ;encode + (set (ifield f-disp8) (and #xff (srl SI (ifield f-sdisp11) 3))) + (set (ifield f-disp3) (and SI (ifield f-sdisp11) 7))) + (sequence () ;decode + (set (ifield f-sdisp11) + (sra SI (sll SI (or SI (sll (ifield f-disp8) 3) + (ifield f-disp3)) + 21) + 21))) + ) + +(dnmf f-imm16 "Short immediate for move/add/sub" () UINT (f-imm8 f-imm-27-8) + (sequence () + (set (ifield f-imm8) (and (ifield f-imm16) #xff)) + (set (ifield f-imm-27-8) (srl (ifield f-imm16) 8))) + (sequence () + (set (ifield f-imm16) (or (sll (ifield f-imm-27-8) 8) + (ifield f-imm8)))) + ) + + +;; 32 bit instructions have the register number broken into two non-contiguous fields + +(define-pmacro (x-reg-field reg) + (define-multi-ifield + (name (.sym "f-" reg "6")) + (mode UINT) + (subfields (.sym "f-" reg "-x") (.sym "f-" reg)) + (insert (sequence () + (set (ifield (.sym "f-" reg)) (and (ifield (.sym "f-" reg "6")) + (const 7))) + (set (ifield (.sym "f-" reg "-x")) (srl (ifield (.sym "f-" reg "6")) + (const 3))) + )) + (extract (sequence () + (set (ifield (.sym "f-" reg "6")) (or (sll (ifield (.sym "f-" reg "-x")) + (const 3)) + (ifield (.sym "f-" reg)))) + )) + ) + ) + +(x-reg-field rd) ; f-rd6 +(x-reg-field rn) ; f-rn6 +(x-reg-field rm) ; f-rm6 +(x-reg-field sd) ; f-sd6 +(x-reg-field sn) ; f-sn6 + + +;;;;;;;;;; + ; Enums. ; +;;;;;;;;;; + + ; insn-opc: bits 3..0 - major family selector +(define-normal-insn-enum insn-opc "opc enums" () OP4_ f-opc + ( + BRANCH16 ;; 0000 + LDSTR16X ;; 0001 + FLOW16 ;; 0010 + IMM16 ;; 0011 + LDSTR16D ;; 0100 + LDSTR16P ;; 0101 + LSHIFT16 ;; 0110 - logical shift + DSP16 ;; 0111 - 3 reg DSP 16 bit insns + BRANCH ;; 1000 + LDSTRX ;; 1001 + ALU16 ;; 1010 - 3 reg 16 bit + IMM32 ;; 1011 + LDSTRD ;; 1100 + LDSTRP ;; 1101 + ASHIFT16 ;; 1110 ASR, BITR + MISC ;; 1111 - 32 bit shifts, 3 reg ALU, 3 reg DSP, FLOW, BITR + ) + ) + +(define-normal-insn-enum insn-wordsize "memory access width" () OPW_ f-wordsize + ; specifies the size of a memory load/store operation + (BYTE SHORT WORD DOUBLE) + ) + +(define-normal-insn-enum insn-memory-access "memory access direction" () OP_ f-store + ; load=0, store=1 + (LOAD STORE) + ) + + ; enum for trap codes used by simulator +(define-normal-insn-enum trap-codes "trap instruction dispatch code" () TRAP_ f-trap-num + (write read open exit pass fail close other) + ) + + ; cond branch: bits 7..4 + ; +(define-normal-insn-enum insn-cond "branch conditions" () OPC_ f-condcode + (EQ NE GTU GTEU LTEU LTU GT GTE LT LTE BEQ BNE BLT BLTE B BL)) + + ; dsp 3 operand opcodes +(define-normal-insn-enum insn-bop "binary operator subcodes" () OPB_ f-opc-6-3 + (EOR ADD LSL SUB LSR AND ASR ORR)) + + ; dsp 3 operand opcodes +(define-normal-insn-enum insn-bopext "binary operator subcodes" () OPBE_ f-opc-6-3 + (FEXT FDEP LFSR - - - - -)) + + +(define-normal-insn-enum insn-fop "floating operators" () OPF_ f-opc-6-3 + (ADD SUB MUL MADD MSUB FLOAT FIX FABS)) + +(define-normal-insn-enum insn-fopexn "extended floating operators" () OPF_ f-opc-6-3 + (FRECIP FSQRT - - - - - -)) + + + + +; Immediate operation secondary opcodes +(define-normal-insn-enum insn-immop "immediate operators" () OPI_ f-opc-6-3 + (- ADD - SUB - - - TRAP) ; TRAP is special extension for simulator + ) + + ; don't care fields +(define-normal-insn-enum insn-dc-25-2 "don't cares" () OPI_25_2_ f-dc-25-2 + (MBZ)) + +; General Register keyword names. +(define-keyword + (name gr-names) + (print-name h-registers) + (prefix "") + (values +; some preferred aliases + (sb 9) (sl 10) (fp 11) (ip 12) (sp 13) (lr 14) +; the default register names + (r0 0) (r1 1) (r2 2) (r3 3) (r4 4) (r5 5) (r6 6) (r7 7) + (r8 8) (r9 9) (r10 10) (r11 11) (r12 12) (r13 13) (r14 14) (r15 15) + (r16 16) (r17 17) (r18 18) (r19 19) (r20 20) (r21 21) (r22 22) (r23 23) + (r24 24) (r25 25) (r26 26) (r27 27) (r28 28) (r29 29) (r30 30) (r31 31) + (r32 32) (r33 33) (r34 34) (r35 35) (r36 36) (r37 37) (r38 38) (r39 39) + (r40 40) (r41 41) (r42 42) (r43 43) (r44 44) (r45 45) (r46 46) (r47 47) + (r48 48) (r49 49) (r50 50) (r51 51) (r52 52) (r53 53) (r54 54) (r55 55) + (r56 56) (r57 57) (r58 58) (r59 59) (r60 60) (r61 61) (r62 62) (r63 63) +; some less popular aliases + (a1 0) (a2 1) (a3 2) (a4 3) (v1 4) (v2 5) (v3 6) (v4 7) + (v5 8) (v6 9) (v7 10) (v8 11) + ) + ) + +(define-normal-insn-enum post-index "+/- index register" () DIR_ f-addsubx (POSTINC POSTDEC)) + +(define-normal-insn-enum disp-post-modify "postmodify displacement" () PMOD_ f-pm (DISP POST)) + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + ; Hardware pieces. +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + +;; 64 general-purpose registers +(define-hardware + (name h-registers) + (comment "all addressable registers") + (type register SI (64)) + (attrs PROFILE CACHE-ADDR) + (indices extern-keyword gr-names) + ) + + + +;; Same 64 registers as floating point registers +(define-hardware + (name h-fpregisters) + (comment "all GPRs as float values") + (type register SF (64)) + (attrs PROFILE VIRTUAL) + (indices extern-keyword gr-names) + (get (index) (subword SF (reg h-registers index) 0)) + (set (index newval) (set (reg h-registers index) (subword SI newval 0))) + ) + +;; define processor status bits as physical hardware + +(define-pmacro (psw-h-bit name cmt) + (dsh name cmt () (register BI))) + +(psw-h-bit h-zbit "integer zero bit") +(psw-h-bit h-nbit "integer neg bit") +(psw-h-bit h-cbit "integer carry bit") +(psw-h-bit h-vbit "integer overflow bit") +(psw-h-bit h-vsbit "integer overflow sticky") + + +(psw-h-bit h-bzbit "floating point zero bit") +(psw-h-bit h-bnbit "floating point neg bit") +(psw-h-bit h-bvbit "floating point ovfl bit") +(psw-h-bit h-bubit "floating point underfl bit") +(psw-h-bit h-bibit "floating point invalid bit") +(psw-h-bit h-bcbit "floating point carry bit") + +(psw-h-bit h-bvsbit "floating point overflow sticky") +(psw-h-bit h-bisbit "floating point invalid sticky") +(psw-h-bit h-busbit "floating point underflow sticky") + +(psw-h-bit h-expcause0bit "exceprion cause bit0") +(psw-h-bit h-expcause1bit "exceprion cause bit1") +(psw-h-bit h-expcause2bit "external load stalled bit") +(psw-h-bit h-extFstallbit "external fetch stalled bit") + +(psw-h-bit h-trmbit "0=round to nearest, 1=trunacte select bit") +(psw-h-bit h-invExcEnbit "invalid exception enable bit") +(psw-h-bit h-ovfExcEnbit "overflow exception enable bit") +(psw-h-bit h-unExcEnbit "underflow exception enablebit ") + +(psw-h-bit h-timer0bit0 "timer 0 mode selection 0") +(psw-h-bit h-timer0bit1 "timer 0 mode selection 1") +(psw-h-bit h-timer0bit2 "timer 0 mode selection 2") +(psw-h-bit h-timer0bit3 "timer 0 mode selection 3") +(psw-h-bit h-timer1bit0 "timer 1 mode selection 0") +(psw-h-bit h-timer1bit1 "timer 1 mode selection 1") +(psw-h-bit h-timer1bit2 "timer 1 mode selection 2") +(psw-h-bit h-timer1bit3 "timer 1 mode selection 3") + +(psw-h-bit h-mbkptEnbit "multicore bkpt enable") +(psw-h-bit h-clockGateEnbit "clock gating enable bkpt enable") + + +(psw-h-bit h-coreCfgResBit12 "core config bit 12") +(psw-h-bit h-coreCfgResBit13 "core config bit 13") +(psw-h-bit h-coreCfgResBit14 "core config bit 14") +(psw-h-bit h-coreCfgResBit15 "core config bit 15") +(psw-h-bit h-coreCfgResBit16 "core config bit 16") + + +(psw-h-bit h-coreCfgResBit20 "core config bit 20") +(psw-h-bit h-coreCfgResBit21 "core config bit 21") + +(psw-h-bit h-coreCfgResBit24 "core config bit 24") +(psw-h-bit h-coreCfgResBit25 "core config bit 25") +(psw-h-bit h-coreCfgResBit26 "core config bit 26") +(psw-h-bit h-coreCfgResBit27 "core config bit 27") +(psw-h-bit h-coreCfgResBit28 "core config bit 28") +(psw-h-bit h-coreCfgResBit29 "core config bit 29") +(psw-h-bit h-coreCfgResBit30 "core config bit 30") +(psw-h-bit h-coreCfgResBit31 "core config bit 31") + + +(psw-h-bit h-arithmetic-modebit0 "arithmetic mode bit0") +(psw-h-bit h-arithmetic-modebit1 "arithmetic mode bit1") +(psw-h-bit h-arithmetic-modebit2 "arithmetic mode bit2") + + +(psw-h-bit h-gidisablebit "global interrupt disable bit") +(psw-h-bit h-kmbit "kernel mode bit") +(psw-h-bit h-caibit "core active indicator mode bit") +(psw-h-bit h-sflagbit "sflag bit") + + + ; Define operands for each of the physical bits +(define-pmacro (psw-bit name hname cmt) + (dnop name cmt (SEM-ONLY) hname f-nil) + ) + +(psw-bit zbit h-zbit "integer zero bit") +(psw-bit nbit h-nbit "integer neg bit") +(psw-bit cbit h-cbit "integer carry bit") +(psw-bit vbit h-vbit "integer overflow bit") + +(psw-bit bzbit h-bzbit "floating point zero bit") +(psw-bit bnbit h-bnbit "floating point neg bit") +(psw-bit bvbit h-bvbit "floating point ovfl bit") +(psw-bit bcbit h-bcbit "floating point carry bit") + +(psw-bit bubit h-bubit "floating point underfl bit") +(psw-bit bibit h-bibit "floating point invalid bit") + + +(psw-bit vsbit h-vsbit "integer overflow sticky") +(psw-bit bvsbit h-bvsbit "floating point overflow sticky") +(psw-bit bisbit h-bisbit "floating point invalid sticky") +(psw-bit busbit h-busbit "floating point underflow sticky") +(psw-bit expcause0bit h-expcause0bit "exceprion cause bit0") +(psw-bit expcause1bit h-expcause1bit "exceprion cause bit1") + + +(psw-bit expcause2bit h-expcause2bit "external load stalled bit") +(psw-bit extFstallbit h-extFstallbit "external fetch stalled bit") + +(psw-bit trmbit h-trmbit "0=round to nearest, 1=trunacte selct bit") +(psw-bit invExcEnbit h-invExcEnbit "invalid exception enable bit") +(psw-bit ovfExcEnbit h-ovfExcEnbit "overflow exception enable bit") +(psw-bit unExcEnbit h-unExcEnbit "underflow exception enable bit") + +(psw-bit timer0bit0 h-timer0bit0 "timer 0 mode selection 0") +(psw-bit timer0bit1 h-timer0bit1 "timer 0 mode selection 1") +(psw-bit timer0bit2 h-timer0bit2 "timer 0 mode selection 2") +(psw-bit timer0bit3 h-timer0bit3 "timer 0 mode selection 3") + +(psw-bit timer1bit0 h-timer1bit0 "timer 1 mode selection 0") +(psw-bit timer1bit1 h-timer1bit1 "timer 1 mode selection 1") +(psw-bit timer1bit2 h-timer1bit2 "timer 1 mode selection 2") +(psw-bit timer1bit3 h-timer1bit3 "timer 1 mode selection 3") + +(psw-bit mbkptEnbit h-mbkptEnbit "multicore bkpt enable") +(psw-bit clockGateEnbit h-clockGateEnbit "clock gate enable enable") + +(psw-bit arithmetic-modebit0 h-arithmetic-modebit0 "arithmetic mode bit0") +(psw-bit arithmetic-modebit1 h-arithmetic-modebit1 "arithmetic mode bit1") +(psw-bit arithmetic-modebit2 h-arithmetic-modebit2 "arithmetic mode bit2") + +(psw-bit coreCfgResBit12 h-coreCfgResBit12 "core config bit 12") +(psw-bit coreCfgResBit13 h-coreCfgResBit13 "core config bit 13") +(psw-bit coreCfgResBit14 h-coreCfgResBit14 "core config bit 14") +(psw-bit coreCfgResBit15 h-coreCfgResBit15 "core config bit 15") +(psw-bit coreCfgResBit16 h-coreCfgResBit16 "core config bit 16") + +(psw-bit coreCfgResBit20 h-coreCfgResBit20 "core config bit 20") +(psw-bit coreCfgResBit21 h-coreCfgResBit21 "core config bit 21") + +(psw-bit coreCfgResBit24 h-coreCfgResBit24 "core config bit 24") +(psw-bit coreCfgResBit25 h-coreCfgResBit25 "core config bit 25") +(psw-bit coreCfgResBit26 h-coreCfgResBit26 "core config bit 26") +(psw-bit coreCfgResBit27 h-coreCfgResBit27 "core config bit 27") +(psw-bit coreCfgResBit28 h-coreCfgResBit28 "core config bit 28") +(psw-bit coreCfgResBit29 h-coreCfgResBit29 "core config bit 29") +(psw-bit coreCfgResBit30 h-coreCfgResBit30 "core config bit 30") +(psw-bit coreCfgResBit31 h-coreCfgResBit31 "core config bit 31") + + +(psw-bit gidisablebit h-gidisablebit "global interrupt disable bit") +(psw-bit kmbit h-kmbit "kernel mode bit") +(psw-bit caibit h-caibit "core actibe indicator bit") +(psw-bit sflagbit h-sflagbit "sflag bit") + + + + +;; Special registers - accessed via MOVTS and MOVFS. +;; +;; "Core control and status" in group MR0=0, MR1=0 + +(define-keyword + (name cr-names) + (print-name h-core-registers) + (prefix "") + (values (config 0) + (status 1) ; unified condition codes + (pc 2) ; virtualized PC + (debug 3); + (iab 4) + (lc 5);loop counter Not impemented + (ls 6);loop start address Not impemented + (le 7);loop end address Not impemented + (iret 8) + (imask 9) + (ilat 10) + (ilatst 11) + (ilatcl 12) + (ipend 13) + (ctimer0 14) + (ctimer1 15) + (hstatus 16) + ) + ) +;; DMA registers in group MR0=1, MR1=0 + +(define-keyword + (name crdma-names) + (print-name h-coredma-registers) + (prefix "") + (values + + + (dma0config 0) + (dma0stride 1) + (dma0count 2) + + (dma0srcaddr 3) + (dma0dstaddr 4) + + (dma0auto0 5) + (dma0auto1 6) + + (dma0status 7) + + (dma1config 8) + (dma1stride 9) + (dma1count 10) + + (dma1srcaddr 11) + (dma1dstaddr 12) + + (dma1auto0 13) + (dma1auto1 14) + + (dma1status 15) + + ) + ) +;; mem configuration registers in group MR0=0, MR1=1 + +(define-keyword + (name crmem-names) + (print-name h-coremem-registers) + (prefix "") + (values + (memconfig 0) + (memstatus 1) + (memprotect 2) + (memreserve 3) + ) + ) + +;; mesh configuration registers in group MR0=1, MR1=1 + +(define-keyword + (name crmesh-names) + (print-name h-coremesh-registers) + (prefix "") + + (values + + + (meshconfig 0) + (coreid 1) + (meshmulticast 2) + (swreset 3) + ) + ) + + + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + ; PC is a byte-addressed register +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + +(dnh h-pc "program counter" (PC PROFILE) (pc) () () ()) + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + ; Memory Effective Address wants to be visible +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + +(dnh h-memaddr "memory effective address" (PROFILE) (register SI) () () ()) +(dnop memaddr "memory effective address" (SEM-ONLY) h-memaddr f-nil) + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + ; Special Core Registers +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; STATUS +;; [0]=core active indicator +;; [1]=global interrupt disable +;; [2]=processor mode(1=user mode, 0=kernel mode) +;; [3]=wired AND global flag + +;; [4]=integer zero zbit +;; [5]=integer negative nbit +;; [6]=integer carry cbit +;; [7]=integer overflow vbit + +;; [8]=fpu zero flag bzbit +;; [9]=fpu negative flag bnbit +;; [10]=fpu overflow flag bvbit +;; [11]=fpu carry flag(not used) bcbit + +;; [12]=ialu overflow flag(sticky) vsbit +;; [13]=fpu invalid flag(sticky) bisbit +;; [14]=fpu overflow flag(sticky) bvsbit +;; [15]=fpu underflow flag(sticky) busbit + +;; [17:16]=exception cause 00=no exception 01=load-store exception 10=fpu exception 11=unimplemented instruction +;; expcause1bit +;; expcause0bit + +;; [18]=external load stalled expcause2bit +;; [19]=external fetch stalled extFstallbit + +;; [31:20]=RESERVED + + + + + +(define-hardware + (name h-core-registers) + (comment "Special Core Registers") + (type register USI (17)) + (attrs) + (indices extern-keyword cr-names) + (get (index) + (cond USI + ((eq index (const 1)) ; STATUS reg ? + (or (or (or (or (sll USI kmbit (const 2)) + (sll USI gidisablebit (const 1))) + (or (or (sll USI expcause1bit (const 17)) + (sll USI expcause0bit (const 16))) + (or (sll USI expcause2bit (const 18)) + (sll USI extFstallbit (const 19))))) + (or (or (or (sll USI busbit (const 15)) + (sll USI bisbit (const 13))) + (or (sll USI bvsbit (const 14)) + (sll USI vsbit (const 12)))) + (or (or (sll USI bvbit (const 10)) + (sll USI bcbit (const 11))) + (or (sll USI bnbit (const 9)) + (sll USI bzbit (const 8)))))) + (or (or (or (sll USI vbit (const 7)) + (sll USI cbit (const 6))) + (or (sll USI nbit (const 5)) + (sll USI zbit (const 4)))) + (or (sll USI sflagbit (const 3)) + (sll USI (const 1) (const 0)))))) ;caibit + ((eq index (const 0)) ; Config reg ? + (or (or (or (or (or (or (sll USI timer0bit2 (const 6)) + (sll USI timer0bit3 (const 7))) + (or (or (sll USI coreCfgResBit28 (const 28)) + (sll USI coreCfgResBit29 (const 29))) + (or (sll USI coreCfgResBit30 (const 30)) + (sll USI coreCfgResBit31 (const 31))))) + (or (or (sll USI coreCfgResBit24 (const 24)) + (sll USI coreCfgResBit25 (const 25))) + (or (sll USI coreCfgResBit26 (const 26)) + (sll USI coreCfgResBit27 (const 27))))) + (or (or (sll USI timer0bit0 (const 4)) + (sll USI timer0bit1 (const 5))) + (or (sll USI coreCfgResBit14 (const 14)) + (sll USI coreCfgResBit15 (const 15))))) + (or (or (or (or (sll USI timer1bit2 (const 10)) + (sll USI timer1bit3 (const 11))) + (or (sll USI coreCfgResBit12 (const 12)) + (sll USI coreCfgResBit13 (const 13)))) + (or (sll USI clockGateEnbit (const 22)) + (sll USI mbkptEnbit (const 23)))) + (or (or (sll USI timer1bit0 (const 8)) + (sll USI timer1bit1 (const 9))) + (or (sll USI coreCfgResBit20 (const 20)) + (sll USI coreCfgResBit21 (const 21)))))) + (or (or (sll USI invExcEnbit (const 1)) + (sll USI ovfExcEnbit (const 2))) + (or (or (sll USI trmbit (const 0)) + (sll USI unExcEnbit (const 3))) + (or (or (sll USI arithmetic-modebit0 (const 17)) + (sll USI arithmetic-modebit1 (const 18))) + (or (sll USI arithmetic-modebit2 (const 19)) + (sll USI coreCfgResBit16 (const 16)))))))) ;config reg + + ((eq index (const 2)) (raw-reg USI h-pc)) ;PC reg + + (else (raw-reg USI h-core-registers index)))) + + (set (index val) + (cond VOID + ((eq index (const 0)) ; CONFIG reg + (sequence () + (set trmbit (and (const 1) (srl val (const 0)))) + (set invExcEnbit (and (const 1) (srl val (const 1)))) + (set ovfExcEnbit (and (const 1) (srl val (const 2)))) + (set unExcEnbit (and (const 1) (srl val (const 3)))) + (set timer0bit0 (and (const 1) (srl val (const 4)))) + (set timer0bit1 (and (const 1) (srl val (const 5)))) + (set timer0bit2 (and (const 1) (srl val (const 6)))) + (set timer0bit3 (and (const 1) (srl val (const 7)))) + (set timer1bit0 (and (const 1) (srl val (const 8)))) + (set timer1bit1 (and (const 1) (srl val (const 9)))) + (set timer1bit2 (and (const 1) (srl val (const 10)))) + (set timer1bit3 (and (const 1) (srl val (const 11)))) + + (set coreCfgResBit12 (and (const 1) (srl val (const 12)))) + (set coreCfgResBit13 (and (const 1) (srl val (const 13)))) + (set coreCfgResBit14 (and (const 1) (srl val (const 14)))) + (set coreCfgResBit15 (and (const 1) (srl val (const 15)))) + (set coreCfgResBit16 (and (const 1) (srl val (const 16)))) + + (set arithmetic-modebit0 (and (const 1) (srl val (const 17)))) + (set arithmetic-modebit1 (and (const 1) (srl val (const 18)))) + (set arithmetic-modebit2 (and (const 1) (srl val (const 19)))) + + (set coreCfgResBit20 (and (const 1) (srl val (const 20)))) + (set coreCfgResBit21 (and (const 1) (srl val (const 21)))) + + (set clockGateEnbit (and (const 1) (srl val (const 22)))) + (set mbkptEnbit (and (const 1) (srl val (const 23)))) + + (set coreCfgResBit24 (and (const 1) (srl val (const 24)))) + (set coreCfgResBit25 (and (const 1) (srl val (const 25)))) + (set coreCfgResBit26 (and (const 1) (srl val (const 26)))) + (set coreCfgResBit27 (and (const 1) (srl val (const 27)))) + (set coreCfgResBit28 (and (const 1) (srl val (const 28)))) + (set coreCfgResBit29 (and (const 1) (srl val (const 29)))) + (set coreCfgResBit30 (and (const 1) (srl val (const 30)))) + (set coreCfgResBit31 (and (const 1) (srl val (const 31)))) + + (set (raw-reg USI h-core-registers index) val) + ;; check LSB of CONFIG for rounding mode + (c-call "epiphany_set_rounding_mode" val) + ) + ) + ((eq index (const 1)) ;STATUS reg ; TODO check which bits can be set or clear + (sequence ((USI newval)) + (set newval (and val (const #xfff2))) + (set extFstallbit (and (const 1) (srl newval (const 19)))) + (set expcause2bit (and (const 1) (srl newval (const 18)))) + (set expcause1bit (and (const 1) (srl newval (const 17)))) + (set expcause0bit (and (const 1) (srl newval (const 16)))) + (set busbit (and (const 1) (srl newval (const 15)))) + (set bisbit (and (const 1) (srl newval (const 13)))) + (set bvsbit (and (const 1) (srl newval (const 14)))) + (set vsbit (and (const 1) (srl newval (const 12)))) + (set bvbit (and (const 1) (srl newval (const 10)))) + (set bcbit (and (const 1) (srl newval (const 11)))) + (set bnbit (and (const 1) (srl newval (const 9)))) + (set bzbit (and (const 1) (srl newval (const 8)))) + (set vbit (and (const 1) (srl newval (const 7)))) + (set cbit (and (const 1) (srl newval (const 6)))) + (set nbit (and (const 1) (srl newval (const 5)))) + (set zbit (and (const 1) (srl newval (const 4)))) + (set sflagbit (and (const 1) (srl newval (const 3)))) + (set kmbit (and (const 1) (srl newval (const 2)))) + ;;(set gie (and (const 1) (srl newval (const 1)))) + (set (raw-reg SI h-core-registers (const 1)) newval) + )) + ;; causes simulator errors + ;; ((eq index (const 2)) ;PC reg + ;; (set pc val)) + + (else (set (raw-reg USI h-core-registers index) val)) + )) +) + ; (define-pmacro (hcr-config) (reg h-core-registers 0)) etc. +(.splice begin (.unsplice (.map + (.pmacro (xname xnum) + (define-pmacro ((.sym hcr- xname)) (reg h-core-registers xnum))) + + ( + config + status + pc + debug + iab + lc + ls + le + iret + imask + ilat + ilatst + ilatcl + ipend + ctimer0 + ctimer1 + hstatus + + + + ) + + (0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 + ) + ))) + + + +;; DMA registers in MMR space +(define-hardware + (name h-coredma-registers) + (comment "DMA registers in MMR space") + (type register USI (16)) + (attrs) + (indices extern-keyword crdma-names) + ) + +;; MEM registers in MMR space +(define-hardware + (name h-coremem-registers) + (comment "MEM registers in MMR space") + (type register USI (4)) + (attrs) + (indices extern-keyword crmem-names) + ) + +;; MEM registers in MMR space +(define-hardware + (name h-coremesh-registers) + (comment "MESH registers in MMR space") + (type register USI (4)) + (attrs) + (indices extern-keyword crmesh-names) + ) + + + + ; Operands + + ; Branch displacements +(define-operand + (name simm24) + (comment "branch address pc-relative") + (attrs RELAX) + (type h-iaddr) + (index f-simm24) + (handlers (parse "branch_addr"))) + +(define-operand + (name simm8) + (comment "branch address pc-relative") + (attrs RELAX) + (type h-iaddr) + (index f-simm8) + (handlers (parse "branch_addr"))) + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + ; Register operands +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + +(define-pmacro (short-regs nm group hw cmt) + (define-operand + (name nm) + (comment cmt) + (attrs) + (type hw) + (index (.sym "f-r" group)) + (handlers (parse "shortregs") (print "keyword")) + ) + ) + +(define-pmacro (short-regs-core nm group hw cmt) + (define-operand + (name nm) + (comment cmt) + (attrs) + (type hw) + (index (.sym "f-s" group)) + (handlers (parse "shortregs") (print "keyword")) + ) + ) + + + ; short regs (0-7) +(short-regs rd d h-registers "destination register") +(short-regs rn n h-registers "source register") +(short-regs rm m h-registers "source register") + +(short-regs frd d h-fpregisters "fp destination register") +(short-regs frn n h-fpregisters "fp source register") +(short-regs frm m h-fpregisters "fp source register") + + ; long regs (0-63) +(dnop rd6 "destination register" () h-registers f-rd6) +(dnop rn6 "source register" () h-registers f-rn6) +(dnop rm6 "source register" () h-registers f-rm6) + +(dnop frd6 "fp destination register" () h-fpregisters f-rd6) +(dnop frn6 "fp source register" () h-fpregisters f-rn6) +(dnop frm6 "fp source register" () h-fpregisters f-rm6) + + ; special regs (0-7) +(short-regs-core sd d h-core-registers "special destination") +(short-regs-core sn n h-core-registers "special source") + + ; special regs (long form) +(dnop sd6 "special destination register" () h-core-registers f-sd6) +(dnop sn6 "special source register" () h-core-registers f-sn6) + +(dnop sddma "dma register" () h-coredma-registers f-sd6) +(dnop sndma "dma register" () h-coredma-registers f-sn6) +(dnop sdmem "mem register" () h-coremem-registers f-sd6) +(dnop snmem "mem register" () h-coremem-registers f-sn6) +(dnop sdmesh "mesh register" () h-coremesh-registers f-sd6) +(dnop snmesh "mesh register" () h-coremesh-registers f-sn6) + + ; Immediate literals - but don't allow register names! +(define-pmacro (dimmop nm cmt hwtype idx) + (define-operand (name nm) (comment cmt) (type hwtype) (index idx) + (attrs RELAX) + (handlers (parse "simm_not_reg") + (print "simm_not_reg"))) + ) + +(dimmop simm3 "signed 3-bit literal" h-sint f-sdisp3) +(dimmop simm11 "signed 11-bit literal" h-sint f-sdisp11) +(dnop disp3 "short data displacement" () h-uint f-disp3) +(dnop trapnum6 "parameter for swi or trap" () h-uint f-trap-num) + +(define-pmacro (duimmop nm cmt hwtype idx) + (define-operand (name nm) (comment cmt) (type hwtype) (index idx) + (attrs) + (handlers (parse "uimm_not_reg") + (print "uimm_not_reg"))) + ) + +(duimmop swi_num "unsigned 6-bit swi#" h-uint f-trap-num) +(duimmop disp11 "sign-magnitude data displacement" h-uint f-disp11) + +(dnop shift "immediate shift amount" () h-uint f-shift) + +(define-operand (name imm16) (comment "16-bit unsigned literal") (attrs RELAX) + (type h-addr) (index f-imm16) (handlers (parse "imm16"))) +(define-operand (name imm8) (comment "8-bit unsigned literal") (attrs RELAX) + (type h-addr) (index f-imm8) (handlers (parse "imm8"))) + +(define-operand + (name direction) + (comment "+/- indexing") + (attrs) + (type h-uint) + (index f-addsubx) + (handlers (parse "postindex") + (print "postindex"))) + +(define-operand + (name dpmi) + (comment "+/- magnitude immediate displacement") + (attrs) + (type h-uint) + (index f-subd) + (handlers (parse "postindex") + (print "postindex"))) + + + +;; call exception macro - no check for imask +(define-pmacro (call-exception vaddr bit-in-ilat) + (if (eq gidisablebit 0) + (if (eq (and (hcr-imask) bit-in-ilat) 0) + (sequence () + (set kmbit 1) + (set gidisablebit 1) + (set (hcr-iret) (add pc (const 2))) + (set (hcr-ipend) (or (hcr-ipend) (const bit-in-ilat))) + (set pc (const vaddr)) + + ) + ;; schedule interrupt + (set (hcr-ilat) (or (hcr-ilat) (const bit-in-ilat))) + ) + ) + ) + + +;; (lc 5);loop counter Not impemented +;; (ls 6);loop start address Not impemented +;; (le 7);loop end address Not impemented + +;;have callback to adjust pc in case od events ( HW loops ... ) +(define-pmacro (dni_wrapper isnid stdrdesc attr_ strassembl iopcode proceed null_b) + (begin + (dni isnid stdrdesc attr_ strassembl iopcode + (sequence () proceed + (sequence ((USI tmpPC)) + ;;(set tmpPC (c-call USI "epiphany_post_isn_callback" pc)) + + (if (eq pc (hcr-le)) + (set (hcr-lc) (sub (hcr-lc) #x1))) + (if (and + (eq pc (hcr-le)) + (not (eq (hcr-lc) #x0))) + (set pc (hcr-ls))) + ) + ) + null_b) + ) + ) + + + + + +;; Some handy macros +;; + +;; define instructions +;; Short (16 bit forms) must appear first so that instruction +;; selection can reject them and match long forms when registers +;; or immediates exceed the values in the 16 bit instructions + + +;; B<COND> SIMM8 +;; B<COND> SIMM24 + +(define-pmacro (br-insn name cond g-op) + (begin + ; the 16-bit versions of branch + (dni (.sym "b" name "16") + (.str "Conditional Branch - 16 bit" name) + (COND-CTI SHORT-INSN) + (.str "b" name ".s $simm8") + (+ OP4_BRANCH16 (.sym "OPC_" cond) simm8) + (if (g-op) + (set pc simm8) + ) + () + ) + + (dnmi (.sym "b" name "16r") "relaxable conditional branch" + (COND-CTI RELAXABLE) + (.str "b" name " $simm8") + (emit (.sym "b" name "16") simm8) + ) + + (dni (.sym "b" name) + (.str "Conditional Branch " name) + (COND-CTI) + (.str "b" name ".l $simm24") + (+ OP4_BRANCH (.sym "OPC_" cond) simm24) + (if (g-op) + (set pc simm24) + ) + () + ) + + (dnmi (.sym "b" name "32r") "relaxable conditional branch" + (COND-CTI RELAXED) + (.str "b" name " $simm24") + (emit (.sym "b" name) simm24) + ) + ) + ) + + + ; basic conditional branches for integer arithmetic +(br-insn "eq" EQ (.pmacro () (eq zbit #x1))) +(br-insn "ne" NE (.pmacro () (eq zbit #x0))) +(br-insn "gtu" GTU (.pmacro () (and BI cbit (not BI zbit)))) +(br-insn "gteu" GTEU (.pmacro () (eq cbit #x1))) +(br-insn "lteu" LTEU (.pmacro () (or BI (not BI cbit) zbit))) +(br-insn "ltu" LTU (.pmacro () (eq cbit #x0))) +(br-insn "gt" GT (.pmacro () (and BI (not BI zbit) (eq vbit nbit)))) +(br-insn "gte" GTE (.pmacro () (eq vbit nbit))) +(br-insn "lt" LT (.pmacro () (xor BI vbit nbit))) +(br-insn "lte" LTE (.pmacro () (or BI zbit (xor vbit nbit)))) + + + ; floating point condition codes (floating point instructions) +(br-insn "beq" BEQ (.pmacro () (or BI bzbit bzbit))) +(br-insn "bne" BNE (.pmacro () (not BI bzbit))) +(br-insn "blt" BLT (.pmacro () (and BI bnbit (not bzbit)))) +(br-insn "blte" BLTE (.pmacro () (or BI bnbit bzbit))) + + ; unconditional branches +(dni b16 "short unconditional branch" (UNCOND-CTI SHORT-INSN) + "b.s $simm8" + (+ OP4_BRANCH16 OPC_B simm8) + (set pc simm8) + () + ) + +(dnmi b16r "relaxable b16" + (UNCOND-CTI RELAXABLE) + "b $simm8" + (emit b16 simm8) + ) + +(dni b "long unconditional branch" (UNCOND-CTI) + "b.l $simm24" + (+ OP4_BRANCH OPC_B simm24) + (set pc simm24) + () + ) + +(dnmi b32r "relaxable b" + (UNCOND-CTI RELAXED) + "b $simm24" + (emit b simm24)) + +;; BL R,ADDR + +(dni bl16 "branch and link" + (UNCOND-CTI SHORT-INSN) + ("bl.s $simm8") + (+ OP4_BRANCH16 OPC_BL simm8) + (sequence () + (set (reg h-registers 14) (add pc (const 2))) + (set pc simm8)) + () + ) + +(dnmi bl16r "bl16 relaxable" + (UNCOND-CTI RELAXABLE) + "bl $simm8" + (emit bl16 simm8)) + +(dni bl "branch and link" + (UNCOND-CTI) + ("bl.l $simm24") + (+ OP4_BRANCH OPC_BL simm24) + (sequence () + (set (reg h-registers 14) (add pc (const 4))) + (set pc simm24)) + () + ) + +(dnmi blr "bl relaxable" + (UNCOND-CTI RELAXED) + "bl $simm24" + (emit bl simm24)) + +;; JUMP <RN> +(dni jr16 "unconditional jump 16" + (UNCOND-CTI SHORT-INSN) + ("jr $rn") + (+ OP4_FLOW16 (f-opc-8-5 #x14) (f-dc-15-3 #x0) (f-dc-9-1 #x0) rn) + (set pc rn) + () + ) + +;; RTS / JR +;; ??? Putting a constant into a multi-ifield does not work - +;; the constant gets inserted in full into each part. + ;(dnmi rts "return from subroutine" + ; (UNCOND-CTI) + ; ("rts") + ; (emit jr (rn6 14)) ; jr lr / jr r14 + ;) +;; RTS / JR +(dni rts "return from subroutine" + (ALIAS UNCOND-CTI) + ("rts") + (+ OP4_MISC (f-opc-8-5 #x14) (f-opc-19-4 #x2) (f-rn 6) (f-rn-x 1) + (f-dc-9-1 #x0) + (f-dc-15-3 #x0) + (f-dc-25-6 #x0) + (f-dc-31-3 #x0) + ) + (set pc (reg h-registers 14)) + () + ) + +(dni jr "unconditional jump" + (UNCOND-CTI) + ("jr $rn6") + (+ OP4_MISC (f-opc-8-5 #x14) (f-opc-19-4 #x2) rn6 + (f-dc-9-1 #x0) + (f-dc-15-3 #x0) + (f-dc-25-6 #x0) + (f-dc-31-3 #x0) + ) + (set pc rn6) + () + ) + + +;; JALR <RN> +(dni jalr16 "jump and link register" + (UNCOND-CTI SHORT-INSN) + ("jalr $rn") + (+ OP4_FLOW16 (f-opc-8-5 #x15) (f-dc-15-3 #x0) (f-dc-9-1 #x0) rn) + (sequence () + (set (reg h-registers 14) (add pc (const 2))) + (set pc rn) + ) + () + ) + +(dni jalr "jump and link register" + (UNCOND-CTI) + ("jalr $rn6") + (+ OP4_MISC + (f-opc-8-5 #x15) + (f-opc-19-4 #x2) + rn6 + (f-dc-9-1 #x0) + (f-dc-15-3 #x0) + (f-dc-25-6 #x0) + (f-dc-31-3 #x0) + + ) + (sequence () + (set (reg h-registers 14) (add pc (const 4))) + (set pc rn6)) + () + ) + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + ; Load/Store Memory Instructions +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + + +(define-pmacro (callMisaligmentExceptionIfNeeded sel addr isAligmentAccess) + (sequence ((BI scale)) + (set isAligmentAccess + (case BI sel + ((OPW_BYTE) (eq (and addr #x0) #x0)) + ((OPW_SHORT) (eq (and addr #x1) #x0)) + ((OPW_WORD) (eq (and addr #x3) #x0)) + (else (eq (and addr #x7) #x0)))) + (if (not BI isAligmentAccess) + (call-exception #x4 #x2)) + ) +) + + + +;; helper to convert size selector OPW_<mode> into a literal scale factor +(define-pmacro (ConvertSelectorToShift sel scale) + (set scale + (case SI sel + ((OPW_BYTE) (const 0)) + ((OPW_SHORT) (const 1)) + ((OPW_WORD) (const 2)) + (else (const 3)))) +) + +;; common load macros from effective address, handling 8/16/32/64 bits +(define-pmacro (load-double-from-ea regnum eff-addr mode sel) + (sequence ((SI loadaddr) (BI isAligmentAccess)) + (set loadaddr eff-addr) + (callMisaligmentExceptionIfNeeded sel loadaddr isAligmentAccess) + + (if (not (not BI isAligmentAccess)) + (sequence () + (set memaddr loadaddr) + (set regnum (mem SI loadaddr)) + (set loadaddr (add loadaddr (const 4))) + (set memaddr loadaddr) + (set (reg h-registers + (add (index-of regnum) + (const 1))) + (mem SI loadaddr)) + + ) + ) + ) + ) + +(define-pmacro (load-from-ea regnum eff-addr mode sel) + (sequence ((BI isAligmentAccess)) + + (callMisaligmentExceptionIfNeeded sel eff-addr isAligmentAccess) + (if (not (not BI isAligmentAccess)) + (sequence () + (set memaddr eff-addr) + (set regnum (zext SI (mem mode eff-addr))) + ) + ) + ) + ) ;; 8/16/32 bit cases + + +;; common store to effective address, handling 8/16/32/64 bit data +(define-pmacro (store-double-to-ea eff-addr regnum mode sel) + (sequence ((SI storeaddr) (BI isAligmentAccess)) + (set storeaddr eff-addr) + (callMisaligmentExceptionIfNeeded sel storeaddr isAligmentAccess) + (if (not (not BI isAligmentAccess)) + (sequence () + (set memaddr storeaddr) + (set (mem SI storeaddr) regnum) + (set storeaddr (add storeaddr (const 4))) + (set memaddr storeaddr) + (set (mem SI storeaddr) + (reg h-registers (add (index-of regnum) (const 1)))) + ) + ) + ) + ) + +(define-pmacro (store-to-ea eff-addr regnum mode sel) + (sequence ((BI isAligmentAccess)) + (callMisaligmentExceptionIfNeeded sel eff-addr isAligmentAccess) + (if (not (not BI isAligmentAccess)) + (sequence () + (set memaddr eff-addr) + (set (mem mode eff-addr) regnum) + ) + ) + ) + ) ;8/16/32 bit cases + + +(define-pmacro (load-insn name mode sel sem-op) + (begin + (dni_wrapper (.sym name "x16.s") + (.str "load " mode " indexed") + (SHORT-INSN) + (.str name " $rd,[$rn,$rm]") + (+ OP4_LDSTR16X sel OP_LOAD rd rn rm) + (sequence () + (sem-op rd (add rn rm) mode sel)) + () + ) + + + (dni_wrapper (.sym name "p16.s") + (.str "load " mode " postmodify") + (SHORT-INSN) + (.str name " $rd,[$rn],$rm") + (+ OP4_LDSTR16P sel OP_LOAD rd rn rm) + (sequence ((SI tmprm)) + (set tmprm rm) + (sem-op rd rn mode sel) + (set rn (add rn tmprm))) + () + ) + + + (dni_wrapper (.sym name "x.l") + (.str "load " mode " indexed") + () + (.str name " $rd6,[$rn6,$direction$rm6]") + (+ OP4_LDSTRX sel OP_LOAD (f-opc-19-4 #x0) (f-dc-22-1 #x0) (f-dc-21-1 #x0) rd6 rn6 direction rm6) + (sequence () + (if (ifield f-addsubx) + (sem-op rd6 (sub rn6 rm6) mode sel) + (sem-op rd6 (add rn6 rm6) mode sel))) + () + ) + + (dnmi (.sym name "x") + (.str "load " mode " indexed") + () + (.str name ".l $rd6,[$rn6,$direction$rm6]") + (emit (.sym name "x.l") rd6 rn6 direction rm6) + ) + + + + (dni_wrapper (.sym name "p.l") + (.str "load " mode " postmodify") + () + (.str name " $rd6,[$rn6],$direction$rm6") + (+ OP4_LDSTRP sel OP_LOAD (f-opc-19-4 #x0) (f-dc-22-2 #x0) rd6 rn6 direction rm6) + (sequence ((SI tmprm)) + (set tmprm rm6) + (sem-op rd6 rn6 mode sel) + (if (ifield f-addsubx) + (set rn6 (sub rn6 tmprm)) + (set rn6 (add rn6 tmprm))) + ) + () + ) + + + (dnmi (.sym name "p") + (.str "load " mode " postmodify") + () + (.str name ".l $rd6,[$rn6],$direction$rm6") + (emit (.sym name "p.l") rd6 rn6 direction rm6) + ) + + + ;;immediate modes last so reg forms found first. + (dni_wrapper (.sym name "d16.s") + (.str "load " mode " displacement") + (SHORT-INSN IMM3) + (.str name " $rd,[$rn,$disp3]") + (+ OP4_LDSTR16D sel OP_LOAD rd rn disp3) ;; convert size to 'B' + (sequence ((SI effa) + (SI scale)) + (ConvertSelectorToShift sel scale) + (set effa (add rn (sll disp3 scale))) + (sem-op rd effa mode sel) + ) + () + ) + + + (dni_wrapper (.sym name "d.l") + (.str "load " mode " displacement") + () + (.str name " $rd6,[$rn6,$dpmi$disp11]") + (+ OP4_LDSTRD sel OP_LOAD PMOD_DISP rd6 rn6 dpmi disp11) + (sequence ((SI effa) + (SI scale)) + (ConvertSelectorToShift sel scale) + (if dpmi + (set effa (sub rn6 (sll disp11 scale))) + (set effa (add rn6 (sll disp11 scale))) + ) + (sem-op rd6 effa mode sel) + ) + () + ) + + (dnmi (.sym name "d") + (.str "load " mode " displacement") + () + (.str name ".l $rd6,[$rn6,$dpmi$disp11]") + (emit (.sym name "d.l") rd6 rn6 dpmi disp11) + ) + + + + (dni_wrapper (.sym name "dpm.l") + (.str "load " mode " displacement post-modify") + () + (.str name " $rd6,[$rn6],$dpmi$disp11") + (+ OP4_LDSTRD sel OP_LOAD PMOD_POST rd6 rn6 dpmi disp11) + (sequence ((SI scale)) + (ConvertSelectorToShift sel scale) + (sem-op rd6 rn6 mode sel) + (if dpmi + (set rn6 (sub rn6 (sll disp11 scale))) + (set rn6 (add rn6 (sll disp11 scale))) + ) + ) + () + ) + + (dnmi (.sym name "dpm") + (.str "load " mode " displacement post-modify") + () + (.str name ".l $rd6,[$rn6],$dpmi$disp11") + (emit (.sym name "dpm.l") rd6 rn6 dpmi disp11) + ) + + + ;; ;; macro form with a zero displacement + (dnmi (.sym name "ds0") "load with 0 disp" + (SHORT-INSN IMM3) + (.str name " $rd,[$rn]") + (emit (.sym name "d16.s") rd rn (disp3 0)) + ) + (dnmi (.sym name "dl0") "load with 0 disp" + () + (.str name " $rd6,[$rn6]") + (emit (.sym name "d.l") rd6 rn6 (dpmi 0) (disp11 0)) + ) + (dnmi (.sym name "dl0.l") "load with 0 disp" + () + (.str name ".l $rd6,[$rn6]") + (emit (.sym name "d.l") rd6 rn6 (dpmi 0) (disp11 0)) + ) + + + ) + ) + +(load-insn ldrb QI OPW_BYTE load-from-ea) +(load-insn ldrh HI OPW_SHORT load-from-ea) +(load-insn ldr SI OPW_WORD load-from-ea) +(load-insn ldrd DI OPW_DOUBLE load-double-from-ea) + + + + +;; TMP = MEM[RD+RM]; /* Copy content of memory to tmp. */ +;; if (~TMP) /* Check if memory location is zero. */ +;; MEM[RD+RM] = RD; /* If zero, write RD to memory. */ +;; RD = TMP; /* Always write tmp into RD (NOTE it's destructive). */ + + +(define-pmacro (testset-insn name mode sel) + (begin + + + (dni_wrapper (.sym name "t") + (.str "testset " mode " indexed") + () + (.str name " $rd6,[$rn6,$direction$rm6]") + (+ OP4_LDSTRX sel OP_LOAD (f-opc-19-4 #x0) (f-dc-22-1 #x0) (f-dc-21-1 #x1) + rd6 rn6 direction rm6) + (sequence ((SI tmemaddr) (SI tmpValReg)) + + ;;back up register + (set tmpValReg rd6) + + (if (ifield f-addsubx) + (set tmemaddr (sub rn6 rm6)) + (set tmemaddr (add rn6 rm6)) + ) + ;;always update rd + (load-from-ea rd6 tmemaddr mode sel) + ;;if zero + (if rd6 + (nop) + (set (mem mode tmemaddr) tmpValReg) + ) + + ) + () + ) + + + (dnmi (.sym name "t.l") + (.str "testset " mode ".l indexed") + () + (.str name ".l $rd6,[$rn6,$direction$rm6]") + (emit (.sym name "t") rd6 rn6 direction rm6) + ) + + + ) + ) + +(testset-insn testsetb QI OPW_BYTE) +(testset-insn testseth HI OPW_SHORT) +(testset-insn testset SI OPW_WORD) +;;no double mode support, since we have to send the src address, data +;;(testset-insn testsetd DI OPW_DOUBLE load-double-from-ea) + + + +;; need 16 bit forms too +(define-pmacro (store-insn name mode sel sem-op) + (begin + (dni_wrapper (.sym name "x16") + (.str "store" mode " indexed") + (SHORT-INSN) + (.str name " $rd,[$rn,$rm]") + (+ OP4_LDSTR16X sel OP_STORE rd rn rm) + (sequence () + (sem-op (add rn rm) rd mode sel) + ) + () + ) + + (dni_wrapper (.sym name "x") + (.str "store" mode " indexed") + () + (.str name " $rd6,[$rn6,$direction$rm6]") + (+ OP4_LDSTRX sel OP_STORE (f-opc-19-4 #x0) (f-dc-22-1 #x0) (f-dc-21-1 #x0) rd6 rn6 direction rm6) + (sequence () + (if (ifield f-addsubx) + (sem-op (sub rn6 rm6) rd6 mode sel) + (sem-op (add rn6 rm6) rd6 mode sel) + )) + () + ) + + (dnmi (.sym name "x.l") + (.str "store" mode " indexed") + () + (.str name ".l $rd6,[$rn6,$direction$rm6]") + (emit (.sym name "x") rd6 rn6 direction rm6) + ) + + + + + + (dni_wrapper (.sym name "p16") + (.str "store " mode " postmodify") + (SHORT-INSN) + (.str name " $rd,[$rn],$rm") + (+ OP4_LDSTR16P sel OP_STORE rd rn rm) + (sequence () + (sem-op rn rd mode sel) + (set rn (add rn rm)) + ) + () + ) + + (dni_wrapper (.sym name "p") + (.str "store " mode " postmodify") + () + (.str name " $rd6,[$rn6],$direction$rm6") + (+ OP4_LDSTRP sel OP_STORE (f-opc-19-4 #x0) (f-dc-22-2 #x0) rd6 rn6 direction rm6) + (sequence () + (sem-op rn6 rd6 mode sel) + (if (ifield f-addsubx) + (set rn6 (sub rn6 rm6)) + (set rn6 (add rn6 rm6))) + ) + () + ) + (dnmi (.sym name "p.l") + (.str "store " mode " postmodify") + () + (.str name ".l $rd6,[$rn6],$direction$rm6") + (emit (.sym name "p") rd6 rn6 direction rm6) + ) + + (dni_wrapper (.sym name "d16") + (.str "store " mode " displacement") + (SHORT-INSN IMM3) + (.str name " $rd,[$rn,$disp3]") + (+ OP4_LDSTR16D sel OP_STORE rd rn disp3) ;; convert size to 'B' + (sequence ((SI effa) + (SI scale)) + (ConvertSelectorToShift sel scale) + (set effa (add rn (sll disp3 scale))) + (sem-op effa rd mode sel) + ) + () + ) + + (dni_wrapper (.sym name "d") + (.str "store " mode " displacement") + () + (.str name " $rd6,[$rn6,$dpmi$disp11]") + (+ OP4_LDSTRD sel OP_STORE PMOD_DISP rd6 rn6 dpmi disp11) + (sequence ((SI effa) + (SI scale)) + (ConvertSelectorToShift sel scale) + (if dpmi + (set effa (sub rn6 (sll disp11 scale))) + (set effa (add rn6 (sll disp11 scale))) + ) + (sem-op effa rd6 mode sel) + ) + () + ) + + (dnmi (.sym name "d.l") + (.str "store " mode " displacement") + () + (.str name ".l $rd6,[$rn6,$dpmi$disp11]") + (emit (.sym name "d") rd6 rn6 dpmi disp11) + ) + + + (dni_wrapper (.sym name "dpm") + (.str "store " mode " displacement post-modify") + () + (.str name " $rd6,[$rn6],$dpmi$disp11") + (+ OP4_LDSTRD sel OP_STORE PMOD_POST rd6 rn6 dpmi disp11) ;; convert size to 'B' + (sequence ((SI scale)) + (ConvertSelectorToShift sel scale) + (sem-op rn6 rd6 mode sel) + (if dpmi + (set rn6 (sub rn6 (sll disp11 scale))) + (set rn6 (add rn6 (sll disp11 scale))) + ) + ) + () + ) + (dnmi (.sym name "dpm.l") + (.str "store " mode " displacement post-modify") + () + (.str name ".l $rd6,[$rn6],$dpmi$disp11") + (emit (.sym name "dpm") rd6 rn6 dpmi disp11) + ) + + ;; macro form with a zero displacement + (dnmi (.sym name "ds0") "store w 0 disp" + (SHORT-INSN IMM3) + (.str name " $rd,[$rn]") + (emit (.sym name "d16") rd rn (disp3 0)) + ) + + (dnmi (.sym name "dl0") "store w 0 disp" + () + (.str name " $rd6,[$rn6]") + (emit (.sym name "d") rd6 rn6 (dpmi 0) (disp11 0)) + ) + + (dnmi (.sym name "dl0.l") "store w 0 disp" + () + (.str name ".l $rd6,[$rn6]") + (emit (.sym name "d") rd6 rn6 (dpmi 0) (disp11 0)) + ) + + + + ) + ) + +(store-insn strb QI OPW_BYTE store-to-ea) +(store-insn strh HI OPW_SHORT store-to-ea) +(store-insn str SI OPW_WORD store-to-ea) +(store-insn strd DI OPW_DOUBLE store-double-to-ea) + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; MOV<COND> RD,RN +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + +(define-pmacro (move-insns name cond g-op) + (begin + (dni_wrapper (.sym "cmov16" cond) + (.str "move register " cond) + (SHORT-INSN) + (.str "mov" name " $rd,$rn") + (+ OP4_FLOW16 (.sym "OPC_" cond) (f-opc-8-1 #x0) (f-dc-9-1 #x0) rd rn) + (if (g-op) + (set rd rn)) + () + ) + + (dni_wrapper (.sym "cmov" cond) + (.str "move register " cond) + () + (.str "mov" name " $rd6,$rn6") + (+ OP4_MISC (.sym "OPC_" cond) (f-opc-8-1 #x0) (f-dc-9-1 #x0) (f-opc-19-4 #x2) (f-dc-25-6 #x0) rd6 rn6) + (if (g-op) + (set rd6 rn6)) + () + ) + (dnmi (.sym "cmov.l" cond) + (.str "move register " cond) + () + (.str "mov" name ".l $rd6,$rn6") + (emit (.sym "cmov" cond) rd6 rn6) + ) + + + + ) + ) + + ; basic conditional moves +(move-insns "eq" EQ (.pmacro () (eq zbit #x1))) +(move-insns "ne" NE (.pmacro () (eq zbit #x0))) +(move-insns "gtu" GTU (.pmacro () (and BI cbit (not BI zbit)))) +(move-insns "gteu" GTEU (.pmacro () (eq cbit #x1))) +(move-insns "lteu" LTEU (.pmacro () (or BI (not BI cbit) zbit))) +(move-insns "ltu" LTU (.pmacro () (eq cbit #x0))) +(move-insns "gt" GT (.pmacro () (and BI (not BI zbit) (eq vbit nbit)))) +(move-insns "gte" GTE (.pmacro () (eq vbit nbit))) +(move-insns "lt" LT (.pmacro () (xor BI vbit nbit))) +(move-insns "lte" LTE (.pmacro () (or BI zbit (xor vbit nbit)))) + + ; unconditional move +(move-insns "" B (.pmacro () #x1)) + + + ; floating point condition codes (floating point instructions) +(move-insns "beq" BEQ (.pmacro () (or BI bzbit bzbit))) +(move-insns "bne" BNE (.pmacro () (not BI bzbit))) +(move-insns "blt" BLT (.pmacro () (and BI bnbit (not bzbit)))) +(move-insns "blte" BLTE (.pmacro () (or BI bnbit bzbit))) + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; MOVTS RD,RN +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + +;; 16 bits form exists for group zero ( M1 and M0 equals to zero ) only + +(dni_wrapper movts16 + "move to special reg" + (SHORT-INSN) + "movts $sn,$rd" + (+ OP4_FLOW16 (f-opc-8-5 #x10) (f-dc-9-1 #x0) rd sn) ;; rd is source for movts + (set sn rd) + () + ) + +(define-pmacro (op-mmr-movts name sdreg code) + (begin + + (dni_wrapper (.sym "movts" name) + (.str "move to " name) + () + (.str "movts $" sdreg ",$rd6") + (+ OP4_MISC (f-dc-7-4 #x0) (f-opc-8-1 #x1) (f-dc-9-1 #x0) (f-opc-19-4 #x2) (f-dc-25-4 #x0) (f-dc-21-2 code) sdreg rd6);; rd is source for movts + (set sdreg rd6) + () + ) + + (dnmi (.sym "movts.l" name) + (.str "move to " name) + () + (.str "movts.l $" sdreg ",$rd6") + (emit (.sym "movts" name) sdreg rd6) + ) + + + + + ) + ) + +(op-mmr-movts 6 sn6 #x0) +(op-mmr-movts dma sndma #x1) +(op-mmr-movts mem snmem #x2) +(op-mmr-movts mesh snmesh #x3) + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; MOVFS +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +(dni_wrapper movfs16 + "move from special register" + (SHORT-INSN) + "movfs $rd,$sn" + (+ OP4_FLOW16 (f-opc-8-5 #x11) (f-dc-9-1 #x0) rd sn) + (set rd sn) + () + ) + + + +(define-pmacro (op-mmr-movfs name snreg code) + (begin + + (dni_wrapper (.sym "movfs" name) + (.str "move from " name) + () + (.str "movfs $rd6,$" snreg) + (+ OP4_MISC (f-dc-7-4 #x1) (f-opc-8-1 #x1) (f-dc-9-1 #x0) (f-opc-19-4 #x2) (f-dc-25-4 #x0) (f-dc-21-2 code) rd6 snreg) + (set rd6 snreg) + () + ) + + (dnmi (.sym "movfs.l" name) + (.str "move from " name) + () + (.str "movfs.l $rd6,$" snreg) + (emit (.sym "movfs" name) rd6 snreg) + ) + + + + ) + ) + +(op-mmr-movfs 6 sn6 #x0) +(op-mmr-movfs dma sndma #x1) +(op-mmr-movfs mem snmem #x2) +(op-mmr-movfs mesh snmesh #x3) + + + + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; NOP 0x1a2 +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +(dni_wrapper nop + "no-operation" + (SHORT-INSN) + "nop" + (+ OP4_FLOW16 (f-opc-8-5 #x1a) (f-dc-15-7 #x0)) + (nop) + () + ) + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; SNOP 0x3a2 +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +(dni_wrapper snop + "no-operation" + (SHORT-INSN) + "snop" + (+ OP4_FLOW16 (f-opc-8-5 #x3a) (f-dc-15-7 #x0)) + (nop) + () + ) + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; UNIMPL +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +(dni_wrapper unimpl + "not-implemented" + () + "unimpl" + (+ (f-opc-31-32 #x000F000F)) + (nop) + () + ) + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; IDLE +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + +(dni idle "idle until interrupt" () "idle" + (+ OP4_FLOW16 (f-opc-8-5 #x1b) (f-dc-15-7 #x0)) + ;; (set pc pc) ;; should branch to self until interrupt, but not modeling interrupts + (sequence () + (set caibit 0) + (c-code "sim_engine_halt (CPU_STATE (current_cpu), current_cpu, NULL, \ + pc, sim_exited, 0);")) + () + ) + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; BKPT +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + +(dni bkpt + "breakpoint" + (SHORT-INSN) + "bkpt" + (+ OP4_FLOW16 (f-opc-8-5 #x1c) (f-dc-15-7 #x0)) + (sequence () + (c-call "epiphany_break" pc) + (set pc pc) + ) + () + ) + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; MBKPT +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + +(dni mbkpt + "multicorebreakpoint" + (SHORT-INSN) + "mbkpt" + (+ OP4_FLOW16 (f-opc-8-5 #x1c) (f-dc-15-7 #x1)) + ;;;(c-call "epiphany_break" pc) + (nop) ;; ignore the multi core break point in the simulator + () + ) + +;;;;;;;;;;;;;;;; +;; RTI +;;;;;;;;;;;;;;;; + +(dni rti "return from interrupt" (SHORT-INSN UNCOND-CTI) + "rti" + (+ OP4_FLOW16 (f-opc-8-5 #x1d) (f-dc-15-7 #x0)) + (sequence () + ;; (set (hcr-ipend) + ;; (xor (hcr-ipend) + ;; (sll (const 1) + ;; (sub (c-raw-call SI "ffs" (and (hcr-ipend) (not (hcr-imask)))) + ;; (const 1))))) + + (set (hcr-ipend) + (c-call SI "epiphany_rti" (hcr-ipend) (hcr-imask))) + (set gidisablebit 0) + (set kmbit 0) + ;(set caibit 1) + (set pc (hcr-iret))) + () + ) +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; WAND is a wired flag that runs around the chip +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +(dni_wrapper wand "wand" + (SHORT-INSN) + "wand" + (+ OP4_FLOW16 (f-opc-8-5 #x18) (f-dc-15-7 #x0)) + (set sflagbit 1) + () + ) + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; Sync likes wand, but wired OR +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +(dni_wrapper sync "sync" + (SHORT-INSN) + "sync" + (+ OP4_FLOW16 (f-opc-8-5 #x1f) (f-dc-15-7 #x0)) + (nop);;TODO + () + ) + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; GIE +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +(dni_wrapper gien "global interrupt enable" + (SHORT-INSN) + "gie" + (+ OP4_FLOW16 (f-gien-gidis-9-1 #x0) (f-opc-8-5 #x19) (f-dc-15-6 #x0)) + (set gidisablebit 0) + () + ) + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; GIDIS +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +(dni_wrapper gidis "global interrupt disable" + (SHORT-INSN) + "gid" + (+ OP4_FLOW16 (f-gien-gidis-9-1 #x1) (f-opc-8-5 #x19) (f-dc-15-6 #x0)) + (set gidisablebit 1) + () + ) + + + +;;;;;;;;;;;;;;;; +;; SWI +;;;;;;;;;;;;;;;; + +;; Model only immediate 'fire' exception, if gien cleared or masked don't fire and don't check later - no ilat like behavior +(dni swi_num "software interrupt" (SHORT-INSN UNCOND-CTI) + "swi $swi_num" + (+ OP4_FLOW16 (f-opc-8-5 #x1e) (f-trap-swi-9-1 #x0) swi_num) + (sequence () (call-exception #x24 #x80)) + ;; (if (eq gie 1) + ;; (sequence () + ;; (set kmbit 1) + ;; (set gie 0) + ;; (set (hcr-iret) (add pc (const 2))) + ;; (set (hcr-ipend) (or (hcr-ipend) (const #x80))) + ;; (set pc (const #x1c)) + + ;; ) + ;; ;; schedule interrupt + ;; (set (hcr-ilat) (or (hcr-ilat) (const #x80))) + ;; ) + () + ) +(dni swi "software interrupt" (ALIAS SHORT-INSN UNCOND-CTI) + "swi" + (+ OP4_FLOW16 (f-opc-8-5 #x1e) (f-trap-swi-9-1 #x0) (f-dc-15-6 #x0)) + (sequence () (call-exception #x24 #x80)) + () + ) + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; TRAP #disp3 - simulator only and chip as well - make the same grouop as swi +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + +;; Only defining 16-bit form of this instruction. It exists to support the +;; simulator, by giving us a simple input/output mechanism beyond returning values +;; in registers or memory. +;; TRAP #N - special sw trap for simulator support; allows simple i/o using fixed arguments +;; TRAP #0 - write (r0=i/o channel, r1=addr, r2=len) returns status in r0 +;; TRAP #1 - read (r0=i/o channel, r1=addr, r2=len) returns length or -<code> on error +;; TRAP #2 - open (r0=string path, r1=mode) returns channel# or -<code> on error +;; TRAP #3 - exit (r0=status code) never returns. +;; TRAP #4 - print "pass\n" and exit +;; TRAP #5 - print "fail\n" and exit +;; TRAP #6 - close (r0=i/o channel) + +(dni trap16 "trap to simulator" + (SHORT-INSN UNCOND-CTI) + "trap $trapnum6" + (+ OP4_FLOW16 (f-opc-8-5 #x1e) (f-trap-swi-9-1 #x1) trapnum6) ;; (+ OP4_IMM16 OPI_TRAP (f-rd 0) (f-rn 0) disp3) + (set (reg SI h-registers 0) (c-call SI "epiphany_trap" pc trapnum6)) + () + ) + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; Integer arithmetic instructions 3 address forms +;; both 16 and 32 bit forms +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + +(define-pmacro (op-rrr name sem-op cond-op) + (begin + (dni_wrapper (.sym name "16") + (.str name) + (SHORT-INSN) + (.str name " $rd,$rn,$rm") + (+ OP4_ALU16 (.sym "OPB_" (.upcase (.str name))) rd rn rm) + (sequence () + (cond-op rn rm) + (set rd (sem-op SI rn rm)) + (set zbit (zflag rd)) + (set nbit (nflag rd)) + ) + () + ) + + (dni_wrapper (.sym name) + (.str name) + () + (.str name " $rd6,$rn6,$rm6") + (+ OP4_MISC (.sym "OPB_" (.upcase (.str name))) (f-opc-19-4 #xa) (f-dc-22-3 #x0) rd6 rn6 rm6) + (sequence () + (cond-op rn6 rm6) + (set rd6 (sem-op SI rn6 rm6)) + (set zbit (zflag rd6)) + (set nbit (nflag rd6)) + ) + () + ) + + (dnmi (.sym name ".l") + (.str name) + () + (.str name ".l $rd6,$rn6,$rm6") + (emit (.sym name) rd6 rn6 rm6) + ) + + + + ) + ) + +;; submacros to set condition codes +;; NZ are always set to reflect the sign and value of the result +;; CV are a function of the operator +(define-pmacro (add-vc a b) (sequence () + (set cbit (add-cflag SI a b 0)) + (set vbit (add-oflag SI a b 0)) + (set vsbit (or BI vsbit vbit)) + )) + +(define-pmacro (sub-vc a b) (sequence () + (set cbit (not (sub-cflag SI a b 0))) + (set vbit (sub-oflag SI a b 0)) + (set vsbit (or vsbit vbit)) + )) + +(define-pmacro (logic-vc a b) (sequence () + (set cbit 0) + (set vbit 0) + )) + +(op-rrr add add add-vc) +(op-rrr sub sub sub-vc) +(op-rrr and and logic-vc) +(op-rrr orr or logic-vc) +(op-rrr eor xor logic-vc) + +;; Integer arithmetic immediate forms + +(define-pmacro (op-rri name code cond-op) + (begin + (dni_wrapper (.sym name "i16") + (.str name) + (SHORT-INSN IMM3) + (.str name ".s $rd,$rn,$simm3") + (+ OP4_IMM16 code rd rn simm3) + (sequence () + (cond-op rn simm3) + (set rd (name SI rn simm3)) + (set zbit (zflag rd)) + (set nbit (nflag rd)) + ) + () + ) + + + (dni_wrapper (.sym name "i") + (.str name) + () + (.str name ".l $rd6,$rn6,$simm11") + (+ OP4_IMM32 code OPI_25_2_MBZ rd6 rn6 simm11) + (sequence () + (cond-op rn6 simm11) + (set rd6 (name SI rn6 simm11)) + (set zbit (zflag rd6)) + (set nbit (nflag rd6)) + ) + () + ) + + ;; (dnmi (.sym name "ri") "relaxed arithmetic immediate" (RELAXED) + ;; (.str name " $rd6,$rn6,$simm11") + ;; (emit (.sym name "i") rd6 rn6 simm11)) + ) + ) + +(op-rri add OPI_ADD add-vc) +(op-rri sub OPI_SUB sub-vc) + +(dnmi addir "relaxable short immediate add" (RELAXABLE IMM3) + "add $rd,$rn,$simm3" + (emit addi16 rd rn simm3)) + +(dnmi addi32r "relaxed long immediate add" (RELAXED) + "add $rd6,$rn6,$simm11" + (emit addi rd6 rn6 simm11)) + +;; Again, but not relaxable so that full sized registers are handled +(dnmi addi32m "relaxed long immediate add" () + "add $rd6,$rn6,$simm11" + (emit addi rd6 rn6 simm11)) + + +(dnmi subir "relaxable short immediate sub" (RELAXABLE IMM3) + "sub $rd,$rn,$simm3" + (emit subi16 rd rn simm3)) + +(dnmi subi32r "relaxed long immediate sub" (RELAXED) + "sub $rd6,$rn6,$simm11" + (emit subi rd6 rn6 simm11)) + +(dnmi subi32m "relaxed long immediate sub" () + "sub $rd6,$rn6,$simm11" + (emit subi rd6 rn6 simm11)) + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; Shift instructions 3 address forms +;; both 16 and 32 bit forms +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + +(define-pmacro (shift-rrr name sem-op) + (begin + (dni_wrapper (.sym name "16") + (.str name) + (SHORT-INSN) + (.str name " $rd,$rn,$rm") + (+ OP4_ALU16 (.sym "OPB_" (.upcase (.str name))) rd rn rm) + (sequence () + (logic-vc rn rm) + (set rd (sem-op SI rn (and rm (const 31)))) + (set zbit (zflag rd)) + (set nbit (nflag rd)) + ) + () + ) + + (dni_wrapper (.sym name) + (.str name) + () + (.str name " $rd6,$rn6,$rm6") + (+ OP4_MISC (.sym "OPB_" (.upcase (.str name))) (f-opc-19-4 #xa) (f-dc-22-3 #x0) rd6 rn6 rm6) + (sequence () + (logic-vc rn6 rm6) + (set rd6 (sem-op SI rn6 (and rm6 (const 31)))) + (set zbit (zflag rd6)) + (set nbit (nflag rd6)) + ) + () + ) + + (dnmi (.sym name ".l") + (.str name) + () + (.str name ".l $rd6,$rn6,$rm6") + (emit (.sym name) rd6 rn6 rm6) + ) + ) + ) + +(shift-rrr asr sra) +(shift-rrr lsr srl) +(shift-rrr lsl sll) + +(define-pmacro (op-shift-rri name shortcode f5 longcode sem-op) + (begin + (dni_wrapper (.sym name "i16") + (.str name) + (SHORT-INSN) + (.str name " $rd,$rn,$shift") + (+ shortcode (f-opc-4-1 f5) rd rn shift) + (sequence () + (logic-vc rn shift) + (set rd (sem-op SI rn shift)) + (set zbit (zflag rd)) + (set nbit (nflag rd)) + ) + () + ) + (dni_wrapper (.sym name "i32") + (.str name) + () + (.str name " $rd6,$rn6,$shift") + (+ OP4_MISC (f-opc-4-1 f5) (f-opc-19-4 longcode) (f-dc-25-6 0) rd6 rn6 shift) + (sequence () + (logic-vc rn6 shift) + (set rd6 (sem-op SI rn6 shift)) + (set zbit (zflag rd6)) + (set nbit (nflag rd6)) + ) + () + ) + + (dnmi (.sym name "i32.l") + (.str name) + () + (.str name ".l $rd6,$rn6,$shift") + (emit (.sym name "i32") rd6 rn6 shift) + ) + + + ) + ) + +(op-shift-rri lsr OP4_LSHIFT16 0 #x6 srl) +(op-shift-rri lsl OP4_LSHIFT16 1 #x6 sll) +(op-shift-rri asr OP4_ASHIFT16 0 #xe sra) + +;; BITR - bitreversal (FFT) +;; +;; From Dr Dobbs et al. +;; +;; unsigned int v; +;; v = ((v >> 1) & 0x55555555) | ((v & 0x55555555) << 1); ;; swap odd-even bits +;; v = ((v >> 2) & 0x33333333) | ((v & 0x33333333) << 2); ;; swap pairs +;; v = ((v >> 4) & 0x0f0f0f0f) | ((v & 0x0f0f0f0f) << 4); ;; swap nibbles +;; v = ((v >> 8) & 0x00ff00ff) | ((v & 0x00ff00ff) << 8); ;; swap bytes +;; v = (v >> 16) | (v << 16); ;; swap halves +(define-pmacro (bit-reversal dest src) + (sequence ((SI v)) + (set v src) + (set v (or (and (srl v 1) #x55555555) (sll (and v #x55555555) 1))) + (set v (or (and (srl v 2) #x33333333) (sll (and v #x33333333) 2))) + (set v (or (and (srl v 4) #x0f0f0f0f) (sll (and v #x0f0f0f0f) 4))) + (set v (or (and (srl v 8) #x00ff00ff) (sll (and v #x00ff00ff) 8))) + (set v (or (srl v 16) (sll v 16))) + (set dest v) + )) + +(dni_wrapper bitr16 "bit reverse short" + (SHORT-INSN) + ("bitr $rd,$rn") + (+ OP4_ASHIFT16 (f-opc-4-1 1) rd rn (f-shift 0)) + (sequence () + (bit-reversal rd rn) + (set zbit (zflag rd)) + (set nbit (nflag rd)) + (set cbit 0) + (set vbit 0) + ) + () + ) + +(dni_wrapper bitr "bit reverse" + () + ("bitr $rd6,$rn6") + (+ OP4_MISC (f-opc-4-1 1) (f-opc-19-4 #xe) (f-dc-25-6 0) rd6 rn6 (f-shift 0)) + (sequence () + (bit-reversal rd6 rn6) + (set zbit (zflag rd6)) + (set nbit (nflag rd6)) + (set cbit 0) + (set vbit 0) + ) + () + ) +(dnmi bitrl "bit reverse l" + () + ("bitr.l $rd6,$rn6") + (emit bitr rd6 rn6) + ) + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; Integer arithmetic instructions +;; Extended operation +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + +(define-pmacro (op-iextrrr name cond-op) + (begin + + (dni_wrapper (.sym name) + (.str name) + () + (.str name " $rd6,$rn6,$rm6") + (+ OP4_MISC (.sym "OPBE_" (.upcase (.str name))) (f-opc-19-4 #xa) (f-dc-22-2 #x0) (f-dc-20-1 #x1) + rd6 rn6 rm6) + (sequence () + ;; TODO cond operation (cond-op rn6 rm6) + ;;(set rd6 (sem-op SI rn6 rm6)) + (set zbit (zflag rd6)) + (set nbit (nflag rd6)) + ) + () + ) + + (dnmi (.sym name ".l") + (.str name) + () + (.str name ".l $rd6,$rn6,$rm6") + (emit (.sym name) rd6 rn6 rm6) + ) + ) + ) + +(op-iextrrr fext sub-vc) +(op-iextrrr fdep sub-vc) +(op-iextrrr lfsr sub-vc) + + + +;; Immediate moves. The 8 bit form is relaxed if it doesn't fit or is external +;; Move RD,#IMM +(dni_wrapper mov8 + "mov imm8" + (SHORT-INSN) + "mov.b $rd,$imm8" + (+ OP4_IMM16 (f-opc-4-1 #x0) rd imm8) + (set rd (zext SI imm8)) + () + ) + +(dnmi mov8r "mov imm8 relaxable" + (RELAXABLE) + "mov $rd,$imm8" + (emit mov8 rd imm8)) + +(dni_wrapper mov16 + "mov imm16" + () + "mov.l $rd6,$imm16" + (+ OP4_IMM32 (f-opc-4-1 #x0) (f-opc-19-4 #x2) (f-dc-28-1 #x0) rd6 imm16) + (set rd6 (zext SI imm16)) + () + ) + +(dnmi mov16r "mov imm16 relaxable" + () + "mov $rd6,$imm16" + (emit mov16 rd6 imm16)) + +;; MOVE TO HIGH WORD +(dni_wrapper movt + "movt imm16" + () + "movt $rd6,$imm16" + (+ OP4_IMM32 (f-opc-4-1 #x0) (f-opc-19-4 #x2) (f-dc-28-1 #x1) rd6 imm16) + (set rd6 (or (and SI rd6 (const #xffff)) ; keep low bits of rd + (sll SI imm16 (const 16)))) ; replacing just high bits + () + ) +(dnmi movtl + "movt imm16" + () + "movt.l $rd6,$imm16" + (emit movt rd6 imm16) + ) + + + +;; FLOATING POINT OPERATIONS +;; TWO operands +(define-pmacro (op-two_operands-float name code) + (begin + (dni_wrapper + (.sym "f_" name "f16") + (.str "f_" name) + (SHORT-INSN) + (.str "f" name " $rd,$rn,$rm") + (+ OP4_DSP16 code rd rn rm) + (sequence () + (if + (eq arithmetic-modebit2 0) + (sequence ((SF fptemp) (SI sdtmp)) + (set sdtmp (c-call SI (.str "epiphany_f" name) rd rn rm)) + + ;;All bits are calculated in C + (set bzbit (c-call BI "get_epiphany_fzeroflag" sdtmp)) + (set bnbit (c-call BI "get_epiphany_fnegativeflag" sdtmp)) + (set bvbit (c-call BI "get_epiphany_foverflowflag" sdtmp)) + (set bubit (c-call BI "get_epiphany_funderflowflag" sdtmp)) + (set bibit (c-call BI "get_epiphany_finvalidflag" sdtmp)) + (set bvsbit (or bvsbit bvbit)) + (set busbit (or busbit bubit)) + (set bisbit (or bisbit bibit)) + (set rd sdtmp) + (if (or (and invExcEnbit bisbit) + (or (and ovfExcEnbit bvsbit) (and unExcEnbit busbit))) + (sequence () + (set expcause0bit (const 1)) + (set expcause1bit (const 1)) + (call-exception #x4 #x2))) + )) + (if (eq arithmetic-modebit2 1) + (sequence ((SI sdtmp)) + (set sdtmp (c-call SI (.str "epiphany_i" name) rd rn rm)) + ;; carry is not connected inb the design (set bcbit bcbit) + (set bzbit (zflag sdtmp)) + (set bnbit (nflag sdtmp)) + (set rd sdtmp))) + ) + + () + ) + (dnmi (.sym "i_" name "f16") + (.str "i_" name) + (SHORT-INSN NO-DIS) + (.str "i" name " $rd,$rn,$rm") + (emit (.sym "f_" name "f16") rd rn rm) + ) + + + (dni_wrapper + (.sym "f_" name "f32") + (.str "f_" name) + () + (.str "f" name " $rd6,$rn6,$rm6") + (+ OP4_MISC code (f-opc-19-4 #x7) (f-dc-22-3 #x0) rd6 rn6 rm6) + (sequence () + (if + (eq arithmetic-modebit2 0) + (sequence ((SF fptemp) (SI sdtmp)) + (set sdtmp (c-call SI (.str "epiphany_f" name) rd6 rn6 rm6)) + + ;;All bits are calculated in C + (set bzbit (c-call BI "get_epiphany_fzeroflag" sdtmp)) + (set bnbit (c-call BI "get_epiphany_fnegativeflag" sdtmp)) + (set bvbit (c-call BI "get_epiphany_foverflowflag" sdtmp)) + (set bubit (c-call BI "get_epiphany_funderflowflag" sdtmp)) + (set bibit (c-call BI "get_epiphany_finvalidflag" sdtmp)) + (set bvsbit (or bvsbit bvbit)) + (set busbit (or busbit bubit)) + (set bisbit (or bisbit bibit)) + + (set rd6 sdtmp) + + (if (or (and invExcEnbit bisbit) + (or (and ovfExcEnbit bvsbit) (and unExcEnbit busbit))) + (sequence () + (set expcause0bit (const 1)) + (set expcause1bit (const 1)) + (call-exception #x4 #x2))) + ) + ) + (if (eq arithmetic-modebit2 1) + (sequence ((SI sdtmp)) + (set sdtmp (c-call SI (.str "epiphany_i" name) rd6 rn6 rm6)) + ;; carry is not connected inb the design (set bcbit bcbit) + (set bzbit (zflag sdtmp)) + (set bnbit (nflag sdtmp)) + (set rd6 sdtmp) + ) + ) + ) + () + ) + + (dnmi (.sym "f_" name "f32.l") + (.str "f_" name) + () + (.str "f" name ".l $rd6,$rn6,$rm6") + (emit (.sym "f_" name "f32") rd6 rn6 rm6) + ) + (dnmi (.sym "i_" name "f32") + (.str "i_" name) + (NO-DIS) + (.str "i" name " $rd6,$rn6,$rm6") + (emit (.sym "f_" name "f32") rd6 rn6 rm6) + ) + (dnmi (.sym "i_" name "f32.l") + (.str "i_" name) + (NO-DIS) + (.str "i" name ".l $rd6,$rn6,$rm6") + (emit (.sym "f_" name "f32") rd6 rn6 rm6) + ) + + + + ) + ) + +(op-two_operands-float add OPF_ADD) +(op-two_operands-float sub OPF_SUB) +(op-two_operands-float mul OPF_MUL) +(op-two_operands-float madd OPF_MADD) +(op-two_operands-float msub OPF_MSUB) + +;; ONE operands +;; FABS +(define-pmacro (op-fabs-float name code) + (begin + (dni_wrapper (.sym "f_" name "f16") + (.str "f_" name) + (SHORT-INSN) + (.str "f" name " rd,rn") + (+ OP4_DSP16 code rd rn rn) + (sequence ((SF fptemp) (SI sdtmp)) + + ;(set sdtmp (and rn #x7fffffff)) + (set sdtmp (c-call SI (.str "epiphany_fabs") rd rn rn)) + + + (set bnbit (const SI 0)) + (set bzbit (eq SI sdtmp (const SI 0))) + + ;;TODO subnormal ?? + (set bvsbit (or bvsbit bvbit)) + (set busbit (or busbit bubit)) + (set bisbit (or bisbit bibit)) + + (set rd sdtmp) + ) + () + ) + + (dni_wrapper (.sym "f_" name "f32") + (.str "f_" name) + () + (.str "f" name " $rd6,$rn6") + (+ OP4_MISC code (f-opc-19-4 #x7) (f-dc-22-3 #x0) rd6 rn6 rn6) + (sequence ((SF fptemp) (SI sdtmp)) + + + ;(set sdtmp (and rn6 #x7fffffff)) + + (set sdtmp (c-call SI (.str "epiphany_fabs") rd6 rn6 rn6)) + + + (set bnbit (const SI 0)) + (set bzbit (eq SI sdtmp (const SI 0))) + + (set bvsbit (or bvsbit bvbit)) + (set busbit (or busbit bubit)) + (set bisbit (or bisbit bibit)) + + (set rd6 sdtmp) + + ) + () + ) + + (dnmi (.sym "f_" name "f32.l") + (.str "f_" name) + () + (.str "f" name ".l $rd6,$rn6") + (emit (.sym "f_" name "f32") rd6 rn6) + ) + + + ) + ) + +(op-fabs-float abs OPF_FABS) + + +(define-pmacro (op-fix2float-float name code) + (begin + (dni_wrapper (.sym "f_" name "f16") + (.str "f_" name) + (SHORT-INSN) + (.str "f" name " $rd,$rn") + (+ OP4_DSP16 code frd frn frn) + (sequence ((SF fptemp) (SI sdtmp)) + + (set sdtmp (c-call SI (.str "epiphany_f" name) rd rn rn)) + + (set bnbit (lt SI sdtmp (const SI 0))) + (set bzbit (eq SI sdtmp (const SI 0))) + + (set bvsbit (or bvsbit bvbit)) + (set busbit (or busbit bubit)) + (set bisbit (or bisbit bibit)) + + (set rd sdtmp) + ) + () + ) + + + (dni_wrapper (.sym "f_" name "f32") + (.str "f_" name) + () + (.str "f" name " $rd6,$rn6") + (+ OP4_MISC code (f-opc-19-4 #x7) (f-dc-22-3 #x0) rd6 rn6 rn6) + (sequence ((SF fptemp) (SI sdtmp)) + + (set sdtmp (c-call SI (.str "epiphany_f" name) rd6 rn6 rn6)) + + (set bnbit (lt SI sdtmp (const SI 0))) + (set bzbit (eq SI sdtmp (const SI 0))) + + (set bvsbit (or bvsbit bvbit)) + (set busbit (or busbit bubit)) + (set bisbit (or bisbit bibit)) + + (set rd6 sdtmp) + + ) + () + ) + + (dnmi (.sym "f_" name "f32.l") + (.str "f_" name) + () + (.str "f" name ".l $rd6,$rn6") + (emit (.sym "f_" name "f32") rd6 rn6) + ) + ) + ) + +(op-fix2float-float loat OPF_FLOAT) + +(define-pmacro (op-float2fix-float name code) + (begin + (dni_wrapper (.sym "f_" name "f16") + (.str "f_" name) + (SHORT-INSN) + (.str "f" name " $rd,$rn") + (+ OP4_DSP16 code rd rn rn) + (sequence ((SF fptemp) (SI sdtmp)) + + (set sdtmp (c-call SI (.str "epiphany_f" name) rd rn rn)) + + (set bzbit (zflag sdtmp)) + (set bnbit (nflag sdtmp)) + + (set bvbit (c-call BI "get_epiphany_foverflowflag" sdtmp)) + (set bubit (c-call BI "get_epiphany_funderflowflag" sdtmp)) + (set bibit (c-call BI "get_epiphany_finvalidflag" sdtmp)) + + (set bvsbit (or bvsbit bvbit)) + (set busbit (or busbit bubit)) + (set bisbit (or bisbit bibit)) + + (set rd6 sdtmp) + + (if (or (and invExcEnbit bisbit) + (or (and ovfExcEnbit busbit) + (and unExcEnbit bvsbit))) + (sequence () + (set expcause0bit (const 1)) + (set expcause1bit (const 1)) + (call-exception #x4 #x2))) + (set rd sdtmp) + ) + () + ) + + + + (dni_wrapper (.sym "f_" name "f32") + (.str "f_" name) + () + (.str "f" name " $rd6,$rn6") + (+ OP4_MISC code (f-opc-19-4 #x7) (f-dc-22-3 #x0) rd6 rn6 rn6) + (sequence ((SF fptemp) (SI sdtmp)) + + (set sdtmp (c-call SI (.str "epiphany_f" name) rd6 rn6 rm6)) + + (set bzbit (zflag sdtmp)) + (set bnbit (nflag sdtmp)) + + (set bvbit (c-call BI "get_epiphany_foverflowflag" sdtmp)) + (set bubit (c-call BI "get_epiphany_funderflowflag" sdtmp)) + (set bibit (c-call BI "get_epiphany_finvalidflag" sdtmp)) + + (set bvsbit (or bvsbit bvbit)) + (set busbit (or busbit bubit)) + (set bisbit (or bisbit bibit)) + + (set rd6 sdtmp) + + (if (or (and invExcEnbit bisbit) + (or (and ovfExcEnbit busbit) + (and unExcEnbit bvsbit))) + (sequence () + (set expcause0bit (const 1)) + (set expcause1bit (const 1)) + (call-exception #x4 #x2)) + ) + + ) + () + ) + + (dnmi (.sym "f_" name "f32.l") + (.str "f_" name) + () + (.str "f" name ".l $rd6,$rn6") + (emit (.sym "f_" name "f32") rd6 rn6) + ) + + + ) + ) + + + + + +(op-float2fix-float ix OPF_FIX) + +;; MAC (Multiply and Accumulate Instructions +;; (define-pmacro (op-mac-float name code) +;; (begin +;; (dni_wrapper (.sym "fm" name "f16") +;; (.str "fm" name) +;; (SHORT-INSN) +;; (.str "fm" name " $frd,$frn,$frm") +;; (+ OP4_DSP16 code frd frn frm) +;; (sequence ((SF fptemp)) +;; (set bvbit 0) +;; (set busbit 0) +;; (set fptemp (c-call SF (.str "epiphany_fm" name) frd frm frn)) +;; (set bnbit (lt SF fptemp (const SF 0))) +;; (set bzbit (eq SF fptemp (const SF 0))) +;; (set bvsbit (or bvsbit bvbit)) +;; (set frd fptemp) +;; ; (set rd (subword SI frd 0)) +;; ) +;; () +;; ) + +;; (dni_wrapper (.sym "fm" name "f32") +;; (.str "fm" name) +;; () +;; (.str "fm" name " $frd6,$frn6,$frm6") +;; (+ OP4_MISC code (f-opc-19-4 #x7) (f-dc-22-3 #x0) frd6 frn6 frm6) +;; (sequence ((SF fptemp)) +;; (set bvbit 0) +;; (set busbit 0) +;; (set fptemp (c-call SF (.str "epiphany_fm" name) frd6 frm6 frn6)) +;; (set bnbit (lt SF fptemp (const SF 0))) +;; (set bzbit (eq SF fptemp (const SF 0))) +;; (set bvsbit (or bvsbit bvbit)) +;; (set frd6 fptemp) +;; ; (set rd6 (subword SI frd6 0)) +;; ) +;; () +;; ) +;; ) +;; ) + + + + + + + + ; extended floating point operation + + +(define-pmacro (op-fextop-float name code) + (begin + + (dni_wrapper (.sym "f_" name "f32") + (.str "f_" name) + () + (.str "f" name " $frd6,$frn6") + (+ OP4_MISC code (f-opc-19-4 #x7) (f-dc-22-2 #x0) (f-dc-20-1 #x1) frd6 frn6 frn6) + (sequence ((SF fptemp)) + (set bvbit 0) + (set busbit 0) + (set fptemp (c-call SF (.str "epiphany_f" name) frn6)) + (set bnbit (lt SF fptemp (const SF 0))) + (set bzbit (eq SF fptemp (const SF 0))) + (set bvsbit (or bvsbit bvbit)) + (set frd6 fptemp) + + ) + () + ) + + + (dnmi (.sym "f_" name "f32.l") + (.str "f_" name) + () + (.str "f" name ".l $frd6,$frn6") + (emit (.sym "f_" name "f32") frd6 frn6) + ) + ) + ) + +(op-fextop-float recip OPF_FRECIP) +(op-fextop-float sqrt OPF_FSQRT) + + + + + diff --git a/cpu/epiphany.opc b/cpu/epiphany.opc new file mode 100755 index 00000000000..22e2f7635f9 --- /dev/null +++ b/cpu/epiphany.opc @@ -0,0 +1,416 @@ +/* Adapteva epiphany opcode support. -*- C -*- + + Copyright 2011 Free Software Foundation, Inc. + + Contributed by Embecosm on behalf of Adapteva, Inc. + + This file is part of the GNU Binutils and of GDB. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +/* + Each section is delimited with start and end markers. + + <arch>-opc.h additions use: "-- opc.h" + <arch>-opc.c additions use: "-- opc.c" + <arch>-asm.c additions use: "-- asm.c" + <arch>-dis.c additions use: "-- dis.c" + <arch>-ibd.h additions use: "-- ibd.h". */ + +/* -- opc.h */ + +/* enumerate relaxation types for gas. */ +typedef enum epiphany_relax_types +{ + EPIPHANY_RELAX_NONE=0, + EPIPHANY_RELAX_NEED_RELAXING, + + EPIPHANY_RELAX_BRANCH_SHORT, /* Fits into +127..-128 */ + EPIPHANY_RELAX_BRANCH_LONG, /* b/bl/b<cond> +-2*16 */ + + EPIPHANY_RELAX_ARITH_SIMM3, /* add/sub -7..3 */ + EPIPHANY_RELAX_ARITH_SIMM11, /* add/sub -2**11-1 .. 2**10-1 */ + + EPIPHANY_RELAX_MOV_IMM8, /* mov r,imm8 */ + EPIPHANY_RELAX_MOV_IMM16, /* mov r,imm16 */ + + EPIPHANY_RELAX_LDST_IMM3, /* (ldr|str)* r,[r,disp3] */ + EPIPHANY_RELAX_LDST_IMM11 /* (ldr|str)* r,[r,disp11] */ + +} EPIPHANY_RELAX_TYPES; + +/* Override disassembly hashing... */ + +/* Can only depend on instruction having 4 decode bits which gets us to the + major groups of 16/32 instructions. */ +#undef CGEN_DIS_HASH_SIZE +#if 1 + +/* hash code on the 4 LSBs */ +#define CGEN_DIS_HASH_SIZE 16 + +#define CGEN_DIS_HASH(buf, value) ((*buf) & 0xf) +#else +#define CGEN_DIS_HASH_SIZE 1 +#define CGEN_DIS_HASH(buf, value) 0 +#endif + +extern const char * parse_shortregs (CGEN_CPU_DESC cd, + const char ** strp, + CGEN_KEYWORD * keywords, + long * valuep); + +extern const char * parse_branch_addr (CGEN_CPU_DESC cd, + const char ** strp, + int opindex, + int opinfo, + enum cgen_parse_operand_result * resultp, + unsigned long * valuep); + +/* Allows reason codes to be output when assembler errors occur. */ +#define CGEN_VERBOSE_ASSEMBLER_ERRORS + + +/* -- opc.c */ + + + +/* -- asm.c */ +const char * +parse_shortregs (CGEN_CPU_DESC cd, + const char ** strp, + CGEN_KEYWORD * keywords, + long * regno) +{ + const char * errmsg; + + /* Parse register. */ + errmsg = cgen_parse_keyword (cd, strp, keywords, regno); + + if (errmsg) + return errmsg; + + if (*regno > 7) + errmsg = _("register unavailable for short instructions"); + + return errmsg; +} + +static const char * parse_simm_not_reg (CGEN_CPU_DESC, const char **, int, + long *); + +static const char * +parse_uimm_not_reg (CGEN_CPU_DESC cd, + const char ** strp, + int opindex, + unsigned long * valuep) +{ + long * svalp = (void *) valuep; + return parse_simm_not_reg (cd, strp, opindex, svalp); +} + +/* Handle simm3/simm11/imm3/imm12. */ + +static const char * +parse_simm_not_reg (CGEN_CPU_DESC cd, + const char ** strp, + int opindex, + long * valuep) +{ + const char * errmsg; + + int sign = 0; + int bits = 0; + + switch (opindex) + { + case EPIPHANY_OPERAND_SIMM3: + sign = 1; bits = 3; break; + case EPIPHANY_OPERAND_SIMM11: + sign = 1; bits = 11; break; + case EPIPHANY_OPERAND_DISP3: + sign = 0; bits = 3; break; + case EPIPHANY_OPERAND_DISP11: + /* Load/store displacement is a sign-magnitude 12 bit value. */ + sign = 0; bits = 11; break; + } + + /* First try to parse as a register name and reject the operand. */ + errmsg = cgen_parse_keyword (cd, strp, & epiphany_cgen_opval_gr_names,valuep); + if (!errmsg) + return _("register name used as immediate value"); + + errmsg = (sign ? cgen_parse_signed_integer (cd, strp, opindex, valuep) + : cgen_parse_unsigned_integer (cd, strp, opindex, + (unsigned long *) valuep)); + if (errmsg) + return errmsg; + + if (sign) + errmsg = cgen_validate_signed_integer (*valuep, + -((1L << bits) - 1), (1 << (bits - 1)) - 1); + else + errmsg = cgen_validate_unsigned_integer (*valuep, 0, (1L << bits) - 1); + + return errmsg; +} + +static const char * +parse_postindex (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + const char ** strp, + int opindex ATTRIBUTE_UNUSED, + bfd_vma * valuep) +{ + if (**strp == '#') + ++*strp; /* Skip leading hashes. */ + + if (**strp == '-') + { + *valuep = 1; + ++*strp; + } + else if (**strp == '+') + { + *valuep = 0; + ++*strp; + } + else + *valuep = 0; + + return NULL; +} + +static const char * +parse_imm8 (CGEN_CPU_DESC cd, + const char ** strp, + int opindex, + bfd_reloc_code_real_type code, + enum cgen_parse_operand_result * result_type, + bfd_vma * valuep) +{ + const char * errmsg; + enum cgen_parse_operand_result rt; + long dummyval; + + if (!result_type) + result_type = &rt; + + code = BFD_RELOC_NONE; + + if (!cgen_parse_keyword (cd, strp, &epiphany_cgen_opval_gr_names, &dummyval) + || !cgen_parse_keyword (cd, strp, &epiphany_cgen_opval_cr_names, + &dummyval)) + /* Don't treat "mov ip,ip" as a move-immediate. */ + return _("register source in immediate move"); + + errmsg = cgen_parse_address (cd, strp, opindex, code, result_type, valuep); + if (errmsg) + return errmsg; + + if (*result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER) + errmsg = cgen_validate_unsigned_integer (*valuep, 0, 0xff); + else + errmsg = _("byte relocation unsupported"); + + *valuep &= 0xff; + return errmsg; +} + +static const char * MISSING_CLOSE_PARENTHESIS = N_("missing `)'"); + +static const char * +parse_imm16 (CGEN_CPU_DESC cd, + const char ** strp, + int opindex, + bfd_reloc_code_real_type code ATTRIBUTE_UNUSED, + enum cgen_parse_operand_result * result_type, + bfd_vma * valuep) +{ + const char * errmsg; + enum cgen_parse_operand_result rt; + long dummyval; + + if (!result_type) + result_type = &rt; + + if (strncasecmp (*strp, "%high(", 6) == 0) + { + *strp += 6; + errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_EPIPHANY_HIGH, + result_type, valuep); + if (**strp != ')') + return MISSING_CLOSE_PARENTHESIS; + ++*strp; + *valuep >>= 16; + } + else if (strncasecmp (*strp, "%low(", 5) == 0) + { + *strp += 5; + errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_EPIPHANY_LOW, + result_type, valuep); + if (**strp != ')') + return MISSING_CLOSE_PARENTHESIS; + ++*strp; + } + else if (!cgen_parse_keyword (cd, strp, &epiphany_cgen_opval_gr_names, + &dummyval) + || !cgen_parse_keyword (cd, strp, &epiphany_cgen_opval_cr_names, + &dummyval)) + /* Don't treat "mov ip,ip" as a move-immediate. */ + return _("register source in immediate move"); + else + errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_16, + result_type, valuep); + + if (!errmsg && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER) + errmsg = cgen_validate_unsigned_integer (*valuep, 0, 0xffff); + + *valuep &= 0xffff; + return errmsg; +} + +const char * +parse_branch_addr (CGEN_CPU_DESC cd, + const char ** strp, + int opindex, + int opinfo ATTRIBUTE_UNUSED, + enum cgen_parse_operand_result * resultp ATTRIBUTE_UNUSED, + unsigned long * valuep ATTRIBUTE_UNUSED) +{ + const char * errmsg; + enum cgen_parse_operand_result result_type; + bfd_reloc_code_real_type code = BFD_RELOC_NONE; + bfd_vma value; + + switch (opindex) + { + case EPIPHANY_OPERAND_SIMM24: + code = BFD_RELOC_EPIPHANY_SIMM24; + break; + + case EPIPHANY_OPERAND_SIMM8: + code = BFD_RELOC_EPIPHANY_SIMM8; + break; + + default: + errmsg = _("ABORT: unknown operand"); + return errmsg; + } + + errmsg = cgen_parse_address (cd, strp, opindex, code, + &result_type, &value); + if (errmsg == NULL) + { + if (result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER) + { + /* Act as if we had done a PC-relative branch, ala .+num. */ + char buf[20]; + const char * bufp = (const char *) buf; + + sprintf (buf, ".+%ld", value); + errmsg = cgen_parse_address (cd, &bufp, opindex, code, &result_type, + &value); + } + + if (result_type == CGEN_PARSE_OPERAND_RESULT_QUEUED) + { + /* This will happen for things like (s2-s1) where s2 and s1 + are labels. */ + /* Nothing further to be done. */ + } + else + errmsg = _("Not a pc-relative address."); + } + return errmsg; +} + +/* -- dis.c */ + +#define CGEN_PRINT_INSN epiphany_print_insn + +static int +epiphany_print_insn (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info) +{ + bfd_byte buf[CGEN_MAX_INSN_SIZE]; + int buflen; + int status; + + info->bytes_per_chunk = 2; + + /* Attempt to read the base part of the insn. */ + info->bytes_per_line = buflen = cd->base_insn_bitsize / 8; + status = (*info->read_memory_func) (pc, buf, buflen, info); + + /* Try again with the minimum part, if min < base. */ + if (status != 0 && (cd->min_insn_bitsize < cd->base_insn_bitsize)) + { + info->bytes_per_line = buflen = cd->min_insn_bitsize / 8; + status = (*info->read_memory_func) (pc, buf, buflen, info); + } + + if (status != 0) + { + (*info->memory_error_func) (status, pc, info); + return -1; + } + + return print_insn (cd, pc, info, buf, buflen); +} + + +static void +print_postindex (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + void * dis_info, + long value, + unsigned int attrs ATTRIBUTE_UNUSED, + bfd_vma pc ATTRIBUTE_UNUSED, + int length ATTRIBUTE_UNUSED) +{ + disassemble_info *info = (disassemble_info *) dis_info; + (*info->fprintf_func) (info->stream, value ? "-" : "+"); +} + +static void +print_simm_not_reg (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + void * dis_info, + long value, + unsigned int attrs ATTRIBUTE_UNUSED, + bfd_vma pc ATTRIBUTE_UNUSED, + int length ATTRIBUTE_UNUSED) +{ + print_address (cd, dis_info, value, attrs, pc, length); +} + +static void +print_uimm_not_reg (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + void * dis_info, + unsigned long value, + unsigned int attrs ATTRIBUTE_UNUSED, + bfd_vma pc ATTRIBUTE_UNUSED, + int length ATTRIBUTE_UNUSED) +{ + disassemble_info *info = (disassemble_info *)dis_info; + + if (value & 0x800) + (*info->fprintf_func) (info->stream, "-"); + + value &= 0x7ff; + print_address (cd, dis_info, value, attrs, pc, length); +} + + +/* -- */ + diff --git a/include/ChangeLog b/include/ChangeLog index 716b43b66a8..cec4c43c914 100644 --- a/include/ChangeLog +++ b/include/ChangeLog @@ -1,3 +1,7 @@ +2011-10-25 Joern Rennecke <joern.rennecke@embecosm.com> + + * dis-asm.h (print_insn_epiphany): Declare. + 2011-10-21 Ulrich Drepper <drepper@gmail.com> * obstack.h [!GNUC] (obstack_free): Avoid cast to int. diff --git a/include/dis-asm.h b/include/dis-asm.h index d654211c3a8..ff4732568e3 100644 --- a/include/dis-asm.h +++ b/include/dis-asm.h @@ -233,6 +233,7 @@ extern int print_insn_crx (bfd_vma, disassemble_info *); extern int print_insn_d10v (bfd_vma, disassemble_info *); extern int print_insn_d30v (bfd_vma, disassemble_info *); extern int print_insn_dlx (bfd_vma, disassemble_info *); +extern int print_insn_epiphany (bfd_vma, disassemble_info *); extern int print_insn_fr30 (bfd_vma, disassemble_info *); extern int print_insn_frv (bfd_vma, disassemble_info *); extern int print_insn_h8300 (bfd_vma, disassemble_info *); diff --git a/include/elf/ChangeLog b/include/elf/ChangeLog index 369654393e7..b269004f2f1 100644 --- a/include/elf/ChangeLog +++ b/include/elf/ChangeLog @@ -1,3 +1,8 @@ +2011-10-25 Joern Rennecke <joern.rennecke@embecosm.com> + + * epiphany.h: New file. + * common.h (EM_ADAPTEVA_EPIPHANY): Define. + 2011-10-10 Alan Modra <amodra@gmail.com> * ppc64.h (R_PPC64_TOCSAVE): Add. diff --git a/include/elf/common.h b/include/elf/common.h index e46ae3370d8..a62db77aa4f 100644 --- a/include/elf/common.h +++ b/include/elf/common.h @@ -401,6 +401,8 @@ #define EM_MICROBLAZE_OLD 0xbaab /* Old MicroBlaze */ +#define EM_ADAPTEVA_EPIPHANY 0x1223 /* Adapteva's Epiphany architecture. */ + /* See the above comment before you add a new EM_* value here. */ /* Values for e_version. */ diff --git a/include/elf/epiphany.h b/include/elf/epiphany.h new file mode 100755 index 00000000000..33376250609 --- /dev/null +++ b/include/elf/epiphany.h @@ -0,0 +1,59 @@ +/* Adapteva EPIPHANY ELF support for BFD. + Copyright (C) 2011 Free Software Foundation, Inc. + Contributed by Embecosm on behalf of Adapteva, Inc. + + This file is part of BFD, the Binary File Descriptor library. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software Foundation, + Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ + +#ifndef _ELF_EPIPHANY_H +#define _ELF_EPIPHANY_H + +#include "elf/reloc-macros.h" + +/* Relocations. */ +START_RELOC_NUMBERS (elf_epiphany_reloc_type) + RELOC_NUMBER (R_EPIPHANY_NONE, 0) + + /* Absolute address relocations. */ + RELOC_NUMBER (R_EPIPHANY_8, 1) + RELOC_NUMBER (R_EPIPHANY_16, 2) + RELOC_NUMBER (R_EPIPHANY_32, 3) + + /* PC-relative relocations. */ + RELOC_NUMBER (R_EPIPHANY_8_PCREL, 4) + RELOC_NUMBER (R_EPIPHANY_16_PCREL,5) + RELOC_NUMBER (R_EPIPHANY_32_PCREL,6) + + /* special forms for 8/24 bit branch displacements. */ + RELOC_NUMBER (R_EPIPHANY_SIMM8, 7) + RELOC_NUMBER (R_EPIPHANY_SIMM24, 8) + + /* HIGH and LOW relocations taking part of a 32 bit address and + depositing it into the IMM16 field of a destination. */ + RELOC_NUMBER (R_EPIPHANY_HIGH, 9) + RELOC_NUMBER (R_EPIPHANY_LOW,10) + + /* 11 bit signed immediate value. */ + RELOC_NUMBER (R_EPIPHANY_SIMM11, 11) + /* 11 bit magnitude addressing displacement. */ + RELOC_NUMBER (R_EPIPHANY_IMM11, 12) + + /* 8 bit immediate for MOV.S R,IMM8. */ + RELOC_NUMBER (R_EPIPHANY_IMM8, 13) + +END_RELOC_NUMBERS(R_EPIPHANY_max) + +#endif /* _ELF_EPIPHANY_H */ diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 0158cf19add..6ad9cf386bf 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,26 @@ +2011-10-25 Joern Rennecke <joern.rennecke@embecosm.com> + + * Makefile.am (HFILES): Add epiphany-desc.h and epiphany-opc.h . + (TARGET_LIBOPCODES_CFILES): Add epiphany-asm.c, epiphany-desc.c, + epiphany-dis.c, epiphany-ibld.c and epiphany-opc.c . + (CLEANFILES): Add stamp-epiphany. + (EPIPHANY_DEPS): Set. Make CGEN-generated Epiphany files depend on it. + (stamp-epiphany): New rule. + * configure.in: Handle bfd_epiphany_arch. + * disassemble.c (ARCH_epiphany): Define. + (disassembler): Handle bfd_arch_epiphany. + * epiphany-asm.c: New file. + * epiphany-desc.c: New file. + * epiphany-desc.h: New file. + * epiphany-dis.c: New file. + * epiphany-ibld.c: New file. + * epiphany-opc.c: New file. + * epiphany-opc.h: New file. + * Makefile.in: Regenerate. + * configure: Regenerate. + * po/POTFILES.in: Regenerate. + * po/opcodes.pot: Regenerate. + 2011-10-24 Julian Brown <julian@codesourcery.com> * m68k-opc.c (m68k_opcodes): Fix entries for ColdFire moveml. diff --git a/opcodes/Makefile.am b/opcodes/Makefile.am index ec7fa3e64c8..cae73c2ab60 100644 --- a/opcodes/Makefile.am +++ b/opcodes/Makefile.am @@ -41,6 +41,7 @@ BUILD_LIB_DEPS = @BUILD_LIB_DEPS@ # Header files. HFILES = \ + epiphany-desc.h epiphany-opc.h \ fr30-desc.h fr30-opc.h \ frv-desc.h frv-opc.h \ h8500-opc.h \ @@ -95,6 +96,11 @@ TARGET_LIBOPCODES_CFILES = \ d30v-dis.c \ d30v-opc.c \ dlx-dis.c \ + epiphany-asm.c \ + epiphany-desc.c \ + epiphany-dis.c \ + epiphany-ibld.c \ + epiphany-opc.c \ fr30-asm.c \ fr30-desc.c \ fr30-dis.c \ @@ -311,7 +317,7 @@ po/POTFILES.in: @MAINT@ Makefile && mv tmp $(srcdir)/po/POTFILES.in CLEANFILES = \ - stamp-fr30 stamp-frv stamp-ip2k stamp-iq2000 stamp-lm32 \ + stamp-epiphany stamp-fr30 stamp-frv stamp-ip2k stamp-iq2000 stamp-lm32 \ stamp-m32c stamp-m32r stamp-mep stamp-mt \ stamp-openrisc stamp-xc16x stamp-xstormy16 \ libopcodes.a stamp-lib @@ -329,9 +335,10 @@ CGENDEPS = \ $(CGENDIR)/opc-opinst.scm \ cgen-asm.in cgen-dis.in cgen-ibld.in -CGEN_CPUS = fr30 frv ip2k iq2000 lm32 m32c m32r mep mt openrisc xc16x xstormy16 +CGEN_CPUS = epiphany fr30 frv ip2k iq2000 lm32 m32c m32r mep mt openrisc xc16x xstormy16 if CGEN_MAINT +EPIPHANY_DEPS = stamp-epiphany FR30_DEPS = stamp-fr30 FRV_DEPS = stamp-frv IP2K_DEPS = stamp-ip2k @@ -345,6 +352,7 @@ OPENRISC_DEPS = stamp-openrisc XC16X_DEPS = stamp-xc16x XSTORMY16_DEPS = stamp-xstormy16 else +EPIPHANY_DEPS = FR30_DEPS = FRV_DEPS = IP2K_DEPS = @@ -376,6 +384,16 @@ run-cgen-all: # For now, require developers to configure with --enable-cgen-maint. +$(srcdir)/epiphany-desc.h $(srcdir)/epiphany-desc.c $(srcdir)/epiphany-opc.h \ + $(srcdir)/epiphany-opc.c $(srcdir)/epiphany-ibld.c \ + $(srcdir)/epiphany-opinst.c $(srcdir)/epiphany-asm.c \ + $(srcdir)/epiphany-dis.c: $(EPIPHANY_DEPS) + @true + +stamp-epiphany: $(CGENDEPS) $(CPUDIR)/epiphany.cpu $(CPUDIR)/epiphany.opc + $(MAKE) run-cgen arch=epiphany prefix=epiphany options= \ + archfile=$(CPUDIR)/epiphany.cpu opcfile=$(CPUDIR)/epiphany.opc extrafiles= + $(srcdir)/fr30-desc.h $(srcdir)/fr30-desc.c $(srcdir)/fr30-opc.h $(srcdir)/fr30-opc.c $(srcdir)/fr30-ibld.c $(srcdir)/fr30-asm.c $(srcdir)/fr30-dis.c: $(FR30_DEPS) @true stamp-fr30: $(CGENDEPS) $(CPUDIR)/fr30.cpu $(CPUDIR)/fr30.opc diff --git a/opcodes/Makefile.in b/opcodes/Makefile.in index 7d260a76021..6c2815d8f89 100644 --- a/opcodes/Makefile.in +++ b/opcodes/Makefile.in @@ -310,6 +310,7 @@ BFD_H = ../bfd/bfd.h # Header files. HFILES = \ + epiphany-desc.h epiphany-opc.h \ fr30-desc.h fr30-opc.h \ frv-desc.h frv-opc.h \ h8500-opc.h \ @@ -365,6 +366,11 @@ TARGET_LIBOPCODES_CFILES = \ d30v-dis.c \ d30v-opc.c \ dlx-dis.c \ + epiphany-asm.c \ + epiphany-desc.c \ + epiphany-dis.c \ + epiphany-ibld.c \ + epiphany-opc.c \ fr30-asm.c \ fr30-desc.c \ fr30-dis.c \ @@ -550,7 +556,7 @@ noinst_LIBRARIES = libopcodes.a libopcodes_a_SOURCES = POTFILES = $(HFILES) $(CFILES) CLEANFILES = \ - stamp-fr30 stamp-frv stamp-ip2k stamp-iq2000 stamp-lm32 \ + stamp-epiphany stamp-fr30 stamp-frv stamp-ip2k stamp-iq2000 stamp-lm32 \ stamp-m32c stamp-m32r stamp-mep stamp-mt \ stamp-openrisc stamp-xc16x stamp-xstormy16 \ libopcodes.a stamp-lib @@ -566,7 +572,9 @@ CGENDEPS = \ $(CGENDIR)/opc-opinst.scm \ cgen-asm.in cgen-dis.in cgen-ibld.in -CGEN_CPUS = fr30 frv ip2k iq2000 lm32 m32c m32r mep mt openrisc xc16x xstormy16 +CGEN_CPUS = epiphany fr30 frv ip2k iq2000 lm32 m32c m32r mep mt openrisc xc16x xstormy16 +@CGEN_MAINT_FALSE@EPIPHANY_DEPS = +@CGEN_MAINT_TRUE@EPIPHANY_DEPS = stamp-epiphany @CGEN_MAINT_FALSE@FR30_DEPS = @CGEN_MAINT_TRUE@FR30_DEPS = stamp-fr30 @CGEN_MAINT_FALSE@FRV_DEPS = @@ -741,6 +749,11 @@ distclean-compile: @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/dis-init.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/disassemble.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/dlx-dis.Plo@am__quote@ +@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/epiphany-asm.Plo@am__quote@ +@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/epiphany-desc.Plo@am__quote@ +@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/epiphany-dis.Plo@am__quote@ +@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/epiphany-ibld.Plo@am__quote@ +@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/epiphany-opc.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/fr30-asm.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/fr30-desc.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/fr30-dis.Plo@am__quote@ @@ -1229,6 +1242,16 @@ run-cgen-all: # For now, require developers to configure with --enable-cgen-maint. +$(srcdir)/epiphany-desc.h $(srcdir)/epiphany-desc.c $(srcdir)/epiphany-opc.h \ + $(srcdir)/epiphany-opc.c $(srcdir)/epiphany-ibld.c \ + $(srcdir)/epiphany-opinst.c $(srcdir)/epiphany-asm.c \ + $(srcdir)/epiphany-dis.c: $(EPIPHANY_DEPS) + @true + +stamp-epiphany: $(CGENDEPS) $(CPUDIR)/epiphany.cpu $(CPUDIR)/epiphany.opc + $(MAKE) run-cgen arch=epiphany prefix=epiphany options= \ + archfile=$(CPUDIR)/epiphany.cpu opcfile=$(CPUDIR)/epiphany.opc extrafiles= + $(srcdir)/fr30-desc.h $(srcdir)/fr30-desc.c $(srcdir)/fr30-opc.h $(srcdir)/fr30-opc.c $(srcdir)/fr30-ibld.c $(srcdir)/fr30-asm.c $(srcdir)/fr30-dis.c: $(FR30_DEPS) @true stamp-fr30: $(CGENDEPS) $(CPUDIR)/fr30.cpu $(CPUDIR)/fr30.opc diff --git a/opcodes/configure b/opcodes/configure index 746070e550d..d89ed6a58d4 100755 --- a/opcodes/configure +++ b/opcodes/configure @@ -12429,6 +12429,7 @@ if test x${all_targets} = xfalse ; then bfd_i960_arch) ta="$ta i960-dis.lo" ;; bfd_ia64_arch) ta="$ta ia64-dis.lo ia64-opc.lo" ;; bfd_ip2k_arch) ta="$ta ip2k-asm.lo ip2k-desc.lo ip2k-dis.lo ip2k-ibld.lo ip2k-opc.lo" using_cgen=yes ;; + bfd_epiphany_arch) ta="$ta epiphany-asm.lo epiphany-desc.lo epiphany-dis.lo epiphany-ibld.lo epiphany-opc.lo" using_cgen=yes ;; bfd_iq2000_arch) ta="$ta iq2000-asm.lo iq2000-desc.lo iq2000-dis.lo iq2000-ibld.lo iq2000-opc.lo" using_cgen=yes ;; bfd_lm32_arch) ta="$ta lm32-asm.lo lm32-desc.lo lm32-dis.lo lm32-ibld.lo lm32-opc.lo lm32-opinst.lo" using_cgen=yes ;; bfd_m32c_arch) ta="$ta m32c-asm.lo m32c-desc.lo m32c-dis.lo m32c-ibld.lo m32c-opc.lo" using_cgen=yes ;; diff --git a/opcodes/configure.in b/opcodes/configure.in index 3776be37fcd..fc87735f0fa 100644 --- a/opcodes/configure.in +++ b/opcodes/configure.in @@ -243,6 +243,7 @@ if test x${all_targets} = xfalse ; then bfd_i960_arch) ta="$ta i960-dis.lo" ;; bfd_ia64_arch) ta="$ta ia64-dis.lo ia64-opc.lo" ;; bfd_ip2k_arch) ta="$ta ip2k-asm.lo ip2k-desc.lo ip2k-dis.lo ip2k-ibld.lo ip2k-opc.lo" using_cgen=yes ;; + bfd_epiphany_arch) ta="$ta epiphany-asm.lo epiphany-desc.lo epiphany-dis.lo epiphany-ibld.lo epiphany-opc.lo" using_cgen=yes ;; bfd_iq2000_arch) ta="$ta iq2000-asm.lo iq2000-desc.lo iq2000-dis.lo iq2000-ibld.lo iq2000-opc.lo" using_cgen=yes ;; bfd_lm32_arch) ta="$ta lm32-asm.lo lm32-desc.lo lm32-dis.lo lm32-ibld.lo lm32-opc.lo lm32-opinst.lo" using_cgen=yes ;; bfd_m32c_arch) ta="$ta m32c-asm.lo m32c-desc.lo m32c-dis.lo m32c-ibld.lo m32c-opc.lo" using_cgen=yes ;; diff --git a/opcodes/disassemble.c b/opcodes/disassemble.c index 29192716205..a9c65f32f5f 100644 --- a/opcodes/disassemble.c +++ b/opcodes/disassemble.c @@ -26,6 +26,7 @@ #define ARCH_alpha #define ARCH_arc #define ARCH_arm +#define ARCH_epiphany #define ARCH_avr #define ARCH_bfin #define ARCH_cr16 @@ -224,6 +225,11 @@ disassembler (abfd) disassemble = print_insn_ip2k; break; #endif +#ifdef ARCH_epiphany + case bfd_arch_epiphany: + disassemble = print_insn_epiphany; + break; +#endif #ifdef ARCH_fr30 case bfd_arch_fr30: disassemble = print_insn_fr30; diff --git a/opcodes/epiphany-asm.c b/opcodes/epiphany-asm.c new file mode 100644 index 00000000000..31ceb3e542b --- /dev/null +++ b/opcodes/epiphany-asm.c @@ -0,0 +1,863 @@ +/* Assembler interface for targets using CGEN. -*- C -*- + CGEN: Cpu tools GENerator + + THIS FILE IS MACHINE GENERATED WITH CGEN. + - the resultant file is machine generated, cgen-asm.in isn't + + Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2005, 2007, 2008, 2010 + Free Software Foundation, Inc. + + This file is part of libopcodes. + + This library is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + It is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software Foundation, Inc., + 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ + + +/* ??? Eventually more and more of this stuff can go to cpu-independent files. + Keep that in mind. */ + +#include "sysdep.h" +#include <stdio.h> +#include "ansidecl.h" +#include "bfd.h" +#include "symcat.h" +#include "epiphany-desc.h" +#include "epiphany-opc.h" +#include "opintl.h" +#include "xregex.h" +#include "libiberty.h" +#include "safe-ctype.h" + +#undef min +#define min(a,b) ((a) < (b) ? (a) : (b)) +#undef max +#define max(a,b) ((a) > (b) ? (a) : (b)) + +static const char * parse_insn_normal + (CGEN_CPU_DESC, const CGEN_INSN *, const char **, CGEN_FIELDS *); + +/* -- assembler routines inserted here. */ + +/* -- asm.c */ +const char * +parse_shortregs (CGEN_CPU_DESC cd, + const char ** strp, + CGEN_KEYWORD * keywords, + long * regno) +{ + const char * errmsg; + + /* Parse register. */ + errmsg = cgen_parse_keyword (cd, strp, keywords, regno); + + if (errmsg) + return errmsg; + + if (*regno > 7) + errmsg = _("register unavailable for short instructions"); + + return errmsg; +} + +static const char * parse_simm_not_reg (CGEN_CPU_DESC, const char **, int, + long *); + +static const char * +parse_uimm_not_reg (CGEN_CPU_DESC cd, + const char ** strp, + int opindex, + unsigned long * valuep) +{ + long * svalp = (void *) valuep; + return parse_simm_not_reg (cd, strp, opindex, svalp); +} + +/* Handle simm3/simm11/imm3/imm12. */ + +static const char * +parse_simm_not_reg (CGEN_CPU_DESC cd, + const char ** strp, + int opindex, + long * valuep) +{ + const char * errmsg; + + int sign = 0; + int bits = 0; + + switch (opindex) + { + case EPIPHANY_OPERAND_SIMM3: + sign = 1; bits = 3; break; + case EPIPHANY_OPERAND_SIMM11: + sign = 1; bits = 11; break; + case EPIPHANY_OPERAND_DISP3: + sign = 0; bits = 3; break; + case EPIPHANY_OPERAND_DISP11: + /* Load/store displacement is a sign-magnitude 12 bit value. */ + sign = 0; bits = 11; break; + } + + /* First try to parse as a register name and reject the operand. */ + errmsg = cgen_parse_keyword (cd, strp, & epiphany_cgen_opval_gr_names,valuep); + if (!errmsg) + return _("register name used as immediate value"); + + errmsg = (sign ? cgen_parse_signed_integer (cd, strp, opindex, valuep) + : cgen_parse_unsigned_integer (cd, strp, opindex, + (unsigned long *) valuep)); + if (errmsg) + return errmsg; + + if (sign) + errmsg = cgen_validate_signed_integer (*valuep, + -((1L << bits) - 1), (1 << (bits - 1)) - 1); + else + errmsg = cgen_validate_unsigned_integer (*valuep, 0, (1L << bits) - 1); + + return errmsg; +} + +static const char * +parse_postindex (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + const char ** strp, + int opindex ATTRIBUTE_UNUSED, + bfd_vma * valuep) +{ + if (**strp == '#') + ++*strp; /* Skip leading hashes. */ + + if (**strp == '-') + { + *valuep = 1; + ++*strp; + } + else if (**strp == '+') + { + *valuep = 0; + ++*strp; + } + else + *valuep = 0; + + return NULL; +} + +static const char * +parse_imm8 (CGEN_CPU_DESC cd, + const char ** strp, + int opindex, + bfd_reloc_code_real_type code, + enum cgen_parse_operand_result * result_type, + bfd_vma * valuep) +{ + const char * errmsg; + enum cgen_parse_operand_result rt; + long dummyval; + + if (!result_type) + result_type = &rt; + + code = BFD_RELOC_NONE; + + if (!cgen_parse_keyword (cd, strp, &epiphany_cgen_opval_gr_names, &dummyval) + || !cgen_parse_keyword (cd, strp, &epiphany_cgen_opval_cr_names, + &dummyval)) + /* Don't treat "mov ip,ip" as a move-immediate. */ + return _("register source in immediate move"); + + errmsg = cgen_parse_address (cd, strp, opindex, code, result_type, valuep); + if (errmsg) + return errmsg; + + if (*result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER) + errmsg = cgen_validate_unsigned_integer (*valuep, 0, 0xff); + else + errmsg = _("byte relocation unsupported"); + + *valuep &= 0xff; + return errmsg; +} + +static const char * MISSING_CLOSE_PARENTHESIS = N_("missing `)'"); + +static const char * +parse_imm16 (CGEN_CPU_DESC cd, + const char ** strp, + int opindex, + bfd_reloc_code_real_type code ATTRIBUTE_UNUSED, + enum cgen_parse_operand_result * result_type, + bfd_vma * valuep) +{ + const char * errmsg; + enum cgen_parse_operand_result rt; + long dummyval; + + if (!result_type) + result_type = &rt; + + if (strncasecmp (*strp, "%high(", 6) == 0) + { + *strp += 6; + errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_EPIPHANY_HIGH, + result_type, valuep); + if (**strp != ')') + return MISSING_CLOSE_PARENTHESIS; + ++*strp; + *valuep >>= 16; + } + else if (strncasecmp (*strp, "%low(", 5) == 0) + { + *strp += 5; + errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_EPIPHANY_LOW, + result_type, valuep); + if (**strp != ')') + return MISSING_CLOSE_PARENTHESIS; + ++*strp; + } + else if (!cgen_parse_keyword (cd, strp, &epiphany_cgen_opval_gr_names, + &dummyval) + || !cgen_parse_keyword (cd, strp, &epiphany_cgen_opval_cr_names, + &dummyval)) + /* Don't treat "mov ip,ip" as a move-immediate. */ + return _("register source in immediate move"); + else + errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_16, + result_type, valuep); + + if (!errmsg && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER) + errmsg = cgen_validate_unsigned_integer (*valuep, 0, 0xffff); + + *valuep &= 0xffff; + return errmsg; +} + +const char * +parse_branch_addr (CGEN_CPU_DESC cd, + const char ** strp, + int opindex, + int opinfo ATTRIBUTE_UNUSED, + enum cgen_parse_operand_result * resultp ATTRIBUTE_UNUSED, + unsigned long * valuep ATTRIBUTE_UNUSED) +{ + const char * errmsg; + enum cgen_parse_operand_result result_type; + bfd_reloc_code_real_type code = BFD_RELOC_NONE; + bfd_vma value; + + switch (opindex) + { + case EPIPHANY_OPERAND_SIMM24: + code = BFD_RELOC_EPIPHANY_SIMM24; + break; + + case EPIPHANY_OPERAND_SIMM8: + code = BFD_RELOC_EPIPHANY_SIMM8; + break; + + default: + errmsg = _("ABORT: unknown operand"); + return errmsg; + } + + errmsg = cgen_parse_address (cd, strp, opindex, code, + &result_type, &value); + if (errmsg == NULL) + { + if (result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER) + { + /* Act as if we had done a PC-relative branch, ala .+num. */ + char buf[20]; + const char * bufp = (const char *) buf; + + sprintf (buf, ".+%ld", value); + errmsg = cgen_parse_address (cd, &bufp, opindex, code, &result_type, + &value); + } + + if (result_type == CGEN_PARSE_OPERAND_RESULT_QUEUED) + { + /* This will happen for things like (s2-s1) where s2 and s1 + are labels. */ + /* Nothing further to be done. */ + } + else + errmsg = _("Not a pc-relative address."); + } + return errmsg; +} + +/* -- dis.c */ + +const char * epiphany_cgen_parse_operand + (CGEN_CPU_DESC, int, const char **, CGEN_FIELDS *); + +/* Main entry point for operand parsing. + + This function is basically just a big switch statement. Earlier versions + used tables to look up the function to use, but + - if the table contains both assembler and disassembler functions then + the disassembler contains much of the assembler and vice-versa, + - there's a lot of inlining possibilities as things grow, + - using a switch statement avoids the function call overhead. + + This function could be moved into `parse_insn_normal', but keeping it + separate makes clear the interface between `parse_insn_normal' and each of + the handlers. */ + +const char * +epiphany_cgen_parse_operand (CGEN_CPU_DESC cd, + int opindex, + const char ** strp, + CGEN_FIELDS * fields) +{ + const char * errmsg = NULL; + /* Used by scalar operands that still need to be parsed. */ + long junk ATTRIBUTE_UNUSED; + + switch (opindex) + { + case EPIPHANY_OPERAND_DIRECTION : + errmsg = parse_postindex (cd, strp, EPIPHANY_OPERAND_DIRECTION, (unsigned long *) (& fields->f_addsubx)); + break; + case EPIPHANY_OPERAND_DISP11 : + errmsg = parse_uimm_not_reg (cd, strp, EPIPHANY_OPERAND_DISP11, (unsigned long *) (& fields->f_disp11)); + break; + case EPIPHANY_OPERAND_DISP3 : + errmsg = cgen_parse_unsigned_integer (cd, strp, EPIPHANY_OPERAND_DISP3, (unsigned long *) (& fields->f_disp3)); + break; + case EPIPHANY_OPERAND_DPMI : + errmsg = parse_postindex (cd, strp, EPIPHANY_OPERAND_DPMI, (unsigned long *) (& fields->f_subd)); + break; + case EPIPHANY_OPERAND_FRD : + errmsg = parse_shortregs (cd, strp, & epiphany_cgen_opval_gr_names, & fields->f_rd); + break; + case EPIPHANY_OPERAND_FRD6 : + errmsg = cgen_parse_keyword (cd, strp, & epiphany_cgen_opval_gr_names, & fields->f_rd6); + break; + case EPIPHANY_OPERAND_FRM : + errmsg = parse_shortregs (cd, strp, & epiphany_cgen_opval_gr_names, & fields->f_rm); + break; + case EPIPHANY_OPERAND_FRM6 : + errmsg = cgen_parse_keyword (cd, strp, & epiphany_cgen_opval_gr_names, & fields->f_rm6); + break; + case EPIPHANY_OPERAND_FRN : + errmsg = parse_shortregs (cd, strp, & epiphany_cgen_opval_gr_names, & fields->f_rn); + break; + case EPIPHANY_OPERAND_FRN6 : + errmsg = cgen_parse_keyword (cd, strp, & epiphany_cgen_opval_gr_names, & fields->f_rn6); + break; + case EPIPHANY_OPERAND_IMM16 : + { + bfd_vma value = 0; + errmsg = parse_imm16 (cd, strp, EPIPHANY_OPERAND_IMM16, 0, NULL, & value); + fields->f_imm16 = value; + } + break; + case EPIPHANY_OPERAND_IMM8 : + { + bfd_vma value = 0; + errmsg = parse_imm8 (cd, strp, EPIPHANY_OPERAND_IMM8, 0, NULL, & value); + fields->f_imm8 = value; + } + break; + case EPIPHANY_OPERAND_RD : + errmsg = parse_shortregs (cd, strp, & epiphany_cgen_opval_gr_names, & fields->f_rd); + break; + case EPIPHANY_OPERAND_RD6 : + errmsg = cgen_parse_keyword (cd, strp, & epiphany_cgen_opval_gr_names, & fields->f_rd6); + break; + case EPIPHANY_OPERAND_RM : + errmsg = parse_shortregs (cd, strp, & epiphany_cgen_opval_gr_names, & fields->f_rm); + break; + case EPIPHANY_OPERAND_RM6 : + errmsg = cgen_parse_keyword (cd, strp, & epiphany_cgen_opval_gr_names, & fields->f_rm6); + break; + case EPIPHANY_OPERAND_RN : + errmsg = parse_shortregs (cd, strp, & epiphany_cgen_opval_gr_names, & fields->f_rn); + break; + case EPIPHANY_OPERAND_RN6 : + errmsg = cgen_parse_keyword (cd, strp, & epiphany_cgen_opval_gr_names, & fields->f_rn6); + break; + case EPIPHANY_OPERAND_SD : + errmsg = parse_shortregs (cd, strp, & epiphany_cgen_opval_cr_names, & fields->f_sd); + break; + case EPIPHANY_OPERAND_SD6 : + errmsg = cgen_parse_keyword (cd, strp, & epiphany_cgen_opval_cr_names, & fields->f_sd6); + break; + case EPIPHANY_OPERAND_SDDMA : + errmsg = cgen_parse_keyword (cd, strp, & epiphany_cgen_opval_crdma_names, & fields->f_sd6); + break; + case EPIPHANY_OPERAND_SDMEM : + errmsg = cgen_parse_keyword (cd, strp, & epiphany_cgen_opval_crmem_names, & fields->f_sd6); + break; + case EPIPHANY_OPERAND_SDMESH : + errmsg = cgen_parse_keyword (cd, strp, & epiphany_cgen_opval_crmesh_names, & fields->f_sd6); + break; + case EPIPHANY_OPERAND_SHIFT : + errmsg = cgen_parse_unsigned_integer (cd, strp, EPIPHANY_OPERAND_SHIFT, (unsigned long *) (& fields->f_shift)); + break; + case EPIPHANY_OPERAND_SIMM11 : + errmsg = parse_simm_not_reg (cd, strp, EPIPHANY_OPERAND_SIMM11, (long *) (& fields->f_sdisp11)); + break; + case EPIPHANY_OPERAND_SIMM24 : + { + bfd_vma value = 0; + errmsg = parse_branch_addr (cd, strp, EPIPHANY_OPERAND_SIMM24, 0, NULL, & value); + fields->f_simm24 = value; + } + break; + case EPIPHANY_OPERAND_SIMM3 : + errmsg = parse_simm_not_reg (cd, strp, EPIPHANY_OPERAND_SIMM3, (long *) (& fields->f_sdisp3)); + break; + case EPIPHANY_OPERAND_SIMM8 : + { + bfd_vma value = 0; + errmsg = parse_branch_addr (cd, strp, EPIPHANY_OPERAND_SIMM8, 0, NULL, & value); + fields->f_simm8 = value; + } + break; + case EPIPHANY_OPERAND_SN : + errmsg = parse_shortregs (cd, strp, & epiphany_cgen_opval_cr_names, & fields->f_sn); + break; + case EPIPHANY_OPERAND_SN6 : + errmsg = cgen_parse_keyword (cd, strp, & epiphany_cgen_opval_cr_names, & fields->f_sn6); + break; + case EPIPHANY_OPERAND_SNDMA : + errmsg = cgen_parse_keyword (cd, strp, & epiphany_cgen_opval_crdma_names, & fields->f_sn6); + break; + case EPIPHANY_OPERAND_SNMEM : + errmsg = cgen_parse_keyword (cd, strp, & epiphany_cgen_opval_crmem_names, & fields->f_sn6); + break; + case EPIPHANY_OPERAND_SNMESH : + errmsg = cgen_parse_keyword (cd, strp, & epiphany_cgen_opval_crmesh_names, & fields->f_sn6); + break; + case EPIPHANY_OPERAND_SWI_NUM : + errmsg = parse_uimm_not_reg (cd, strp, EPIPHANY_OPERAND_SWI_NUM, (unsigned long *) (& fields->f_trap_num)); + break; + case EPIPHANY_OPERAND_TRAPNUM6 : + errmsg = cgen_parse_unsigned_integer (cd, strp, EPIPHANY_OPERAND_TRAPNUM6, (unsigned long *) (& fields->f_trap_num)); + break; + + default : + /* xgettext:c-format */ + fprintf (stderr, _("Unrecognized field %d while parsing.\n"), opindex); + abort (); + } + + return errmsg; +} + +cgen_parse_fn * const epiphany_cgen_parse_handlers[] = +{ + parse_insn_normal, +}; + +void +epiphany_cgen_init_asm (CGEN_CPU_DESC cd) +{ + epiphany_cgen_init_opcode_table (cd); + epiphany_cgen_init_ibld_table (cd); + cd->parse_handlers = & epiphany_cgen_parse_handlers[0]; + cd->parse_operand = epiphany_cgen_parse_operand; +#ifdef CGEN_ASM_INIT_HOOK +CGEN_ASM_INIT_HOOK +#endif +} + + + +/* Regex construction routine. + + This translates an opcode syntax string into a regex string, + by replacing any non-character syntax element (such as an + opcode) with the pattern '.*' + + It then compiles the regex and stores it in the opcode, for + later use by epiphany_cgen_assemble_insn + + Returns NULL for success, an error message for failure. */ + +char * +epiphany_cgen_build_insn_regex (CGEN_INSN *insn) +{ + CGEN_OPCODE *opc = (CGEN_OPCODE *) CGEN_INSN_OPCODE (insn); + const char *mnem = CGEN_INSN_MNEMONIC (insn); + char rxbuf[CGEN_MAX_RX_ELEMENTS]; + char *rx = rxbuf; + const CGEN_SYNTAX_CHAR_TYPE *syn; + int reg_err; + + syn = CGEN_SYNTAX_STRING (CGEN_OPCODE_SYNTAX (opc)); + + /* Mnemonics come first in the syntax string. */ + if (! CGEN_SYNTAX_MNEMONIC_P (* syn)) + return _("missing mnemonic in syntax string"); + ++syn; + + /* Generate a case sensitive regular expression that emulates case + insensitive matching in the "C" locale. We cannot generate a case + insensitive regular expression because in Turkish locales, 'i' and 'I' + are not equal modulo case conversion. */ + + /* Copy the literal mnemonic out of the insn. */ + for (; *mnem; mnem++) + { + char c = *mnem; + + if (ISALPHA (c)) + { + *rx++ = '['; + *rx++ = TOLOWER (c); + *rx++ = TOUPPER (c); + *rx++ = ']'; + } + else + *rx++ = c; + } + + /* Copy any remaining literals from the syntax string into the rx. */ + for(; * syn != 0 && rx <= rxbuf + (CGEN_MAX_RX_ELEMENTS - 7 - 4); ++syn) + { + if (CGEN_SYNTAX_CHAR_P (* syn)) + { + char c = CGEN_SYNTAX_CHAR (* syn); + + switch (c) + { + /* Escape any regex metacharacters in the syntax. */ + case '.': case '[': case '\\': + case '*': case '^': case '$': + +#ifdef CGEN_ESCAPE_EXTENDED_REGEX + case '?': case '{': case '}': + case '(': case ')': case '*': + case '|': case '+': case ']': +#endif + *rx++ = '\\'; + *rx++ = c; + break; + + default: + if (ISALPHA (c)) + { + *rx++ = '['; + *rx++ = TOLOWER (c); + *rx++ = TOUPPER (c); + *rx++ = ']'; + } + else + *rx++ = c; + break; + } + } + else + { + /* Replace non-syntax fields with globs. */ + *rx++ = '.'; + *rx++ = '*'; + } + } + + /* Trailing whitespace ok. */ + * rx++ = '['; + * rx++ = ' '; + * rx++ = '\t'; + * rx++ = ']'; + * rx++ = '*'; + + /* But anchor it after that. */ + * rx++ = '$'; + * rx = '\0'; + + CGEN_INSN_RX (insn) = xmalloc (sizeof (regex_t)); + reg_err = regcomp ((regex_t *) CGEN_INSN_RX (insn), rxbuf, REG_NOSUB); + + if (reg_err == 0) + return NULL; + else + { + static char msg[80]; + + regerror (reg_err, (regex_t *) CGEN_INSN_RX (insn), msg, 80); + regfree ((regex_t *) CGEN_INSN_RX (insn)); + free (CGEN_INSN_RX (insn)); + (CGEN_INSN_RX (insn)) = NULL; + return msg; + } +} + + +/* Default insn parser. + + The syntax string is scanned and operands are parsed and stored in FIELDS. + Relocs are queued as we go via other callbacks. + + ??? Note that this is currently an all-or-nothing parser. If we fail to + parse the instruction, we return 0 and the caller will start over from + the beginning. Backtracking will be necessary in parsing subexpressions, + but that can be handled there. Not handling backtracking here may get + expensive in the case of the m68k. Deal with later. + + Returns NULL for success, an error message for failure. */ + +static const char * +parse_insn_normal (CGEN_CPU_DESC cd, + const CGEN_INSN *insn, + const char **strp, + CGEN_FIELDS *fields) +{ + /* ??? Runtime added insns not handled yet. */ + const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn); + const char *str = *strp; + const char *errmsg; + const char *p; + const CGEN_SYNTAX_CHAR_TYPE * syn; +#ifdef CGEN_MNEMONIC_OPERANDS + /* FIXME: wip */ + int past_opcode_p; +#endif + + /* For now we assume the mnemonic is first (there are no leading operands). + We can parse it without needing to set up operand parsing. + GAS's input scrubber will ensure mnemonics are lowercase, but we may + not be called from GAS. */ + p = CGEN_INSN_MNEMONIC (insn); + while (*p && TOLOWER (*p) == TOLOWER (*str)) + ++p, ++str; + + if (* p) + return _("unrecognized instruction"); + +#ifndef CGEN_MNEMONIC_OPERANDS + if (* str && ! ISSPACE (* str)) + return _("unrecognized instruction"); +#endif + + CGEN_INIT_PARSE (cd); + cgen_init_parse_operand (cd); +#ifdef CGEN_MNEMONIC_OPERANDS + past_opcode_p = 0; +#endif + + /* We don't check for (*str != '\0') here because we want to parse + any trailing fake arguments in the syntax string. */ + syn = CGEN_SYNTAX_STRING (syntax); + + /* Mnemonics come first for now, ensure valid string. */ + if (! CGEN_SYNTAX_MNEMONIC_P (* syn)) + abort (); + + ++syn; + + while (* syn != 0) + { + /* Non operand chars must match exactly. */ + if (CGEN_SYNTAX_CHAR_P (* syn)) + { + /* FIXME: While we allow for non-GAS callers above, we assume the + first char after the mnemonic part is a space. */ + /* FIXME: We also take inappropriate advantage of the fact that + GAS's input scrubber will remove extraneous blanks. */ + if (TOLOWER (*str) == TOLOWER (CGEN_SYNTAX_CHAR (* syn))) + { +#ifdef CGEN_MNEMONIC_OPERANDS + if (CGEN_SYNTAX_CHAR(* syn) == ' ') + past_opcode_p = 1; +#endif + ++ syn; + ++ str; + } + else if (*str) + { + /* Syntax char didn't match. Can't be this insn. */ + static char msg [80]; + + /* xgettext:c-format */ + sprintf (msg, _("syntax error (expected char `%c', found `%c')"), + CGEN_SYNTAX_CHAR(*syn), *str); + return msg; + } + else + { + /* Ran out of input. */ + static char msg [80]; + + /* xgettext:c-format */ + sprintf (msg, _("syntax error (expected char `%c', found end of instruction)"), + CGEN_SYNTAX_CHAR(*syn)); + return msg; + } + continue; + } + +#ifdef CGEN_MNEMONIC_OPERANDS + (void) past_opcode_p; +#endif + /* We have an operand of some sort. */ + errmsg = cd->parse_operand (cd, CGEN_SYNTAX_FIELD (*syn), &str, fields); + if (errmsg) + return errmsg; + + /* Done with this operand, continue with next one. */ + ++ syn; + } + + /* If we're at the end of the syntax string, we're done. */ + if (* syn == 0) + { + /* FIXME: For the moment we assume a valid `str' can only contain + blanks now. IE: We needn't try again with a longer version of + the insn and it is assumed that longer versions of insns appear + before shorter ones (eg: lsr r2,r3,1 vs lsr r2,r3). */ + while (ISSPACE (* str)) + ++ str; + + if (* str != '\0') + return _("junk at end of line"); /* FIXME: would like to include `str' */ + + return NULL; + } + + /* We couldn't parse it. */ + return _("unrecognized instruction"); +} + +/* Main entry point. + This routine is called for each instruction to be assembled. + STR points to the insn to be assembled. + We assume all necessary tables have been initialized. + The assembled instruction, less any fixups, is stored in BUF. + Remember that if CGEN_INT_INSN_P then BUF is an int and thus the value + still needs to be converted to target byte order, otherwise BUF is an array + of bytes in target byte order. + The result is a pointer to the insn's entry in the opcode table, + or NULL if an error occured (an error message will have already been + printed). + + Note that when processing (non-alias) macro-insns, + this function recurses. + + ??? It's possible to make this cpu-independent. + One would have to deal with a few minor things. + At this point in time doing so would be more of a curiosity than useful + [for example this file isn't _that_ big], but keeping the possibility in + mind helps keep the design clean. */ + +const CGEN_INSN * +epiphany_cgen_assemble_insn (CGEN_CPU_DESC cd, + const char *str, + CGEN_FIELDS *fields, + CGEN_INSN_BYTES_PTR buf, + char **errmsg) +{ + const char *start; + CGEN_INSN_LIST *ilist; + const char *parse_errmsg = NULL; + const char *insert_errmsg = NULL; + int recognized_mnemonic = 0; + + /* Skip leading white space. */ + while (ISSPACE (* str)) + ++ str; + + /* The instructions are stored in hashed lists. + Get the first in the list. */ + ilist = CGEN_ASM_LOOKUP_INSN (cd, str); + + /* Keep looking until we find a match. */ + start = str; + for ( ; ilist != NULL ; ilist = CGEN_ASM_NEXT_INSN (ilist)) + { + const CGEN_INSN *insn = ilist->insn; + recognized_mnemonic = 1; + +#ifdef CGEN_VALIDATE_INSN_SUPPORTED + /* Not usually needed as unsupported opcodes + shouldn't be in the hash lists. */ + /* Is this insn supported by the selected cpu? */ + if (! epiphany_cgen_insn_supported (cd, insn)) + continue; +#endif + /* If the RELAXED attribute is set, this is an insn that shouldn't be + chosen immediately. Instead, it is used during assembler/linker + relaxation if possible. */ + if (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_RELAXED) != 0) + continue; + + str = start; + + /* Skip this insn if str doesn't look right lexically. */ + if (CGEN_INSN_RX (insn) != NULL && + regexec ((regex_t *) CGEN_INSN_RX (insn), str, 0, NULL, 0) == REG_NOMATCH) + continue; + + /* Allow parse/insert handlers to obtain length of insn. */ + CGEN_FIELDS_BITSIZE (fields) = CGEN_INSN_BITSIZE (insn); + + parse_errmsg = CGEN_PARSE_FN (cd, insn) (cd, insn, & str, fields); + if (parse_errmsg != NULL) + continue; + + /* ??? 0 is passed for `pc'. */ + insert_errmsg = CGEN_INSERT_FN (cd, insn) (cd, insn, fields, buf, + (bfd_vma) 0); + if (insert_errmsg != NULL) + continue; + + /* It is up to the caller to actually output the insn and any + queued relocs. */ + return insn; + } + + { + static char errbuf[150]; + const char *tmp_errmsg; +#ifdef CGEN_VERBOSE_ASSEMBLER_ERRORS +#define be_verbose 1 +#else +#define be_verbose 0 +#endif + + if (be_verbose) + { + /* If requesting verbose error messages, use insert_errmsg. + Failing that, use parse_errmsg. */ + tmp_errmsg = (insert_errmsg ? insert_errmsg : + parse_errmsg ? parse_errmsg : + recognized_mnemonic ? + _("unrecognized form of instruction") : + _("unrecognized instruction")); + + if (strlen (start) > 50) + /* xgettext:c-format */ + sprintf (errbuf, "%s `%.50s...'", tmp_errmsg, start); + else + /* xgettext:c-format */ + sprintf (errbuf, "%s `%.50s'", tmp_errmsg, start); + } + else + { + if (strlen (start) > 50) + /* xgettext:c-format */ + sprintf (errbuf, _("bad instruction `%.50s...'"), start); + else + /* xgettext:c-format */ + sprintf (errbuf, _("bad instruction `%.50s'"), start); + } + + *errmsg = errbuf; + return NULL; + } +} diff --git a/opcodes/epiphany-desc.c b/opcodes/epiphany-desc.c new file mode 100644 index 00000000000..271f8a78a74 --- /dev/null +++ b/opcodes/epiphany-desc.c @@ -0,0 +1,2271 @@ +/* CPU data for epiphany. + +THIS FILE IS MACHINE GENERATED WITH CGEN. + +Copyright 1996-2010 Free Software Foundation, Inc. + +This file is part of the GNU Binutils and/or GDB, the GNU debugger. + + This file is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + It is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License along + with this program; if not, write to the Free Software Foundation, Inc., + 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. + +*/ + +#include "sysdep.h" +#include <stdio.h> +#include <stdarg.h> +#include "ansidecl.h" +#include "bfd.h" +#include "symcat.h" +#include "epiphany-desc.h" +#include "epiphany-opc.h" +#include "opintl.h" +#include "libiberty.h" +#include "xregex.h" + +/* Attributes. */ + +static const CGEN_ATTR_ENTRY bool_attr[] = +{ + { "#f", 0 }, + { "#t", 1 }, + { 0, 0 } +}; + +static const CGEN_ATTR_ENTRY MACH_attr[] ATTRIBUTE_UNUSED = +{ + { "base", MACH_BASE }, + { "epiphany32", MACH_EPIPHANY32 }, + { "max", MACH_MAX }, + { 0, 0 } +}; + +static const CGEN_ATTR_ENTRY ISA_attr[] ATTRIBUTE_UNUSED = +{ + { "epiphany", ISA_EPIPHANY }, + { "max", ISA_MAX }, + { 0, 0 } +}; + +const CGEN_ATTR_TABLE epiphany_cgen_ifield_attr_table[] = +{ + { "MACH", & MACH_attr[0], & MACH_attr[0] }, + { "VIRTUAL", &bool_attr[0], &bool_attr[0] }, + { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] }, + { "ABS-ADDR", &bool_attr[0], &bool_attr[0] }, + { "RESERVED", &bool_attr[0], &bool_attr[0] }, + { "SIGN-OPT", &bool_attr[0], &bool_attr[0] }, + { "SIGNED", &bool_attr[0], &bool_attr[0] }, + { "RELOC", &bool_attr[0], &bool_attr[0] }, + { 0, 0, 0 } +}; + +const CGEN_ATTR_TABLE epiphany_cgen_hardware_attr_table[] = +{ + { "MACH", & MACH_attr[0], & MACH_attr[0] }, + { "VIRTUAL", &bool_attr[0], &bool_attr[0] }, + { "CACHE-ADDR", &bool_attr[0], &bool_attr[0] }, + { "PC", &bool_attr[0], &bool_attr[0] }, + { "PROFILE", &bool_attr[0], &bool_attr[0] }, + { 0, 0, 0 } +}; + +const CGEN_ATTR_TABLE epiphany_cgen_operand_attr_table[] = +{ + { "MACH", & MACH_attr[0], & MACH_attr[0] }, + { "VIRTUAL", &bool_attr[0], &bool_attr[0] }, + { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] }, + { "ABS-ADDR", &bool_attr[0], &bool_attr[0] }, + { "SIGN-OPT", &bool_attr[0], &bool_attr[0] }, + { "SIGNED", &bool_attr[0], &bool_attr[0] }, + { "NEGATIVE", &bool_attr[0], &bool_attr[0] }, + { "RELAX", &bool_attr[0], &bool_attr[0] }, + { "SEM-ONLY", &bool_attr[0], &bool_attr[0] }, + { "RELOC", &bool_attr[0], &bool_attr[0] }, + { 0, 0, 0 } +}; + +const CGEN_ATTR_TABLE epiphany_cgen_insn_attr_table[] = +{ + { "MACH", & MACH_attr[0], & MACH_attr[0] }, + { "ALIAS", &bool_attr[0], &bool_attr[0] }, + { "VIRTUAL", &bool_attr[0], &bool_attr[0] }, + { "UNCOND-CTI", &bool_attr[0], &bool_attr[0] }, + { "COND-CTI", &bool_attr[0], &bool_attr[0] }, + { "SKIP-CTI", &bool_attr[0], &bool_attr[0] }, + { "DELAY-SLOT", &bool_attr[0], &bool_attr[0] }, + { "RELAXABLE", &bool_attr[0], &bool_attr[0] }, + { "RELAXED", &bool_attr[0], &bool_attr[0] }, + { "NO-DIS", &bool_attr[0], &bool_attr[0] }, + { "PBB", &bool_attr[0], &bool_attr[0] }, + { "SHORT-INSN", &bool_attr[0], &bool_attr[0] }, + { "IMM3", &bool_attr[0], &bool_attr[0] }, + { "IMM8", &bool_attr[0], &bool_attr[0] }, + { 0, 0, 0 } +}; + +/* Instruction set variants. */ + +static const CGEN_ISA epiphany_cgen_isa_table[] = { + { "epiphany", 32, 32, 16, 32 }, + { 0, 0, 0, 0, 0 } +}; + +/* Machine variants. */ + +static const CGEN_MACH epiphany_cgen_mach_table[] = { + { "epiphany32", "epiphany32", MACH_EPIPHANY32, 0 }, + { 0, 0, 0, 0 } +}; + +static CGEN_KEYWORD_ENTRY epiphany_cgen_opval_gr_names_entries[] = +{ + { "sb", 9, {0, {{{0, 0}}}}, 0, 0 }, + { "sl", 10, {0, {{{0, 0}}}}, 0, 0 }, + { "fp", 11, {0, {{{0, 0}}}}, 0, 0 }, + { "ip", 12, {0, {{{0, 0}}}}, 0, 0 }, + { "sp", 13, {0, {{{0, 0}}}}, 0, 0 }, + { "lr", 14, {0, {{{0, 0}}}}, 0, 0 }, + { "r0", 0, {0, {{{0, 0}}}}, 0, 0 }, + { "r1", 1, {0, {{{0, 0}}}}, 0, 0 }, + { "r2", 2, {0, {{{0, 0}}}}, 0, 0 }, + { "r3", 3, {0, {{{0, 0}}}}, 0, 0 }, + { "r4", 4, {0, {{{0, 0}}}}, 0, 0 }, + { "r5", 5, {0, {{{0, 0}}}}, 0, 0 }, + { "r6", 6, {0, {{{0, 0}}}}, 0, 0 }, + { "r7", 7, {0, {{{0, 0}}}}, 0, 0 }, + { "r8", 8, {0, {{{0, 0}}}}, 0, 0 }, + { "r9", 9, {0, {{{0, 0}}}}, 0, 0 }, + { "r10", 10, {0, {{{0, 0}}}}, 0, 0 }, + { "r11", 11, {0, {{{0, 0}}}}, 0, 0 }, + { "r12", 12, {0, {{{0, 0}}}}, 0, 0 }, + { "r13", 13, {0, {{{0, 0}}}}, 0, 0 }, + { "r14", 14, {0, {{{0, 0}}}}, 0, 0 }, + { "r15", 15, {0, {{{0, 0}}}}, 0, 0 }, + { "r16", 16, {0, {{{0, 0}}}}, 0, 0 }, + { "r17", 17, {0, {{{0, 0}}}}, 0, 0 }, + { "r18", 18, {0, {{{0, 0}}}}, 0, 0 }, + { "r19", 19, {0, {{{0, 0}}}}, 0, 0 }, + { "r20", 20, {0, {{{0, 0}}}}, 0, 0 }, + { "r21", 21, {0, {{{0, 0}}}}, 0, 0 }, + { "r22", 22, {0, {{{0, 0}}}}, 0, 0 }, + { "r23", 23, {0, {{{0, 0}}}}, 0, 0 }, + { "r24", 24, {0, {{{0, 0}}}}, 0, 0 }, + { "r25", 25, {0, {{{0, 0}}}}, 0, 0 }, + { "r26", 26, {0, {{{0, 0}}}}, 0, 0 }, + { "r27", 27, {0, {{{0, 0}}}}, 0, 0 }, + { "r28", 28, {0, {{{0, 0}}}}, 0, 0 }, + { "r29", 29, {0, {{{0, 0}}}}, 0, 0 }, + { "r30", 30, {0, {{{0, 0}}}}, 0, 0 }, + { "r31", 31, {0, {{{0, 0}}}}, 0, 0 }, + { "r32", 32, {0, {{{0, 0}}}}, 0, 0 }, + { "r33", 33, {0, {{{0, 0}}}}, 0, 0 }, + { "r34", 34, {0, {{{0, 0}}}}, 0, 0 }, + { "r35", 35, {0, {{{0, 0}}}}, 0, 0 }, + { "r36", 36, {0, {{{0, 0}}}}, 0, 0 }, + { "r37", 37, {0, {{{0, 0}}}}, 0, 0 }, + { "r38", 38, {0, {{{0, 0}}}}, 0, 0 }, + { "r39", 39, {0, {{{0, 0}}}}, 0, 0 }, + { "r40", 40, {0, {{{0, 0}}}}, 0, 0 }, + { "r41", 41, {0, {{{0, 0}}}}, 0, 0 }, + { "r42", 42, {0, {{{0, 0}}}}, 0, 0 }, + { "r43", 43, {0, {{{0, 0}}}}, 0, 0 }, + { "r44", 44, {0, {{{0, 0}}}}, 0, 0 }, + { "r45", 45, {0, {{{0, 0}}}}, 0, 0 }, + { "r46", 46, {0, {{{0, 0}}}}, 0, 0 }, + { "r47", 47, {0, {{{0, 0}}}}, 0, 0 }, + { "r48", 48, {0, {{{0, 0}}}}, 0, 0 }, + { "r49", 49, {0, {{{0, 0}}}}, 0, 0 }, + { "r50", 50, {0, {{{0, 0}}}}, 0, 0 }, + { "r51", 51, {0, {{{0, 0}}}}, 0, 0 }, + { "r52", 52, {0, {{{0, 0}}}}, 0, 0 }, + { "r53", 53, {0, {{{0, 0}}}}, 0, 0 }, + { "r54", 54, {0, {{{0, 0}}}}, 0, 0 }, + { "r55", 55, {0, {{{0, 0}}}}, 0, 0 }, + { "r56", 56, {0, {{{0, 0}}}}, 0, 0 }, + { "r57", 57, {0, {{{0, 0}}}}, 0, 0 }, + { "r58", 58, {0, {{{0, 0}}}}, 0, 0 }, + { "r59", 59, {0, {{{0, 0}}}}, 0, 0 }, + { "r60", 60, {0, {{{0, 0}}}}, 0, 0 }, + { "r61", 61, {0, {{{0, 0}}}}, 0, 0 }, + { "r62", 62, {0, {{{0, 0}}}}, 0, 0 }, + { "r63", 63, {0, {{{0, 0}}}}, 0, 0 }, + { "a1", 0, {0, {{{0, 0}}}}, 0, 0 }, + { "a2", 1, {0, {{{0, 0}}}}, 0, 0 }, + { "a3", 2, {0, {{{0, 0}}}}, 0, 0 }, + { "a4", 3, {0, {{{0, 0}}}}, 0, 0 }, + { "v1", 4, {0, {{{0, 0}}}}, 0, 0 }, + { "v2", 5, {0, {{{0, 0}}}}, 0, 0 }, + { "v3", 6, {0, {{{0, 0}}}}, 0, 0 }, + { "v4", 7, {0, {{{0, 0}}}}, 0, 0 }, + { "v5", 8, {0, {{{0, 0}}}}, 0, 0 }, + { "v6", 9, {0, {{{0, 0}}}}, 0, 0 }, + { "v7", 10, {0, {{{0, 0}}}}, 0, 0 }, + { "v8", 11, {0, {{{0, 0}}}}, 0, 0 } +}; + +CGEN_KEYWORD epiphany_cgen_opval_gr_names = +{ + & epiphany_cgen_opval_gr_names_entries[0], + 82, + 0, 0, 0, 0, "" +}; + +static CGEN_KEYWORD_ENTRY epiphany_cgen_opval_cr_names_entries[] = +{ + { "config", 0, {0, {{{0, 0}}}}, 0, 0 }, + { "status", 1, {0, {{{0, 0}}}}, 0, 0 }, + { "pc", 2, {0, {{{0, 0}}}}, 0, 0 }, + { "debug", 3, {0, {{{0, 0}}}}, 0, 0 }, + { "iab", 4, {0, {{{0, 0}}}}, 0, 0 }, + { "lc", 5, {0, {{{0, 0}}}}, 0, 0 }, + { "ls", 6, {0, {{{0, 0}}}}, 0, 0 }, + { "le", 7, {0, {{{0, 0}}}}, 0, 0 }, + { "iret", 8, {0, {{{0, 0}}}}, 0, 0 }, + { "imask", 9, {0, {{{0, 0}}}}, 0, 0 }, + { "ilat", 10, {0, {{{0, 0}}}}, 0, 0 }, + { "ilatst", 11, {0, {{{0, 0}}}}, 0, 0 }, + { "ilatcl", 12, {0, {{{0, 0}}}}, 0, 0 }, + { "ipend", 13, {0, {{{0, 0}}}}, 0, 0 }, + { "ctimer0", 14, {0, {{{0, 0}}}}, 0, 0 }, + { "ctimer1", 15, {0, {{{0, 0}}}}, 0, 0 }, + { "hstatus", 16, {0, {{{0, 0}}}}, 0, 0 } +}; + +CGEN_KEYWORD epiphany_cgen_opval_cr_names = +{ + & epiphany_cgen_opval_cr_names_entries[0], + 17, + 0, 0, 0, 0, "" +}; + +static CGEN_KEYWORD_ENTRY epiphany_cgen_opval_crdma_names_entries[] = +{ + { "dma0config", 0, {0, {{{0, 0}}}}, 0, 0 }, + { "dma0stride", 1, {0, {{{0, 0}}}}, 0, 0 }, + { "dma0count", 2, {0, {{{0, 0}}}}, 0, 0 }, + { "dma0srcaddr", 3, {0, {{{0, 0}}}}, 0, 0 }, + { "dma0dstaddr", 4, {0, {{{0, 0}}}}, 0, 0 }, + { "dma0auto0", 5, {0, {{{0, 0}}}}, 0, 0 }, + { "dma0auto1", 6, {0, {{{0, 0}}}}, 0, 0 }, + { "dma0status", 7, {0, {{{0, 0}}}}, 0, 0 }, + { "dma1config", 8, {0, {{{0, 0}}}}, 0, 0 }, + { "dma1stride", 9, {0, {{{0, 0}}}}, 0, 0 }, + { "dma1count", 10, {0, {{{0, 0}}}}, 0, 0 }, + { "dma1srcaddr", 11, {0, {{{0, 0}}}}, 0, 0 }, + { "dma1dstaddr", 12, {0, {{{0, 0}}}}, 0, 0 }, + { "dma1auto0", 13, {0, {{{0, 0}}}}, 0, 0 }, + { "dma1auto1", 14, {0, {{{0, 0}}}}, 0, 0 }, + { "dma1status", 15, {0, {{{0, 0}}}}, 0, 0 } +}; + +CGEN_KEYWORD epiphany_cgen_opval_crdma_names = +{ + & epiphany_cgen_opval_crdma_names_entries[0], + 16, + 0, 0, 0, 0, "" +}; + +static CGEN_KEYWORD_ENTRY epiphany_cgen_opval_crmem_names_entries[] = +{ + { "memconfig", 0, {0, {{{0, 0}}}}, 0, 0 }, + { "memstatus", 1, {0, {{{0, 0}}}}, 0, 0 }, + { "memprotect", 2, {0, {{{0, 0}}}}, 0, 0 }, + { "memreserve", 3, {0, {{{0, 0}}}}, 0, 0 } +}; + +CGEN_KEYWORD epiphany_cgen_opval_crmem_names = +{ + & epiphany_cgen_opval_crmem_names_entries[0], + 4, + 0, 0, 0, 0, "" +}; + +static CGEN_KEYWORD_ENTRY epiphany_cgen_opval_crmesh_names_entries[] = +{ + { "meshconfig", 0, {0, {{{0, 0}}}}, 0, 0 }, + { "coreid", 1, {0, {{{0, 0}}}}, 0, 0 }, + { "meshmulticast", 2, {0, {{{0, 0}}}}, 0, 0 }, + { "swreset", 3, {0, {{{0, 0}}}}, 0, 0 } +}; + +CGEN_KEYWORD epiphany_cgen_opval_crmesh_names = +{ + & epiphany_cgen_opval_crmesh_names_entries[0], + 4, + 0, 0, 0, 0, "" +}; + + +/* The hardware table. */ + +#define A(a) (1 << CGEN_HW_##a) + +const CGEN_HW_ENTRY epiphany_cgen_hw_table[] = +{ + { "h-memory", HW_H_MEMORY, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { "h-sint", HW_H_SINT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { "h-uint", HW_H_UINT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { "h-addr", HW_H_ADDR, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { "h-iaddr", HW_H_IADDR, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { "h-registers", HW_H_REGISTERS, CGEN_ASM_KEYWORD, (PTR) & epiphany_cgen_opval_gr_names, { 0|A(CACHE_ADDR)|A(PROFILE), { { { (1<<MACH_BASE), 0 } } } } }, + { "h-fpregisters", HW_H_FPREGISTERS, CGEN_ASM_KEYWORD, (PTR) & epiphany_cgen_opval_gr_names, { 0|A(VIRTUAL)|A(PROFILE), { { { (1<<MACH_BASE), 0 } } } } }, + { "h-zbit", HW_H_ZBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { "h-nbit", HW_H_NBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { "h-cbit", HW_H_CBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { "h-vbit", HW_H_VBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { "h-vsbit", HW_H_VSBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { "h-bzbit", HW_H_BZBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { "h-bnbit", HW_H_BNBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { "h-bvbit", HW_H_BVBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { "h-bubit", HW_H_BUBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { "h-bibit", HW_H_BIBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { "h-bcbit", HW_H_BCBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { "h-bvsbit", HW_H_BVSBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { "h-bisbit", HW_H_BISBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { "h-busbit", HW_H_BUSBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { "h-expcause0bit", HW_H_EXPCAUSE0BIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { "h-expcause1bit", HW_H_EXPCAUSE1BIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { "h-expcause2bit", HW_H_EXPCAUSE2BIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { "h-extFstallbit", HW_H_EXTFSTALLBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { "h-trmbit", HW_H_TRMBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { "h-invExcEnbit", HW_H_INVEXCENBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { "h-ovfExcEnbit", HW_H_OVFEXCENBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { "h-unExcEnbit", HW_H_UNEXCENBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { "h-timer0bit0", HW_H_TIMER0BIT0, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { "h-timer0bit1", HW_H_TIMER0BIT1, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { "h-timer0bit2", HW_H_TIMER0BIT2, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { "h-timer0bit3", HW_H_TIMER0BIT3, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { "h-timer1bit0", HW_H_TIMER1BIT0, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { "h-timer1bit1", HW_H_TIMER1BIT1, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { "h-timer1bit2", HW_H_TIMER1BIT2, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { "h-timer1bit3", HW_H_TIMER1BIT3, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { "h-mbkptEnbit", HW_H_MBKPTENBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { "h-clockGateEnbit", HW_H_CLOCKGATEENBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { "h-coreCfgResBit12", HW_H_CORECFGRESBIT12, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { "h-coreCfgResBit13", HW_H_CORECFGRESBIT13, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { "h-coreCfgResBit14", HW_H_CORECFGRESBIT14, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { "h-coreCfgResBit15", HW_H_CORECFGRESBIT15, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { "h-coreCfgResBit16", HW_H_CORECFGRESBIT16, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { "h-coreCfgResBit20", HW_H_CORECFGRESBIT20, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { "h-coreCfgResBit21", HW_H_CORECFGRESBIT21, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { "h-coreCfgResBit24", HW_H_CORECFGRESBIT24, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { "h-coreCfgResBit25", HW_H_CORECFGRESBIT25, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { "h-coreCfgResBit26", HW_H_CORECFGRESBIT26, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { "h-coreCfgResBit27", HW_H_CORECFGRESBIT27, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { "h-coreCfgResBit28", HW_H_CORECFGRESBIT28, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { "h-coreCfgResBit29", HW_H_CORECFGRESBIT29, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { "h-coreCfgResBit30", HW_H_CORECFGRESBIT30, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { "h-coreCfgResBit31", HW_H_CORECFGRESBIT31, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { "h-arithmetic-modebit0", HW_H_ARITHMETIC_MODEBIT0, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { "h-arithmetic-modebit1", HW_H_ARITHMETIC_MODEBIT1, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { "h-arithmetic-modebit2", HW_H_ARITHMETIC_MODEBIT2, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { "h-gidisablebit", HW_H_GIDISABLEBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { "h-kmbit", HW_H_KMBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { "h-caibit", HW_H_CAIBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { "h-sflagbit", HW_H_SFLAGBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { "h-pc", HW_H_PC, CGEN_ASM_NONE, 0, { 0|A(PROFILE)|A(PC), { { { (1<<MACH_BASE), 0 } } } } }, + { "h-memaddr", HW_H_MEMADDR, CGEN_ASM_NONE, 0, { 0|A(PROFILE), { { { (1<<MACH_BASE), 0 } } } } }, + { "h-core-registers", HW_H_CORE_REGISTERS, CGEN_ASM_KEYWORD, (PTR) & epiphany_cgen_opval_cr_names, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { "h-coredma-registers", HW_H_COREDMA_REGISTERS, CGEN_ASM_KEYWORD, (PTR) & epiphany_cgen_opval_crdma_names, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { "h-coremem-registers", HW_H_COREMEM_REGISTERS, CGEN_ASM_KEYWORD, (PTR) & epiphany_cgen_opval_crmem_names, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { "h-coremesh-registers", HW_H_COREMESH_REGISTERS, CGEN_ASM_KEYWORD, (PTR) & epiphany_cgen_opval_crmesh_names, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { 0, 0, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } } +}; + +#undef A + + +/* The instruction field table. */ + +#define A(a) (1 << CGEN_IFLD_##a) + +const CGEN_IFLD epiphany_cgen_ifld_table[] = +{ + { EPIPHANY_F_NIL, "f-nil", 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { EPIPHANY_F_ANYOF, "f-anyof", 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { EPIPHANY_F_OPC, "f-opc", 0, 32, 3, 4, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { EPIPHANY_F_OPC_4_1, "f-opc-4-1", 0, 32, 4, 1, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { EPIPHANY_F_OPC_6_3, "f-opc-6-3", 0, 32, 6, 3, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { EPIPHANY_F_OPC_8_5, "f-opc-8-5", 0, 32, 8, 5, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { EPIPHANY_F_OPC_19_4, "f-opc-19-4", 0, 32, 19, 4, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { EPIPHANY_F_CONDCODE, "f-condcode", 0, 32, 7, 4, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { EPIPHANY_F_SECONDARY_CCS, "f-secondary-ccs", 0, 32, 7, 1, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { EPIPHANY_F_SHIFT, "f-shift", 0, 32, 9, 5, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { EPIPHANY_F_WORDSIZE, "f-wordsize", 0, 32, 6, 2, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { EPIPHANY_F_STORE, "f-store", 0, 32, 4, 1, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { EPIPHANY_F_OPC_8_1, "f-opc-8-1", 0, 32, 8, 1, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { EPIPHANY_F_OPC_31_32, "f-opc-31-32", 0, 32, 31, 32, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { EPIPHANY_F_SIMM8, "f-simm8", 0, 32, 15, 8, { 0|A(RELOC)|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } } }, + { EPIPHANY_F_SIMM24, "f-simm24", 0, 32, 31, 24, { 0|A(RELOC)|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } } }, + { EPIPHANY_F_SDISP3, "f-sdisp3", 0, 32, 9, 3, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { EPIPHANY_F_DISP3, "f-disp3", 0, 32, 9, 3, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { EPIPHANY_F_DISP8, "f-disp8", 0, 32, 23, 8, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { EPIPHANY_F_IMM8, "f-imm8", 0, 32, 12, 8, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { EPIPHANY_F_IMM_27_8, "f-imm-27-8", 0, 32, 27, 8, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { EPIPHANY_F_ADDSUBX, "f-addsubx", 0, 32, 20, 1, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { EPIPHANY_F_SUBD, "f-subd", 0, 32, 24, 1, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { EPIPHANY_F_PM, "f-pm", 0, 32, 25, 1, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { EPIPHANY_F_RM, "f-rm", 0, 32, 9, 3, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { EPIPHANY_F_RN, "f-rn", 0, 32, 12, 3, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { EPIPHANY_F_RD, "f-rd", 0, 32, 15, 3, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { EPIPHANY_F_RM_X, "f-rm-x", 0, 32, 25, 3, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { EPIPHANY_F_RN_X, "f-rn-x", 0, 32, 28, 3, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { EPIPHANY_F_RD_X, "f-rd-x", 0, 32, 31, 3, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { EPIPHANY_F_DC_9_1, "f-dc-9-1", 0, 32, 9, 1, { 0|A(RESERVED), { { { (1<<MACH_BASE), 0 } } } } }, + { EPIPHANY_F_SN, "f-sn", 0, 32, 12, 3, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { EPIPHANY_F_SD, "f-sd", 0, 32, 15, 3, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { EPIPHANY_F_SN_X, "f-sn-x", 0, 32, 28, 3, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { EPIPHANY_F_SD_X, "f-sd-x", 0, 32, 31, 3, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { EPIPHANY_F_DC_7_4, "f-dc-7-4", 0, 32, 7, 4, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { EPIPHANY_F_TRAP_SWI_9_1, "f-trap-swi-9-1", 0, 32, 9, 1, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { EPIPHANY_F_GIEN_GIDIS_9_1, "f-gien-gidis-9-1", 0, 32, 9, 1, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { EPIPHANY_F_DC_15_3, "f-dc-15-3", 0, 32, 15, 3, { 0|A(RESERVED), { { { (1<<MACH_BASE), 0 } } } } }, + { EPIPHANY_F_DC_15_7, "f-dc-15-7", 0, 32, 15, 7, { 0|A(RESERVED), { { { (1<<MACH_BASE), 0 } } } } }, + { EPIPHANY_F_DC_15_6, "f-dc-15-6", 0, 32, 15, 6, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { EPIPHANY_F_TRAP_NUM, "f-trap-num", 0, 32, 15, 6, { 0, { { { (1<<MACH_BASE), 0 } } } } }, + { EPIPHANY_F_DC_20_1, "f-dc-20-1", 0, 32, 20, 1, { 0|A(RESERVED), { { { (1<<MACH_BASE), 0 } } } } }, + { EPIPHANY_F_DC_21_1, "f-dc-21-1", 0, 32, 21, 1, { 0|A(RESERVED), { { { (1<<MACH_BASE), 0 } } } } }, + { EPIPHANY_F_DC_21_2, "f-dc-21-2", 0, 32, 21, 2, { 0|A(RESERVED), { { { (1<<MACH_BASE), 0 } } } } }, + { EPIPHANY_F_DC_22_3, "f-dc-22-3", 0, 32, 22, 3, { 0|A(RESERVED), { { { (1<<MACH_BASE), 0 } } } } }, + { EPIPHANY_F_DC_22_2, "f-dc-22-2", 0, 32, 22, 2, { 0|A(RESERVED), { { { (1<<MACH_BASE), 0 } } } } }, + { EPIPHANY_F_DC_22_1, "f-dc-22-1", 0, 32, 22, 1, { 0|A(RESERVED), { { { (1<<MACH_BASE), 0 } } } } }, + { EPIPHANY_F_DC_25_6, "f-dc-25-6", 0, 32, 25, 6, { 0|A(RESERVED), { { { (1<<MACH_BASE), 0 } } } } }, + { EPIPHANY_F_DC_25_4, "f-dc-25-4", 0, 32, 25, 4, { 0|A(RESERVED), { { { (1<<MACH_BASE), 0 } } } } }, + { EPIPHANY_F_DC_25_2, "f-dc-25-2", 0, 32, 25, 2, { 0|A(RESERVED), { { { (1<<MACH_BASE), 0 } } } } }, + { EPIPHANY_F_DC_25_1, "f-dc-25-1", 0, 32, 25, 1, { 0|A(RESERVED), { { { (1<<MACH_BASE), 0 } } } } }, + { EPIPHANY_F_DC_28_1, "f-dc-28-1", 0, 32, 28, 1, { 0|A(RESERVED), { { { (1<<MACH_BASE), 0 } } } } }, + { EPIPHANY_F_DC_31_3, "f-dc-31-3", 0, 32, 31, 3, { 0|A(RESERVED), { { { (1<<MACH_BASE), 0 } } } } }, + { EPIPHANY_F_DISP11, "f-disp11", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } }, + { EPIPHANY_F_SDISP11, "f-sdisp11", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } }, + { EPIPHANY_F_IMM16, "f-imm16", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } }, + { EPIPHANY_F_RD6, "f-rd6", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } }, + { EPIPHANY_F_RN6, "f-rn6", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } }, + { EPIPHANY_F_RM6, "f-rm6", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } }, + { EPIPHANY_F_SD6, "f-sd6", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } }, + { EPIPHANY_F_SN6, "f-sn6", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } }, + { 0, 0, 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } } +}; + +#undef A + + + +/* multi ifield declarations */ + +const CGEN_MAYBE_MULTI_IFLD EPIPHANY_F_DISP11_MULTI_IFIELD []; +const CGEN_MAYBE_MULTI_IFLD EPIPHANY_F_SDISP11_MULTI_IFIELD []; +const CGEN_MAYBE_MULTI_IFLD EPIPHANY_F_IMM16_MULTI_IFIELD []; +const CGEN_MAYBE_MULTI_IFLD EPIPHANY_F_RD6_MULTI_IFIELD []; +const CGEN_MAYBE_MULTI_IFLD EPIPHANY_F_RN6_MULTI_IFIELD []; +const CGEN_MAYBE_MULTI_IFLD EPIPHANY_F_RM6_MULTI_IFIELD []; +const CGEN_MAYBE_MULTI_IFLD EPIPHANY_F_SD6_MULTI_IFIELD []; +const CGEN_MAYBE_MULTI_IFLD EPIPHANY_F_SN6_MULTI_IFIELD []; + + +/* multi ifield definitions */ + +const CGEN_MAYBE_MULTI_IFLD EPIPHANY_F_DISP11_MULTI_IFIELD [] = +{ + { 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_DISP3] } }, + { 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_DISP8] } }, + { 0, { (const PTR) 0 } } +}; +const CGEN_MAYBE_MULTI_IFLD EPIPHANY_F_SDISP11_MULTI_IFIELD [] = +{ + { 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_DISP3] } }, + { 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_DISP8] } }, + { 0, { (const PTR) 0 } } +}; +const CGEN_MAYBE_MULTI_IFLD EPIPHANY_F_IMM16_MULTI_IFIELD [] = +{ + { 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_IMM8] } }, + { 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_IMM_27_8] } }, + { 0, { (const PTR) 0 } } +}; +const CGEN_MAYBE_MULTI_IFLD EPIPHANY_F_RD6_MULTI_IFIELD [] = +{ + { 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_RD_X] } }, + { 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_RD] } }, + { 0, { (const PTR) 0 } } +}; +const CGEN_MAYBE_MULTI_IFLD EPIPHANY_F_RN6_MULTI_IFIELD [] = +{ + { 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_RN_X] } }, + { 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_RN] } }, + { 0, { (const PTR) 0 } } +}; +const CGEN_MAYBE_MULTI_IFLD EPIPHANY_F_RM6_MULTI_IFIELD [] = +{ + { 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_RM_X] } }, + { 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_RM] } }, + { 0, { (const PTR) 0 } } +}; +const CGEN_MAYBE_MULTI_IFLD EPIPHANY_F_SD6_MULTI_IFIELD [] = +{ + { 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_SD_X] } }, + { 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_SD] } }, + { 0, { (const PTR) 0 } } +}; +const CGEN_MAYBE_MULTI_IFLD EPIPHANY_F_SN6_MULTI_IFIELD [] = +{ + { 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_SN_X] } }, + { 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_SN] } }, + { 0, { (const PTR) 0 } } +}; + +/* The operand table. */ + +#define A(a) (1 << CGEN_OPERAND_##a) +#define OPERAND(op) EPIPHANY_OPERAND_##op + +const CGEN_OPERAND epiphany_cgen_operand_table[] = +{ +/* pc: program counter */ + { "pc", EPIPHANY_OPERAND_PC, HW_H_PC, 0, 0, + { 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_NIL] } }, + { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } }, +/* zbit: integer zero bit */ + { "zbit", EPIPHANY_OPERAND_ZBIT, HW_H_ZBIT, 0, 0, + { 0, { (const PTR) 0 } }, + { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } }, +/* nbit: integer neg bit */ + { "nbit", EPIPHANY_OPERAND_NBIT, HW_H_NBIT, 0, 0, + { 0, { (const PTR) 0 } }, + { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } }, +/* cbit: integer carry bit */ + { "cbit", EPIPHANY_OPERAND_CBIT, HW_H_CBIT, 0, 0, + { 0, { (const PTR) 0 } }, + { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } }, +/* vbit: integer overflow bit */ + { "vbit", EPIPHANY_OPERAND_VBIT, HW_H_VBIT, 0, 0, + { 0, { (const PTR) 0 } }, + { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } }, +/* bzbit: floating point zero bit */ + { "bzbit", EPIPHANY_OPERAND_BZBIT, HW_H_BZBIT, 0, 0, + { 0, { (const PTR) 0 } }, + { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } }, +/* bnbit: floating point neg bit */ + { "bnbit", EPIPHANY_OPERAND_BNBIT, HW_H_BNBIT, 0, 0, + { 0, { (const PTR) 0 } }, + { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } }, +/* bvbit: floating point ovfl bit */ + { "bvbit", EPIPHANY_OPERAND_BVBIT, HW_H_BVBIT, 0, 0, + { 0, { (const PTR) 0 } }, + { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } }, +/* bcbit: floating point carry bit */ + { "bcbit", EPIPHANY_OPERAND_BCBIT, HW_H_BCBIT, 0, 0, + { 0, { (const PTR) 0 } }, + { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } }, +/* bubit: floating point underfl bit */ + { "bubit", EPIPHANY_OPERAND_BUBIT, HW_H_BUBIT, 0, 0, + { 0, { (const PTR) 0 } }, + { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } }, +/* bibit: floating point invalid bit */ + { "bibit", EPIPHANY_OPERAND_BIBIT, HW_H_BIBIT, 0, 0, + { 0, { (const PTR) 0 } }, + { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } }, +/* vsbit: integer overflow sticky */ + { "vsbit", EPIPHANY_OPERAND_VSBIT, HW_H_VSBIT, 0, 0, + { 0, { (const PTR) 0 } }, + { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } }, +/* bvsbit: floating point overflow sticky */ + { "bvsbit", EPIPHANY_OPERAND_BVSBIT, HW_H_BVSBIT, 0, 0, + { 0, { (const PTR) 0 } }, + { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } }, +/* bisbit: floating point invalid sticky */ + { "bisbit", EPIPHANY_OPERAND_BISBIT, HW_H_BISBIT, 0, 0, + { 0, { (const PTR) 0 } }, + { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } }, +/* busbit: floating point underflow sticky */ + { "busbit", EPIPHANY_OPERAND_BUSBIT, HW_H_BUSBIT, 0, 0, + { 0, { (const PTR) 0 } }, + { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } }, +/* expcause0bit: exceprion cause bit0 */ + { "expcause0bit", EPIPHANY_OPERAND_EXPCAUSE0BIT, HW_H_EXPCAUSE0BIT, 0, 0, + { 0, { (const PTR) 0 } }, + { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } }, +/* expcause1bit: exceprion cause bit1 */ + { "expcause1bit", EPIPHANY_OPERAND_EXPCAUSE1BIT, HW_H_EXPCAUSE1BIT, 0, 0, + { 0, { (const PTR) 0 } }, + { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } }, +/* expcause2bit: external load stalled bit */ + { "expcause2bit", EPIPHANY_OPERAND_EXPCAUSE2BIT, HW_H_EXPCAUSE2BIT, 0, 0, + { 0, { (const PTR) 0 } }, + { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } }, +/* extFstallbit: external fetch stalled bit */ + { "extFstallbit", EPIPHANY_OPERAND_EXTFSTALLBIT, HW_H_EXTFSTALLBIT, 0, 0, + { 0, { (const PTR) 0 } }, + { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } }, +/* trmbit: 0=round to nearest, 1=trunacte selct bit */ + { "trmbit", EPIPHANY_OPERAND_TRMBIT, HW_H_TRMBIT, 0, 0, + { 0, { (const PTR) 0 } }, + { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } }, +/* invExcEnbit: invalid exception enable bit */ + { "invExcEnbit", EPIPHANY_OPERAND_INVEXCENBIT, HW_H_INVEXCENBIT, 0, 0, + { 0, { (const PTR) 0 } }, + { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } }, +/* ovfExcEnbit: overflow exception enable bit */ + { "ovfExcEnbit", EPIPHANY_OPERAND_OVFEXCENBIT, HW_H_OVFEXCENBIT, 0, 0, + { 0, { (const PTR) 0 } }, + { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } }, +/* unExcEnbit: underflow exception enable bit */ + { "unExcEnbit", EPIPHANY_OPERAND_UNEXCENBIT, HW_H_UNEXCENBIT, 0, 0, + { 0, { (const PTR) 0 } }, + { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } }, +/* timer0bit0: timer 0 mode selection 0 */ + { "timer0bit0", EPIPHANY_OPERAND_TIMER0BIT0, HW_H_TIMER0BIT0, 0, 0, + { 0, { (const PTR) 0 } }, + { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } }, +/* timer0bit1: timer 0 mode selection 1 */ + { "timer0bit1", EPIPHANY_OPERAND_TIMER0BIT1, HW_H_TIMER0BIT1, 0, 0, + { 0, { (const PTR) 0 } }, + { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } }, +/* timer0bit2: timer 0 mode selection 2 */ + { "timer0bit2", EPIPHANY_OPERAND_TIMER0BIT2, HW_H_TIMER0BIT2, 0, 0, + { 0, { (const PTR) 0 } }, + { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } }, +/* timer0bit3: timer 0 mode selection 3 */ + { "timer0bit3", EPIPHANY_OPERAND_TIMER0BIT3, HW_H_TIMER0BIT3, 0, 0, + { 0, { (const PTR) 0 } }, + { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } }, +/* timer1bit0: timer 1 mode selection 0 */ + { "timer1bit0", EPIPHANY_OPERAND_TIMER1BIT0, HW_H_TIMER1BIT0, 0, 0, + { 0, { (const PTR) 0 } }, + { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } }, +/* timer1bit1: timer 1 mode selection 1 */ + { "timer1bit1", EPIPHANY_OPERAND_TIMER1BIT1, HW_H_TIMER1BIT1, 0, 0, + { 0, { (const PTR) 0 } }, + { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } }, +/* timer1bit2: timer 1 mode selection 2 */ + { "timer1bit2", EPIPHANY_OPERAND_TIMER1BIT2, HW_H_TIMER1BIT2, 0, 0, + { 0, { (const PTR) 0 } }, + { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } }, +/* timer1bit3: timer 1 mode selection 3 */ + { "timer1bit3", EPIPHANY_OPERAND_TIMER1BIT3, HW_H_TIMER1BIT3, 0, 0, + { 0, { (const PTR) 0 } }, + { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } }, +/* mbkptEnbit: multicore bkpt enable */ + { "mbkptEnbit", EPIPHANY_OPERAND_MBKPTENBIT, HW_H_MBKPTENBIT, 0, 0, + { 0, { (const PTR) 0 } }, + { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } }, +/* clockGateEnbit: clock gate enable enable */ + { "clockGateEnbit", EPIPHANY_OPERAND_CLOCKGATEENBIT, HW_H_CLOCKGATEENBIT, 0, 0, + { 0, { (const PTR) 0 } }, + { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } }, +/* arithmetic-modebit0: arithmetic mode bit0 */ + { "arithmetic-modebit0", EPIPHANY_OPERAND_ARITHMETIC_MODEBIT0, HW_H_ARITHMETIC_MODEBIT0, 0, 0, + { 0, { (const PTR) 0 } }, + { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } }, +/* arithmetic-modebit1: arithmetic mode bit1 */ + { "arithmetic-modebit1", EPIPHANY_OPERAND_ARITHMETIC_MODEBIT1, HW_H_ARITHMETIC_MODEBIT1, 0, 0, + { 0, { (const PTR) 0 } }, + { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } }, +/* arithmetic-modebit2: arithmetic mode bit2 */ + { "arithmetic-modebit2", EPIPHANY_OPERAND_ARITHMETIC_MODEBIT2, HW_H_ARITHMETIC_MODEBIT2, 0, 0, + { 0, { (const PTR) 0 } }, + { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } }, +/* coreCfgResBit12: core config bit 12 */ + { "coreCfgResBit12", EPIPHANY_OPERAND_CORECFGRESBIT12, HW_H_CORECFGRESBIT12, 0, 0, + { 0, { (const PTR) 0 } }, + { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } }, +/* coreCfgResBit13: core config bit 13 */ + { "coreCfgResBit13", EPIPHANY_OPERAND_CORECFGRESBIT13, HW_H_CORECFGRESBIT13, 0, 0, + { 0, { (const PTR) 0 } }, + { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } }, +/* coreCfgResBit14: core config bit 14 */ + { "coreCfgResBit14", EPIPHANY_OPERAND_CORECFGRESBIT14, HW_H_CORECFGRESBIT14, 0, 0, + { 0, { (const PTR) 0 } }, + { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } }, +/* coreCfgResBit15: core config bit 15 */ + { "coreCfgResBit15", EPIPHANY_OPERAND_CORECFGRESBIT15, HW_H_CORECFGRESBIT15, 0, 0, + { 0, { (const PTR) 0 } }, + { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } }, +/* coreCfgResBit16: core config bit 16 */ + { "coreCfgResBit16", EPIPHANY_OPERAND_CORECFGRESBIT16, HW_H_CORECFGRESBIT16, 0, 0, + { 0, { (const PTR) 0 } }, + { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } }, +/* coreCfgResBit20: core config bit 20 */ + { "coreCfgResBit20", EPIPHANY_OPERAND_CORECFGRESBIT20, HW_H_CORECFGRESBIT20, 0, 0, + { 0, { (const PTR) 0 } }, + { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } }, +/* coreCfgResBit21: core config bit 21 */ + { "coreCfgResBit21", EPIPHANY_OPERAND_CORECFGRESBIT21, HW_H_CORECFGRESBIT21, 0, 0, + { 0, { (const PTR) 0 } }, + { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } }, +/* coreCfgResBit24: core config bit 24 */ + { "coreCfgResBit24", EPIPHANY_OPERAND_CORECFGRESBIT24, HW_H_CORECFGRESBIT24, 0, 0, + { 0, { (const PTR) 0 } }, + { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } }, +/* coreCfgResBit25: core config bit 25 */ + { "coreCfgResBit25", EPIPHANY_OPERAND_CORECFGRESBIT25, HW_H_CORECFGRESBIT25, 0, 0, + { 0, { (const PTR) 0 } }, + { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } }, +/* coreCfgResBit26: core config bit 26 */ + { "coreCfgResBit26", EPIPHANY_OPERAND_CORECFGRESBIT26, HW_H_CORECFGRESBIT26, 0, 0, + { 0, { (const PTR) 0 } }, + { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } }, +/* coreCfgResBit27: core config bit 27 */ + { "coreCfgResBit27", EPIPHANY_OPERAND_CORECFGRESBIT27, HW_H_CORECFGRESBIT27, 0, 0, + { 0, { (const PTR) 0 } }, + { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } }, +/* coreCfgResBit28: core config bit 28 */ + { "coreCfgResBit28", EPIPHANY_OPERAND_CORECFGRESBIT28, HW_H_CORECFGRESBIT28, 0, 0, + { 0, { (const PTR) 0 } }, + { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } }, +/* coreCfgResBit29: core config bit 29 */ + { "coreCfgResBit29", EPIPHANY_OPERAND_CORECFGRESBIT29, HW_H_CORECFGRESBIT29, 0, 0, + { 0, { (const PTR) 0 } }, + { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } }, +/* coreCfgResBit30: core config bit 30 */ + { "coreCfgResBit30", EPIPHANY_OPERAND_CORECFGRESBIT30, HW_H_CORECFGRESBIT30, 0, 0, + { 0, { (const PTR) 0 } }, + { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } }, +/* coreCfgResBit31: core config bit 31 */ + { "coreCfgResBit31", EPIPHANY_OPERAND_CORECFGRESBIT31, HW_H_CORECFGRESBIT31, 0, 0, + { 0, { (const PTR) 0 } }, + { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } }, +/* gidisablebit: global interrupt disable bit */ + { "gidisablebit", EPIPHANY_OPERAND_GIDISABLEBIT, HW_H_GIDISABLEBIT, 0, 0, + { 0, { (const PTR) 0 } }, + { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } }, +/* kmbit: kernel mode bit */ + { "kmbit", EPIPHANY_OPERAND_KMBIT, HW_H_KMBIT, 0, 0, + { 0, { (const PTR) 0 } }, + { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } }, +/* caibit: core actibe indicator bit */ + { "caibit", EPIPHANY_OPERAND_CAIBIT, HW_H_CAIBIT, 0, 0, + { 0, { (const PTR) 0 } }, + { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } }, +/* sflagbit: sflag bit */ + { "sflagbit", EPIPHANY_OPERAND_SFLAGBIT, HW_H_SFLAGBIT, 0, 0, + { 0, { (const PTR) 0 } }, + { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } }, +/* memaddr: memory effective address */ + { "memaddr", EPIPHANY_OPERAND_MEMADDR, HW_H_MEMADDR, 0, 0, + { 0, { (const PTR) 0 } }, + { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } }, +/* simm24: branch address pc-relative */ + { "simm24", EPIPHANY_OPERAND_SIMM24, HW_H_IADDR, 31, 24, + { 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_SIMM24] } }, + { 0|A(RELAX)|A(RELOC)|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } } }, +/* simm8: branch address pc-relative */ + { "simm8", EPIPHANY_OPERAND_SIMM8, HW_H_IADDR, 15, 8, + { 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_SIMM8] } }, + { 0|A(RELAX)|A(RELOC)|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } } }, +/* rd: destination register */ + { "rd", EPIPHANY_OPERAND_RD, HW_H_REGISTERS, 15, 3, + { 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_RD] } }, + { 0, { { { (1<<MACH_BASE), 0 } } } } }, +/* rn: source register */ + { "rn", EPIPHANY_OPERAND_RN, HW_H_REGISTERS, 12, 3, + { 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_RN] } }, + { 0, { { { (1<<MACH_BASE), 0 } } } } }, +/* rm: source register */ + { "rm", EPIPHANY_OPERAND_RM, HW_H_REGISTERS, 9, 3, + { 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_RM] } }, + { 0, { { { (1<<MACH_BASE), 0 } } } } }, +/* frd: fp destination register */ + { "frd", EPIPHANY_OPERAND_FRD, HW_H_FPREGISTERS, 15, 3, + { 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_RD] } }, + { 0, { { { (1<<MACH_BASE), 0 } } } } }, +/* frn: fp source register */ + { "frn", EPIPHANY_OPERAND_FRN, HW_H_FPREGISTERS, 12, 3, + { 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_RN] } }, + { 0, { { { (1<<MACH_BASE), 0 } } } } }, +/* frm: fp source register */ + { "frm", EPIPHANY_OPERAND_FRM, HW_H_FPREGISTERS, 9, 3, + { 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_RM] } }, + { 0, { { { (1<<MACH_BASE), 0 } } } } }, +/* rd6: destination register */ + { "rd6", EPIPHANY_OPERAND_RD6, HW_H_REGISTERS, 15, 6, + { 2, { (const PTR) &EPIPHANY_F_RD6_MULTI_IFIELD[0] } }, + { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } }, +/* rn6: source register */ + { "rn6", EPIPHANY_OPERAND_RN6, HW_H_REGISTERS, 12, 6, + { 2, { (const PTR) &EPIPHANY_F_RN6_MULTI_IFIELD[0] } }, + { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } }, +/* rm6: source register */ + { "rm6", EPIPHANY_OPERAND_RM6, HW_H_REGISTERS, 9, 6, + { 2, { (const PTR) &EPIPHANY_F_RM6_MULTI_IFIELD[0] } }, + { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } }, +/* frd6: fp destination register */ + { "frd6", EPIPHANY_OPERAND_FRD6, HW_H_FPREGISTERS, 15, 6, + { 2, { (const PTR) &EPIPHANY_F_RD6_MULTI_IFIELD[0] } }, + { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } }, +/* frn6: fp source register */ + { "frn6", EPIPHANY_OPERAND_FRN6, HW_H_FPREGISTERS, 12, 6, + { 2, { (const PTR) &EPIPHANY_F_RN6_MULTI_IFIELD[0] } }, + { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } }, +/* frm6: fp source register */ + { "frm6", EPIPHANY_OPERAND_FRM6, HW_H_FPREGISTERS, 9, 6, + { 2, { (const PTR) &EPIPHANY_F_RM6_MULTI_IFIELD[0] } }, + { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } }, +/* sd: special destination */ + { "sd", EPIPHANY_OPERAND_SD, HW_H_CORE_REGISTERS, 15, 3, + { 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_SD] } }, + { 0, { { { (1<<MACH_BASE), 0 } } } } }, +/* sn: special source */ + { "sn", EPIPHANY_OPERAND_SN, HW_H_CORE_REGISTERS, 12, 3, + { 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_SN] } }, + { 0, { { { (1<<MACH_BASE), 0 } } } } }, +/* sd6: special destination register */ + { "sd6", EPIPHANY_OPERAND_SD6, HW_H_CORE_REGISTERS, 15, 6, + { 2, { (const PTR) &EPIPHANY_F_SD6_MULTI_IFIELD[0] } }, + { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } }, +/* sn6: special source register */ + { "sn6", EPIPHANY_OPERAND_SN6, HW_H_CORE_REGISTERS, 12, 6, + { 2, { (const PTR) &EPIPHANY_F_SN6_MULTI_IFIELD[0] } }, + { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } }, +/* sddma: dma register */ + { "sddma", EPIPHANY_OPERAND_SDDMA, HW_H_COREDMA_REGISTERS, 15, 6, + { 2, { (const PTR) &EPIPHANY_F_SD6_MULTI_IFIELD[0] } }, + { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } }, +/* sndma: dma register */ + { "sndma", EPIPHANY_OPERAND_SNDMA, HW_H_COREDMA_REGISTERS, 12, 6, + { 2, { (const PTR) &EPIPHANY_F_SN6_MULTI_IFIELD[0] } }, + { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } }, +/* sdmem: mem register */ + { "sdmem", EPIPHANY_OPERAND_SDMEM, HW_H_COREMEM_REGISTERS, 15, 6, + { 2, { (const PTR) &EPIPHANY_F_SD6_MULTI_IFIELD[0] } }, + { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } }, +/* snmem: mem register */ + { "snmem", EPIPHANY_OPERAND_SNMEM, HW_H_COREMEM_REGISTERS, 12, 6, + { 2, { (const PTR) &EPIPHANY_F_SN6_MULTI_IFIELD[0] } }, + { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } }, +/* sdmesh: mesh register */ + { "sdmesh", EPIPHANY_OPERAND_SDMESH, HW_H_COREMESH_REGISTERS, 15, 6, + { 2, { (const PTR) &EPIPHANY_F_SD6_MULTI_IFIELD[0] } }, + { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } }, +/* snmesh: mesh register */ + { "snmesh", EPIPHANY_OPERAND_SNMESH, HW_H_COREMESH_REGISTERS, 12, 6, + { 2, { (const PTR) &EPIPHANY_F_SN6_MULTI_IFIELD[0] } }, + { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } }, +/* simm3: signed 3-bit literal */ + { "simm3", EPIPHANY_OPERAND_SIMM3, HW_H_SINT, 9, 3, + { 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_SDISP3] } }, + { 0|A(RELAX), { { { (1<<MACH_BASE), 0 } } } } }, +/* simm11: signed 11-bit literal */ + { "simm11", EPIPHANY_OPERAND_SIMM11, HW_H_SINT, 9, 11, + { 2, { (const PTR) &EPIPHANY_F_SDISP11_MULTI_IFIELD[0] } }, + { 0|A(RELAX)|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } }, +/* disp3: short data displacement */ + { "disp3", EPIPHANY_OPERAND_DISP3, HW_H_UINT, 9, 3, + { 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_DISP3] } }, + { 0, { { { (1<<MACH_BASE), 0 } } } } }, +/* trapnum6: parameter for swi or trap */ + { "trapnum6", EPIPHANY_OPERAND_TRAPNUM6, HW_H_UINT, 15, 6, + { 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_TRAP_NUM] } }, + { 0, { { { (1<<MACH_BASE), 0 } } } } }, +/* swi_num: unsigned 6-bit swi# */ + { "swi_num", EPIPHANY_OPERAND_SWI_NUM, HW_H_UINT, 15, 6, + { 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_TRAP_NUM] } }, + { 0, { { { (1<<MACH_BASE), 0 } } } } }, +/* disp11: sign-magnitude data displacement */ + { "disp11", EPIPHANY_OPERAND_DISP11, HW_H_UINT, 9, 11, + { 2, { (const PTR) &EPIPHANY_F_DISP11_MULTI_IFIELD[0] } }, + { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } }, +/* shift: immediate shift amount */ + { "shift", EPIPHANY_OPERAND_SHIFT, HW_H_UINT, 9, 5, + { 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_SHIFT] } }, + { 0, { { { (1<<MACH_BASE), 0 } } } } }, +/* imm16: 16-bit unsigned literal */ + { "imm16", EPIPHANY_OPERAND_IMM16, HW_H_ADDR, 12, 16, + { 2, { (const PTR) &EPIPHANY_F_IMM16_MULTI_IFIELD[0] } }, + { 0|A(RELAX)|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } }, +/* imm8: 8-bit unsigned literal */ + { "imm8", EPIPHANY_OPERAND_IMM8, HW_H_ADDR, 12, 8, + { 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_IMM8] } }, + { 0|A(RELAX), { { { (1<<MACH_BASE), 0 } } } } }, +/* direction: +/- indexing */ + { "direction", EPIPHANY_OPERAND_DIRECTION, HW_H_UINT, 20, 1, + { 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_ADDSUBX] } }, + { 0, { { { (1<<MACH_BASE), 0 } } } } }, +/* dpmi: +/- magnitude immediate displacement */ + { "dpmi", EPIPHANY_OPERAND_DPMI, HW_H_UINT, 24, 1, + { 0, { (const PTR) &epiphany_cgen_ifld_table[EPIPHANY_F_SUBD] } }, + { 0, { { { (1<<MACH_BASE), 0 } } } } }, +/* sentinel */ + { 0, 0, 0, 0, 0, + { 0, { (const PTR) 0 } }, + { 0, { { { (1<<MACH_BASE), 0 } } } } } +}; + +#undef A + + +/* The instruction table. */ + +#define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field)) +#define A(a) (1 << CGEN_INSN_##a) + +static const CGEN_IBASE epiphany_cgen_insn_table[MAX_INSNS] = +{ + /* Special null first entry. + A `num' value of zero is thus invalid. + Also, the special `invalid' insn resides here. */ + { 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, +/* beq.s $simm8 */ + { + EPIPHANY_INSN_BEQ16, "beq16", "beq.s", 16, + { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } } + }, +/* beq.l $simm24 */ + { + EPIPHANY_INSN_BEQ, "beq", "beq.l", 32, + { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } } + }, +/* bne.s $simm8 */ + { + EPIPHANY_INSN_BNE16, "bne16", "bne.s", 16, + { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } } + }, +/* bne.l $simm24 */ + { + EPIPHANY_INSN_BNE, "bne", "bne.l", 32, + { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } } + }, +/* bgtu.s $simm8 */ + { + EPIPHANY_INSN_BGTU16, "bgtu16", "bgtu.s", 16, + { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } } + }, +/* bgtu.l $simm24 */ + { + EPIPHANY_INSN_BGTU, "bgtu", "bgtu.l", 32, + { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } } + }, +/* bgteu.s $simm8 */ + { + EPIPHANY_INSN_BGTEU16, "bgteu16", "bgteu.s", 16, + { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } } + }, +/* bgteu.l $simm24 */ + { + EPIPHANY_INSN_BGTEU, "bgteu", "bgteu.l", 32, + { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } } + }, +/* blteu.s $simm8 */ + { + EPIPHANY_INSN_BLTEU16, "blteu16", "blteu.s", 16, + { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } } + }, +/* blteu.l $simm24 */ + { + EPIPHANY_INSN_BLTEU, "blteu", "blteu.l", 32, + { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } } + }, +/* bltu.s $simm8 */ + { + EPIPHANY_INSN_BLTU16, "bltu16", "bltu.s", 16, + { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } } + }, +/* bltu.l $simm24 */ + { + EPIPHANY_INSN_BLTU, "bltu", "bltu.l", 32, + { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } } + }, +/* bgt.s $simm8 */ + { + EPIPHANY_INSN_BGT16, "bgt16", "bgt.s", 16, + { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } } + }, +/* bgt.l $simm24 */ + { + EPIPHANY_INSN_BGT, "bgt", "bgt.l", 32, + { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } } + }, +/* bgte.s $simm8 */ + { + EPIPHANY_INSN_BGTE16, "bgte16", "bgte.s", 16, + { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } } + }, +/* bgte.l $simm24 */ + { + EPIPHANY_INSN_BGTE, "bgte", "bgte.l", 32, + { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } } + }, +/* blt.s $simm8 */ + { + EPIPHANY_INSN_BLT16, "blt16", "blt.s", 16, + { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } } + }, +/* blt.l $simm24 */ + { + EPIPHANY_INSN_BLT, "blt", "blt.l", 32, + { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } } + }, +/* blte.s $simm8 */ + { + EPIPHANY_INSN_BLTE16, "blte16", "blte.s", 16, + { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } } + }, +/* blte.l $simm24 */ + { + EPIPHANY_INSN_BLTE, "blte", "blte.l", 32, + { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } } + }, +/* bbeq.s $simm8 */ + { + EPIPHANY_INSN_BBEQ16, "bbeq16", "bbeq.s", 16, + { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } } + }, +/* bbeq.l $simm24 */ + { + EPIPHANY_INSN_BBEQ, "bbeq", "bbeq.l", 32, + { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } } + }, +/* bbne.s $simm8 */ + { + EPIPHANY_INSN_BBNE16, "bbne16", "bbne.s", 16, + { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } } + }, +/* bbne.l $simm24 */ + { + EPIPHANY_INSN_BBNE, "bbne", "bbne.l", 32, + { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } } + }, +/* bblt.s $simm8 */ + { + EPIPHANY_INSN_BBLT16, "bblt16", "bblt.s", 16, + { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } } + }, +/* bblt.l $simm24 */ + { + EPIPHANY_INSN_BBLT, "bblt", "bblt.l", 32, + { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } } + }, +/* bblte.s $simm8 */ + { + EPIPHANY_INSN_BBLTE16, "bblte16", "bblte.s", 16, + { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } } + }, +/* bblte.l $simm24 */ + { + EPIPHANY_INSN_BBLTE, "bblte", "bblte.l", 32, + { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } } + }, +/* b.s $simm8 */ + { + EPIPHANY_INSN_B16, "b16", "b.s", 16, + { 0|A(SHORT_INSN)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } } } } + }, +/* b.l $simm24 */ + { + EPIPHANY_INSN_B, "b", "b.l", 32, + { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } } } } + }, +/* bl.s $simm8 */ + { + EPIPHANY_INSN_BL16, "bl16", "bl.s", 16, + { 0|A(SHORT_INSN)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } } } } + }, +/* bl.l $simm24 */ + { + EPIPHANY_INSN_BL, "bl", "bl.l", 32, + { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } } } } + }, +/* jr $rn */ + { + EPIPHANY_INSN_JR16, "jr16", "jr", 16, + { 0|A(SHORT_INSN)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } } } } + }, +/* rts */ + { + -1, "rts", "rts", 32, + { 0|A(UNCOND_CTI)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } } + }, +/* jr $rn6 */ + { + EPIPHANY_INSN_JR, "jr", "jr", 32, + { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } } } } + }, +/* jalr $rn */ + { + EPIPHANY_INSN_JALR16, "jalr16", "jalr", 16, + { 0|A(SHORT_INSN)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } } } } + }, +/* jalr $rn6 */ + { + EPIPHANY_INSN_JALR, "jalr", "jalr", 32, + { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } } } } + }, +/* ldrb $rd,[$rn,$rm] */ + { + EPIPHANY_INSN_LDRBX16_S, "ldrbx16.s", "ldrb", 16, + { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } } + }, +/* ldrb $rd,[$rn],$rm */ + { + EPIPHANY_INSN_LDRBP16_S, "ldrbp16.s", "ldrb", 16, + { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } } + }, +/* ldrb $rd6,[$rn6,$direction$rm6] */ + { + EPIPHANY_INSN_LDRBX_L, "ldrbx.l", "ldrb", 32, + { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } } + }, +/* ldrb $rd6,[$rn6],$direction$rm6 */ + { + EPIPHANY_INSN_LDRBP_L, "ldrbp.l", "ldrb", 32, + { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } } + }, +/* ldrb $rd,[$rn,$disp3] */ + { + EPIPHANY_INSN_LDRBD16_S, "ldrbd16.s", "ldrb", 16, + { 0|A(IMM3)|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } } + }, +/* ldrb $rd6,[$rn6,$dpmi$disp11] */ + { + EPIPHANY_INSN_LDRBD_L, "ldrbd.l", "ldrb", 32, + { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } } + }, +/* ldrb $rd6,[$rn6],$dpmi$disp11 */ + { + EPIPHANY_INSN_LDRBDPM_L, "ldrbdpm.l", "ldrb", 32, + { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } } + }, +/* ldrh $rd,[$rn,$rm] */ + { + EPIPHANY_INSN_LDRHX16_S, "ldrhx16.s", "ldrh", 16, + { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } } + }, +/* ldrh $rd,[$rn],$rm */ + { + EPIPHANY_INSN_LDRHP16_S, "ldrhp16.s", "ldrh", 16, + { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } } + }, +/* ldrh $rd6,[$rn6,$direction$rm6] */ + { + EPIPHANY_INSN_LDRHX_L, "ldrhx.l", "ldrh", 32, + { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } } + }, +/* ldrh $rd6,[$rn6],$direction$rm6 */ + { + EPIPHANY_INSN_LDRHP_L, "ldrhp.l", "ldrh", 32, + { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } } + }, +/* ldrh $rd,[$rn,$disp3] */ + { + EPIPHANY_INSN_LDRHD16_S, "ldrhd16.s", "ldrh", 16, + { 0|A(IMM3)|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } } + }, +/* ldrh $rd6,[$rn6,$dpmi$disp11] */ + { + EPIPHANY_INSN_LDRHD_L, "ldrhd.l", "ldrh", 32, + { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } } + }, +/* ldrh $rd6,[$rn6],$dpmi$disp11 */ + { + EPIPHANY_INSN_LDRHDPM_L, "ldrhdpm.l", "ldrh", 32, + { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } } + }, +/* ldr $rd,[$rn,$rm] */ + { + EPIPHANY_INSN_LDRX16_S, "ldrx16.s", "ldr", 16, + { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } } + }, +/* ldr $rd,[$rn],$rm */ + { + EPIPHANY_INSN_LDRP16_S, "ldrp16.s", "ldr", 16, + { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } } + }, +/* ldr $rd6,[$rn6,$direction$rm6] */ + { + EPIPHANY_INSN_LDRX_L, "ldrx.l", "ldr", 32, + { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } } + }, +/* ldr $rd6,[$rn6],$direction$rm6 */ + { + EPIPHANY_INSN_LDRP_L, "ldrp.l", "ldr", 32, + { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } } + }, +/* ldr $rd,[$rn,$disp3] */ + { + EPIPHANY_INSN_LDRD16_S, "ldrd16.s", "ldr", 16, + { 0|A(IMM3)|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } } + }, +/* ldr $rd6,[$rn6,$dpmi$disp11] */ + { + EPIPHANY_INSN_LDRD_L, "ldrd.l", "ldr", 32, + { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } } + }, +/* ldr $rd6,[$rn6],$dpmi$disp11 */ + { + EPIPHANY_INSN_LDRDPM_L, "ldrdpm.l", "ldr", 32, + { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } } + }, +/* ldrd $rd,[$rn,$rm] */ + { + EPIPHANY_INSN_LDRDX16_S, "ldrdx16.s", "ldrd", 16, + { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } } + }, +/* ldrd $rd,[$rn],$rm */ + { + EPIPHANY_INSN_LDRDP16_S, "ldrdp16.s", "ldrd", 16, + { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } } + }, +/* ldrd $rd6,[$rn6,$direction$rm6] */ + { + EPIPHANY_INSN_LDRDX_L, "ldrdx.l", "ldrd", 32, + { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } } + }, +/* ldrd $rd6,[$rn6],$direction$rm6 */ + { + EPIPHANY_INSN_LDRDP_L, "ldrdp.l", "ldrd", 32, + { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } } + }, +/* ldrd $rd,[$rn,$disp3] */ + { + EPIPHANY_INSN_LDRDD16_S, "ldrdd16.s", "ldrd", 16, + { 0|A(IMM3)|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } } + }, +/* ldrd $rd6,[$rn6,$dpmi$disp11] */ + { + EPIPHANY_INSN_LDRDD_L, "ldrdd.l", "ldrd", 32, + { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } } + }, +/* ldrd $rd6,[$rn6],$dpmi$disp11 */ + { + EPIPHANY_INSN_LDRDDPM_L, "ldrddpm.l", "ldrd", 32, + { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } } + }, +/* testsetb $rd6,[$rn6,$direction$rm6] */ + { + EPIPHANY_INSN_TESTSETBT, "testsetbt", "testsetb", 32, + { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } } + }, +/* testseth $rd6,[$rn6,$direction$rm6] */ + { + EPIPHANY_INSN_TESTSETHT, "testsetht", "testseth", 32, + { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } } + }, +/* testset $rd6,[$rn6,$direction$rm6] */ + { + EPIPHANY_INSN_TESTSETT, "testsett", "testset", 32, + { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } } + }, +/* strb $rd,[$rn,$rm] */ + { + EPIPHANY_INSN_STRBX16, "strbx16", "strb", 16, + { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } } + }, +/* strb $rd6,[$rn6,$direction$rm6] */ + { + EPIPHANY_INSN_STRBX, "strbx", "strb", 32, + { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } } + }, +/* strb $rd,[$rn],$rm */ + { + EPIPHANY_INSN_STRBP16, "strbp16", "strb", 16, + { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } } + }, +/* strb $rd6,[$rn6],$direction$rm6 */ + { + EPIPHANY_INSN_STRBP, "strbp", "strb", 32, + { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } } + }, +/* strb $rd,[$rn,$disp3] */ + { + EPIPHANY_INSN_STRBD16, "strbd16", "strb", 16, + { 0|A(IMM3)|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } } + }, +/* strb $rd6,[$rn6,$dpmi$disp11] */ + { + EPIPHANY_INSN_STRBD, "strbd", "strb", 32, + { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } } + }, +/* strb $rd6,[$rn6],$dpmi$disp11 */ + { + EPIPHANY_INSN_STRBDPM, "strbdpm", "strb", 32, + { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } } + }, +/* strh $rd,[$rn,$rm] */ + { + EPIPHANY_INSN_STRHX16, "strhx16", "strh", 16, + { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } } + }, +/* strh $rd6,[$rn6,$direction$rm6] */ + { + EPIPHANY_INSN_STRHX, "strhx", "strh", 32, + { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } } + }, +/* strh $rd,[$rn],$rm */ + { + EPIPHANY_INSN_STRHP16, "strhp16", "strh", 16, + { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } } + }, +/* strh $rd6,[$rn6],$direction$rm6 */ + { + EPIPHANY_INSN_STRHP, "strhp", "strh", 32, + { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } } + }, +/* strh $rd,[$rn,$disp3] */ + { + EPIPHANY_INSN_STRHD16, "strhd16", "strh", 16, + { 0|A(IMM3)|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } } + }, +/* strh $rd6,[$rn6,$dpmi$disp11] */ + { + EPIPHANY_INSN_STRHD, "strhd", "strh", 32, + { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } } + }, +/* strh $rd6,[$rn6],$dpmi$disp11 */ + { + EPIPHANY_INSN_STRHDPM, "strhdpm", "strh", 32, + { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } } + }, +/* str $rd,[$rn,$rm] */ + { + EPIPHANY_INSN_STRX16, "strx16", "str", 16, + { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } } + }, +/* str $rd6,[$rn6,$direction$rm6] */ + { + EPIPHANY_INSN_STRX, "strx", "str", 32, + { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } } + }, +/* str $rd,[$rn],$rm */ + { + EPIPHANY_INSN_STRP16, "strp16", "str", 16, + { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } } + }, +/* str $rd6,[$rn6],$direction$rm6 */ + { + EPIPHANY_INSN_STRP, "strp", "str", 32, + { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } } + }, +/* str $rd,[$rn,$disp3] */ + { + EPIPHANY_INSN_STRD16, "strd16", "str", 16, + { 0|A(IMM3)|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } } + }, +/* str $rd6,[$rn6,$dpmi$disp11] */ + { + EPIPHANY_INSN_STRD, "strd", "str", 32, + { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } } + }, +/* str $rd6,[$rn6],$dpmi$disp11 */ + { + EPIPHANY_INSN_STRDPM, "strdpm", "str", 32, + { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } } + }, +/* strd $rd,[$rn,$rm] */ + { + EPIPHANY_INSN_STRDX16, "strdx16", "strd", 16, + { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } } + }, +/* strd $rd6,[$rn6,$direction$rm6] */ + { + EPIPHANY_INSN_STRDX, "strdx", "strd", 32, + { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } } + }, +/* strd $rd,[$rn],$rm */ + { + EPIPHANY_INSN_STRDP16, "strdp16", "strd", 16, + { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } } + }, +/* strd $rd6,[$rn6],$direction$rm6 */ + { + EPIPHANY_INSN_STRDP, "strdp", "strd", 32, + { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } } + }, +/* strd $rd,[$rn,$disp3] */ + { + EPIPHANY_INSN_STRDD16, "strdd16", "strd", 16, + { 0|A(IMM3)|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } } + }, +/* strd $rd6,[$rn6,$dpmi$disp11] */ + { + EPIPHANY_INSN_STRDD, "strdd", "strd", 32, + { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } } + }, +/* strd $rd6,[$rn6],$dpmi$disp11 */ + { + EPIPHANY_INSN_STRDDPM, "strddpm", "strd", 32, + { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } } + }, +/* moveq $rd,$rn */ + { + EPIPHANY_INSN_CMOV16EQ, "cmov16EQ", "moveq", 16, + { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } } + }, +/* moveq $rd6,$rn6 */ + { + EPIPHANY_INSN_CMOVEQ, "cmovEQ", "moveq", 32, + { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } } + }, +/* movne $rd,$rn */ + { + EPIPHANY_INSN_CMOV16NE, "cmov16NE", "movne", 16, + { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } } + }, +/* movne $rd6,$rn6 */ + { + EPIPHANY_INSN_CMOVNE, "cmovNE", "movne", 32, + { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } } + }, +/* movgtu $rd,$rn */ + { + EPIPHANY_INSN_CMOV16GTU, "cmov16GTU", "movgtu", 16, + { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } } + }, +/* movgtu $rd6,$rn6 */ + { + EPIPHANY_INSN_CMOVGTU, "cmovGTU", "movgtu", 32, + { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } } + }, +/* movgteu $rd,$rn */ + { + EPIPHANY_INSN_CMOV16GTEU, "cmov16GTEU", "movgteu", 16, + { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } } + }, +/* movgteu $rd6,$rn6 */ + { + EPIPHANY_INSN_CMOVGTEU, "cmovGTEU", "movgteu", 32, + { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } } + }, +/* movlteu $rd,$rn */ + { + EPIPHANY_INSN_CMOV16LTEU, "cmov16LTEU", "movlteu", 16, + { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } } + }, +/* movlteu $rd6,$rn6 */ + { + EPIPHANY_INSN_CMOVLTEU, "cmovLTEU", "movlteu", 32, + { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } } + }, +/* movltu $rd,$rn */ + { + EPIPHANY_INSN_CMOV16LTU, "cmov16LTU", "movltu", 16, + { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } } + }, +/* movltu $rd6,$rn6 */ + { + EPIPHANY_INSN_CMOVLTU, "cmovLTU", "movltu", 32, + { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } } + }, +/* movgt $rd,$rn */ + { + EPIPHANY_INSN_CMOV16GT, "cmov16GT", "movgt", 16, + { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } } + }, +/* movgt $rd6,$rn6 */ + { + EPIPHANY_INSN_CMOVGT, "cmovGT", "movgt", 32, + { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } } + }, +/* movgte $rd,$rn */ + { + EPIPHANY_INSN_CMOV16GTE, "cmov16GTE", "movgte", 16, + { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } } + }, +/* movgte $rd6,$rn6 */ + { + EPIPHANY_INSN_CMOVGTE, "cmovGTE", "movgte", 32, + { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } } + }, +/* movlt $rd,$rn */ + { + EPIPHANY_INSN_CMOV16LT, "cmov16LT", "movlt", 16, + { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } } + }, +/* movlt $rd6,$rn6 */ + { + EPIPHANY_INSN_CMOVLT, "cmovLT", "movlt", 32, + { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } } + }, +/* movlte $rd,$rn */ + { + EPIPHANY_INSN_CMOV16LTE, "cmov16LTE", "movlte", 16, + { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } } + }, +/* movlte $rd6,$rn6 */ + { + EPIPHANY_INSN_CMOVLTE, "cmovLTE", "movlte", 32, + { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } } + }, +/* mov $rd,$rn */ + { + EPIPHANY_INSN_CMOV16B, "cmov16B", "mov", 16, + { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } } + }, +/* mov $rd6,$rn6 */ + { + EPIPHANY_INSN_CMOVB, "cmovB", "mov", 32, + { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } } + }, +/* movbeq $rd,$rn */ + { + EPIPHANY_INSN_CMOV16BEQ, "cmov16BEQ", "movbeq", 16, + { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } } + }, +/* movbeq $rd6,$rn6 */ + { + EPIPHANY_INSN_CMOVBEQ, "cmovBEQ", "movbeq", 32, + { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } } + }, +/* movbne $rd,$rn */ + { + EPIPHANY_INSN_CMOV16BNE, "cmov16BNE", "movbne", 16, + { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } } + }, +/* movbne $rd6,$rn6 */ + { + EPIPHANY_INSN_CMOVBNE, "cmovBNE", "movbne", 32, + { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } } + }, +/* movblt $rd,$rn */ + { + EPIPHANY_INSN_CMOV16BLT, "cmov16BLT", "movblt", 16, + { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } } + }, +/* movblt $rd6,$rn6 */ + { + EPIPHANY_INSN_CMOVBLT, "cmovBLT", "movblt", 32, + { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } } + }, +/* movblte $rd,$rn */ + { + EPIPHANY_INSN_CMOV16BLTE, "cmov16BLTE", "movblte", 16, + { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } } + }, +/* movblte $rd6,$rn6 */ + { + EPIPHANY_INSN_CMOVBLTE, "cmovBLTE", "movblte", 32, + { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } } + }, +/* movts $sn,$rd */ + { + EPIPHANY_INSN_MOVTS16, "movts16", "movts", 16, + { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } } + }, +/* movts $sn6,$rd6 */ + { + EPIPHANY_INSN_MOVTS6, "movts6", "movts", 32, + { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } } + }, +/* movts $sndma,$rd6 */ + { + EPIPHANY_INSN_MOVTSDMA, "movtsdma", "movts", 32, + { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } } + }, +/* movts $snmem,$rd6 */ + { + EPIPHANY_INSN_MOVTSMEM, "movtsmem", "movts", 32, + { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } } + }, +/* movts $snmesh,$rd6 */ + { + EPIPHANY_INSN_MOVTSMESH, "movtsmesh", "movts", 32, + { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } } + }, +/* movfs $rd,$sn */ + { + EPIPHANY_INSN_MOVFS16, "movfs16", "movfs", 16, + { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } } + }, +/* movfs $rd6,$sn6 */ + { + EPIPHANY_INSN_MOVFS6, "movfs6", "movfs", 32, + { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } } + }, +/* movfs $rd6,$sndma */ + { + EPIPHANY_INSN_MOVFSDMA, "movfsdma", "movfs", 32, + { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } } + }, +/* movfs $rd6,$snmem */ + { + EPIPHANY_INSN_MOVFSMEM, "movfsmem", "movfs", 32, + { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } } + }, +/* movfs $rd6,$snmesh */ + { + EPIPHANY_INSN_MOVFSMESH, "movfsmesh", "movfs", 32, + { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } } + }, +/* nop */ + { + EPIPHANY_INSN_NOP, "nop", "nop", 16, + { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } } + }, +/* snop */ + { + EPIPHANY_INSN_SNOP, "snop", "snop", 16, + { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } } + }, +/* unimpl */ + { + EPIPHANY_INSN_UNIMPL, "unimpl", "unimpl", 32, + { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } } + }, +/* idle */ + { + EPIPHANY_INSN_IDLE, "idle", "idle", 16, + { 0, { { { (1<<MACH_BASE), 0 } } } } + }, +/* bkpt */ + { + EPIPHANY_INSN_BKPT, "bkpt", "bkpt", 16, + { 0|A(SHORT_INSN)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } } } } + }, +/* mbkpt */ + { + EPIPHANY_INSN_MBKPT, "mbkpt", "mbkpt", 16, + { 0|A(SHORT_INSN), { { { (1<<MACH_BASE), 0 } } } } + }, +/* rti */ + { + EPIPHANY_INSN_RTI, "rti", "rti", 16, + { 0|A(UNCOND_CTI)|A(SHORT_INSN), { { { (1<<MACH_BASE), 0 } } } } + }, +/* wand */ + { + EPIPHANY_INSN_WAND, "wand", "wand", 16, + { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } } + }, +/* sync */ + { + EPIPHANY_INSN_SYNC, "sync", "sync", 16, + { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } } + }, +/* gie */ + { + EPIPHANY_INSN_GIEN, "gien", "gie", 16, + { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } } + }, +/* gid */ + { + EPIPHANY_INSN_GIDIS, "gidis", "gid", 16, + { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } } + }, +/* swi $swi_num */ + { + EPIPHANY_INSN_SWI_NUM, "swi_num", "swi", 16, + { 0|A(UNCOND_CTI)|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } } + }, +/* swi */ + { + -1, "swi", "swi", 16, + { 0|A(UNCOND_CTI)|A(SHORT_INSN)|A(ALIAS)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } } + }, +/* trap $trapnum6 */ + { + EPIPHANY_INSN_TRAP16, "trap16", "trap", 16, + { 0|A(UNCOND_CTI)|A(SHORT_INSN), { { { (1<<MACH_BASE), 0 } } } } + }, +/* add $rd,$rn,$rm */ + { + EPIPHANY_INSN_ADD16, "add16", "add", 16, + { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } } + }, +/* add $rd6,$rn6,$rm6 */ + { + EPIPHANY_INSN_ADD, "add", "add", 32, + { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } } + }, +/* sub $rd,$rn,$rm */ + { + EPIPHANY_INSN_SUB16, "sub16", "sub", 16, + { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } } + }, +/* sub $rd6,$rn6,$rm6 */ + { + EPIPHANY_INSN_SUB, "sub", "sub", 32, + { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } } + }, +/* and $rd,$rn,$rm */ + { + EPIPHANY_INSN_AND16, "and16", "and", 16, + { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } } + }, +/* and $rd6,$rn6,$rm6 */ + { + EPIPHANY_INSN_AND, "and", "and", 32, + { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } } + }, +/* orr $rd,$rn,$rm */ + { + EPIPHANY_INSN_ORR16, "orr16", "orr", 16, + { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } } + }, +/* orr $rd6,$rn6,$rm6 */ + { + EPIPHANY_INSN_ORR, "orr", "orr", 32, + { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } } + }, +/* eor $rd,$rn,$rm */ + { + EPIPHANY_INSN_EOR16, "eor16", "eor", 16, + { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } } + }, +/* eor $rd6,$rn6,$rm6 */ + { + EPIPHANY_INSN_EOR, "eor", "eor", 32, + { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } } + }, +/* add.s $rd,$rn,$simm3 */ + { + EPIPHANY_INSN_ADDI16, "addi16", "add.s", 16, + { 0|A(IMM3)|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } } + }, +/* add.l $rd6,$rn6,$simm11 */ + { + EPIPHANY_INSN_ADDI, "addi", "add.l", 32, + { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } } + }, +/* sub.s $rd,$rn,$simm3 */ + { + EPIPHANY_INSN_SUBI16, "subi16", "sub.s", 16, + { 0|A(IMM3)|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } } + }, +/* sub.l $rd6,$rn6,$simm11 */ + { + EPIPHANY_INSN_SUBI, "subi", "sub.l", 32, + { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } } + }, +/* asr $rd,$rn,$rm */ + { + EPIPHANY_INSN_ASR16, "asr16", "asr", 16, + { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } } + }, +/* asr $rd6,$rn6,$rm6 */ + { + EPIPHANY_INSN_ASR, "asr", "asr", 32, + { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } } + }, +/* lsr $rd,$rn,$rm */ + { + EPIPHANY_INSN_LSR16, "lsr16", "lsr", 16, + { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } } + }, +/* lsr $rd6,$rn6,$rm6 */ + { + EPIPHANY_INSN_LSR, "lsr", "lsr", 32, + { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } } + }, +/* lsl $rd,$rn,$rm */ + { + EPIPHANY_INSN_LSL16, "lsl16", "lsl", 16, + { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } } + }, +/* lsl $rd6,$rn6,$rm6 */ + { + EPIPHANY_INSN_LSL, "lsl", "lsl", 32, + { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } } + }, +/* lsr $rd,$rn,$shift */ + { + EPIPHANY_INSN_LSRI16, "lsri16", "lsr", 16, + { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } } + }, +/* lsr $rd6,$rn6,$shift */ + { + EPIPHANY_INSN_LSRI32, "lsri32", "lsr", 32, + { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } } + }, +/* lsl $rd,$rn,$shift */ + { + EPIPHANY_INSN_LSLI16, "lsli16", "lsl", 16, + { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } } + }, +/* lsl $rd6,$rn6,$shift */ + { + EPIPHANY_INSN_LSLI32, "lsli32", "lsl", 32, + { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } } + }, +/* asr $rd,$rn,$shift */ + { + EPIPHANY_INSN_ASRI16, "asri16", "asr", 16, + { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } } + }, +/* asr $rd6,$rn6,$shift */ + { + EPIPHANY_INSN_ASRI32, "asri32", "asr", 32, + { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } } + }, +/* bitr $rd,$rn */ + { + EPIPHANY_INSN_BITR16, "bitr16", "bitr", 16, + { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } } + }, +/* bitr $rd6,$rn6 */ + { + EPIPHANY_INSN_BITR, "bitr", "bitr", 32, + { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } } + }, +/* fext $rd6,$rn6,$rm6 */ + { + EPIPHANY_INSN_FEXT, "fext", "fext", 32, + { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } } + }, +/* fdep $rd6,$rn6,$rm6 */ + { + EPIPHANY_INSN_FDEP, "fdep", "fdep", 32, + { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } } + }, +/* lfsr $rd6,$rn6,$rm6 */ + { + EPIPHANY_INSN_LFSR, "lfsr", "lfsr", 32, + { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } } + }, +/* mov.b $rd,$imm8 */ + { + EPIPHANY_INSN_MOV8, "mov8", "mov.b", 16, + { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } } + }, +/* mov.l $rd6,$imm16 */ + { + EPIPHANY_INSN_MOV16, "mov16", "mov.l", 32, + { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } } + }, +/* movt $rd6,$imm16 */ + { + EPIPHANY_INSN_MOVT, "movt", "movt", 32, + { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } } + }, +/* fadd $rd,$rn,$rm */ + { + EPIPHANY_INSN_F_ADDF16, "f_addf16", "fadd", 16, + { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } } + }, +/* fadd $rd6,$rn6,$rm6 */ + { + EPIPHANY_INSN_F_ADDF32, "f_addf32", "fadd", 32, + { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } } + }, +/* fsub $rd,$rn,$rm */ + { + EPIPHANY_INSN_F_SUBF16, "f_subf16", "fsub", 16, + { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } } + }, +/* fsub $rd6,$rn6,$rm6 */ + { + EPIPHANY_INSN_F_SUBF32, "f_subf32", "fsub", 32, + { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } } + }, +/* fmul $rd,$rn,$rm */ + { + EPIPHANY_INSN_F_MULF16, "f_mulf16", "fmul", 16, + { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } } + }, +/* fmul $rd6,$rn6,$rm6 */ + { + EPIPHANY_INSN_F_MULF32, "f_mulf32", "fmul", 32, + { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } } + }, +/* fmadd $rd,$rn,$rm */ + { + EPIPHANY_INSN_F_MADDF16, "f_maddf16", "fmadd", 16, + { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } } + }, +/* fmadd $rd6,$rn6,$rm6 */ + { + EPIPHANY_INSN_F_MADDF32, "f_maddf32", "fmadd", 32, + { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } } + }, +/* fmsub $rd,$rn,$rm */ + { + EPIPHANY_INSN_F_MSUBF16, "f_msubf16", "fmsub", 16, + { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } } + }, +/* fmsub $rd6,$rn6,$rm6 */ + { + EPIPHANY_INSN_F_MSUBF32, "f_msubf32", "fmsub", 32, + { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } } + }, +/* fabs rd,rn */ + { + EPIPHANY_INSN_F_ABSF16, "f_absf16", "fabs", 16, + { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } } + }, +/* fabs $rd6,$rn6 */ + { + EPIPHANY_INSN_F_ABSF32, "f_absf32", "fabs", 32, + { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } } + }, +/* float $rd,$rn */ + { + EPIPHANY_INSN_F_LOATF16, "f_loatf16", "float", 16, + { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } } + }, +/* float $rd6,$rn6 */ + { + EPIPHANY_INSN_F_LOATF32, "f_loatf32", "float", 32, + { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } } + }, +/* fix $rd,$rn */ + { + EPIPHANY_INSN_F_IXF16, "f_ixf16", "fix", 16, + { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } } + }, +/* fix $rd6,$rn6 */ + { + EPIPHANY_INSN_F_IXF32, "f_ixf32", "fix", 32, + { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } } + }, +/* frecip $frd6,$frn6 */ + { + EPIPHANY_INSN_F_RECIPF32, "f_recipf32", "frecip", 32, + { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } } + }, +/* fsqrt $frd6,$frn6 */ + { + EPIPHANY_INSN_F_SQRTF32, "f_sqrtf32", "fsqrt", 32, + { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } } + }, +}; + +#undef OP +#undef A + +/* Initialize anything needed to be done once, before any cpu_open call. */ + +static void +init_tables (void) +{ +} + +static const CGEN_MACH * lookup_mach_via_bfd_name (const CGEN_MACH *, const char *); +static void build_hw_table (CGEN_CPU_TABLE *); +static void build_ifield_table (CGEN_CPU_TABLE *); +static void build_operand_table (CGEN_CPU_TABLE *); +static void build_insn_table (CGEN_CPU_TABLE *); +static void epiphany_cgen_rebuild_tables (CGEN_CPU_TABLE *); + +/* Subroutine of epiphany_cgen_cpu_open to look up a mach via its bfd name. */ + +static const CGEN_MACH * +lookup_mach_via_bfd_name (const CGEN_MACH *table, const char *name) +{ + while (table->name) + { + if (strcmp (name, table->bfd_name) == 0) + return table; + ++table; + } + abort (); +} + +/* Subroutine of epiphany_cgen_cpu_open to build the hardware table. */ + +static void +build_hw_table (CGEN_CPU_TABLE *cd) +{ + int i; + int machs = cd->machs; + const CGEN_HW_ENTRY *init = & epiphany_cgen_hw_table[0]; + /* MAX_HW is only an upper bound on the number of selected entries. + However each entry is indexed by it's enum so there can be holes in + the table. */ + const CGEN_HW_ENTRY **selected = + (const CGEN_HW_ENTRY **) xmalloc (MAX_HW * sizeof (CGEN_HW_ENTRY *)); + + cd->hw_table.init_entries = init; + cd->hw_table.entry_size = sizeof (CGEN_HW_ENTRY); + memset (selected, 0, MAX_HW * sizeof (CGEN_HW_ENTRY *)); + /* ??? For now we just use machs to determine which ones we want. */ + for (i = 0; init[i].name != NULL; ++i) + if (CGEN_HW_ATTR_VALUE (&init[i], CGEN_HW_MACH) + & machs) + selected[init[i].type] = &init[i]; + cd->hw_table.entries = selected; + cd->hw_table.num_entries = MAX_HW; +} + +/* Subroutine of epiphany_cgen_cpu_open to build the hardware table. */ + +static void +build_ifield_table (CGEN_CPU_TABLE *cd) +{ + cd->ifld_table = & epiphany_cgen_ifld_table[0]; +} + +/* Subroutine of epiphany_cgen_cpu_open to build the hardware table. */ + +static void +build_operand_table (CGEN_CPU_TABLE *cd) +{ + int i; + int machs = cd->machs; + const CGEN_OPERAND *init = & epiphany_cgen_operand_table[0]; + /* MAX_OPERANDS is only an upper bound on the number of selected entries. + However each entry is indexed by it's enum so there can be holes in + the table. */ + const CGEN_OPERAND **selected = xmalloc (MAX_OPERANDS * sizeof (* selected)); + + cd->operand_table.init_entries = init; + cd->operand_table.entry_size = sizeof (CGEN_OPERAND); + memset (selected, 0, MAX_OPERANDS * sizeof (CGEN_OPERAND *)); + /* ??? For now we just use mach to determine which ones we want. */ + for (i = 0; init[i].name != NULL; ++i) + if (CGEN_OPERAND_ATTR_VALUE (&init[i], CGEN_OPERAND_MACH) + & machs) + selected[init[i].type] = &init[i]; + cd->operand_table.entries = selected; + cd->operand_table.num_entries = MAX_OPERANDS; +} + +/* Subroutine of epiphany_cgen_cpu_open to build the hardware table. + ??? This could leave out insns not supported by the specified mach/isa, + but that would cause errors like "foo only supported by bar" to become + "unknown insn", so for now we include all insns and require the app to + do the checking later. + ??? On the other hand, parsing of such insns may require their hardware or + operand elements to be in the table [which they mightn't be]. */ + +static void +build_insn_table (CGEN_CPU_TABLE *cd) +{ + int i; + const CGEN_IBASE *ib = & epiphany_cgen_insn_table[0]; + CGEN_INSN *insns = xmalloc (MAX_INSNS * sizeof (CGEN_INSN)); + + memset (insns, 0, MAX_INSNS * sizeof (CGEN_INSN)); + for (i = 0; i < MAX_INSNS; ++i) + insns[i].base = &ib[i]; + cd->insn_table.init_entries = insns; + cd->insn_table.entry_size = sizeof (CGEN_IBASE); + cd->insn_table.num_init_entries = MAX_INSNS; +} + +/* Subroutine of epiphany_cgen_cpu_open to rebuild the tables. */ + +static void +epiphany_cgen_rebuild_tables (CGEN_CPU_TABLE *cd) +{ + int i; + CGEN_BITSET *isas = cd->isas; + unsigned int machs = cd->machs; + + cd->int_insn_p = CGEN_INT_INSN_P; + + /* Data derived from the isa spec. */ +#define UNSET (CGEN_SIZE_UNKNOWN + 1) + cd->default_insn_bitsize = UNSET; + cd->base_insn_bitsize = UNSET; + cd->min_insn_bitsize = 65535; /* Some ridiculously big number. */ + cd->max_insn_bitsize = 0; + for (i = 0; i < MAX_ISAS; ++i) + if (cgen_bitset_contains (isas, i)) + { + const CGEN_ISA *isa = & epiphany_cgen_isa_table[i]; + + /* Default insn sizes of all selected isas must be + equal or we set the result to 0, meaning "unknown". */ + if (cd->default_insn_bitsize == UNSET) + cd->default_insn_bitsize = isa->default_insn_bitsize; + else if (isa->default_insn_bitsize == cd->default_insn_bitsize) + ; /* This is ok. */ + else + cd->default_insn_bitsize = CGEN_SIZE_UNKNOWN; + + /* Base insn sizes of all selected isas must be equal + or we set the result to 0, meaning "unknown". */ + if (cd->base_insn_bitsize == UNSET) + cd->base_insn_bitsize = isa->base_insn_bitsize; + else if (isa->base_insn_bitsize == cd->base_insn_bitsize) + ; /* This is ok. */ + else + cd->base_insn_bitsize = CGEN_SIZE_UNKNOWN; + + /* Set min,max insn sizes. */ + if (isa->min_insn_bitsize < cd->min_insn_bitsize) + cd->min_insn_bitsize = isa->min_insn_bitsize; + if (isa->max_insn_bitsize > cd->max_insn_bitsize) + cd->max_insn_bitsize = isa->max_insn_bitsize; + } + + /* Data derived from the mach spec. */ + for (i = 0; i < MAX_MACHS; ++i) + if (((1 << i) & machs) != 0) + { + const CGEN_MACH *mach = & epiphany_cgen_mach_table[i]; + + if (mach->insn_chunk_bitsize != 0) + { + if (cd->insn_chunk_bitsize != 0 && cd->insn_chunk_bitsize != mach->insn_chunk_bitsize) + { + fprintf (stderr, "epiphany_cgen_rebuild_tables: conflicting insn-chunk-bitsize values: `%d' vs. `%d'\n", + cd->insn_chunk_bitsize, mach->insn_chunk_bitsize); + abort (); + } + + cd->insn_chunk_bitsize = mach->insn_chunk_bitsize; + } + } + + /* Determine which hw elements are used by MACH. */ + build_hw_table (cd); + + /* Build the ifield table. */ + build_ifield_table (cd); + + /* Determine which operands are used by MACH/ISA. */ + build_operand_table (cd); + + /* Build the instruction table. */ + build_insn_table (cd); +} + +/* Initialize a cpu table and return a descriptor. + It's much like opening a file, and must be the first function called. + The arguments are a set of (type/value) pairs, terminated with + CGEN_CPU_OPEN_END. + + Currently supported values: + CGEN_CPU_OPEN_ISAS: bitmap of values in enum isa_attr + CGEN_CPU_OPEN_MACHS: bitmap of values in enum mach_attr + CGEN_CPU_OPEN_BFDMACH: specify 1 mach using bfd name + CGEN_CPU_OPEN_ENDIAN: specify endian choice + CGEN_CPU_OPEN_END: terminates arguments + + ??? Simultaneous multiple isas might not make sense, but it's not (yet) + precluded. */ + +CGEN_CPU_DESC +epiphany_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...) +{ + CGEN_CPU_TABLE *cd = (CGEN_CPU_TABLE *) xmalloc (sizeof (CGEN_CPU_TABLE)); + static int init_p; + CGEN_BITSET *isas = 0; /* 0 = "unspecified" */ + unsigned int machs = 0; /* 0 = "unspecified" */ + enum cgen_endian endian = CGEN_ENDIAN_UNKNOWN; + va_list ap; + + if (! init_p) + { + init_tables (); + init_p = 1; + } + + memset (cd, 0, sizeof (*cd)); + + va_start (ap, arg_type); + while (arg_type != CGEN_CPU_OPEN_END) + { + switch (arg_type) + { + case CGEN_CPU_OPEN_ISAS : + isas = va_arg (ap, CGEN_BITSET *); + break; + case CGEN_CPU_OPEN_MACHS : + machs = va_arg (ap, unsigned int); + break; + case CGEN_CPU_OPEN_BFDMACH : + { + const char *name = va_arg (ap, const char *); + const CGEN_MACH *mach = + lookup_mach_via_bfd_name (epiphany_cgen_mach_table, name); + + machs |= 1 << mach->num; + break; + } + case CGEN_CPU_OPEN_ENDIAN : + endian = va_arg (ap, enum cgen_endian); + break; + default : + fprintf (stderr, "epiphany_cgen_cpu_open: unsupported argument `%d'\n", + arg_type); + abort (); /* ??? return NULL? */ + } + arg_type = va_arg (ap, enum cgen_cpu_open_arg); + } + va_end (ap); + + /* Mach unspecified means "all". */ + if (machs == 0) + machs = (1 << MAX_MACHS) - 1; + /* Base mach is always selected. */ + machs |= 1; + if (endian == CGEN_ENDIAN_UNKNOWN) + { + /* ??? If target has only one, could have a default. */ + fprintf (stderr, "epiphany_cgen_cpu_open: no endianness specified\n"); + abort (); + } + + cd->isas = cgen_bitset_copy (isas); + cd->machs = machs; + cd->endian = endian; + /* FIXME: for the sparc case we can determine insn-endianness statically. + The worry here is where both data and insn endian can be independently + chosen, in which case this function will need another argument. + Actually, will want to allow for more arguments in the future anyway. */ + cd->insn_endian = endian; + + /* Table (re)builder. */ + cd->rebuild_tables = epiphany_cgen_rebuild_tables; + epiphany_cgen_rebuild_tables (cd); + + /* Default to not allowing signed overflow. */ + cd->signed_overflow_ok_p = 0; + + return (CGEN_CPU_DESC) cd; +} + +/* Cover fn to epiphany_cgen_cpu_open to handle the simple case of 1 isa, 1 mach. + MACH_NAME is the bfd name of the mach. */ + +CGEN_CPU_DESC +epiphany_cgen_cpu_open_1 (const char *mach_name, enum cgen_endian endian) +{ + return epiphany_cgen_cpu_open (CGEN_CPU_OPEN_BFDMACH, mach_name, + CGEN_CPU_OPEN_ENDIAN, endian, + CGEN_CPU_OPEN_END); +} + +/* Close a cpu table. + ??? This can live in a machine independent file, but there's currently + no place to put this file (there's no libcgen). libopcodes is the wrong + place as some simulator ports use this but they don't use libopcodes. */ + +void +epiphany_cgen_cpu_close (CGEN_CPU_DESC cd) +{ + unsigned int i; + const CGEN_INSN *insns; + + if (cd->macro_insn_table.init_entries) + { + insns = cd->macro_insn_table.init_entries; + for (i = 0; i < cd->macro_insn_table.num_init_entries; ++i, ++insns) + if (CGEN_INSN_RX ((insns))) + regfree (CGEN_INSN_RX (insns)); + } + + if (cd->insn_table.init_entries) + { + insns = cd->insn_table.init_entries; + for (i = 0; i < cd->insn_table.num_init_entries; ++i, ++insns) + if (CGEN_INSN_RX (insns)) + regfree (CGEN_INSN_RX (insns)); + } + + if (cd->macro_insn_table.init_entries) + free ((CGEN_INSN *) cd->macro_insn_table.init_entries); + + if (cd->insn_table.init_entries) + free ((CGEN_INSN *) cd->insn_table.init_entries); + + if (cd->hw_table.entries) + free ((CGEN_HW_ENTRY *) cd->hw_table.entries); + + if (cd->operand_table.entries) + free ((CGEN_HW_ENTRY *) cd->operand_table.entries); + + free (cd); +} + diff --git a/opcodes/epiphany-desc.h b/opcodes/epiphany-desc.h new file mode 100644 index 00000000000..430210e2b55 --- /dev/null +++ b/opcodes/epiphany-desc.h @@ -0,0 +1,402 @@ +/* CPU data header for epiphany. + +THIS FILE IS MACHINE GENERATED WITH CGEN. + +Copyright 1996-2010 Free Software Foundation, Inc. + +This file is part of the GNU Binutils and/or GDB, the GNU debugger. + + This file is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + It is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License along + with this program; if not, write to the Free Software Foundation, Inc., + 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. + +*/ + +#ifndef EPIPHANY_CPU_H +#define EPIPHANY_CPU_H + +#define CGEN_ARCH epiphany + +/* Given symbol S, return epiphany_cgen_<S>. */ +#define CGEN_SYM(s) epiphany##_cgen_##s + + +/* Selected cpu families. */ +#define HAVE_CPU_EPIPHANYBF +#define HAVE_CPU_EPIPHANYMF + +#define CGEN_INSN_LSB0_P 1 + +/* Minimum size of any insn (in bytes). */ +#define CGEN_MIN_INSN_SIZE 2 + +/* Maximum size of any insn (in bytes). */ +#define CGEN_MAX_INSN_SIZE 4 + +#define CGEN_INT_INSN_P 1 + +/* Maximum number of syntax elements in an instruction. */ +#define CGEN_ACTUAL_MAX_SYNTAX_ELEMENTS 19 + +/* CGEN_MNEMONIC_OPERANDS is defined if mnemonics have operands. + e.g. In "b,a foo" the ",a" is an operand. If mnemonics have operands + we can't hash on everything up to the space. */ +#define CGEN_MNEMONIC_OPERANDS + +/* Maximum number of fields in an instruction. */ +#define CGEN_ACTUAL_MAX_IFMT_OPERANDS 10 + +/* Enums. */ + +/* Enum declaration for opc enums. */ +typedef enum insn_opc { + OP4_BRANCH16, OP4_LDSTR16X, OP4_FLOW16, OP4_IMM16 + , OP4_LDSTR16D, OP4_LDSTR16P, OP4_LSHIFT16, OP4_DSP16 + , OP4_BRANCH, OP4_LDSTRX, OP4_ALU16, OP4_IMM32 + , OP4_LDSTRD, OP4_LDSTRP, OP4_ASHIFT16, OP4_MISC +} INSN_OPC; + +/* Enum declaration for memory access width. */ +typedef enum insn_wordsize { + OPW_BYTE, OPW_SHORT, OPW_WORD, OPW_DOUBLE +} INSN_WORDSIZE; + +/* Enum declaration for memory access direction. */ +typedef enum insn_memory_access { + OP_LOAD, OP_STORE +} INSN_MEMORY_ACCESS; + +/* Enum declaration for trap instruction dispatch code. */ +typedef enum trap_codes { + TRAP_WRITE, TRAP_READ, TRAP_OPEN, TRAP_EXIT + , TRAP_PASS, TRAP_FAIL, TRAP_CLOSE, TRAP_OTHER +} TRAP_CODES; + +/* Enum declaration for branch conditions. */ +typedef enum insn_cond { + OPC_EQ, OPC_NE, OPC_GTU, OPC_GTEU + , OPC_LTEU, OPC_LTU, OPC_GT, OPC_GTE + , OPC_LT, OPC_LTE, OPC_BEQ, OPC_BNE + , OPC_BLT, OPC_BLTE, OPC_B, OPC_BL +} INSN_COND; + +/* Enum declaration for binary operator subcodes. */ +typedef enum insn_bop { + OPB_EOR, OPB_ADD, OPB_LSL, OPB_SUB + , OPB_LSR, OPB_AND, OPB_ASR, OPB_ORR +} INSN_BOP; + +/* Enum declaration for binary operator subcodes. */ +typedef enum insn_bopext { + OPBE_FEXT, OPBE_FDEP, OPBE_LFSR +} INSN_BOPEXT; + +/* Enum declaration for floating operators. */ +typedef enum insn_fop { + OPF_ADD, OPF_SUB, OPF_MUL, OPF_MADD + , OPF_MSUB, OPF_FLOAT, OPF_FIX, OPF_FABS +} INSN_FOP; + +/* Enum declaration for extended floating operators. */ +typedef enum insn_fopexn { + OPF_FRECIP, OPF_FSQRT +} INSN_FOPEXN; + +/* Enum declaration for immediate operators. */ +typedef enum insn_immop { + OPI_ADD = 1, OPI_SUB = 3, OPI_TRAP = 7 +} INSN_IMMOP; + +/* Enum declaration for don't cares. */ +typedef enum insn_dc_25_2 { + OPI_25_2_MBZ +} INSN_DC_25_2; + +/* Enum declaration for . */ +typedef enum gr_names { + H_REGISTERS_SB = 9, H_REGISTERS_SL = 10, H_REGISTERS_FP = 11, H_REGISTERS_IP = 12 + , H_REGISTERS_SP = 13, H_REGISTERS_LR = 14, H_REGISTERS_R0 = 0, H_REGISTERS_R1 = 1 + , H_REGISTERS_R2 = 2, H_REGISTERS_R3 = 3, H_REGISTERS_R4 = 4, H_REGISTERS_R5 = 5 + , H_REGISTERS_R6 = 6, H_REGISTERS_R7 = 7, H_REGISTERS_R8 = 8, H_REGISTERS_R9 = 9 + , H_REGISTERS_R10 = 10, H_REGISTERS_R11 = 11, H_REGISTERS_R12 = 12, H_REGISTERS_R13 = 13 + , H_REGISTERS_R14 = 14, H_REGISTERS_R15 = 15, H_REGISTERS_R16 = 16, H_REGISTERS_R17 = 17 + , H_REGISTERS_R18 = 18, H_REGISTERS_R19 = 19, H_REGISTERS_R20 = 20, H_REGISTERS_R21 = 21 + , H_REGISTERS_R22 = 22, H_REGISTERS_R23 = 23, H_REGISTERS_R24 = 24, H_REGISTERS_R25 = 25 + , H_REGISTERS_R26 = 26, H_REGISTERS_R27 = 27, H_REGISTERS_R28 = 28, H_REGISTERS_R29 = 29 + , H_REGISTERS_R30 = 30, H_REGISTERS_R31 = 31, H_REGISTERS_R32 = 32, H_REGISTERS_R33 = 33 + , H_REGISTERS_R34 = 34, H_REGISTERS_R35 = 35, H_REGISTERS_R36 = 36, H_REGISTERS_R37 = 37 + , H_REGISTERS_R38 = 38, H_REGISTERS_R39 = 39, H_REGISTERS_R40 = 40, H_REGISTERS_R41 = 41 + , H_REGISTERS_R42 = 42, H_REGISTERS_R43 = 43, H_REGISTERS_R44 = 44, H_REGISTERS_R45 = 45 + , H_REGISTERS_R46 = 46, H_REGISTERS_R47 = 47, H_REGISTERS_R48 = 48, H_REGISTERS_R49 = 49 + , H_REGISTERS_R50 = 50, H_REGISTERS_R51 = 51, H_REGISTERS_R52 = 52, H_REGISTERS_R53 = 53 + , H_REGISTERS_R54 = 54, H_REGISTERS_R55 = 55, H_REGISTERS_R56 = 56, H_REGISTERS_R57 = 57 + , H_REGISTERS_R58 = 58, H_REGISTERS_R59 = 59, H_REGISTERS_R60 = 60, H_REGISTERS_R61 = 61 + , H_REGISTERS_R62 = 62, H_REGISTERS_R63 = 63, H_REGISTERS_A1 = 0, H_REGISTERS_A2 = 1 + , H_REGISTERS_A3 = 2, H_REGISTERS_A4 = 3, H_REGISTERS_V1 = 4, H_REGISTERS_V2 = 5 + , H_REGISTERS_V3 = 6, H_REGISTERS_V4 = 7, H_REGISTERS_V5 = 8, H_REGISTERS_V6 = 9 + , H_REGISTERS_V7 = 10, H_REGISTERS_V8 = 11 +} GR_NAMES; + +/* Enum declaration for +/- index register. */ +typedef enum post_index { + DIR_POSTINC, DIR_POSTDEC +} POST_INDEX; + +/* Enum declaration for postmodify displacement. */ +typedef enum disp_post_modify { + PMOD_DISP, PMOD_POST +} DISP_POST_MODIFY; + +/* Enum declaration for . */ +typedef enum cr_names { + H_CORE_REGISTERS_CONFIG, H_CORE_REGISTERS_STATUS, H_CORE_REGISTERS_PC, H_CORE_REGISTERS_DEBUG + , H_CORE_REGISTERS_IAB, H_CORE_REGISTERS_LC, H_CORE_REGISTERS_LS, H_CORE_REGISTERS_LE + , H_CORE_REGISTERS_IRET, H_CORE_REGISTERS_IMASK, H_CORE_REGISTERS_ILAT, H_CORE_REGISTERS_ILATST + , H_CORE_REGISTERS_ILATCL, H_CORE_REGISTERS_IPEND, H_CORE_REGISTERS_CTIMER0, H_CORE_REGISTERS_CTIMER1 + , H_CORE_REGISTERS_HSTATUS +} CR_NAMES; + +/* Enum declaration for . */ +typedef enum crdma_names { + H_COREDMA_REGISTERS_DMA0CONFIG, H_COREDMA_REGISTERS_DMA0STRIDE, H_COREDMA_REGISTERS_DMA0COUNT, H_COREDMA_REGISTERS_DMA0SRCADDR + , H_COREDMA_REGISTERS_DMA0DSTADDR, H_COREDMA_REGISTERS_DMA0AUTO0, H_COREDMA_REGISTERS_DMA0AUTO1, H_COREDMA_REGISTERS_DMA0STATUS + , H_COREDMA_REGISTERS_DMA1CONFIG, H_COREDMA_REGISTERS_DMA1STRIDE, H_COREDMA_REGISTERS_DMA1COUNT, H_COREDMA_REGISTERS_DMA1SRCADDR + , H_COREDMA_REGISTERS_DMA1DSTADDR, H_COREDMA_REGISTERS_DMA1AUTO0, H_COREDMA_REGISTERS_DMA1AUTO1, H_COREDMA_REGISTERS_DMA1STATUS +} CRDMA_NAMES; + +/* Enum declaration for . */ +typedef enum crmem_names { + H_COREMEM_REGISTERS_MEMCONFIG, H_COREMEM_REGISTERS_MEMSTATUS, H_COREMEM_REGISTERS_MEMPROTECT, H_COREMEM_REGISTERS_MEMRESERVE +} CRMEM_NAMES; + +/* Enum declaration for . */ +typedef enum crmesh_names { + H_COREMESH_REGISTERS_MESHCONFIG, H_COREMESH_REGISTERS_COREID, H_COREMESH_REGISTERS_MESHMULTICAST, H_COREMESH_REGISTERS_SWRESET +} CRMESH_NAMES; + +/* Attributes. */ + +/* Enum declaration for machine type selection. */ +typedef enum mach_attr { + MACH_BASE, MACH_EPIPHANY32, MACH_MAX +} MACH_ATTR; + +/* Enum declaration for instruction set selection. */ +typedef enum isa_attr { + ISA_EPIPHANY, ISA_MAX +} ISA_ATTR; + +/* Number of architecture variants. */ +#define MAX_ISAS 1 +#define MAX_MACHS ((int) MACH_MAX) + +/* Ifield support. */ + +/* Ifield attribute indices. */ + +/* Enum declaration for cgen_ifld attrs. */ +typedef enum cgen_ifld_attr { + CGEN_IFLD_VIRTUAL, CGEN_IFLD_PCREL_ADDR, CGEN_IFLD_ABS_ADDR, CGEN_IFLD_RESERVED + , CGEN_IFLD_SIGN_OPT, CGEN_IFLD_SIGNED, CGEN_IFLD_RELOC, CGEN_IFLD_END_BOOLS + , CGEN_IFLD_START_NBOOLS = 31, CGEN_IFLD_MACH, CGEN_IFLD_END_NBOOLS +} CGEN_IFLD_ATTR; + +/* Number of non-boolean elements in cgen_ifld_attr. */ +#define CGEN_IFLD_NBOOL_ATTRS (CGEN_IFLD_END_NBOOLS - CGEN_IFLD_START_NBOOLS - 1) + +/* cgen_ifld attribute accessor macros. */ +#define CGEN_ATTR_CGEN_IFLD_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_IFLD_MACH-CGEN_IFLD_START_NBOOLS-1].nonbitset) +#define CGEN_ATTR_CGEN_IFLD_VIRTUAL_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_VIRTUAL)) != 0) +#define CGEN_ATTR_CGEN_IFLD_PCREL_ADDR_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_PCREL_ADDR)) != 0) +#define CGEN_ATTR_CGEN_IFLD_ABS_ADDR_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_ABS_ADDR)) != 0) +#define CGEN_ATTR_CGEN_IFLD_RESERVED_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_RESERVED)) != 0) +#define CGEN_ATTR_CGEN_IFLD_SIGN_OPT_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_SIGN_OPT)) != 0) +#define CGEN_ATTR_CGEN_IFLD_SIGNED_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_SIGNED)) != 0) +#define CGEN_ATTR_CGEN_IFLD_RELOC_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_RELOC)) != 0) + +/* Enum declaration for epiphany ifield types. */ +typedef enum ifield_type { + EPIPHANY_F_NIL, EPIPHANY_F_ANYOF, EPIPHANY_F_OPC, EPIPHANY_F_OPC_4_1 + , EPIPHANY_F_OPC_6_3, EPIPHANY_F_OPC_8_5, EPIPHANY_F_OPC_19_4, EPIPHANY_F_CONDCODE + , EPIPHANY_F_SECONDARY_CCS, EPIPHANY_F_SHIFT, EPIPHANY_F_WORDSIZE, EPIPHANY_F_STORE + , EPIPHANY_F_OPC_8_1, EPIPHANY_F_OPC_31_32, EPIPHANY_F_SIMM8, EPIPHANY_F_SIMM24 + , EPIPHANY_F_SDISP3, EPIPHANY_F_DISP3, EPIPHANY_F_DISP8, EPIPHANY_F_IMM8 + , EPIPHANY_F_IMM_27_8, EPIPHANY_F_ADDSUBX, EPIPHANY_F_SUBD, EPIPHANY_F_PM + , EPIPHANY_F_RM, EPIPHANY_F_RN, EPIPHANY_F_RD, EPIPHANY_F_RM_X + , EPIPHANY_F_RN_X, EPIPHANY_F_RD_X, EPIPHANY_F_DC_9_1, EPIPHANY_F_SN + , EPIPHANY_F_SD, EPIPHANY_F_SN_X, EPIPHANY_F_SD_X, EPIPHANY_F_DC_7_4 + , EPIPHANY_F_TRAP_SWI_9_1, EPIPHANY_F_GIEN_GIDIS_9_1, EPIPHANY_F_DC_15_3, EPIPHANY_F_DC_15_7 + , EPIPHANY_F_DC_15_6, EPIPHANY_F_TRAP_NUM, EPIPHANY_F_DC_20_1, EPIPHANY_F_DC_21_1 + , EPIPHANY_F_DC_21_2, EPIPHANY_F_DC_22_3, EPIPHANY_F_DC_22_2, EPIPHANY_F_DC_22_1 + , EPIPHANY_F_DC_25_6, EPIPHANY_F_DC_25_4, EPIPHANY_F_DC_25_2, EPIPHANY_F_DC_25_1 + , EPIPHANY_F_DC_28_1, EPIPHANY_F_DC_31_3, EPIPHANY_F_DISP11, EPIPHANY_F_SDISP11 + , EPIPHANY_F_IMM16, EPIPHANY_F_RD6, EPIPHANY_F_RN6, EPIPHANY_F_RM6 + , EPIPHANY_F_SD6, EPIPHANY_F_SN6, EPIPHANY_F_MAX +} IFIELD_TYPE; + +#define MAX_IFLD ((int) EPIPHANY_F_MAX) + +/* Hardware attribute indices. */ + +/* Enum declaration for cgen_hw attrs. */ +typedef enum cgen_hw_attr { + CGEN_HW_VIRTUAL, CGEN_HW_CACHE_ADDR, CGEN_HW_PC, CGEN_HW_PROFILE + , CGEN_HW_END_BOOLS, CGEN_HW_START_NBOOLS = 31, CGEN_HW_MACH, CGEN_HW_END_NBOOLS +} CGEN_HW_ATTR; + +/* Number of non-boolean elements in cgen_hw_attr. */ +#define CGEN_HW_NBOOL_ATTRS (CGEN_HW_END_NBOOLS - CGEN_HW_START_NBOOLS - 1) + +/* cgen_hw attribute accessor macros. */ +#define CGEN_ATTR_CGEN_HW_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_HW_MACH-CGEN_HW_START_NBOOLS-1].nonbitset) +#define CGEN_ATTR_CGEN_HW_VIRTUAL_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_HW_VIRTUAL)) != 0) +#define CGEN_ATTR_CGEN_HW_CACHE_ADDR_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_HW_CACHE_ADDR)) != 0) +#define CGEN_ATTR_CGEN_HW_PC_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_HW_PC)) != 0) +#define CGEN_ATTR_CGEN_HW_PROFILE_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_HW_PROFILE)) != 0) + +/* Enum declaration for epiphany hardware types. */ +typedef enum cgen_hw_type { + HW_H_MEMORY, HW_H_SINT, HW_H_UINT, HW_H_ADDR + , HW_H_IADDR, HW_H_REGISTERS, HW_H_FPREGISTERS, HW_H_ZBIT + , HW_H_NBIT, HW_H_CBIT, HW_H_VBIT, HW_H_VSBIT + , HW_H_BZBIT, HW_H_BNBIT, HW_H_BVBIT, HW_H_BUBIT + , HW_H_BIBIT, HW_H_BCBIT, HW_H_BVSBIT, HW_H_BISBIT + , HW_H_BUSBIT, HW_H_EXPCAUSE0BIT, HW_H_EXPCAUSE1BIT, HW_H_EXPCAUSE2BIT + , HW_H_EXTFSTALLBIT, HW_H_TRMBIT, HW_H_INVEXCENBIT, HW_H_OVFEXCENBIT + , HW_H_UNEXCENBIT, HW_H_TIMER0BIT0, HW_H_TIMER0BIT1, HW_H_TIMER0BIT2 + , HW_H_TIMER0BIT3, HW_H_TIMER1BIT0, HW_H_TIMER1BIT1, HW_H_TIMER1BIT2 + , HW_H_TIMER1BIT3, HW_H_MBKPTENBIT, HW_H_CLOCKGATEENBIT, HW_H_CORECFGRESBIT12 + , HW_H_CORECFGRESBIT13, HW_H_CORECFGRESBIT14, HW_H_CORECFGRESBIT15, HW_H_CORECFGRESBIT16 + , HW_H_CORECFGRESBIT20, HW_H_CORECFGRESBIT21, HW_H_CORECFGRESBIT24, HW_H_CORECFGRESBIT25 + , HW_H_CORECFGRESBIT26, HW_H_CORECFGRESBIT27, HW_H_CORECFGRESBIT28, HW_H_CORECFGRESBIT29 + , HW_H_CORECFGRESBIT30, HW_H_CORECFGRESBIT31, HW_H_ARITHMETIC_MODEBIT0, HW_H_ARITHMETIC_MODEBIT1 + , HW_H_ARITHMETIC_MODEBIT2, HW_H_GIDISABLEBIT, HW_H_KMBIT, HW_H_CAIBIT + , HW_H_SFLAGBIT, HW_H_PC, HW_H_MEMADDR, HW_H_CORE_REGISTERS + , HW_H_COREDMA_REGISTERS, HW_H_COREMEM_REGISTERS, HW_H_COREMESH_REGISTERS, HW_MAX +} CGEN_HW_TYPE; + +#define MAX_HW ((int) HW_MAX) + +/* Operand attribute indices. */ + +/* Enum declaration for cgen_operand attrs. */ +typedef enum cgen_operand_attr { + CGEN_OPERAND_VIRTUAL, CGEN_OPERAND_PCREL_ADDR, CGEN_OPERAND_ABS_ADDR, CGEN_OPERAND_SIGN_OPT + , CGEN_OPERAND_SIGNED, CGEN_OPERAND_NEGATIVE, CGEN_OPERAND_RELAX, CGEN_OPERAND_SEM_ONLY + , CGEN_OPERAND_RELOC, CGEN_OPERAND_END_BOOLS, CGEN_OPERAND_START_NBOOLS = 31, CGEN_OPERAND_MACH + , CGEN_OPERAND_END_NBOOLS +} CGEN_OPERAND_ATTR; + +/* Number of non-boolean elements in cgen_operand_attr. */ +#define CGEN_OPERAND_NBOOL_ATTRS (CGEN_OPERAND_END_NBOOLS - CGEN_OPERAND_START_NBOOLS - 1) + +/* cgen_operand attribute accessor macros. */ +#define CGEN_ATTR_CGEN_OPERAND_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_OPERAND_MACH-CGEN_OPERAND_START_NBOOLS-1].nonbitset) +#define CGEN_ATTR_CGEN_OPERAND_VIRTUAL_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_VIRTUAL)) != 0) +#define CGEN_ATTR_CGEN_OPERAND_PCREL_ADDR_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_PCREL_ADDR)) != 0) +#define CGEN_ATTR_CGEN_OPERAND_ABS_ADDR_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_ABS_ADDR)) != 0) +#define CGEN_ATTR_CGEN_OPERAND_SIGN_OPT_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_SIGN_OPT)) != 0) +#define CGEN_ATTR_CGEN_OPERAND_SIGNED_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_SIGNED)) != 0) +#define CGEN_ATTR_CGEN_OPERAND_NEGATIVE_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_NEGATIVE)) != 0) +#define CGEN_ATTR_CGEN_OPERAND_RELAX_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_RELAX)) != 0) +#define CGEN_ATTR_CGEN_OPERAND_SEM_ONLY_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_SEM_ONLY)) != 0) +#define CGEN_ATTR_CGEN_OPERAND_RELOC_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_RELOC)) != 0) + +/* Enum declaration for epiphany operand types. */ +typedef enum cgen_operand_type { + EPIPHANY_OPERAND_PC, EPIPHANY_OPERAND_ZBIT, EPIPHANY_OPERAND_NBIT, EPIPHANY_OPERAND_CBIT + , EPIPHANY_OPERAND_VBIT, EPIPHANY_OPERAND_BZBIT, EPIPHANY_OPERAND_BNBIT, EPIPHANY_OPERAND_BVBIT + , EPIPHANY_OPERAND_BCBIT, EPIPHANY_OPERAND_BUBIT, EPIPHANY_OPERAND_BIBIT, EPIPHANY_OPERAND_VSBIT + , EPIPHANY_OPERAND_BVSBIT, EPIPHANY_OPERAND_BISBIT, EPIPHANY_OPERAND_BUSBIT, EPIPHANY_OPERAND_EXPCAUSE0BIT + , EPIPHANY_OPERAND_EXPCAUSE1BIT, EPIPHANY_OPERAND_EXPCAUSE2BIT, EPIPHANY_OPERAND_EXTFSTALLBIT, EPIPHANY_OPERAND_TRMBIT + , EPIPHANY_OPERAND_INVEXCENBIT, EPIPHANY_OPERAND_OVFEXCENBIT, EPIPHANY_OPERAND_UNEXCENBIT, EPIPHANY_OPERAND_TIMER0BIT0 + , EPIPHANY_OPERAND_TIMER0BIT1, EPIPHANY_OPERAND_TIMER0BIT2, EPIPHANY_OPERAND_TIMER0BIT3, EPIPHANY_OPERAND_TIMER1BIT0 + , EPIPHANY_OPERAND_TIMER1BIT1, EPIPHANY_OPERAND_TIMER1BIT2, EPIPHANY_OPERAND_TIMER1BIT3, EPIPHANY_OPERAND_MBKPTENBIT + , EPIPHANY_OPERAND_CLOCKGATEENBIT, EPIPHANY_OPERAND_ARITHMETIC_MODEBIT0, EPIPHANY_OPERAND_ARITHMETIC_MODEBIT1, EPIPHANY_OPERAND_ARITHMETIC_MODEBIT2 + , EPIPHANY_OPERAND_CORECFGRESBIT12, EPIPHANY_OPERAND_CORECFGRESBIT13, EPIPHANY_OPERAND_CORECFGRESBIT14, EPIPHANY_OPERAND_CORECFGRESBIT15 + , EPIPHANY_OPERAND_CORECFGRESBIT16, EPIPHANY_OPERAND_CORECFGRESBIT20, EPIPHANY_OPERAND_CORECFGRESBIT21, EPIPHANY_OPERAND_CORECFGRESBIT24 + , EPIPHANY_OPERAND_CORECFGRESBIT25, EPIPHANY_OPERAND_CORECFGRESBIT26, EPIPHANY_OPERAND_CORECFGRESBIT27, EPIPHANY_OPERAND_CORECFGRESBIT28 + , EPIPHANY_OPERAND_CORECFGRESBIT29, EPIPHANY_OPERAND_CORECFGRESBIT30, EPIPHANY_OPERAND_CORECFGRESBIT31, EPIPHANY_OPERAND_GIDISABLEBIT + , EPIPHANY_OPERAND_KMBIT, EPIPHANY_OPERAND_CAIBIT, EPIPHANY_OPERAND_SFLAGBIT, EPIPHANY_OPERAND_MEMADDR + , EPIPHANY_OPERAND_SIMM24, EPIPHANY_OPERAND_SIMM8, EPIPHANY_OPERAND_RD, EPIPHANY_OPERAND_RN + , EPIPHANY_OPERAND_RM, EPIPHANY_OPERAND_FRD, EPIPHANY_OPERAND_FRN, EPIPHANY_OPERAND_FRM + , EPIPHANY_OPERAND_RD6, EPIPHANY_OPERAND_RN6, EPIPHANY_OPERAND_RM6, EPIPHANY_OPERAND_FRD6 + , EPIPHANY_OPERAND_FRN6, EPIPHANY_OPERAND_FRM6, EPIPHANY_OPERAND_SD, EPIPHANY_OPERAND_SN + , EPIPHANY_OPERAND_SD6, EPIPHANY_OPERAND_SN6, EPIPHANY_OPERAND_SDDMA, EPIPHANY_OPERAND_SNDMA + , EPIPHANY_OPERAND_SDMEM, EPIPHANY_OPERAND_SNMEM, EPIPHANY_OPERAND_SDMESH, EPIPHANY_OPERAND_SNMESH + , EPIPHANY_OPERAND_SIMM3, EPIPHANY_OPERAND_SIMM11, EPIPHANY_OPERAND_DISP3, EPIPHANY_OPERAND_TRAPNUM6 + , EPIPHANY_OPERAND_SWI_NUM, EPIPHANY_OPERAND_DISP11, EPIPHANY_OPERAND_SHIFT, EPIPHANY_OPERAND_IMM16 + , EPIPHANY_OPERAND_IMM8, EPIPHANY_OPERAND_DIRECTION, EPIPHANY_OPERAND_DPMI, EPIPHANY_OPERAND_MAX +} CGEN_OPERAND_TYPE; + +/* Number of operands types. */ +#define MAX_OPERANDS 91 + +/* Maximum number of operands referenced by any insn. */ +#define MAX_OPERAND_INSTANCES 8 + +/* Insn attribute indices. */ + +/* Enum declaration for cgen_insn attrs. */ +typedef enum cgen_insn_attr { + CGEN_INSN_ALIAS, CGEN_INSN_VIRTUAL, CGEN_INSN_UNCOND_CTI, CGEN_INSN_COND_CTI + , CGEN_INSN_SKIP_CTI, CGEN_INSN_DELAY_SLOT, CGEN_INSN_RELAXABLE, CGEN_INSN_RELAXED + , CGEN_INSN_NO_DIS, CGEN_INSN_PBB, CGEN_INSN_SHORT_INSN, CGEN_INSN_IMM3 + , CGEN_INSN_IMM8, CGEN_INSN_END_BOOLS, CGEN_INSN_START_NBOOLS = 31, CGEN_INSN_MACH + , CGEN_INSN_END_NBOOLS +} CGEN_INSN_ATTR; + +/* Number of non-boolean elements in cgen_insn_attr. */ +#define CGEN_INSN_NBOOL_ATTRS (CGEN_INSN_END_NBOOLS - CGEN_INSN_START_NBOOLS - 1) + +/* cgen_insn attribute accessor macros. */ +#define CGEN_ATTR_CGEN_INSN_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_INSN_MACH-CGEN_INSN_START_NBOOLS-1].nonbitset) +#define CGEN_ATTR_CGEN_INSN_ALIAS_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_ALIAS)) != 0) +#define CGEN_ATTR_CGEN_INSN_VIRTUAL_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_VIRTUAL)) != 0) +#define CGEN_ATTR_CGEN_INSN_UNCOND_CTI_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_UNCOND_CTI)) != 0) +#define CGEN_ATTR_CGEN_INSN_COND_CTI_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_COND_CTI)) != 0) +#define CGEN_ATTR_CGEN_INSN_SKIP_CTI_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_SKIP_CTI)) != 0) +#define CGEN_ATTR_CGEN_INSN_DELAY_SLOT_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_DELAY_SLOT)) != 0) +#define CGEN_ATTR_CGEN_INSN_RELAXABLE_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_RELAXABLE)) != 0) +#define CGEN_ATTR_CGEN_INSN_RELAXED_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_RELAXED)) != 0) +#define CGEN_ATTR_CGEN_INSN_NO_DIS_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_NO_DIS)) != 0) +#define CGEN_ATTR_CGEN_INSN_PBB_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_PBB)) != 0) +#define CGEN_ATTR_CGEN_INSN_SHORT_INSN_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_SHORT_INSN)) != 0) +#define CGEN_ATTR_CGEN_INSN_IMM3_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_IMM3)) != 0) +#define CGEN_ATTR_CGEN_INSN_IMM8_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_IMM8)) != 0) + +/* cgen.h uses things we just defined. */ +#include "opcode/cgen.h" + +extern const struct cgen_ifld epiphany_cgen_ifld_table[]; + +/* Attributes. */ +extern const CGEN_ATTR_TABLE epiphany_cgen_hardware_attr_table[]; +extern const CGEN_ATTR_TABLE epiphany_cgen_ifield_attr_table[]; +extern const CGEN_ATTR_TABLE epiphany_cgen_operand_attr_table[]; +extern const CGEN_ATTR_TABLE epiphany_cgen_insn_attr_table[]; + +/* Hardware decls. */ + +extern CGEN_KEYWORD epiphany_cgen_opval_gr_names; +extern CGEN_KEYWORD epiphany_cgen_opval_gr_names; +extern CGEN_KEYWORD epiphany_cgen_opval_cr_names; +extern CGEN_KEYWORD epiphany_cgen_opval_crdma_names; +extern CGEN_KEYWORD epiphany_cgen_opval_crmem_names; +extern CGEN_KEYWORD epiphany_cgen_opval_crmesh_names; + +extern const CGEN_HW_ENTRY epiphany_cgen_hw_table[]; + + + +#endif /* EPIPHANY_CPU_H */ diff --git a/opcodes/epiphany-dis.c b/opcodes/epiphany-dis.c new file mode 100644 index 00000000000..bd86f46219b --- /dev/null +++ b/opcodes/epiphany-dis.c @@ -0,0 +1,698 @@ +/* Disassembler interface for targets using CGEN. -*- C -*- + CGEN: Cpu tools GENerator + + THIS FILE IS MACHINE GENERATED WITH CGEN. + - the resultant file is machine generated, cgen-dis.in isn't + + Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2005, 2007, + 2008, 2010 Free Software Foundation, Inc. + + This file is part of libopcodes. + + This library is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + It is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software Foundation, Inc., + 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ + +/* ??? Eventually more and more of this stuff can go to cpu-independent files. + Keep that in mind. */ + +#include "sysdep.h" +#include <stdio.h> +#include "ansidecl.h" +#include "dis-asm.h" +#include "bfd.h" +#include "symcat.h" +#include "libiberty.h" +#include "epiphany-desc.h" +#include "epiphany-opc.h" +#include "opintl.h" + +/* Default text to print if an instruction isn't recognized. */ +#define UNKNOWN_INSN_MSG _("*unknown*") + +static void print_normal + (CGEN_CPU_DESC, void *, long, unsigned int, bfd_vma, int); +static void print_address + (CGEN_CPU_DESC, void *, bfd_vma, unsigned int, bfd_vma, int) ATTRIBUTE_UNUSED; +static void print_keyword + (CGEN_CPU_DESC, void *, CGEN_KEYWORD *, long, unsigned int) ATTRIBUTE_UNUSED; +static void print_insn_normal + (CGEN_CPU_DESC, void *, const CGEN_INSN *, CGEN_FIELDS *, bfd_vma, int); +static int print_insn + (CGEN_CPU_DESC, bfd_vma, disassemble_info *, bfd_byte *, unsigned); +static int default_print_insn + (CGEN_CPU_DESC, bfd_vma, disassemble_info *) ATTRIBUTE_UNUSED; +static int read_insn + (CGEN_CPU_DESC, bfd_vma, disassemble_info *, bfd_byte *, int, CGEN_EXTRACT_INFO *, + unsigned long *); + +/* -- disassembler routines inserted here. */ + +/* -- dis.c */ + +#define CGEN_PRINT_INSN epiphany_print_insn + +static int +epiphany_print_insn (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info) +{ + bfd_byte buf[CGEN_MAX_INSN_SIZE]; + int buflen; + int status; + + info->bytes_per_chunk = 2; + + /* Attempt to read the base part of the insn. */ + info->bytes_per_line = buflen = cd->base_insn_bitsize / 8; + status = (*info->read_memory_func) (pc, buf, buflen, info); + + /* Try again with the minimum part, if min < base. */ + if (status != 0 && (cd->min_insn_bitsize < cd->base_insn_bitsize)) + { + info->bytes_per_line = buflen = cd->min_insn_bitsize / 8; + status = (*info->read_memory_func) (pc, buf, buflen, info); + } + + if (status != 0) + { + (*info->memory_error_func) (status, pc, info); + return -1; + } + + return print_insn (cd, pc, info, buf, buflen); +} + + +static void +print_postindex (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + void * dis_info, + long value, + unsigned int attrs ATTRIBUTE_UNUSED, + bfd_vma pc ATTRIBUTE_UNUSED, + int length ATTRIBUTE_UNUSED) +{ + disassemble_info *info = (disassemble_info *) dis_info; + (*info->fprintf_func) (info->stream, value ? "-" : "+"); +} + +static void +print_simm_not_reg (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + void * dis_info, + long value, + unsigned int attrs ATTRIBUTE_UNUSED, + bfd_vma pc ATTRIBUTE_UNUSED, + int length ATTRIBUTE_UNUSED) +{ + print_address (cd, dis_info, value, attrs, pc, length); +} + +static void +print_uimm_not_reg (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + void * dis_info, + unsigned long value, + unsigned int attrs ATTRIBUTE_UNUSED, + bfd_vma pc ATTRIBUTE_UNUSED, + int length ATTRIBUTE_UNUSED) +{ + disassemble_info *info = (disassemble_info *)dis_info; + + if (value & 0x800) + (*info->fprintf_func) (info->stream, "-"); + + value &= 0x7ff; + print_address (cd, dis_info, value, attrs, pc, length); +} + + +/* -- */ + +void epiphany_cgen_print_operand + (CGEN_CPU_DESC, int, PTR, CGEN_FIELDS *, void const *, bfd_vma, int); + +/* Main entry point for printing operands. + XINFO is a `void *' and not a `disassemble_info *' to not put a requirement + of dis-asm.h on cgen.h. + + This function is basically just a big switch statement. Earlier versions + used tables to look up the function to use, but + - if the table contains both assembler and disassembler functions then + the disassembler contains much of the assembler and vice-versa, + - there's a lot of inlining possibilities as things grow, + - using a switch statement avoids the function call overhead. + + This function could be moved into `print_insn_normal', but keeping it + separate makes clear the interface between `print_insn_normal' and each of + the handlers. */ + +void +epiphany_cgen_print_operand (CGEN_CPU_DESC cd, + int opindex, + void * xinfo, + CGEN_FIELDS *fields, + void const *attrs ATTRIBUTE_UNUSED, + bfd_vma pc, + int length) +{ + disassemble_info *info = (disassemble_info *) xinfo; + + switch (opindex) + { + case EPIPHANY_OPERAND_DIRECTION : + print_postindex (cd, info, fields->f_addsubx, 0, pc, length); + break; + case EPIPHANY_OPERAND_DISP11 : + print_uimm_not_reg (cd, info, fields->f_disp11, 0|(1<<CGEN_OPERAND_VIRTUAL), pc, length); + break; + case EPIPHANY_OPERAND_DISP3 : + print_normal (cd, info, fields->f_disp3, 0, pc, length); + break; + case EPIPHANY_OPERAND_DPMI : + print_postindex (cd, info, fields->f_subd, 0, pc, length); + break; + case EPIPHANY_OPERAND_FRD : + print_keyword (cd, info, & epiphany_cgen_opval_gr_names, fields->f_rd, 0); + break; + case EPIPHANY_OPERAND_FRD6 : + print_keyword (cd, info, & epiphany_cgen_opval_gr_names, fields->f_rd6, 0|(1<<CGEN_OPERAND_VIRTUAL)); + break; + case EPIPHANY_OPERAND_FRM : + print_keyword (cd, info, & epiphany_cgen_opval_gr_names, fields->f_rm, 0); + break; + case EPIPHANY_OPERAND_FRM6 : + print_keyword (cd, info, & epiphany_cgen_opval_gr_names, fields->f_rm6, 0|(1<<CGEN_OPERAND_VIRTUAL)); + break; + case EPIPHANY_OPERAND_FRN : + print_keyword (cd, info, & epiphany_cgen_opval_gr_names, fields->f_rn, 0); + break; + case EPIPHANY_OPERAND_FRN6 : + print_keyword (cd, info, & epiphany_cgen_opval_gr_names, fields->f_rn6, 0|(1<<CGEN_OPERAND_VIRTUAL)); + break; + case EPIPHANY_OPERAND_IMM16 : + print_address (cd, info, fields->f_imm16, 0|(1<<CGEN_OPERAND_RELAX)|(1<<CGEN_OPERAND_VIRTUAL), pc, length); + break; + case EPIPHANY_OPERAND_IMM8 : + print_address (cd, info, fields->f_imm8, 0|(1<<CGEN_OPERAND_RELAX), pc, length); + break; + case EPIPHANY_OPERAND_RD : + print_keyword (cd, info, & epiphany_cgen_opval_gr_names, fields->f_rd, 0); + break; + case EPIPHANY_OPERAND_RD6 : + print_keyword (cd, info, & epiphany_cgen_opval_gr_names, fields->f_rd6, 0|(1<<CGEN_OPERAND_VIRTUAL)); + break; + case EPIPHANY_OPERAND_RM : + print_keyword (cd, info, & epiphany_cgen_opval_gr_names, fields->f_rm, 0); + break; + case EPIPHANY_OPERAND_RM6 : + print_keyword (cd, info, & epiphany_cgen_opval_gr_names, fields->f_rm6, 0|(1<<CGEN_OPERAND_VIRTUAL)); + break; + case EPIPHANY_OPERAND_RN : + print_keyword (cd, info, & epiphany_cgen_opval_gr_names, fields->f_rn, 0); + break; + case EPIPHANY_OPERAND_RN6 : + print_keyword (cd, info, & epiphany_cgen_opval_gr_names, fields->f_rn6, 0|(1<<CGEN_OPERAND_VIRTUAL)); + break; + case EPIPHANY_OPERAND_SD : + print_keyword (cd, info, & epiphany_cgen_opval_cr_names, fields->f_sd, 0); + break; + case EPIPHANY_OPERAND_SD6 : + print_keyword (cd, info, & epiphany_cgen_opval_cr_names, fields->f_sd6, 0|(1<<CGEN_OPERAND_VIRTUAL)); + break; + case EPIPHANY_OPERAND_SDDMA : + print_keyword (cd, info, & epiphany_cgen_opval_crdma_names, fields->f_sd6, 0|(1<<CGEN_OPERAND_VIRTUAL)); + break; + case EPIPHANY_OPERAND_SDMEM : + print_keyword (cd, info, & epiphany_cgen_opval_crmem_names, fields->f_sd6, 0|(1<<CGEN_OPERAND_VIRTUAL)); + break; + case EPIPHANY_OPERAND_SDMESH : + print_keyword (cd, info, & epiphany_cgen_opval_crmesh_names, fields->f_sd6, 0|(1<<CGEN_OPERAND_VIRTUAL)); + break; + case EPIPHANY_OPERAND_SHIFT : + print_normal (cd, info, fields->f_shift, 0, pc, length); + break; + case EPIPHANY_OPERAND_SIMM11 : + print_simm_not_reg (cd, info, fields->f_sdisp11, 0|(1<<CGEN_OPERAND_SIGNED)|(1<<CGEN_OPERAND_RELAX)|(1<<CGEN_OPERAND_VIRTUAL), pc, length); + break; + case EPIPHANY_OPERAND_SIMM24 : + print_address (cd, info, fields->f_simm24, 0|(1<<CGEN_OPERAND_RELAX)|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), pc, length); + break; + case EPIPHANY_OPERAND_SIMM3 : + print_simm_not_reg (cd, info, fields->f_sdisp3, 0|(1<<CGEN_OPERAND_SIGNED)|(1<<CGEN_OPERAND_RELAX), pc, length); + break; + case EPIPHANY_OPERAND_SIMM8 : + print_address (cd, info, fields->f_simm8, 0|(1<<CGEN_OPERAND_RELAX)|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), pc, length); + break; + case EPIPHANY_OPERAND_SN : + print_keyword (cd, info, & epiphany_cgen_opval_cr_names, fields->f_sn, 0); + break; + case EPIPHANY_OPERAND_SN6 : + print_keyword (cd, info, & epiphany_cgen_opval_cr_names, fields->f_sn6, 0|(1<<CGEN_OPERAND_VIRTUAL)); + break; + case EPIPHANY_OPERAND_SNDMA : + print_keyword (cd, info, & epiphany_cgen_opval_crdma_names, fields->f_sn6, 0|(1<<CGEN_OPERAND_VIRTUAL)); + break; + case EPIPHANY_OPERAND_SNMEM : + print_keyword (cd, info, & epiphany_cgen_opval_crmem_names, fields->f_sn6, 0|(1<<CGEN_OPERAND_VIRTUAL)); + break; + case EPIPHANY_OPERAND_SNMESH : + print_keyword (cd, info, & epiphany_cgen_opval_crmesh_names, fields->f_sn6, 0|(1<<CGEN_OPERAND_VIRTUAL)); + break; + case EPIPHANY_OPERAND_SWI_NUM : + print_uimm_not_reg (cd, info, fields->f_trap_num, 0, pc, length); + break; + case EPIPHANY_OPERAND_TRAPNUM6 : + print_normal (cd, info, fields->f_trap_num, 0, pc, length); + break; + + default : + /* xgettext:c-format */ + fprintf (stderr, _("Unrecognized field %d while printing insn.\n"), + opindex); + abort (); + } +} + +cgen_print_fn * const epiphany_cgen_print_handlers[] = +{ + print_insn_normal, +}; + + +void +epiphany_cgen_init_dis (CGEN_CPU_DESC cd) +{ + epiphany_cgen_init_opcode_table (cd); + epiphany_cgen_init_ibld_table (cd); + cd->print_handlers = & epiphany_cgen_print_handlers[0]; + cd->print_operand = epiphany_cgen_print_operand; +} + + +/* Default print handler. */ + +static void +print_normal (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + void *dis_info, + long value, + unsigned int attrs, + bfd_vma pc ATTRIBUTE_UNUSED, + int length ATTRIBUTE_UNUSED) +{ + disassemble_info *info = (disassemble_info *) dis_info; + + /* Print the operand as directed by the attributes. */ + if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SEM_ONLY)) + ; /* nothing to do */ + else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SIGNED)) + (*info->fprintf_func) (info->stream, "%ld", value); + else + (*info->fprintf_func) (info->stream, "0x%lx", value); +} + +/* Default address handler. */ + +static void +print_address (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + void *dis_info, + bfd_vma value, + unsigned int attrs, + bfd_vma pc ATTRIBUTE_UNUSED, + int length ATTRIBUTE_UNUSED) +{ + disassemble_info *info = (disassemble_info *) dis_info; + + /* Print the operand as directed by the attributes. */ + if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SEM_ONLY)) + ; /* Nothing to do. */ + else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_PCREL_ADDR)) + (*info->print_address_func) (value, info); + else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_ABS_ADDR)) + (*info->print_address_func) (value, info); + else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SIGNED)) + (*info->fprintf_func) (info->stream, "%ld", (long) value); + else + (*info->fprintf_func) (info->stream, "0x%lx", (long) value); +} + +/* Keyword print handler. */ + +static void +print_keyword (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + void *dis_info, + CGEN_KEYWORD *keyword_table, + long value, + unsigned int attrs ATTRIBUTE_UNUSED) +{ + disassemble_info *info = (disassemble_info *) dis_info; + const CGEN_KEYWORD_ENTRY *ke; + + ke = cgen_keyword_lookup_value (keyword_table, value); + if (ke != NULL) + (*info->fprintf_func) (info->stream, "%s", ke->name); + else + (*info->fprintf_func) (info->stream, "???"); +} + +/* Default insn printer. + + DIS_INFO is defined as `void *' so the disassembler needn't know anything + about disassemble_info. */ + +static void +print_insn_normal (CGEN_CPU_DESC cd, + void *dis_info, + const CGEN_INSN *insn, + CGEN_FIELDS *fields, + bfd_vma pc, + int length) +{ + const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn); + disassemble_info *info = (disassemble_info *) dis_info; + const CGEN_SYNTAX_CHAR_TYPE *syn; + + CGEN_INIT_PRINT (cd); + + for (syn = CGEN_SYNTAX_STRING (syntax); *syn; ++syn) + { + if (CGEN_SYNTAX_MNEMONIC_P (*syn)) + { + (*info->fprintf_func) (info->stream, "%s", CGEN_INSN_MNEMONIC (insn)); + continue; + } + if (CGEN_SYNTAX_CHAR_P (*syn)) + { + (*info->fprintf_func) (info->stream, "%c", CGEN_SYNTAX_CHAR (*syn)); + continue; + } + + /* We have an operand. */ + epiphany_cgen_print_operand (cd, CGEN_SYNTAX_FIELD (*syn), info, + fields, CGEN_INSN_ATTRS (insn), pc, length); + } +} + +/* Subroutine of print_insn. Reads an insn into the given buffers and updates + the extract info. + Returns 0 if all is well, non-zero otherwise. */ + +static int +read_insn (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + bfd_vma pc, + disassemble_info *info, + bfd_byte *buf, + int buflen, + CGEN_EXTRACT_INFO *ex_info, + unsigned long *insn_value) +{ + int status = (*info->read_memory_func) (pc, buf, buflen, info); + + if (status != 0) + { + (*info->memory_error_func) (status, pc, info); + return -1; + } + + ex_info->dis_info = info; + ex_info->valid = (1 << buflen) - 1; + ex_info->insn_bytes = buf; + + *insn_value = bfd_get_bits (buf, buflen * 8, info->endian == BFD_ENDIAN_BIG); + return 0; +} + +/* Utility to print an insn. + BUF is the base part of the insn, target byte order, BUFLEN bytes long. + The result is the size of the insn in bytes or zero for an unknown insn + or -1 if an error occurs fetching data (memory_error_func will have + been called). */ + +static int +print_insn (CGEN_CPU_DESC cd, + bfd_vma pc, + disassemble_info *info, + bfd_byte *buf, + unsigned int buflen) +{ + CGEN_INSN_INT insn_value; + const CGEN_INSN_LIST *insn_list; + CGEN_EXTRACT_INFO ex_info; + int basesize; + + /* Extract base part of instruction, just in case CGEN_DIS_* uses it. */ + basesize = cd->base_insn_bitsize < buflen * 8 ? + cd->base_insn_bitsize : buflen * 8; + insn_value = cgen_get_insn_value (cd, buf, basesize); + + + /* Fill in ex_info fields like read_insn would. Don't actually call + read_insn, since the incoming buffer is already read (and possibly + modified a la m32r). */ + ex_info.valid = (1 << buflen) - 1; + ex_info.dis_info = info; + ex_info.insn_bytes = buf; + + /* The instructions are stored in hash lists. + Pick the first one and keep trying until we find the right one. */ + + insn_list = CGEN_DIS_LOOKUP_INSN (cd, (char *) buf, insn_value); + while (insn_list != NULL) + { + const CGEN_INSN *insn = insn_list->insn; + CGEN_FIELDS fields; + int length; + unsigned long insn_value_cropped; + +#ifdef CGEN_VALIDATE_INSN_SUPPORTED + /* Not needed as insn shouldn't be in hash lists if not supported. */ + /* Supported by this cpu? */ + if (! epiphany_cgen_insn_supported (cd, insn)) + { + insn_list = CGEN_DIS_NEXT_INSN (insn_list); + continue; + } +#endif + + /* Basic bit mask must be correct. */ + /* ??? May wish to allow target to defer this check until the extract + handler. */ + + /* Base size may exceed this instruction's size. Extract the + relevant part from the buffer. */ + if ((unsigned) (CGEN_INSN_BITSIZE (insn) / 8) < buflen && + (unsigned) (CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long)) + insn_value_cropped = bfd_get_bits (buf, CGEN_INSN_BITSIZE (insn), + info->endian == BFD_ENDIAN_BIG); + else + insn_value_cropped = insn_value; + + if ((insn_value_cropped & CGEN_INSN_BASE_MASK (insn)) + == CGEN_INSN_BASE_VALUE (insn)) + { + /* Printing is handled in two passes. The first pass parses the + machine insn and extracts the fields. The second pass prints + them. */ + + /* Make sure the entire insn is loaded into insn_value, if it + can fit. */ + if (((unsigned) CGEN_INSN_BITSIZE (insn) > cd->base_insn_bitsize) && + (unsigned) (CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long)) + { + unsigned long full_insn_value; + int rc = read_insn (cd, pc, info, buf, + CGEN_INSN_BITSIZE (insn) / 8, + & ex_info, & full_insn_value); + if (rc != 0) + return rc; + length = CGEN_EXTRACT_FN (cd, insn) + (cd, insn, &ex_info, full_insn_value, &fields, pc); + } + else + length = CGEN_EXTRACT_FN (cd, insn) + (cd, insn, &ex_info, insn_value_cropped, &fields, pc); + + /* Length < 0 -> error. */ + if (length < 0) + return length; + if (length > 0) + { + CGEN_PRINT_FN (cd, insn) (cd, info, insn, &fields, pc, length); + /* Length is in bits, result is in bytes. */ + return length / 8; + } + } + + insn_list = CGEN_DIS_NEXT_INSN (insn_list); + } + + return 0; +} + +/* Default value for CGEN_PRINT_INSN. + The result is the size of the insn in bytes or zero for an unknown insn + or -1 if an error occured fetching bytes. */ + +#ifndef CGEN_PRINT_INSN +#define CGEN_PRINT_INSN default_print_insn +#endif + +static int +default_print_insn (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info) +{ + bfd_byte buf[CGEN_MAX_INSN_SIZE]; + int buflen; + int status; + + /* Attempt to read the base part of the insn. */ + buflen = cd->base_insn_bitsize / 8; + status = (*info->read_memory_func) (pc, buf, buflen, info); + + /* Try again with the minimum part, if min < base. */ + if (status != 0 && (cd->min_insn_bitsize < cd->base_insn_bitsize)) + { + buflen = cd->min_insn_bitsize / 8; + status = (*info->read_memory_func) (pc, buf, buflen, info); + } + + if (status != 0) + { + (*info->memory_error_func) (status, pc, info); + return -1; + } + + return print_insn (cd, pc, info, buf, buflen); +} + +/* Main entry point. + Print one instruction from PC on INFO->STREAM. + Return the size of the instruction (in bytes). */ + +typedef struct cpu_desc_list +{ + struct cpu_desc_list *next; + CGEN_BITSET *isa; + int mach; + int endian; + CGEN_CPU_DESC cd; +} cpu_desc_list; + +int +print_insn_epiphany (bfd_vma pc, disassemble_info *info) +{ + static cpu_desc_list *cd_list = 0; + cpu_desc_list *cl = 0; + static CGEN_CPU_DESC cd = 0; + static CGEN_BITSET *prev_isa; + static int prev_mach; + static int prev_endian; + int length; + CGEN_BITSET *isa; + int mach; + int endian = (info->endian == BFD_ENDIAN_BIG + ? CGEN_ENDIAN_BIG + : CGEN_ENDIAN_LITTLE); + enum bfd_architecture arch; + + /* ??? gdb will set mach but leave the architecture as "unknown" */ +#ifndef CGEN_BFD_ARCH +#define CGEN_BFD_ARCH bfd_arch_epiphany +#endif + arch = info->arch; + if (arch == bfd_arch_unknown) + arch = CGEN_BFD_ARCH; + + /* There's no standard way to compute the machine or isa number + so we leave it to the target. */ +#ifdef CGEN_COMPUTE_MACH + mach = CGEN_COMPUTE_MACH (info); +#else + mach = info->mach; +#endif + +#ifdef CGEN_COMPUTE_ISA + { + static CGEN_BITSET *permanent_isa; + + if (!permanent_isa) + permanent_isa = cgen_bitset_create (MAX_ISAS); + isa = permanent_isa; + cgen_bitset_clear (isa); + cgen_bitset_add (isa, CGEN_COMPUTE_ISA (info)); + } +#else + isa = info->insn_sets; +#endif + + /* If we've switched cpu's, try to find a handle we've used before */ + if (cd + && (cgen_bitset_compare (isa, prev_isa) != 0 + || mach != prev_mach + || endian != prev_endian)) + { + cd = 0; + for (cl = cd_list; cl; cl = cl->next) + { + if (cgen_bitset_compare (cl->isa, isa) == 0 && + cl->mach == mach && + cl->endian == endian) + { + cd = cl->cd; + prev_isa = cd->isas; + break; + } + } + } + + /* If we haven't initialized yet, initialize the opcode table. */ + if (! cd) + { + const bfd_arch_info_type *arch_type = bfd_lookup_arch (arch, mach); + const char *mach_name; + + if (!arch_type) + abort (); + mach_name = arch_type->printable_name; + + prev_isa = cgen_bitset_copy (isa); + prev_mach = mach; + prev_endian = endian; + cd = epiphany_cgen_cpu_open (CGEN_CPU_OPEN_ISAS, prev_isa, + CGEN_CPU_OPEN_BFDMACH, mach_name, + CGEN_CPU_OPEN_ENDIAN, prev_endian, + CGEN_CPU_OPEN_END); + if (!cd) + abort (); + + /* Save this away for future reference. */ + cl = xmalloc (sizeof (struct cpu_desc_list)); + cl->cd = cd; + cl->isa = prev_isa; + cl->mach = mach; + cl->endian = endian; + cl->next = cd_list; + cd_list = cl; + + epiphany_cgen_init_dis (cd); + } + + /* We try to have as much common code as possible. + But at this point some targets need to take over. */ + /* ??? Some targets may need a hook elsewhere. Try to avoid this, + but if not possible try to move this hook elsewhere rather than + have two hooks. */ + length = CGEN_PRINT_INSN (cd, pc, info); + if (length > 0) + return length; + if (length < 0) + return -1; + + (*info->fprintf_func) (info->stream, UNKNOWN_INSN_MSG); + return cd->default_insn_bitsize / 8; +} diff --git a/opcodes/epiphany-ibld.c b/opcodes/epiphany-ibld.c new file mode 100644 index 00000000000..7b332d5a4cc --- /dev/null +++ b/opcodes/epiphany-ibld.c @@ -0,0 +1,1709 @@ +/* Instruction building/extraction support for epiphany. -*- C -*- + + THIS FILE IS MACHINE GENERATED WITH CGEN: Cpu tools GENerator. + - the resultant file is machine generated, cgen-ibld.in isn't + + Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2005, 2006, 2007, + 2008, 2010 Free Software Foundation, Inc. + + This file is part of libopcodes. + + This library is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + It is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software Foundation, Inc., + 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ + +/* ??? Eventually more and more of this stuff can go to cpu-independent files. + Keep that in mind. */ + +#include "sysdep.h" +#include <stdio.h> +#include "ansidecl.h" +#include "dis-asm.h" +#include "bfd.h" +#include "symcat.h" +#include "epiphany-desc.h" +#include "epiphany-opc.h" +#include "cgen/basic-modes.h" +#include "opintl.h" +#include "safe-ctype.h" + +#undef min +#define min(a,b) ((a) < (b) ? (a) : (b)) +#undef max +#define max(a,b) ((a) > (b) ? (a) : (b)) + +/* Used by the ifield rtx function. */ +#define FLD(f) (fields->f) + +static const char * insert_normal + (CGEN_CPU_DESC, long, unsigned int, unsigned int, unsigned int, + unsigned int, unsigned int, unsigned int, CGEN_INSN_BYTES_PTR); +static const char * insert_insn_normal + (CGEN_CPU_DESC, const CGEN_INSN *, + CGEN_FIELDS *, CGEN_INSN_BYTES_PTR, bfd_vma); +static int extract_normal + (CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, CGEN_INSN_INT, + unsigned int, unsigned int, unsigned int, unsigned int, + unsigned int, unsigned int, bfd_vma, long *); +static int extract_insn_normal + (CGEN_CPU_DESC, const CGEN_INSN *, CGEN_EXTRACT_INFO *, + CGEN_INSN_INT, CGEN_FIELDS *, bfd_vma); +#if CGEN_INT_INSN_P +static void put_insn_int_value + (CGEN_CPU_DESC, CGEN_INSN_BYTES_PTR, int, int, CGEN_INSN_INT); +#endif +#if ! CGEN_INT_INSN_P +static CGEN_INLINE void insert_1 + (CGEN_CPU_DESC, unsigned long, int, int, int, unsigned char *); +static CGEN_INLINE int fill_cache + (CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, int, int, bfd_vma); +static CGEN_INLINE long extract_1 + (CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, int, int, int, unsigned char *, bfd_vma); +#endif + +/* Operand insertion. */ + +#if ! CGEN_INT_INSN_P + +/* Subroutine of insert_normal. */ + +static CGEN_INLINE void +insert_1 (CGEN_CPU_DESC cd, + unsigned long value, + int start, + int length, + int word_length, + unsigned char *bufp) +{ + unsigned long x,mask; + int shift; + + x = cgen_get_insn_value (cd, bufp, word_length); + + /* Written this way to avoid undefined behaviour. */ + mask = (((1L << (length - 1)) - 1) << 1) | 1; + if (CGEN_INSN_LSB0_P) + shift = (start + 1) - length; + else + shift = (word_length - (start + length)); + x = (x & ~(mask << shift)) | ((value & mask) << shift); + + cgen_put_insn_value (cd, bufp, word_length, (bfd_vma) x); +} + +#endif /* ! CGEN_INT_INSN_P */ + +/* Default insertion routine. + + ATTRS is a mask of the boolean attributes. + WORD_OFFSET is the offset in bits from the start of the insn of the value. + WORD_LENGTH is the length of the word in bits in which the value resides. + START is the starting bit number in the word, architecture origin. + LENGTH is the length of VALUE in bits. + TOTAL_LENGTH is the total length of the insn in bits. + + The result is an error message or NULL if success. */ + +/* ??? This duplicates functionality with bfd's howto table and + bfd_install_relocation. */ +/* ??? This doesn't handle bfd_vma's. Create another function when + necessary. */ + +static const char * +insert_normal (CGEN_CPU_DESC cd, + long value, + unsigned int attrs, + unsigned int word_offset, + unsigned int start, + unsigned int length, + unsigned int word_length, + unsigned int total_length, + CGEN_INSN_BYTES_PTR buffer) +{ + static char errbuf[100]; + /* Written this way to avoid undefined behaviour. */ + unsigned long mask = (((1L << (length - 1)) - 1) << 1) | 1; + + /* If LENGTH is zero, this operand doesn't contribute to the value. */ + if (length == 0) + return NULL; + + if (word_length > 8 * sizeof (CGEN_INSN_INT)) + abort (); + + /* For architectures with insns smaller than the base-insn-bitsize, + word_length may be too big. */ + if (cd->min_insn_bitsize < cd->base_insn_bitsize) + { + if (word_offset == 0 + && word_length > total_length) + word_length = total_length; + } + + /* Ensure VALUE will fit. */ + if (CGEN_BOOL_ATTR (attrs, CGEN_IFLD_SIGN_OPT)) + { + long minval = - (1L << (length - 1)); + unsigned long maxval = mask; + + if ((value > 0 && (unsigned long) value > maxval) + || value < minval) + { + /* xgettext:c-format */ + sprintf (errbuf, + _("operand out of range (%ld not between %ld and %lu)"), + value, minval, maxval); + return errbuf; + } + } + else if (! CGEN_BOOL_ATTR (attrs, CGEN_IFLD_SIGNED)) + { + unsigned long maxval = mask; + unsigned long val = (unsigned long) value; + + /* For hosts with a word size > 32 check to see if value has been sign + extended beyond 32 bits. If so then ignore these higher sign bits + as the user is attempting to store a 32-bit signed value into an + unsigned 32-bit field which is allowed. */ + if (sizeof (unsigned long) > 4 && ((value >> 32) == -1)) + val &= 0xFFFFFFFF; + + if (val > maxval) + { + /* xgettext:c-format */ + sprintf (errbuf, + _("operand out of range (0x%lx not between 0 and 0x%lx)"), + val, maxval); + return errbuf; + } + } + else + { + if (! cgen_signed_overflow_ok_p (cd)) + { + long minval = - (1L << (length - 1)); + long maxval = (1L << (length - 1)) - 1; + + if (value < minval || value > maxval) + { + sprintf + /* xgettext:c-format */ + (errbuf, _("operand out of range (%ld not between %ld and %ld)"), + value, minval, maxval); + return errbuf; + } + } + } + +#if CGEN_INT_INSN_P + + { + int shift; + + if (CGEN_INSN_LSB0_P) + shift = (word_offset + start + 1) - length; + else + shift = total_length - (word_offset + start + length); + *buffer = (*buffer & ~(mask << shift)) | ((value & mask) << shift); + } + +#else /* ! CGEN_INT_INSN_P */ + + { + unsigned char *bufp = (unsigned char *) buffer + word_offset / 8; + + insert_1 (cd, value, start, length, word_length, bufp); + } + +#endif /* ! CGEN_INT_INSN_P */ + + return NULL; +} + +/* Default insn builder (insert handler). + The instruction is recorded in CGEN_INT_INSN_P byte order (meaning + that if CGEN_INSN_BYTES_PTR is an int * and thus, the value is + recorded in host byte order, otherwise BUFFER is an array of bytes + and the value is recorded in target byte order). + The result is an error message or NULL if success. */ + +static const char * +insert_insn_normal (CGEN_CPU_DESC cd, + const CGEN_INSN * insn, + CGEN_FIELDS * fields, + CGEN_INSN_BYTES_PTR buffer, + bfd_vma pc) +{ + const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn); + unsigned long value; + const CGEN_SYNTAX_CHAR_TYPE * syn; + + CGEN_INIT_INSERT (cd); + value = CGEN_INSN_BASE_VALUE (insn); + + /* If we're recording insns as numbers (rather than a string of bytes), + target byte order handling is deferred until later. */ + +#if CGEN_INT_INSN_P + + put_insn_int_value (cd, buffer, cd->base_insn_bitsize, + CGEN_FIELDS_BITSIZE (fields), value); + +#else + + cgen_put_insn_value (cd, buffer, min ((unsigned) cd->base_insn_bitsize, + (unsigned) CGEN_FIELDS_BITSIZE (fields)), + value); + +#endif /* ! CGEN_INT_INSN_P */ + + /* ??? It would be better to scan the format's fields. + Still need to be able to insert a value based on the operand though; + e.g. storing a branch displacement that got resolved later. + Needs more thought first. */ + + for (syn = CGEN_SYNTAX_STRING (syntax); * syn; ++ syn) + { + const char *errmsg; + + if (CGEN_SYNTAX_CHAR_P (* syn)) + continue; + + errmsg = (* cd->insert_operand) (cd, CGEN_SYNTAX_FIELD (*syn), + fields, buffer, pc); + if (errmsg) + return errmsg; + } + + return NULL; +} + +#if CGEN_INT_INSN_P +/* Cover function to store an insn value into an integral insn. Must go here + because it needs <prefix>-desc.h for CGEN_INT_INSN_P. */ + +static void +put_insn_int_value (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + CGEN_INSN_BYTES_PTR buf, + int length, + int insn_length, + CGEN_INSN_INT value) +{ + /* For architectures with insns smaller than the base-insn-bitsize, + length may be too big. */ + if (length > insn_length) + *buf = value; + else + { + int shift = insn_length - length; + /* Written this way to avoid undefined behaviour. */ + CGEN_INSN_INT mask = (((1L << (length - 1)) - 1) << 1) | 1; + + *buf = (*buf & ~(mask << shift)) | ((value & mask) << shift); + } +} +#endif + +/* Operand extraction. */ + +#if ! CGEN_INT_INSN_P + +/* Subroutine of extract_normal. + Ensure sufficient bytes are cached in EX_INFO. + OFFSET is the offset in bytes from the start of the insn of the value. + BYTES is the length of the needed value. + Returns 1 for success, 0 for failure. */ + +static CGEN_INLINE int +fill_cache (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + CGEN_EXTRACT_INFO *ex_info, + int offset, + int bytes, + bfd_vma pc) +{ + /* It's doubtful that the middle part has already been fetched so + we don't optimize that case. kiss. */ + unsigned int mask; + disassemble_info *info = (disassemble_info *) ex_info->dis_info; + + /* First do a quick check. */ + mask = (1 << bytes) - 1; + if (((ex_info->valid >> offset) & mask) == mask) + return 1; + + /* Search for the first byte we need to read. */ + for (mask = 1 << offset; bytes > 0; --bytes, ++offset, mask <<= 1) + if (! (mask & ex_info->valid)) + break; + + if (bytes) + { + int status; + + pc += offset; + status = (*info->read_memory_func) + (pc, ex_info->insn_bytes + offset, bytes, info); + + if (status != 0) + { + (*info->memory_error_func) (status, pc, info); + return 0; + } + + ex_info->valid |= ((1 << bytes) - 1) << offset; + } + + return 1; +} + +/* Subroutine of extract_normal. */ + +static CGEN_INLINE long +extract_1 (CGEN_CPU_DESC cd, + CGEN_EXTRACT_INFO *ex_info ATTRIBUTE_UNUSED, + int start, + int length, + int word_length, + unsigned char *bufp, + bfd_vma pc ATTRIBUTE_UNUSED) +{ + unsigned long x; + int shift; + + x = cgen_get_insn_value (cd, bufp, word_length); + + if (CGEN_INSN_LSB0_P) + shift = (start + 1) - length; + else + shift = (word_length - (start + length)); + return x >> shift; +} + +#endif /* ! CGEN_INT_INSN_P */ + +/* Default extraction routine. + + INSN_VALUE is the first base_insn_bitsize bits of the insn in host order, + or sometimes less for cases like the m32r where the base insn size is 32 + but some insns are 16 bits. + ATTRS is a mask of the boolean attributes. We only need `SIGNED', + but for generality we take a bitmask of all of them. + WORD_OFFSET is the offset in bits from the start of the insn of the value. + WORD_LENGTH is the length of the word in bits in which the value resides. + START is the starting bit number in the word, architecture origin. + LENGTH is the length of VALUE in bits. + TOTAL_LENGTH is the total length of the insn in bits. + + Returns 1 for success, 0 for failure. */ + +/* ??? The return code isn't properly used. wip. */ + +/* ??? This doesn't handle bfd_vma's. Create another function when + necessary. */ + +static int +extract_normal (CGEN_CPU_DESC cd, +#if ! CGEN_INT_INSN_P + CGEN_EXTRACT_INFO *ex_info, +#else + CGEN_EXTRACT_INFO *ex_info ATTRIBUTE_UNUSED, +#endif + CGEN_INSN_INT insn_value, + unsigned int attrs, + unsigned int word_offset, + unsigned int start, + unsigned int length, + unsigned int word_length, + unsigned int total_length, +#if ! CGEN_INT_INSN_P + bfd_vma pc, +#else + bfd_vma pc ATTRIBUTE_UNUSED, +#endif + long *valuep) +{ + long value, mask; + + /* If LENGTH is zero, this operand doesn't contribute to the value + so give it a standard value of zero. */ + if (length == 0) + { + *valuep = 0; + return 1; + } + + if (word_length > 8 * sizeof (CGEN_INSN_INT)) + abort (); + + /* For architectures with insns smaller than the insn-base-bitsize, + word_length may be too big. */ + if (cd->min_insn_bitsize < cd->base_insn_bitsize) + { + if (word_offset + word_length > total_length) + word_length = total_length - word_offset; + } + + /* Does the value reside in INSN_VALUE, and at the right alignment? */ + + if (CGEN_INT_INSN_P || (word_offset == 0 && word_length == total_length)) + { + if (CGEN_INSN_LSB0_P) + value = insn_value >> ((word_offset + start + 1) - length); + else + value = insn_value >> (total_length - ( word_offset + start + length)); + } + +#if ! CGEN_INT_INSN_P + + else + { + unsigned char *bufp = ex_info->insn_bytes + word_offset / 8; + + if (word_length > 8 * sizeof (CGEN_INSN_INT)) + abort (); + + if (fill_cache (cd, ex_info, word_offset / 8, word_length / 8, pc) == 0) + return 0; + + value = extract_1 (cd, ex_info, start, length, word_length, bufp, pc); + } + +#endif /* ! CGEN_INT_INSN_P */ + + /* Written this way to avoid undefined behaviour. */ + mask = (((1L << (length - 1)) - 1) << 1) | 1; + + value &= mask; + /* sign extend? */ + if (CGEN_BOOL_ATTR (attrs, CGEN_IFLD_SIGNED) + && (value & (1L << (length - 1)))) + value |= ~mask; + + *valuep = value; + + return 1; +} + +/* Default insn extractor. + + INSN_VALUE is the first base_insn_bitsize bits, translated to host order. + The extracted fields are stored in FIELDS. + EX_INFO is used to handle reading variable length insns. + Return the length of the insn in bits, or 0 if no match, + or -1 if an error occurs fetching data (memory_error_func will have + been called). */ + +static int +extract_insn_normal (CGEN_CPU_DESC cd, + const CGEN_INSN *insn, + CGEN_EXTRACT_INFO *ex_info, + CGEN_INSN_INT insn_value, + CGEN_FIELDS *fields, + bfd_vma pc) +{ + const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn); + const CGEN_SYNTAX_CHAR_TYPE *syn; + + CGEN_FIELDS_BITSIZE (fields) = CGEN_INSN_BITSIZE (insn); + + CGEN_INIT_EXTRACT (cd); + + for (syn = CGEN_SYNTAX_STRING (syntax); *syn; ++syn) + { + int length; + + if (CGEN_SYNTAX_CHAR_P (*syn)) + continue; + + length = (* cd->extract_operand) (cd, CGEN_SYNTAX_FIELD (*syn), + ex_info, insn_value, fields, pc); + if (length <= 0) + return length; + } + + /* We recognized and successfully extracted this insn. */ + return CGEN_INSN_BITSIZE (insn); +} + +/* Machine generated code added here. */ + +const char * epiphany_cgen_insert_operand + (CGEN_CPU_DESC, int, CGEN_FIELDS *, CGEN_INSN_BYTES_PTR, bfd_vma); + +/* Main entry point for operand insertion. + + This function is basically just a big switch statement. Earlier versions + used tables to look up the function to use, but + - if the table contains both assembler and disassembler functions then + the disassembler contains much of the assembler and vice-versa, + - there's a lot of inlining possibilities as things grow, + - using a switch statement avoids the function call overhead. + + This function could be moved into `parse_insn_normal', but keeping it + separate makes clear the interface between `parse_insn_normal' and each of + the handlers. It's also needed by GAS to insert operands that couldn't be + resolved during parsing. */ + +const char * +epiphany_cgen_insert_operand (CGEN_CPU_DESC cd, + int opindex, + CGEN_FIELDS * fields, + CGEN_INSN_BYTES_PTR buffer, + bfd_vma pc ATTRIBUTE_UNUSED) +{ + const char * errmsg = NULL; + unsigned int total_length = CGEN_FIELDS_BITSIZE (fields); + + switch (opindex) + { + case EPIPHANY_OPERAND_DIRECTION : + errmsg = insert_normal (cd, fields->f_addsubx, 0, 0, 20, 1, 32, total_length, buffer); + break; + case EPIPHANY_OPERAND_DISP11 : + { +{ + FLD (f_disp8) = ((((UINT) (FLD (f_disp11)) >> (3))) & (255)); + FLD (f_disp3) = ((FLD (f_disp11)) & (7)); +} + errmsg = insert_normal (cd, fields->f_disp3, 0, 0, 9, 3, 32, total_length, buffer); + if (errmsg) + break; + errmsg = insert_normal (cd, fields->f_disp8, 0, 0, 23, 8, 32, total_length, buffer); + if (errmsg) + break; + } + break; + case EPIPHANY_OPERAND_DISP3 : + errmsg = insert_normal (cd, fields->f_disp3, 0, 0, 9, 3, 32, total_length, buffer); + break; + case EPIPHANY_OPERAND_DPMI : + errmsg = insert_normal (cd, fields->f_subd, 0, 0, 24, 1, 32, total_length, buffer); + break; + case EPIPHANY_OPERAND_FRD : + errmsg = insert_normal (cd, fields->f_rd, 0, 0, 15, 3, 32, total_length, buffer); + break; + case EPIPHANY_OPERAND_FRD6 : + { +{ + FLD (f_rd) = ((FLD (f_rd6)) & (7)); + FLD (f_rd_x) = ((UINT) (FLD (f_rd6)) >> (3)); +} + errmsg = insert_normal (cd, fields->f_rd_x, 0, 0, 31, 3, 32, total_length, buffer); + if (errmsg) + break; + errmsg = insert_normal (cd, fields->f_rd, 0, 0, 15, 3, 32, total_length, buffer); + if (errmsg) + break; + } + break; + case EPIPHANY_OPERAND_FRM : + errmsg = insert_normal (cd, fields->f_rm, 0, 0, 9, 3, 32, total_length, buffer); + break; + case EPIPHANY_OPERAND_FRM6 : + { +{ + FLD (f_rm) = ((FLD (f_rm6)) & (7)); + FLD (f_rm_x) = ((UINT) (FLD (f_rm6)) >> (3)); +} + errmsg = insert_normal (cd, fields->f_rm_x, 0, 0, 25, 3, 32, total_length, buffer); + if (errmsg) + break; + errmsg = insert_normal (cd, fields->f_rm, 0, 0, 9, 3, 32, total_length, buffer); + if (errmsg) + break; + } + break; + case EPIPHANY_OPERAND_FRN : + errmsg = insert_normal (cd, fields->f_rn, 0, 0, 12, 3, 32, total_length, buffer); + break; + case EPIPHANY_OPERAND_FRN6 : + { +{ + FLD (f_rn) = ((FLD (f_rn6)) & (7)); + FLD (f_rn_x) = ((UINT) (FLD (f_rn6)) >> (3)); +} + errmsg = insert_normal (cd, fields->f_rn_x, 0, 0, 28, 3, 32, total_length, buffer); + if (errmsg) + break; + errmsg = insert_normal (cd, fields->f_rn, 0, 0, 12, 3, 32, total_length, buffer); + if (errmsg) + break; + } + break; + case EPIPHANY_OPERAND_IMM16 : + { +{ + FLD (f_imm8) = ((FLD (f_imm16)) & (255)); + FLD (f_imm_27_8) = ((UINT) (FLD (f_imm16)) >> (8)); +} + errmsg = insert_normal (cd, fields->f_imm8, 0, 0, 12, 8, 32, total_length, buffer); + if (errmsg) + break; + errmsg = insert_normal (cd, fields->f_imm_27_8, 0, 0, 27, 8, 32, total_length, buffer); + if (errmsg) + break; + } + break; + case EPIPHANY_OPERAND_IMM8 : + errmsg = insert_normal (cd, fields->f_imm8, 0, 0, 12, 8, 32, total_length, buffer); + break; + case EPIPHANY_OPERAND_RD : + errmsg = insert_normal (cd, fields->f_rd, 0, 0, 15, 3, 32, total_length, buffer); + break; + case EPIPHANY_OPERAND_RD6 : + { +{ + FLD (f_rd) = ((FLD (f_rd6)) & (7)); + FLD (f_rd_x) = ((UINT) (FLD (f_rd6)) >> (3)); +} + errmsg = insert_normal (cd, fields->f_rd_x, 0, 0, 31, 3, 32, total_length, buffer); + if (errmsg) + break; + errmsg = insert_normal (cd, fields->f_rd, 0, 0, 15, 3, 32, total_length, buffer); + if (errmsg) + break; + } + break; + case EPIPHANY_OPERAND_RM : + errmsg = insert_normal (cd, fields->f_rm, 0, 0, 9, 3, 32, total_length, buffer); + break; + case EPIPHANY_OPERAND_RM6 : + { +{ + FLD (f_rm) = ((FLD (f_rm6)) & (7)); + FLD (f_rm_x) = ((UINT) (FLD (f_rm6)) >> (3)); +} + errmsg = insert_normal (cd, fields->f_rm_x, 0, 0, 25, 3, 32, total_length, buffer); + if (errmsg) + break; + errmsg = insert_normal (cd, fields->f_rm, 0, 0, 9, 3, 32, total_length, buffer); + if (errmsg) + break; + } + break; + case EPIPHANY_OPERAND_RN : + errmsg = insert_normal (cd, fields->f_rn, 0, 0, 12, 3, 32, total_length, buffer); + break; + case EPIPHANY_OPERAND_RN6 : + { +{ + FLD (f_rn) = ((FLD (f_rn6)) & (7)); + FLD (f_rn_x) = ((UINT) (FLD (f_rn6)) >> (3)); +} + errmsg = insert_normal (cd, fields->f_rn_x, 0, 0, 28, 3, 32, total_length, buffer); + if (errmsg) + break; + errmsg = insert_normal (cd, fields->f_rn, 0, 0, 12, 3, 32, total_length, buffer); + if (errmsg) + break; + } + break; + case EPIPHANY_OPERAND_SD : + errmsg = insert_normal (cd, fields->f_sd, 0, 0, 15, 3, 32, total_length, buffer); + break; + case EPIPHANY_OPERAND_SD6 : + { +{ + FLD (f_sd) = ((FLD (f_sd6)) & (7)); + FLD (f_sd_x) = ((UINT) (FLD (f_sd6)) >> (3)); +} + errmsg = insert_normal (cd, fields->f_sd_x, 0, 0, 31, 3, 32, total_length, buffer); + if (errmsg) + break; + errmsg = insert_normal (cd, fields->f_sd, 0, 0, 15, 3, 32, total_length, buffer); + if (errmsg) + break; + } + break; + case EPIPHANY_OPERAND_SDDMA : + { +{ + FLD (f_sd) = ((FLD (f_sd6)) & (7)); + FLD (f_sd_x) = ((UINT) (FLD (f_sd6)) >> (3)); +} + errmsg = insert_normal (cd, fields->f_sd_x, 0, 0, 31, 3, 32, total_length, buffer); + if (errmsg) + break; + errmsg = insert_normal (cd, fields->f_sd, 0, 0, 15, 3, 32, total_length, buffer); + if (errmsg) + break; + } + break; + case EPIPHANY_OPERAND_SDMEM : + { +{ + FLD (f_sd) = ((FLD (f_sd6)) & (7)); + FLD (f_sd_x) = ((UINT) (FLD (f_sd6)) >> (3)); +} + errmsg = insert_normal (cd, fields->f_sd_x, 0, 0, 31, 3, 32, total_length, buffer); + if (errmsg) + break; + errmsg = insert_normal (cd, fields->f_sd, 0, 0, 15, 3, 32, total_length, buffer); + if (errmsg) + break; + } + break; + case EPIPHANY_OPERAND_SDMESH : + { +{ + FLD (f_sd) = ((FLD (f_sd6)) & (7)); + FLD (f_sd_x) = ((UINT) (FLD (f_sd6)) >> (3)); +} + errmsg = insert_normal (cd, fields->f_sd_x, 0, 0, 31, 3, 32, total_length, buffer); + if (errmsg) + break; + errmsg = insert_normal (cd, fields->f_sd, 0, 0, 15, 3, 32, total_length, buffer); + if (errmsg) + break; + } + break; + case EPIPHANY_OPERAND_SHIFT : + errmsg = insert_normal (cd, fields->f_shift, 0, 0, 9, 5, 32, total_length, buffer); + break; + case EPIPHANY_OPERAND_SIMM11 : + { +{ + FLD (f_disp8) = ((255) & (((USI) (FLD (f_sdisp11)) >> (3)))); + FLD (f_disp3) = ((FLD (f_sdisp11)) & (7)); +} + errmsg = insert_normal (cd, fields->f_disp3, 0, 0, 9, 3, 32, total_length, buffer); + if (errmsg) + break; + errmsg = insert_normal (cd, fields->f_disp8, 0, 0, 23, 8, 32, total_length, buffer); + if (errmsg) + break; + } + break; + case EPIPHANY_OPERAND_SIMM24 : + { + long value = fields->f_simm24; + value = ((SI) (((value) - (pc))) >> (1)); + errmsg = insert_normal (cd, value, 0|(1<<CGEN_IFLD_SIGNED)|(1<<CGEN_IFLD_RELOC)|(1<<CGEN_IFLD_PCREL_ADDR), 0, 31, 24, 32, total_length, buffer); + } + break; + case EPIPHANY_OPERAND_SIMM3 : + errmsg = insert_normal (cd, fields->f_sdisp3, 0|(1<<CGEN_IFLD_SIGNED), 0, 9, 3, 32, total_length, buffer); + break; + case EPIPHANY_OPERAND_SIMM8 : + { + long value = fields->f_simm8; + value = ((SI) (((value) - (pc))) >> (1)); + errmsg = insert_normal (cd, value, 0|(1<<CGEN_IFLD_SIGNED)|(1<<CGEN_IFLD_RELOC)|(1<<CGEN_IFLD_PCREL_ADDR), 0, 15, 8, 32, total_length, buffer); + } + break; + case EPIPHANY_OPERAND_SN : + errmsg = insert_normal (cd, fields->f_sn, 0, 0, 12, 3, 32, total_length, buffer); + break; + case EPIPHANY_OPERAND_SN6 : + { +{ + FLD (f_sn) = ((FLD (f_sn6)) & (7)); + FLD (f_sn_x) = ((UINT) (FLD (f_sn6)) >> (3)); +} + errmsg = insert_normal (cd, fields->f_sn_x, 0, 0, 28, 3, 32, total_length, buffer); + if (errmsg) + break; + errmsg = insert_normal (cd, fields->f_sn, 0, 0, 12, 3, 32, total_length, buffer); + if (errmsg) + break; + } + break; + case EPIPHANY_OPERAND_SNDMA : + { +{ + FLD (f_sn) = ((FLD (f_sn6)) & (7)); + FLD (f_sn_x) = ((UINT) (FLD (f_sn6)) >> (3)); +} + errmsg = insert_normal (cd, fields->f_sn_x, 0, 0, 28, 3, 32, total_length, buffer); + if (errmsg) + break; + errmsg = insert_normal (cd, fields->f_sn, 0, 0, 12, 3, 32, total_length, buffer); + if (errmsg) + break; + } + break; + case EPIPHANY_OPERAND_SNMEM : + { +{ + FLD (f_sn) = ((FLD (f_sn6)) & (7)); + FLD (f_sn_x) = ((UINT) (FLD (f_sn6)) >> (3)); +} + errmsg = insert_normal (cd, fields->f_sn_x, 0, 0, 28, 3, 32, total_length, buffer); + if (errmsg) + break; + errmsg = insert_normal (cd, fields->f_sn, 0, 0, 12, 3, 32, total_length, buffer); + if (errmsg) + break; + } + break; + case EPIPHANY_OPERAND_SNMESH : + { +{ + FLD (f_sn) = ((FLD (f_sn6)) & (7)); + FLD (f_sn_x) = ((UINT) (FLD (f_sn6)) >> (3)); +} + errmsg = insert_normal (cd, fields->f_sn_x, 0, 0, 28, 3, 32, total_length, buffer); + if (errmsg) + break; + errmsg = insert_normal (cd, fields->f_sn, 0, 0, 12, 3, 32, total_length, buffer); + if (errmsg) + break; + } + break; + case EPIPHANY_OPERAND_SWI_NUM : + errmsg = insert_normal (cd, fields->f_trap_num, 0, 0, 15, 6, 32, total_length, buffer); + break; + case EPIPHANY_OPERAND_TRAPNUM6 : + errmsg = insert_normal (cd, fields->f_trap_num, 0, 0, 15, 6, 32, total_length, buffer); + break; + + default : + /* xgettext:c-format */ + fprintf (stderr, _("Unrecognized field %d while building insn.\n"), + opindex); + abort (); + } + + return errmsg; +} + +int epiphany_cgen_extract_operand + (CGEN_CPU_DESC, int, CGEN_EXTRACT_INFO *, CGEN_INSN_INT, CGEN_FIELDS *, bfd_vma); + +/* Main entry point for operand extraction. + The result is <= 0 for error, >0 for success. + ??? Actual values aren't well defined right now. + + This function is basically just a big switch statement. Earlier versions + used tables to look up the function to use, but + - if the table contains both assembler and disassembler functions then + the disassembler contains much of the assembler and vice-versa, + - there's a lot of inlining possibilities as things grow, + - using a switch statement avoids the function call overhead. + + This function could be moved into `print_insn_normal', but keeping it + separate makes clear the interface between `print_insn_normal' and each of + the handlers. */ + +int +epiphany_cgen_extract_operand (CGEN_CPU_DESC cd, + int opindex, + CGEN_EXTRACT_INFO *ex_info, + CGEN_INSN_INT insn_value, + CGEN_FIELDS * fields, + bfd_vma pc) +{ + /* Assume success (for those operands that are nops). */ + int length = 1; + unsigned int total_length = CGEN_FIELDS_BITSIZE (fields); + + switch (opindex) + { + case EPIPHANY_OPERAND_DIRECTION : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 20, 1, 32, total_length, pc, & fields->f_addsubx); + break; + case EPIPHANY_OPERAND_DISP11 : + { + length = extract_normal (cd, ex_info, insn_value, 0, 0, 9, 3, 32, total_length, pc, & fields->f_disp3); + if (length <= 0) break; + length = extract_normal (cd, ex_info, insn_value, 0, 0, 23, 8, 32, total_length, pc, & fields->f_disp8); + if (length <= 0) break; +{ + FLD (f_disp11) = ((((FLD (f_disp8)) << (3))) | (FLD (f_disp3))); +} + } + break; + case EPIPHANY_OPERAND_DISP3 : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 9, 3, 32, total_length, pc, & fields->f_disp3); + break; + case EPIPHANY_OPERAND_DPMI : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 24, 1, 32, total_length, pc, & fields->f_subd); + break; + case EPIPHANY_OPERAND_FRD : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 3, 32, total_length, pc, & fields->f_rd); + break; + case EPIPHANY_OPERAND_FRD6 : + { + length = extract_normal (cd, ex_info, insn_value, 0, 0, 31, 3, 32, total_length, pc, & fields->f_rd_x); + if (length <= 0) break; + length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 3, 32, total_length, pc, & fields->f_rd); + if (length <= 0) break; +{ + FLD (f_rd6) = ((((FLD (f_rd_x)) << (3))) | (FLD (f_rd))); +} + } + break; + case EPIPHANY_OPERAND_FRM : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 9, 3, 32, total_length, pc, & fields->f_rm); + break; + case EPIPHANY_OPERAND_FRM6 : + { + length = extract_normal (cd, ex_info, insn_value, 0, 0, 25, 3, 32, total_length, pc, & fields->f_rm_x); + if (length <= 0) break; + length = extract_normal (cd, ex_info, insn_value, 0, 0, 9, 3, 32, total_length, pc, & fields->f_rm); + if (length <= 0) break; +{ + FLD (f_rm6) = ((((FLD (f_rm_x)) << (3))) | (FLD (f_rm))); +} + } + break; + case EPIPHANY_OPERAND_FRN : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 12, 3, 32, total_length, pc, & fields->f_rn); + break; + case EPIPHANY_OPERAND_FRN6 : + { + length = extract_normal (cd, ex_info, insn_value, 0, 0, 28, 3, 32, total_length, pc, & fields->f_rn_x); + if (length <= 0) break; + length = extract_normal (cd, ex_info, insn_value, 0, 0, 12, 3, 32, total_length, pc, & fields->f_rn); + if (length <= 0) break; +{ + FLD (f_rn6) = ((((FLD (f_rn_x)) << (3))) | (FLD (f_rn))); +} + } + break; + case EPIPHANY_OPERAND_IMM16 : + { + length = extract_normal (cd, ex_info, insn_value, 0, 0, 12, 8, 32, total_length, pc, & fields->f_imm8); + if (length <= 0) break; + length = extract_normal (cd, ex_info, insn_value, 0, 0, 27, 8, 32, total_length, pc, & fields->f_imm_27_8); + if (length <= 0) break; +{ + FLD (f_imm16) = ((((FLD (f_imm_27_8)) << (8))) | (FLD (f_imm8))); +} + } + break; + case EPIPHANY_OPERAND_IMM8 : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 12, 8, 32, total_length, pc, & fields->f_imm8); + break; + case EPIPHANY_OPERAND_RD : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 3, 32, total_length, pc, & fields->f_rd); + break; + case EPIPHANY_OPERAND_RD6 : + { + length = extract_normal (cd, ex_info, insn_value, 0, 0, 31, 3, 32, total_length, pc, & fields->f_rd_x); + if (length <= 0) break; + length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 3, 32, total_length, pc, & fields->f_rd); + if (length <= 0) break; +{ + FLD (f_rd6) = ((((FLD (f_rd_x)) << (3))) | (FLD (f_rd))); +} + } + break; + case EPIPHANY_OPERAND_RM : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 9, 3, 32, total_length, pc, & fields->f_rm); + break; + case EPIPHANY_OPERAND_RM6 : + { + length = extract_normal (cd, ex_info, insn_value, 0, 0, 25, 3, 32, total_length, pc, & fields->f_rm_x); + if (length <= 0) break; + length = extract_normal (cd, ex_info, insn_value, 0, 0, 9, 3, 32, total_length, pc, & fields->f_rm); + if (length <= 0) break; +{ + FLD (f_rm6) = ((((FLD (f_rm_x)) << (3))) | (FLD (f_rm))); +} + } + break; + case EPIPHANY_OPERAND_RN : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 12, 3, 32, total_length, pc, & fields->f_rn); + break; + case EPIPHANY_OPERAND_RN6 : + { + length = extract_normal (cd, ex_info, insn_value, 0, 0, 28, 3, 32, total_length, pc, & fields->f_rn_x); + if (length <= 0) break; + length = extract_normal (cd, ex_info, insn_value, 0, 0, 12, 3, 32, total_length, pc, & fields->f_rn); + if (length <= 0) break; +{ + FLD (f_rn6) = ((((FLD (f_rn_x)) << (3))) | (FLD (f_rn))); +} + } + break; + case EPIPHANY_OPERAND_SD : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 3, 32, total_length, pc, & fields->f_sd); + break; + case EPIPHANY_OPERAND_SD6 : + { + length = extract_normal (cd, ex_info, insn_value, 0, 0, 31, 3, 32, total_length, pc, & fields->f_sd_x); + if (length <= 0) break; + length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 3, 32, total_length, pc, & fields->f_sd); + if (length <= 0) break; +{ + FLD (f_sd6) = ((((FLD (f_sd_x)) << (3))) | (FLD (f_sd))); +} + } + break; + case EPIPHANY_OPERAND_SDDMA : + { + length = extract_normal (cd, ex_info, insn_value, 0, 0, 31, 3, 32, total_length, pc, & fields->f_sd_x); + if (length <= 0) break; + length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 3, 32, total_length, pc, & fields->f_sd); + if (length <= 0) break; +{ + FLD (f_sd6) = ((((FLD (f_sd_x)) << (3))) | (FLD (f_sd))); +} + } + break; + case EPIPHANY_OPERAND_SDMEM : + { + length = extract_normal (cd, ex_info, insn_value, 0, 0, 31, 3, 32, total_length, pc, & fields->f_sd_x); + if (length <= 0) break; + length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 3, 32, total_length, pc, & fields->f_sd); + if (length <= 0) break; +{ + FLD (f_sd6) = ((((FLD (f_sd_x)) << (3))) | (FLD (f_sd))); +} + } + break; + case EPIPHANY_OPERAND_SDMESH : + { + length = extract_normal (cd, ex_info, insn_value, 0, 0, 31, 3, 32, total_length, pc, & fields->f_sd_x); + if (length <= 0) break; + length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 3, 32, total_length, pc, & fields->f_sd); + if (length <= 0) break; +{ + FLD (f_sd6) = ((((FLD (f_sd_x)) << (3))) | (FLD (f_sd))); +} + } + break; + case EPIPHANY_OPERAND_SHIFT : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 9, 5, 32, total_length, pc, & fields->f_shift); + break; + case EPIPHANY_OPERAND_SIMM11 : + { + length = extract_normal (cd, ex_info, insn_value, 0, 0, 9, 3, 32, total_length, pc, & fields->f_disp3); + if (length <= 0) break; + length = extract_normal (cd, ex_info, insn_value, 0, 0, 23, 8, 32, total_length, pc, & fields->f_disp8); + if (length <= 0) break; +{ + FLD (f_sdisp11) = ((SI) (((((((FLD (f_disp8)) << (3))) | (FLD (f_disp3)))) << (21))) >> (21)); +} + } + break; + case EPIPHANY_OPERAND_SIMM24 : + { + long value; + length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED)|(1<<CGEN_IFLD_RELOC)|(1<<CGEN_IFLD_PCREL_ADDR), 0, 31, 24, 32, total_length, pc, & value); + value = ((((value) << (1))) + (pc)); + fields->f_simm24 = value; + } + break; + case EPIPHANY_OPERAND_SIMM3 : + length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED), 0, 9, 3, 32, total_length, pc, & fields->f_sdisp3); + break; + case EPIPHANY_OPERAND_SIMM8 : + { + long value; + length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED)|(1<<CGEN_IFLD_RELOC)|(1<<CGEN_IFLD_PCREL_ADDR), 0, 15, 8, 32, total_length, pc, & value); + value = ((((value) << (1))) + (pc)); + fields->f_simm8 = value; + } + break; + case EPIPHANY_OPERAND_SN : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 12, 3, 32, total_length, pc, & fields->f_sn); + break; + case EPIPHANY_OPERAND_SN6 : + { + length = extract_normal (cd, ex_info, insn_value, 0, 0, 28, 3, 32, total_length, pc, & fields->f_sn_x); + if (length <= 0) break; + length = extract_normal (cd, ex_info, insn_value, 0, 0, 12, 3, 32, total_length, pc, & fields->f_sn); + if (length <= 0) break; +{ + FLD (f_sn6) = ((((FLD (f_sn_x)) << (3))) | (FLD (f_sn))); +} + } + break; + case EPIPHANY_OPERAND_SNDMA : + { + length = extract_normal (cd, ex_info, insn_value, 0, 0, 28, 3, 32, total_length, pc, & fields->f_sn_x); + if (length <= 0) break; + length = extract_normal (cd, ex_info, insn_value, 0, 0, 12, 3, 32, total_length, pc, & fields->f_sn); + if (length <= 0) break; +{ + FLD (f_sn6) = ((((FLD (f_sn_x)) << (3))) | (FLD (f_sn))); +} + } + break; + case EPIPHANY_OPERAND_SNMEM : + { + length = extract_normal (cd, ex_info, insn_value, 0, 0, 28, 3, 32, total_length, pc, & fields->f_sn_x); + if (length <= 0) break; + length = extract_normal (cd, ex_info, insn_value, 0, 0, 12, 3, 32, total_length, pc, & fields->f_sn); + if (length <= 0) break; +{ + FLD (f_sn6) = ((((FLD (f_sn_x)) << (3))) | (FLD (f_sn))); +} + } + break; + case EPIPHANY_OPERAND_SNMESH : + { + length = extract_normal (cd, ex_info, insn_value, 0, 0, 28, 3, 32, total_length, pc, & fields->f_sn_x); + if (length <= 0) break; + length = extract_normal (cd, ex_info, insn_value, 0, 0, 12, 3, 32, total_length, pc, & fields->f_sn); + if (length <= 0) break; +{ + FLD (f_sn6) = ((((FLD (f_sn_x)) << (3))) | (FLD (f_sn))); +} + } + break; + case EPIPHANY_OPERAND_SWI_NUM : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 6, 32, total_length, pc, & fields->f_trap_num); + break; + case EPIPHANY_OPERAND_TRAPNUM6 : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 6, 32, total_length, pc, & fields->f_trap_num); + break; + + default : + /* xgettext:c-format */ + fprintf (stderr, _("Unrecognized field %d while decoding insn.\n"), + opindex); + abort (); + } + + return length; +} + +cgen_insert_fn * const epiphany_cgen_insert_handlers[] = +{ + insert_insn_normal, +}; + +cgen_extract_fn * const epiphany_cgen_extract_handlers[] = +{ + extract_insn_normal, +}; + +int epiphany_cgen_get_int_operand (CGEN_CPU_DESC, int, const CGEN_FIELDS *); +bfd_vma epiphany_cgen_get_vma_operand (CGEN_CPU_DESC, int, const CGEN_FIELDS *); + +/* Getting values from cgen_fields is handled by a collection of functions. + They are distinguished by the type of the VALUE argument they return. + TODO: floating point, inlining support, remove cases where result type + not appropriate. */ + +int +epiphany_cgen_get_int_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + int opindex, + const CGEN_FIELDS * fields) +{ + int value; + + switch (opindex) + { + case EPIPHANY_OPERAND_DIRECTION : + value = fields->f_addsubx; + break; + case EPIPHANY_OPERAND_DISP11 : + value = fields->f_disp11; + break; + case EPIPHANY_OPERAND_DISP3 : + value = fields->f_disp3; + break; + case EPIPHANY_OPERAND_DPMI : + value = fields->f_subd; + break; + case EPIPHANY_OPERAND_FRD : + value = fields->f_rd; + break; + case EPIPHANY_OPERAND_FRD6 : + value = fields->f_rd6; + break; + case EPIPHANY_OPERAND_FRM : + value = fields->f_rm; + break; + case EPIPHANY_OPERAND_FRM6 : + value = fields->f_rm6; + break; + case EPIPHANY_OPERAND_FRN : + value = fields->f_rn; + break; + case EPIPHANY_OPERAND_FRN6 : + value = fields->f_rn6; + break; + case EPIPHANY_OPERAND_IMM16 : + value = fields->f_imm16; + break; + case EPIPHANY_OPERAND_IMM8 : + value = fields->f_imm8; + break; + case EPIPHANY_OPERAND_RD : + value = fields->f_rd; + break; + case EPIPHANY_OPERAND_RD6 : + value = fields->f_rd6; + break; + case EPIPHANY_OPERAND_RM : + value = fields->f_rm; + break; + case EPIPHANY_OPERAND_RM6 : + value = fields->f_rm6; + break; + case EPIPHANY_OPERAND_RN : + value = fields->f_rn; + break; + case EPIPHANY_OPERAND_RN6 : + value = fields->f_rn6; + break; + case EPIPHANY_OPERAND_SD : + value = fields->f_sd; + break; + case EPIPHANY_OPERAND_SD6 : + value = fields->f_sd6; + break; + case EPIPHANY_OPERAND_SDDMA : + value = fields->f_sd6; + break; + case EPIPHANY_OPERAND_SDMEM : + value = fields->f_sd6; + break; + case EPIPHANY_OPERAND_SDMESH : + value = fields->f_sd6; + break; + case EPIPHANY_OPERAND_SHIFT : + value = fields->f_shift; + break; + case EPIPHANY_OPERAND_SIMM11 : + value = fields->f_sdisp11; + break; + case EPIPHANY_OPERAND_SIMM24 : + value = fields->f_simm24; + break; + case EPIPHANY_OPERAND_SIMM3 : + value = fields->f_sdisp3; + break; + case EPIPHANY_OPERAND_SIMM8 : + value = fields->f_simm8; + break; + case EPIPHANY_OPERAND_SN : + value = fields->f_sn; + break; + case EPIPHANY_OPERAND_SN6 : + value = fields->f_sn6; + break; + case EPIPHANY_OPERAND_SNDMA : + value = fields->f_sn6; + break; + case EPIPHANY_OPERAND_SNMEM : + value = fields->f_sn6; + break; + case EPIPHANY_OPERAND_SNMESH : + value = fields->f_sn6; + break; + case EPIPHANY_OPERAND_SWI_NUM : + value = fields->f_trap_num; + break; + case EPIPHANY_OPERAND_TRAPNUM6 : + value = fields->f_trap_num; + break; + + default : + /* xgettext:c-format */ + fprintf (stderr, _("Unrecognized field %d while getting int operand.\n"), + opindex); + abort (); + } + + return value; +} + +bfd_vma +epiphany_cgen_get_vma_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + int opindex, + const CGEN_FIELDS * fields) +{ + bfd_vma value; + + switch (opindex) + { + case EPIPHANY_OPERAND_DIRECTION : + value = fields->f_addsubx; + break; + case EPIPHANY_OPERAND_DISP11 : + value = fields->f_disp11; + break; + case EPIPHANY_OPERAND_DISP3 : + value = fields->f_disp3; + break; + case EPIPHANY_OPERAND_DPMI : + value = fields->f_subd; + break; + case EPIPHANY_OPERAND_FRD : + value = fields->f_rd; + break; + case EPIPHANY_OPERAND_FRD6 : + value = fields->f_rd6; + break; + case EPIPHANY_OPERAND_FRM : + value = fields->f_rm; + break; + case EPIPHANY_OPERAND_FRM6 : + value = fields->f_rm6; + break; + case EPIPHANY_OPERAND_FRN : + value = fields->f_rn; + break; + case EPIPHANY_OPERAND_FRN6 : + value = fields->f_rn6; + break; + case EPIPHANY_OPERAND_IMM16 : + value = fields->f_imm16; + break; + case EPIPHANY_OPERAND_IMM8 : + value = fields->f_imm8; + break; + case EPIPHANY_OPERAND_RD : + value = fields->f_rd; + break; + case EPIPHANY_OPERAND_RD6 : + value = fields->f_rd6; + break; + case EPIPHANY_OPERAND_RM : + value = fields->f_rm; + break; + case EPIPHANY_OPERAND_RM6 : + value = fields->f_rm6; + break; + case EPIPHANY_OPERAND_RN : + value = fields->f_rn; + break; + case EPIPHANY_OPERAND_RN6 : + value = fields->f_rn6; + break; + case EPIPHANY_OPERAND_SD : + value = fields->f_sd; + break; + case EPIPHANY_OPERAND_SD6 : + value = fields->f_sd6; + break; + case EPIPHANY_OPERAND_SDDMA : + value = fields->f_sd6; + break; + case EPIPHANY_OPERAND_SDMEM : + value = fields->f_sd6; + break; + case EPIPHANY_OPERAND_SDMESH : + value = fields->f_sd6; + break; + case EPIPHANY_OPERAND_SHIFT : + value = fields->f_shift; + break; + case EPIPHANY_OPERAND_SIMM11 : + value = fields->f_sdisp11; + break; + case EPIPHANY_OPERAND_SIMM24 : + value = fields->f_simm24; + break; + case EPIPHANY_OPERAND_SIMM3 : + value = fields->f_sdisp3; + break; + case EPIPHANY_OPERAND_SIMM8 : + value = fields->f_simm8; + break; + case EPIPHANY_OPERAND_SN : + value = fields->f_sn; + break; + case EPIPHANY_OPERAND_SN6 : + value = fields->f_sn6; + break; + case EPIPHANY_OPERAND_SNDMA : + value = fields->f_sn6; + break; + case EPIPHANY_OPERAND_SNMEM : + value = fields->f_sn6; + break; + case EPIPHANY_OPERAND_SNMESH : + value = fields->f_sn6; + break; + case EPIPHANY_OPERAND_SWI_NUM : + value = fields->f_trap_num; + break; + case EPIPHANY_OPERAND_TRAPNUM6 : + value = fields->f_trap_num; + break; + + default : + /* xgettext:c-format */ + fprintf (stderr, _("Unrecognized field %d while getting vma operand.\n"), + opindex); + abort (); + } + + return value; +} + +void epiphany_cgen_set_int_operand (CGEN_CPU_DESC, int, CGEN_FIELDS *, int); +void epiphany_cgen_set_vma_operand (CGEN_CPU_DESC, int, CGEN_FIELDS *, bfd_vma); + +/* Stuffing values in cgen_fields is handled by a collection of functions. + They are distinguished by the type of the VALUE argument they accept. + TODO: floating point, inlining support, remove cases where argument type + not appropriate. */ + +void +epiphany_cgen_set_int_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + int opindex, + CGEN_FIELDS * fields, + int value) +{ + switch (opindex) + { + case EPIPHANY_OPERAND_DIRECTION : + fields->f_addsubx = value; + break; + case EPIPHANY_OPERAND_DISP11 : + fields->f_disp11 = value; + break; + case EPIPHANY_OPERAND_DISP3 : + fields->f_disp3 = value; + break; + case EPIPHANY_OPERAND_DPMI : + fields->f_subd = value; + break; + case EPIPHANY_OPERAND_FRD : + fields->f_rd = value; + break; + case EPIPHANY_OPERAND_FRD6 : + fields->f_rd6 = value; + break; + case EPIPHANY_OPERAND_FRM : + fields->f_rm = value; + break; + case EPIPHANY_OPERAND_FRM6 : + fields->f_rm6 = value; + break; + case EPIPHANY_OPERAND_FRN : + fields->f_rn = value; + break; + case EPIPHANY_OPERAND_FRN6 : + fields->f_rn6 = value; + break; + case EPIPHANY_OPERAND_IMM16 : + fields->f_imm16 = value; + break; + case EPIPHANY_OPERAND_IMM8 : + fields->f_imm8 = value; + break; + case EPIPHANY_OPERAND_RD : + fields->f_rd = value; + break; + case EPIPHANY_OPERAND_RD6 : + fields->f_rd6 = value; + break; + case EPIPHANY_OPERAND_RM : + fields->f_rm = value; + break; + case EPIPHANY_OPERAND_RM6 : + fields->f_rm6 = value; + break; + case EPIPHANY_OPERAND_RN : + fields->f_rn = value; + break; + case EPIPHANY_OPERAND_RN6 : + fields->f_rn6 = value; + break; + case EPIPHANY_OPERAND_SD : + fields->f_sd = value; + break; + case EPIPHANY_OPERAND_SD6 : + fields->f_sd6 = value; + break; + case EPIPHANY_OPERAND_SDDMA : + fields->f_sd6 = value; + break; + case EPIPHANY_OPERAND_SDMEM : + fields->f_sd6 = value; + break; + case EPIPHANY_OPERAND_SDMESH : + fields->f_sd6 = value; + break; + case EPIPHANY_OPERAND_SHIFT : + fields->f_shift = value; + break; + case EPIPHANY_OPERAND_SIMM11 : + fields->f_sdisp11 = value; + break; + case EPIPHANY_OPERAND_SIMM24 : + fields->f_simm24 = value; + break; + case EPIPHANY_OPERAND_SIMM3 : + fields->f_sdisp3 = value; + break; + case EPIPHANY_OPERAND_SIMM8 : + fields->f_simm8 = value; + break; + case EPIPHANY_OPERAND_SN : + fields->f_sn = value; + break; + case EPIPHANY_OPERAND_SN6 : + fields->f_sn6 = value; + break; + case EPIPHANY_OPERAND_SNDMA : + fields->f_sn6 = value; + break; + case EPIPHANY_OPERAND_SNMEM : + fields->f_sn6 = value; + break; + case EPIPHANY_OPERAND_SNMESH : + fields->f_sn6 = value; + break; + case EPIPHANY_OPERAND_SWI_NUM : + fields->f_trap_num = value; + break; + case EPIPHANY_OPERAND_TRAPNUM6 : + fields->f_trap_num = value; + break; + + default : + /* xgettext:c-format */ + fprintf (stderr, _("Unrecognized field %d while setting int operand.\n"), + opindex); + abort (); + } +} + +void +epiphany_cgen_set_vma_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + int opindex, + CGEN_FIELDS * fields, + bfd_vma value) +{ + switch (opindex) + { + case EPIPHANY_OPERAND_DIRECTION : + fields->f_addsubx = value; + break; + case EPIPHANY_OPERAND_DISP11 : + fields->f_disp11 = value; + break; + case EPIPHANY_OPERAND_DISP3 : + fields->f_disp3 = value; + break; + case EPIPHANY_OPERAND_DPMI : + fields->f_subd = value; + break; + case EPIPHANY_OPERAND_FRD : + fields->f_rd = value; + break; + case EPIPHANY_OPERAND_FRD6 : + fields->f_rd6 = value; + break; + case EPIPHANY_OPERAND_FRM : + fields->f_rm = value; + break; + case EPIPHANY_OPERAND_FRM6 : + fields->f_rm6 = value; + break; + case EPIPHANY_OPERAND_FRN : + fields->f_rn = value; + break; + case EPIPHANY_OPERAND_FRN6 : + fields->f_rn6 = value; + break; + case EPIPHANY_OPERAND_IMM16 : + fields->f_imm16 = value; + break; + case EPIPHANY_OPERAND_IMM8 : + fields->f_imm8 = value; + break; + case EPIPHANY_OPERAND_RD : + fields->f_rd = value; + break; + case EPIPHANY_OPERAND_RD6 : + fields->f_rd6 = value; + break; + case EPIPHANY_OPERAND_RM : + fields->f_rm = value; + break; + case EPIPHANY_OPERAND_RM6 : + fields->f_rm6 = value; + break; + case EPIPHANY_OPERAND_RN : + fields->f_rn = value; + break; + case EPIPHANY_OPERAND_RN6 : + fields->f_rn6 = value; + break; + case EPIPHANY_OPERAND_SD : + fields->f_sd = value; + break; + case EPIPHANY_OPERAND_SD6 : + fields->f_sd6 = value; + break; + case EPIPHANY_OPERAND_SDDMA : + fields->f_sd6 = value; + break; + case EPIPHANY_OPERAND_SDMEM : + fields->f_sd6 = value; + break; + case EPIPHANY_OPERAND_SDMESH : + fields->f_sd6 = value; + break; + case EPIPHANY_OPERAND_SHIFT : + fields->f_shift = value; + break; + case EPIPHANY_OPERAND_SIMM11 : + fields->f_sdisp11 = value; + break; + case EPIPHANY_OPERAND_SIMM24 : + fields->f_simm24 = value; + break; + case EPIPHANY_OPERAND_SIMM3 : + fields->f_sdisp3 = value; + break; + case EPIPHANY_OPERAND_SIMM8 : + fields->f_simm8 = value; + break; + case EPIPHANY_OPERAND_SN : + fields->f_sn = value; + break; + case EPIPHANY_OPERAND_SN6 : + fields->f_sn6 = value; + break; + case EPIPHANY_OPERAND_SNDMA : + fields->f_sn6 = value; + break; + case EPIPHANY_OPERAND_SNMEM : + fields->f_sn6 = value; + break; + case EPIPHANY_OPERAND_SNMESH : + fields->f_sn6 = value; + break; + case EPIPHANY_OPERAND_SWI_NUM : + fields->f_trap_num = value; + break; + case EPIPHANY_OPERAND_TRAPNUM6 : + fields->f_trap_num = value; + break; + + default : + /* xgettext:c-format */ + fprintf (stderr, _("Unrecognized field %d while setting vma operand.\n"), + opindex); + abort (); + } +} + +/* Function to call before using the instruction builder tables. */ + +void +epiphany_cgen_init_ibld_table (CGEN_CPU_DESC cd) +{ + cd->insert_handlers = & epiphany_cgen_insert_handlers[0]; + cd->extract_handlers = & epiphany_cgen_extract_handlers[0]; + + cd->insert_operand = epiphany_cgen_insert_operand; + cd->extract_operand = epiphany_cgen_extract_operand; + + cd->get_int_operand = epiphany_cgen_get_int_operand; + cd->set_int_operand = epiphany_cgen_set_int_operand; + cd->get_vma_operand = epiphany_cgen_get_vma_operand; + cd->set_vma_operand = epiphany_cgen_set_vma_operand; +} diff --git a/opcodes/epiphany-opc.c b/opcodes/epiphany-opc.c new file mode 100644 index 00000000000..e761061015e --- /dev/null +++ b/opcodes/epiphany-opc.c @@ -0,0 +1,4035 @@ +/* Instruction opcode table for epiphany. + +THIS FILE IS MACHINE GENERATED WITH CGEN. + +Copyright 1996-2010 Free Software Foundation, Inc. + +This file is part of the GNU Binutils and/or GDB, the GNU debugger. + + This file is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + It is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License along + with this program; if not, write to the Free Software Foundation, Inc., + 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. + +*/ + +#include "sysdep.h" +#include "ansidecl.h" +#include "bfd.h" +#include "symcat.h" +#include "epiphany-desc.h" +#include "epiphany-opc.h" +#include "libiberty.h" + +/* -- opc.c */ + + + +/* -- asm.c */ +/* The hash functions are recorded here to help keep assembler code out of + the disassembler and vice versa. */ + +static int asm_hash_insn_p (const CGEN_INSN *); +static unsigned int asm_hash_insn (const char *); +static int dis_hash_insn_p (const CGEN_INSN *); +static unsigned int dis_hash_insn (const char *, CGEN_INSN_INT); + +/* Instruction formats. */ + +#define F(f) & epiphany_cgen_ifld_table[EPIPHANY_##f] +static const CGEN_IFMT ifmt_empty ATTRIBUTE_UNUSED = { + 0, 0, 0x0, { { 0 } } +}; + +static const CGEN_IFMT ifmt_beq16 ATTRIBUTE_UNUSED = { + 16, 16, 0xff, { { F (F_SIMM8) }, { F (F_CONDCODE) }, { F (F_OPC) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_beq ATTRIBUTE_UNUSED = { + 32, 32, 0xff, { { F (F_SIMM24) }, { F (F_CONDCODE) }, { F (F_OPC) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_jr16 ATTRIBUTE_UNUSED = { + 16, 16, 0xe3ff, { { F (F_DC_15_3) }, { F (F_RN) }, { F (F_DC_9_1) }, { F (F_OPC_8_5) }, { F (F_OPC) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_rts ATTRIBUTE_UNUSED = { + 32, 32, 0xffffffff, { { F (F_DC_31_3) }, { F (F_RN_X) }, { F (F_DC_25_6) }, { F (F_OPC_19_4) }, { F (F_DC_15_3) }, { F (F_RN) }, { F (F_DC_9_1) }, { F (F_OPC_8_5) }, { F (F_OPC) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_jr ATTRIBUTE_UNUSED = { + 32, 32, 0xe3ffe3ff, { { F (F_DC_31_3) }, { F (F_DC_25_6) }, { F (F_OPC_19_4) }, { F (F_DC_15_3) }, { F (F_RN6) }, { F (F_DC_9_1) }, { F (F_OPC_8_5) }, { F (F_OPC) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_ldrbx16_s ATTRIBUTE_UNUSED = { + 16, 16, 0x7f, { { F (F_RD) }, { F (F_RN) }, { F (F_RM) }, { F (F_WORDSIZE) }, { F (F_STORE) }, { F (F_OPC) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_ldrbx_l ATTRIBUTE_UNUSED = { + 32, 32, 0x6f007f, { { F (F_DC_22_1) }, { F (F_DC_21_1) }, { F (F_ADDSUBX) }, { F (F_OPC_19_4) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_RM6) }, { F (F_WORDSIZE) }, { F (F_STORE) }, { F (F_OPC) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_ldrbp_l ATTRIBUTE_UNUSED = { + 32, 32, 0x6f007f, { { F (F_DC_22_2) }, { F (F_ADDSUBX) }, { F (F_OPC_19_4) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_RM6) }, { F (F_WORDSIZE) }, { F (F_STORE) }, { F (F_OPC) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_ldrbd16_s ATTRIBUTE_UNUSED = { + 16, 16, 0x7f, { { F (F_RD) }, { F (F_RN) }, { F (F_DISP3) }, { F (F_WORDSIZE) }, { F (F_STORE) }, { F (F_OPC) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_ldrbd_l ATTRIBUTE_UNUSED = { + 32, 32, 0x200007f, { { F (F_PM) }, { F (F_SUBD) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_DISP11) }, { F (F_WORDSIZE) }, { F (F_STORE) }, { F (F_OPC) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_cmov16EQ ATTRIBUTE_UNUSED = { + 16, 16, 0x3ff, { { F (F_RD) }, { F (F_RN) }, { F (F_DC_9_1) }, { F (F_OPC_8_1) }, { F (F_CONDCODE) }, { F (F_OPC) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_cmovEQ ATTRIBUTE_UNUSED = { + 32, 32, 0x3ff03ff, { { F (F_DC_25_6) }, { F (F_OPC_19_4) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_DC_9_1) }, { F (F_OPC_8_1) }, { F (F_CONDCODE) }, { F (F_OPC) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_movts16 ATTRIBUTE_UNUSED = { + 16, 16, 0x3ff, { { F (F_RD) }, { F (F_SN) }, { F (F_DC_9_1) }, { F (F_OPC_8_5) }, { F (F_OPC) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_movts6 ATTRIBUTE_UNUSED = { + 32, 32, 0x3ff03ff, { { F (F_DC_25_4) }, { F (F_DC_21_2) }, { F (F_OPC_19_4) }, { F (F_RD6) }, { F (F_SN6) }, { F (F_DC_9_1) }, { F (F_OPC_8_1) }, { F (F_DC_7_4) }, { F (F_OPC) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_movtsdma ATTRIBUTE_UNUSED = { + 32, 32, 0x3ff03ff, { { F (F_DC_25_4) }, { F (F_DC_21_2) }, { F (F_OPC_19_4) }, { F (F_RD6) }, { F (F_SN6) }, { F (F_DC_9_1) }, { F (F_OPC_8_1) }, { F (F_DC_7_4) }, { F (F_OPC) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_movtsmem ATTRIBUTE_UNUSED = { + 32, 32, 0x3ff03ff, { { F (F_DC_25_4) }, { F (F_DC_21_2) }, { F (F_OPC_19_4) }, { F (F_RD6) }, { F (F_SN6) }, { F (F_DC_9_1) }, { F (F_OPC_8_1) }, { F (F_DC_7_4) }, { F (F_OPC) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_movtsmesh ATTRIBUTE_UNUSED = { + 32, 32, 0x3ff03ff, { { F (F_DC_25_4) }, { F (F_DC_21_2) }, { F (F_OPC_19_4) }, { F (F_RD6) }, { F (F_SN6) }, { F (F_DC_9_1) }, { F (F_OPC_8_1) }, { F (F_DC_7_4) }, { F (F_OPC) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_nop ATTRIBUTE_UNUSED = { + 16, 16, 0xffff, { { F (F_DC_15_7) }, { F (F_OPC_8_5) }, { F (F_OPC) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_unimpl ATTRIBUTE_UNUSED = { + 32, 32, 0xffffffff, { { F (F_OPC_31_32) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_gien ATTRIBUTE_UNUSED = { + 16, 16, 0xffff, { { F (F_DC_15_6) }, { F (F_GIEN_GIDIS_9_1) }, { F (F_OPC_8_5) }, { F (F_OPC) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_swi_num ATTRIBUTE_UNUSED = { + 16, 16, 0x3ff, { { F (F_TRAP_NUM) }, { F (F_TRAP_SWI_9_1) }, { F (F_OPC_8_5) }, { F (F_OPC) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_swi ATTRIBUTE_UNUSED = { + 16, 16, 0xffff, { { F (F_DC_15_6) }, { F (F_TRAP_SWI_9_1) }, { F (F_OPC_8_5) }, { F (F_OPC) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_trap16 ATTRIBUTE_UNUSED = { + 16, 16, 0x3ff, { { F (F_TRAP_NUM) }, { F (F_TRAP_SWI_9_1) }, { F (F_OPC_8_5) }, { F (F_OPC) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_add16 ATTRIBUTE_UNUSED = { + 16, 16, 0x7f, { { F (F_RD) }, { F (F_RN) }, { F (F_RM) }, { F (F_OPC_6_3) }, { F (F_OPC) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_add ATTRIBUTE_UNUSED = { + 32, 32, 0x7f007f, { { F (F_DC_22_3) }, { F (F_OPC_19_4) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_RM6) }, { F (F_OPC_6_3) }, { F (F_OPC) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_addi16 ATTRIBUTE_UNUSED = { + 16, 16, 0x7f, { { F (F_RD) }, { F (F_RN) }, { F (F_SDISP3) }, { F (F_OPC_6_3) }, { F (F_OPC) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_addi ATTRIBUTE_UNUSED = { + 32, 32, 0x300007f, { { F (F_DC_25_2) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_SDISP11) }, { F (F_OPC_6_3) }, { F (F_OPC) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_lsri16 ATTRIBUTE_UNUSED = { + 16, 16, 0x1f, { { F (F_RD) }, { F (F_RN) }, { F (F_SHIFT) }, { F (F_OPC_4_1) }, { F (F_OPC) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_lsri32 ATTRIBUTE_UNUSED = { + 32, 32, 0x3ff001f, { { F (F_DC_25_6) }, { F (F_OPC_19_4) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_SHIFT) }, { F (F_OPC_4_1) }, { F (F_OPC) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_bitr16 ATTRIBUTE_UNUSED = { + 16, 16, 0x3ff, { { F (F_RD) }, { F (F_RN) }, { F (F_SHIFT) }, { F (F_OPC_4_1) }, { F (F_OPC) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_bitr ATTRIBUTE_UNUSED = { + 32, 32, 0x3ff03ff, { { F (F_DC_25_6) }, { F (F_OPC_19_4) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_SHIFT) }, { F (F_OPC_4_1) }, { F (F_OPC) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_fext ATTRIBUTE_UNUSED = { + 32, 32, 0x7f007f, { { F (F_DC_22_2) }, { F (F_DC_20_1) }, { F (F_OPC_19_4) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_RM6) }, { F (F_OPC_6_3) }, { F (F_OPC) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov8 ATTRIBUTE_UNUSED = { + 16, 16, 0x1f, { { F (F_RD) }, { F (F_IMM8) }, { F (F_OPC_4_1) }, { F (F_OPC) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov16 ATTRIBUTE_UNUSED = { + 32, 32, 0x100f001f, { { F (F_DC_28_1) }, { F (F_OPC_19_4) }, { F (F_RD6) }, { F (F_IMM16) }, { F (F_OPC_4_1) }, { F (F_OPC) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_f_absf16 ATTRIBUTE_UNUSED = { + 16, 16, 0x7f, { { F (F_RD) }, { F (F_RN) }, { F (F_RN) }, { F (F_OPC_6_3) }, { F (F_OPC) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_f_absf32 ATTRIBUTE_UNUSED = { + 32, 32, 0x7f007f, { { F (F_DC_22_3) }, { F (F_OPC_19_4) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_RN6) }, { F (F_OPC_6_3) }, { F (F_OPC) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_f_loatf16 ATTRIBUTE_UNUSED = { + 16, 16, 0x7f, { { F (F_RD) }, { F (F_RN) }, { F (F_RN) }, { F (F_OPC_6_3) }, { F (F_OPC) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_f_recipf32 ATTRIBUTE_UNUSED = { + 32, 32, 0x7f007f, { { F (F_DC_22_2) }, { F (F_DC_20_1) }, { F (F_OPC_19_4) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_RN6) }, { F (F_OPC_6_3) }, { F (F_OPC) }, { 0 } } +}; + +#undef F + +#define A(a) (1 << CGEN_INSN_##a) +#define OPERAND(op) EPIPHANY_OPERAND_##op +#define MNEM CGEN_SYNTAX_MNEMONIC /* syntax value for mnemonic */ +#define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field)) + +/* The instruction table. */ + +static const CGEN_OPCODE epiphany_cgen_insn_opcode_table[MAX_INSNS] = +{ + /* Special null first entry. + A `num' value of zero is thus invalid. + Also, the special `invalid' insn resides here. */ + { { 0, 0, 0, 0 }, {{0}}, 0, {0}}, +/* beq.s $simm8 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (SIMM8), 0 } }, + & ifmt_beq16, { 0x0 } + }, +/* beq.l $simm24 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (SIMM24), 0 } }, + & ifmt_beq, { 0x8 } + }, +/* bne.s $simm8 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (SIMM8), 0 } }, + & ifmt_beq16, { 0x10 } + }, +/* bne.l $simm24 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (SIMM24), 0 } }, + & ifmt_beq, { 0x18 } + }, +/* bgtu.s $simm8 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (SIMM8), 0 } }, + & ifmt_beq16, { 0x20 } + }, +/* bgtu.l $simm24 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (SIMM24), 0 } }, + & ifmt_beq, { 0x28 } + }, +/* bgteu.s $simm8 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (SIMM8), 0 } }, + & ifmt_beq16, { 0x30 } + }, +/* bgteu.l $simm24 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (SIMM24), 0 } }, + & ifmt_beq, { 0x38 } + }, +/* blteu.s $simm8 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (SIMM8), 0 } }, + & ifmt_beq16, { 0x40 } + }, +/* blteu.l $simm24 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (SIMM24), 0 } }, + & ifmt_beq, { 0x48 } + }, +/* bltu.s $simm8 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (SIMM8), 0 } }, + & ifmt_beq16, { 0x50 } + }, +/* bltu.l $simm24 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (SIMM24), 0 } }, + & ifmt_beq, { 0x58 } + }, +/* bgt.s $simm8 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (SIMM8), 0 } }, + & ifmt_beq16, { 0x60 } + }, +/* bgt.l $simm24 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (SIMM24), 0 } }, + & ifmt_beq, { 0x68 } + }, +/* bgte.s $simm8 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (SIMM8), 0 } }, + & ifmt_beq16, { 0x70 } + }, +/* bgte.l $simm24 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (SIMM24), 0 } }, + & ifmt_beq, { 0x78 } + }, +/* blt.s $simm8 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (SIMM8), 0 } }, + & ifmt_beq16, { 0x80 } + }, +/* blt.l $simm24 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (SIMM24), 0 } }, + & ifmt_beq, { 0x88 } + }, +/* blte.s $simm8 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (SIMM8), 0 } }, + & ifmt_beq16, { 0x90 } + }, +/* blte.l $simm24 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (SIMM24), 0 } }, + & ifmt_beq, { 0x98 } + }, +/* bbeq.s $simm8 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (SIMM8), 0 } }, + & ifmt_beq16, { 0xa0 } + }, +/* bbeq.l $simm24 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (SIMM24), 0 } }, + & ifmt_beq, { 0xa8 } + }, +/* bbne.s $simm8 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (SIMM8), 0 } }, + & ifmt_beq16, { 0xb0 } + }, +/* bbne.l $simm24 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (SIMM24), 0 } }, + & ifmt_beq, { 0xb8 } + }, +/* bblt.s $simm8 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (SIMM8), 0 } }, + & ifmt_beq16, { 0xc0 } + }, +/* bblt.l $simm24 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (SIMM24), 0 } }, + & ifmt_beq, { 0xc8 } + }, +/* bblte.s $simm8 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (SIMM8), 0 } }, + & ifmt_beq16, { 0xd0 } + }, +/* bblte.l $simm24 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (SIMM24), 0 } }, + & ifmt_beq, { 0xd8 } + }, +/* b.s $simm8 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (SIMM8), 0 } }, + & ifmt_beq16, { 0xe0 } + }, +/* b.l $simm24 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (SIMM24), 0 } }, + & ifmt_beq, { 0xe8 } + }, +/* bl.s $simm8 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (SIMM8), 0 } }, + & ifmt_beq16, { 0xf0 } + }, +/* bl.l $simm24 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (SIMM24), 0 } }, + & ifmt_beq, { 0xf8 } + }, +/* jr $rn */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RN), 0 } }, + & ifmt_jr16, { 0x142 } + }, +/* rts */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_rts, { 0x402194f } + }, +/* jr $rn6 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RN6), 0 } }, + & ifmt_jr, { 0x2014f } + }, +/* jalr $rn */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RN), 0 } }, + & ifmt_jr16, { 0x152 } + }, +/* jalr $rn6 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RN6), 0 } }, + & ifmt_jr, { 0x2015f } + }, +/* ldrb $rd,[$rn,$rm] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', '[', OP (RN), ',', OP (RM), ']', 0 } }, + & ifmt_ldrbx16_s, { 0x1 } + }, +/* ldrb $rd,[$rn],$rm */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', '[', OP (RN), ']', ',', OP (RM), 0 } }, + & ifmt_ldrbx16_s, { 0x5 } + }, +/* ldrb $rd6,[$rn6,$direction$rm6] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD6), ',', '[', OP (RN6), ',', OP (DIRECTION), OP (RM6), ']', 0 } }, + & ifmt_ldrbx_l, { 0x9 } + }, +/* ldrb $rd6,[$rn6],$direction$rm6 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD6), ',', '[', OP (RN6), ']', ',', OP (DIRECTION), OP (RM6), 0 } }, + & ifmt_ldrbp_l, { 0xd } + }, +/* ldrb $rd,[$rn,$disp3] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', '[', OP (RN), ',', OP (DISP3), ']', 0 } }, + & ifmt_ldrbd16_s, { 0x4 } + }, +/* ldrb $rd6,[$rn6,$dpmi$disp11] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD6), ',', '[', OP (RN6), ',', OP (DPMI), OP (DISP11), ']', 0 } }, + & ifmt_ldrbd_l, { 0xc } + }, +/* ldrb $rd6,[$rn6],$dpmi$disp11 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD6), ',', '[', OP (RN6), ']', ',', OP (DPMI), OP (DISP11), 0 } }, + & ifmt_ldrbd_l, { 0x200000c } + }, +/* ldrh $rd,[$rn,$rm] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', '[', OP (RN), ',', OP (RM), ']', 0 } }, + & ifmt_ldrbx16_s, { 0x21 } + }, +/* ldrh $rd,[$rn],$rm */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', '[', OP (RN), ']', ',', OP (RM), 0 } }, + & ifmt_ldrbx16_s, { 0x25 } + }, +/* ldrh $rd6,[$rn6,$direction$rm6] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD6), ',', '[', OP (RN6), ',', OP (DIRECTION), OP (RM6), ']', 0 } }, + & ifmt_ldrbx_l, { 0x29 } + }, +/* ldrh $rd6,[$rn6],$direction$rm6 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD6), ',', '[', OP (RN6), ']', ',', OP (DIRECTION), OP (RM6), 0 } }, + & ifmt_ldrbp_l, { 0x2d } + }, +/* ldrh $rd,[$rn,$disp3] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', '[', OP (RN), ',', OP (DISP3), ']', 0 } }, + & ifmt_ldrbd16_s, { 0x24 } + }, +/* ldrh $rd6,[$rn6,$dpmi$disp11] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD6), ',', '[', OP (RN6), ',', OP (DPMI), OP (DISP11), ']', 0 } }, + & ifmt_ldrbd_l, { 0x2c } + }, +/* ldrh $rd6,[$rn6],$dpmi$disp11 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD6), ',', '[', OP (RN6), ']', ',', OP (DPMI), OP (DISP11), 0 } }, + & ifmt_ldrbd_l, { 0x200002c } + }, +/* ldr $rd,[$rn,$rm] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', '[', OP (RN), ',', OP (RM), ']', 0 } }, + & ifmt_ldrbx16_s, { 0x41 } + }, +/* ldr $rd,[$rn],$rm */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', '[', OP (RN), ']', ',', OP (RM), 0 } }, + & ifmt_ldrbx16_s, { 0x45 } + }, +/* ldr $rd6,[$rn6,$direction$rm6] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD6), ',', '[', OP (RN6), ',', OP (DIRECTION), OP (RM6), ']', 0 } }, + & ifmt_ldrbx_l, { 0x49 } + }, +/* ldr $rd6,[$rn6],$direction$rm6 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD6), ',', '[', OP (RN6), ']', ',', OP (DIRECTION), OP (RM6), 0 } }, + & ifmt_ldrbp_l, { 0x4d } + }, +/* ldr $rd,[$rn,$disp3] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', '[', OP (RN), ',', OP (DISP3), ']', 0 } }, + & ifmt_ldrbd16_s, { 0x44 } + }, +/* ldr $rd6,[$rn6,$dpmi$disp11] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD6), ',', '[', OP (RN6), ',', OP (DPMI), OP (DISP11), ']', 0 } }, + & ifmt_ldrbd_l, { 0x4c } + }, +/* ldr $rd6,[$rn6],$dpmi$disp11 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD6), ',', '[', OP (RN6), ']', ',', OP (DPMI), OP (DISP11), 0 } }, + & ifmt_ldrbd_l, { 0x200004c } + }, +/* ldrd $rd,[$rn,$rm] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', '[', OP (RN), ',', OP (RM), ']', 0 } }, + & ifmt_ldrbx16_s, { 0x61 } + }, +/* ldrd $rd,[$rn],$rm */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', '[', OP (RN), ']', ',', OP (RM), 0 } }, + & ifmt_ldrbx16_s, { 0x65 } + }, +/* ldrd $rd6,[$rn6,$direction$rm6] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD6), ',', '[', OP (RN6), ',', OP (DIRECTION), OP (RM6), ']', 0 } }, + & ifmt_ldrbx_l, { 0x69 } + }, +/* ldrd $rd6,[$rn6],$direction$rm6 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD6), ',', '[', OP (RN6), ']', ',', OP (DIRECTION), OP (RM6), 0 } }, + & ifmt_ldrbp_l, { 0x6d } + }, +/* ldrd $rd,[$rn,$disp3] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', '[', OP (RN), ',', OP (DISP3), ']', 0 } }, + & ifmt_ldrbd16_s, { 0x64 } + }, +/* ldrd $rd6,[$rn6,$dpmi$disp11] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD6), ',', '[', OP (RN6), ',', OP (DPMI), OP (DISP11), ']', 0 } }, + & ifmt_ldrbd_l, { 0x6c } + }, +/* ldrd $rd6,[$rn6],$dpmi$disp11 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD6), ',', '[', OP (RN6), ']', ',', OP (DPMI), OP (DISP11), 0 } }, + & ifmt_ldrbd_l, { 0x200006c } + }, +/* testsetb $rd6,[$rn6,$direction$rm6] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD6), ',', '[', OP (RN6), ',', OP (DIRECTION), OP (RM6), ']', 0 } }, + & ifmt_ldrbx_l, { 0x200009 } + }, +/* testseth $rd6,[$rn6,$direction$rm6] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD6), ',', '[', OP (RN6), ',', OP (DIRECTION), OP (RM6), ']', 0 } }, + & ifmt_ldrbx_l, { 0x200029 } + }, +/* testset $rd6,[$rn6,$direction$rm6] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD6), ',', '[', OP (RN6), ',', OP (DIRECTION), OP (RM6), ']', 0 } }, + & ifmt_ldrbx_l, { 0x200049 } + }, +/* strb $rd,[$rn,$rm] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', '[', OP (RN), ',', OP (RM), ']', 0 } }, + & ifmt_ldrbx16_s, { 0x11 } + }, +/* strb $rd6,[$rn6,$direction$rm6] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD6), ',', '[', OP (RN6), ',', OP (DIRECTION), OP (RM6), ']', 0 } }, + & ifmt_ldrbx_l, { 0x19 } + }, +/* strb $rd,[$rn],$rm */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', '[', OP (RN), ']', ',', OP (RM), 0 } }, + & ifmt_ldrbx16_s, { 0x15 } + }, +/* strb $rd6,[$rn6],$direction$rm6 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD6), ',', '[', OP (RN6), ']', ',', OP (DIRECTION), OP (RM6), 0 } }, + & ifmt_ldrbp_l, { 0x1d } + }, +/* strb $rd,[$rn,$disp3] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', '[', OP (RN), ',', OP (DISP3), ']', 0 } }, + & ifmt_ldrbd16_s, { 0x14 } + }, +/* strb $rd6,[$rn6,$dpmi$disp11] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD6), ',', '[', OP (RN6), ',', OP (DPMI), OP (DISP11), ']', 0 } }, + & ifmt_ldrbd_l, { 0x1c } + }, +/* strb $rd6,[$rn6],$dpmi$disp11 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD6), ',', '[', OP (RN6), ']', ',', OP (DPMI), OP (DISP11), 0 } }, + & ifmt_ldrbd_l, { 0x200001c } + }, +/* strh $rd,[$rn,$rm] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', '[', OP (RN), ',', OP (RM), ']', 0 } }, + & ifmt_ldrbx16_s, { 0x31 } + }, +/* strh $rd6,[$rn6,$direction$rm6] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD6), ',', '[', OP (RN6), ',', OP (DIRECTION), OP (RM6), ']', 0 } }, + & ifmt_ldrbx_l, { 0x39 } + }, +/* strh $rd,[$rn],$rm */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', '[', OP (RN), ']', ',', OP (RM), 0 } }, + & ifmt_ldrbx16_s, { 0x35 } + }, +/* strh $rd6,[$rn6],$direction$rm6 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD6), ',', '[', OP (RN6), ']', ',', OP (DIRECTION), OP (RM6), 0 } }, + & ifmt_ldrbp_l, { 0x3d } + }, +/* strh $rd,[$rn,$disp3] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', '[', OP (RN), ',', OP (DISP3), ']', 0 } }, + & ifmt_ldrbd16_s, { 0x34 } + }, +/* strh $rd6,[$rn6,$dpmi$disp11] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD6), ',', '[', OP (RN6), ',', OP (DPMI), OP (DISP11), ']', 0 } }, + & ifmt_ldrbd_l, { 0x3c } + }, +/* strh $rd6,[$rn6],$dpmi$disp11 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD6), ',', '[', OP (RN6), ']', ',', OP (DPMI), OP (DISP11), 0 } }, + & ifmt_ldrbd_l, { 0x200003c } + }, +/* str $rd,[$rn,$rm] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', '[', OP (RN), ',', OP (RM), ']', 0 } }, + & ifmt_ldrbx16_s, { 0x51 } + }, +/* str $rd6,[$rn6,$direction$rm6] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD6), ',', '[', OP (RN6), ',', OP (DIRECTION), OP (RM6), ']', 0 } }, + & ifmt_ldrbx_l, { 0x59 } + }, +/* str $rd,[$rn],$rm */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', '[', OP (RN), ']', ',', OP (RM), 0 } }, + & ifmt_ldrbx16_s, { 0x55 } + }, +/* str $rd6,[$rn6],$direction$rm6 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD6), ',', '[', OP (RN6), ']', ',', OP (DIRECTION), OP (RM6), 0 } }, + & ifmt_ldrbp_l, { 0x5d } + }, +/* str $rd,[$rn,$disp3] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', '[', OP (RN), ',', OP (DISP3), ']', 0 } }, + & ifmt_ldrbd16_s, { 0x54 } + }, +/* str $rd6,[$rn6,$dpmi$disp11] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD6), ',', '[', OP (RN6), ',', OP (DPMI), OP (DISP11), ']', 0 } }, + & ifmt_ldrbd_l, { 0x5c } + }, +/* str $rd6,[$rn6],$dpmi$disp11 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD6), ',', '[', OP (RN6), ']', ',', OP (DPMI), OP (DISP11), 0 } }, + & ifmt_ldrbd_l, { 0x200005c } + }, +/* strd $rd,[$rn,$rm] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', '[', OP (RN), ',', OP (RM), ']', 0 } }, + & ifmt_ldrbx16_s, { 0x71 } + }, +/* strd $rd6,[$rn6,$direction$rm6] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD6), ',', '[', OP (RN6), ',', OP (DIRECTION), OP (RM6), ']', 0 } }, + & ifmt_ldrbx_l, { 0x79 } + }, +/* strd $rd,[$rn],$rm */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', '[', OP (RN), ']', ',', OP (RM), 0 } }, + & ifmt_ldrbx16_s, { 0x75 } + }, +/* strd $rd6,[$rn6],$direction$rm6 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD6), ',', '[', OP (RN6), ']', ',', OP (DIRECTION), OP (RM6), 0 } }, + & ifmt_ldrbp_l, { 0x7d } + }, +/* strd $rd,[$rn,$disp3] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', '[', OP (RN), ',', OP (DISP3), ']', 0 } }, + & ifmt_ldrbd16_s, { 0x74 } + }, +/* strd $rd6,[$rn6,$dpmi$disp11] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD6), ',', '[', OP (RN6), ',', OP (DPMI), OP (DISP11), ']', 0 } }, + & ifmt_ldrbd_l, { 0x7c } + }, +/* strd $rd6,[$rn6],$dpmi$disp11 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD6), ',', '[', OP (RN6), ']', ',', OP (DPMI), OP (DISP11), 0 } }, + & ifmt_ldrbd_l, { 0x200007c } + }, +/* moveq $rd,$rn */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RN), 0 } }, + & ifmt_cmov16EQ, { 0x2 } + }, +/* moveq $rd6,$rn6 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD6), ',', OP (RN6), 0 } }, + & ifmt_cmovEQ, { 0x2000f } + }, +/* movne $rd,$rn */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RN), 0 } }, + & ifmt_cmov16EQ, { 0x12 } + }, +/* movne $rd6,$rn6 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD6), ',', OP (RN6), 0 } }, + & ifmt_cmovEQ, { 0x2001f } + }, +/* movgtu $rd,$rn */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RN), 0 } }, + & ifmt_cmov16EQ, { 0x22 } + }, +/* movgtu $rd6,$rn6 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD6), ',', OP (RN6), 0 } }, + & ifmt_cmovEQ, { 0x2002f } + }, +/* movgteu $rd,$rn */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RN), 0 } }, + & ifmt_cmov16EQ, { 0x32 } + }, +/* movgteu $rd6,$rn6 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD6), ',', OP (RN6), 0 } }, + & ifmt_cmovEQ, { 0x2003f } + }, +/* movlteu $rd,$rn */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RN), 0 } }, + & ifmt_cmov16EQ, { 0x42 } + }, +/* movlteu $rd6,$rn6 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD6), ',', OP (RN6), 0 } }, + & ifmt_cmovEQ, { 0x2004f } + }, +/* movltu $rd,$rn */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RN), 0 } }, + & ifmt_cmov16EQ, { 0x52 } + }, +/* movltu $rd6,$rn6 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD6), ',', OP (RN6), 0 } }, + & ifmt_cmovEQ, { 0x2005f } + }, +/* movgt $rd,$rn */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RN), 0 } }, + & ifmt_cmov16EQ, { 0x62 } + }, +/* movgt $rd6,$rn6 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD6), ',', OP (RN6), 0 } }, + & ifmt_cmovEQ, { 0x2006f } + }, +/* movgte $rd,$rn */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RN), 0 } }, + & ifmt_cmov16EQ, { 0x72 } + }, +/* movgte $rd6,$rn6 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD6), ',', OP (RN6), 0 } }, + & ifmt_cmovEQ, { 0x2007f } + }, +/* movlt $rd,$rn */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RN), 0 } }, + & ifmt_cmov16EQ, { 0x82 } + }, +/* movlt $rd6,$rn6 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD6), ',', OP (RN6), 0 } }, + & ifmt_cmovEQ, { 0x2008f } + }, +/* movlte $rd,$rn */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RN), 0 } }, + & ifmt_cmov16EQ, { 0x92 } + }, +/* movlte $rd6,$rn6 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD6), ',', OP (RN6), 0 } }, + & ifmt_cmovEQ, { 0x2009f } + }, +/* mov $rd,$rn */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RN), 0 } }, + & ifmt_cmov16EQ, { 0xe2 } + }, +/* mov $rd6,$rn6 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD6), ',', OP (RN6), 0 } }, + & ifmt_cmovEQ, { 0x200ef } + }, +/* movbeq $rd,$rn */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RN), 0 } }, + & ifmt_cmov16EQ, { 0xa2 } + }, +/* movbeq $rd6,$rn6 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD6), ',', OP (RN6), 0 } }, + & ifmt_cmovEQ, { 0x200af } + }, +/* movbne $rd,$rn */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RN), 0 } }, + & ifmt_cmov16EQ, { 0xb2 } + }, +/* movbne $rd6,$rn6 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD6), ',', OP (RN6), 0 } }, + & ifmt_cmovEQ, { 0x200bf } + }, +/* movblt $rd,$rn */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RN), 0 } }, + & ifmt_cmov16EQ, { 0xc2 } + }, +/* movblt $rd6,$rn6 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD6), ',', OP (RN6), 0 } }, + & ifmt_cmovEQ, { 0x200cf } + }, +/* movblte $rd,$rn */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RN), 0 } }, + & ifmt_cmov16EQ, { 0xd2 } + }, +/* movblte $rd6,$rn6 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD6), ',', OP (RN6), 0 } }, + & ifmt_cmovEQ, { 0x200df } + }, +/* movts $sn,$rd */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (SN), ',', OP (RD), 0 } }, + & ifmt_movts16, { 0x102 } + }, +/* movts $sn6,$rd6 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (SN6), ',', OP (RD6), 0 } }, + & ifmt_movts6, { 0x2010f } + }, +/* movts $sndma,$rd6 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (SNDMA), ',', OP (RD6), 0 } }, + & ifmt_movtsdma, { 0x12010f } + }, +/* movts $snmem,$rd6 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (SNMEM), ',', OP (RD6), 0 } }, + & ifmt_movtsmem, { 0x22010f } + }, +/* movts $snmesh,$rd6 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (SNMESH), ',', OP (RD6), 0 } }, + & ifmt_movtsmesh, { 0x32010f } + }, +/* movfs $rd,$sn */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (SN), 0 } }, + & ifmt_movts16, { 0x112 } + }, +/* movfs $rd6,$sn6 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD6), ',', OP (SN6), 0 } }, + & ifmt_movts6, { 0x2011f } + }, +/* movfs $rd6,$sndma */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD6), ',', OP (SNDMA), 0 } }, + & ifmt_movtsdma, { 0x12011f } + }, +/* movfs $rd6,$snmem */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD6), ',', OP (SNMEM), 0 } }, + & ifmt_movtsmem, { 0x22011f } + }, +/* movfs $rd6,$snmesh */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD6), ',', OP (SNMESH), 0 } }, + & ifmt_movtsmesh, { 0x32011f } + }, +/* nop */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_nop, { 0x1a2 } + }, +/* snop */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_nop, { 0x3a2 } + }, +/* unimpl */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_unimpl, { 0xf000f } + }, +/* idle */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_nop, { 0x1b2 } + }, +/* bkpt */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_nop, { 0x1c2 } + }, +/* mbkpt */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_nop, { 0x3c2 } + }, +/* rti */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_nop, { 0x1d2 } + }, +/* wand */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_nop, { 0x182 } + }, +/* sync */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_nop, { 0x1f2 } + }, +/* gie */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_gien, { 0x192 } + }, +/* gid */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_gien, { 0x392 } + }, +/* swi $swi_num */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (SWI_NUM), 0 } }, + & ifmt_swi_num, { 0x1e2 } + }, +/* swi */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_swi, { 0x1e2 } + }, +/* trap $trapnum6 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (TRAPNUM6), 0 } }, + & ifmt_trap16, { 0x3e2 } + }, +/* add $rd,$rn,$rm */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RN), ',', OP (RM), 0 } }, + & ifmt_add16, { 0x1a } + }, +/* add $rd6,$rn6,$rm6 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD6), ',', OP (RN6), ',', OP (RM6), 0 } }, + & ifmt_add, { 0xa001f } + }, +/* sub $rd,$rn,$rm */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RN), ',', OP (RM), 0 } }, + & ifmt_add16, { 0x3a } + }, +/* sub $rd6,$rn6,$rm6 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD6), ',', OP (RN6), ',', OP (RM6), 0 } }, + & ifmt_add, { 0xa003f } + }, +/* and $rd,$rn,$rm */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RN), ',', OP (RM), 0 } }, + & ifmt_add16, { 0x5a } + }, +/* and $rd6,$rn6,$rm6 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD6), ',', OP (RN6), ',', OP (RM6), 0 } }, + & ifmt_add, { 0xa005f } + }, +/* orr $rd,$rn,$rm */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RN), ',', OP (RM), 0 } }, + & ifmt_add16, { 0x7a } + }, +/* orr $rd6,$rn6,$rm6 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD6), ',', OP (RN6), ',', OP (RM6), 0 } }, + & ifmt_add, { 0xa007f } + }, +/* eor $rd,$rn,$rm */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RN), ',', OP (RM), 0 } }, + & ifmt_add16, { 0xa } + }, +/* eor $rd6,$rn6,$rm6 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD6), ',', OP (RN6), ',', OP (RM6), 0 } }, + & ifmt_add, { 0xa000f } + }, +/* add.s $rd,$rn,$simm3 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RN), ',', OP (SIMM3), 0 } }, + & ifmt_addi16, { 0x13 } + }, +/* add.l $rd6,$rn6,$simm11 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD6), ',', OP (RN6), ',', OP (SIMM11), 0 } }, + & ifmt_addi, { 0x1b } + }, +/* sub.s $rd,$rn,$simm3 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RN), ',', OP (SIMM3), 0 } }, + & ifmt_addi16, { 0x33 } + }, +/* sub.l $rd6,$rn6,$simm11 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD6), ',', OP (RN6), ',', OP (SIMM11), 0 } }, + & ifmt_addi, { 0x3b } + }, +/* asr $rd,$rn,$rm */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RN), ',', OP (RM), 0 } }, + & ifmt_add16, { 0x6a } + }, +/* asr $rd6,$rn6,$rm6 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD6), ',', OP (RN6), ',', OP (RM6), 0 } }, + & ifmt_add, { 0xa006f } + }, +/* lsr $rd,$rn,$rm */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RN), ',', OP (RM), 0 } }, + & ifmt_add16, { 0x4a } + }, +/* lsr $rd6,$rn6,$rm6 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD6), ',', OP (RN6), ',', OP (RM6), 0 } }, + & ifmt_add, { 0xa004f } + }, +/* lsl $rd,$rn,$rm */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RN), ',', OP (RM), 0 } }, + & ifmt_add16, { 0x2a } + }, +/* lsl $rd6,$rn6,$rm6 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD6), ',', OP (RN6), ',', OP (RM6), 0 } }, + & ifmt_add, { 0xa002f } + }, +/* lsr $rd,$rn,$shift */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RN), ',', OP (SHIFT), 0 } }, + & ifmt_lsri16, { 0x6 } + }, +/* lsr $rd6,$rn6,$shift */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD6), ',', OP (RN6), ',', OP (SHIFT), 0 } }, + & ifmt_lsri32, { 0x6000f } + }, +/* lsl $rd,$rn,$shift */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RN), ',', OP (SHIFT), 0 } }, + & ifmt_lsri16, { 0x16 } + }, +/* lsl $rd6,$rn6,$shift */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD6), ',', OP (RN6), ',', OP (SHIFT), 0 } }, + & ifmt_lsri32, { 0x6001f } + }, +/* asr $rd,$rn,$shift */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RN), ',', OP (SHIFT), 0 } }, + & ifmt_lsri16, { 0xe } + }, +/* asr $rd6,$rn6,$shift */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD6), ',', OP (RN6), ',', OP (SHIFT), 0 } }, + & ifmt_lsri32, { 0xe000f } + }, +/* bitr $rd,$rn */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RN), 0 } }, + & ifmt_bitr16, { 0x1e } + }, +/* bitr $rd6,$rn6 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD6), ',', OP (RN6), 0 } }, + & ifmt_bitr, { 0xe001f } + }, +/* fext $rd6,$rn6,$rm6 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD6), ',', OP (RN6), ',', OP (RM6), 0 } }, + & ifmt_fext, { 0x1a000f } + }, +/* fdep $rd6,$rn6,$rm6 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD6), ',', OP (RN6), ',', OP (RM6), 0 } }, + & ifmt_fext, { 0x1a001f } + }, +/* lfsr $rd6,$rn6,$rm6 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD6), ',', OP (RN6), ',', OP (RM6), 0 } }, + & ifmt_fext, { 0x1a002f } + }, +/* mov.b $rd,$imm8 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (IMM8), 0 } }, + & ifmt_mov8, { 0x3 } + }, +/* mov.l $rd6,$imm16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD6), ',', OP (IMM16), 0 } }, + & ifmt_mov16, { 0x2000b } + }, +/* movt $rd6,$imm16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD6), ',', OP (IMM16), 0 } }, + & ifmt_mov16, { 0x1002000b } + }, +/* fadd $rd,$rn,$rm */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RN), ',', OP (RM), 0 } }, + & ifmt_add16, { 0x7 } + }, +/* fadd $rd6,$rn6,$rm6 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD6), ',', OP (RN6), ',', OP (RM6), 0 } }, + & ifmt_add, { 0x7000f } + }, +/* fsub $rd,$rn,$rm */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RN), ',', OP (RM), 0 } }, + & ifmt_add16, { 0x17 } + }, +/* fsub $rd6,$rn6,$rm6 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD6), ',', OP (RN6), ',', OP (RM6), 0 } }, + & ifmt_add, { 0x7001f } + }, +/* fmul $rd,$rn,$rm */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RN), ',', OP (RM), 0 } }, + & ifmt_add16, { 0x27 } + }, +/* fmul $rd6,$rn6,$rm6 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD6), ',', OP (RN6), ',', OP (RM6), 0 } }, + & ifmt_add, { 0x7002f } + }, +/* fmadd $rd,$rn,$rm */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RN), ',', OP (RM), 0 } }, + & ifmt_add16, { 0x37 } + }, +/* fmadd $rd6,$rn6,$rm6 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD6), ',', OP (RN6), ',', OP (RM6), 0 } }, + & ifmt_add, { 0x7003f } + }, +/* fmsub $rd,$rn,$rm */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RN), ',', OP (RM), 0 } }, + & ifmt_add16, { 0x47 } + }, +/* fmsub $rd6,$rn6,$rm6 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD6), ',', OP (RN6), ',', OP (RM6), 0 } }, + & ifmt_add, { 0x7004f } + }, +/* fabs rd,rn */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', 'd', ',', 'r', 'n', 0 } }, + & ifmt_f_absf16, { 0x77 } + }, +/* fabs $rd6,$rn6 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD6), ',', OP (RN6), 0 } }, + & ifmt_f_absf32, { 0x7007f } + }, +/* float $rd,$rn */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RN), 0 } }, + & ifmt_f_loatf16, { 0x57 } + }, +/* float $rd6,$rn6 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD6), ',', OP (RN6), 0 } }, + & ifmt_f_absf32, { 0x7005f } + }, +/* fix $rd,$rn */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RN), 0 } }, + & ifmt_f_absf16, { 0x67 } + }, +/* fix $rd6,$rn6 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD6), ',', OP (RN6), 0 } }, + & ifmt_f_absf32, { 0x7006f } + }, +/* frecip $frd6,$frn6 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (FRD6), ',', OP (FRN6), 0 } }, + & ifmt_f_recipf32, { 0x17000f } + }, +/* fsqrt $frd6,$frn6 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (FRD6), ',', OP (FRN6), 0 } }, + & ifmt_f_recipf32, { 0x17001f } + }, +}; + +#undef A +#undef OPERAND +#undef MNEM +#undef OP + +/* Formats for ALIAS macro-insns. */ + +#define F(f) & epiphany_cgen_ifld_table[EPIPHANY_##f] +static const CGEN_IFMT ifmt_beq16r ATTRIBUTE_UNUSED = { + 16, 16, 0xff, { { F (F_OPC) }, { F (F_CONDCODE) }, { F (F_SIMM8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_beq32r ATTRIBUTE_UNUSED = { + 32, 32, 0xff, { { F (F_OPC) }, { F (F_CONDCODE) }, { F (F_SIMM24) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_bne16r ATTRIBUTE_UNUSED = { + 16, 16, 0xff, { { F (F_OPC) }, { F (F_CONDCODE) }, { F (F_SIMM8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_bne32r ATTRIBUTE_UNUSED = { + 32, 32, 0xff, { { F (F_OPC) }, { F (F_CONDCODE) }, { F (F_SIMM24) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_bgtu16r ATTRIBUTE_UNUSED = { + 16, 16, 0xff, { { F (F_OPC) }, { F (F_CONDCODE) }, { F (F_SIMM8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_bgtu32r ATTRIBUTE_UNUSED = { + 32, 32, 0xff, { { F (F_OPC) }, { F (F_CONDCODE) }, { F (F_SIMM24) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_bgteu16r ATTRIBUTE_UNUSED = { + 16, 16, 0xff, { { F (F_OPC) }, { F (F_CONDCODE) }, { F (F_SIMM8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_bgteu32r ATTRIBUTE_UNUSED = { + 32, 32, 0xff, { { F (F_OPC) }, { F (F_CONDCODE) }, { F (F_SIMM24) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_blteu16r ATTRIBUTE_UNUSED = { + 16, 16, 0xff, { { F (F_OPC) }, { F (F_CONDCODE) }, { F (F_SIMM8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_blteu32r ATTRIBUTE_UNUSED = { + 32, 32, 0xff, { { F (F_OPC) }, { F (F_CONDCODE) }, { F (F_SIMM24) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_bltu16r ATTRIBUTE_UNUSED = { + 16, 16, 0xff, { { F (F_OPC) }, { F (F_CONDCODE) }, { F (F_SIMM8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_bltu32r ATTRIBUTE_UNUSED = { + 32, 32, 0xff, { { F (F_OPC) }, { F (F_CONDCODE) }, { F (F_SIMM24) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_bgt16r ATTRIBUTE_UNUSED = { + 16, 16, 0xff, { { F (F_OPC) }, { F (F_CONDCODE) }, { F (F_SIMM8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_bgt32r ATTRIBUTE_UNUSED = { + 32, 32, 0xff, { { F (F_OPC) }, { F (F_CONDCODE) }, { F (F_SIMM24) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_bgte16r ATTRIBUTE_UNUSED = { + 16, 16, 0xff, { { F (F_OPC) }, { F (F_CONDCODE) }, { F (F_SIMM8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_bgte32r ATTRIBUTE_UNUSED = { + 32, 32, 0xff, { { F (F_OPC) }, { F (F_CONDCODE) }, { F (F_SIMM24) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_blt16r ATTRIBUTE_UNUSED = { + 16, 16, 0xff, { { F (F_OPC) }, { F (F_CONDCODE) }, { F (F_SIMM8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_blt32r ATTRIBUTE_UNUSED = { + 32, 32, 0xff, { { F (F_OPC) }, { F (F_CONDCODE) }, { F (F_SIMM24) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_blte16r ATTRIBUTE_UNUSED = { + 16, 16, 0xff, { { F (F_OPC) }, { F (F_CONDCODE) }, { F (F_SIMM8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_blte32r ATTRIBUTE_UNUSED = { + 32, 32, 0xff, { { F (F_OPC) }, { F (F_CONDCODE) }, { F (F_SIMM24) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_bbeq16r ATTRIBUTE_UNUSED = { + 16, 16, 0xff, { { F (F_OPC) }, { F (F_CONDCODE) }, { F (F_SIMM8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_bbeq32r ATTRIBUTE_UNUSED = { + 32, 32, 0xff, { { F (F_OPC) }, { F (F_CONDCODE) }, { F (F_SIMM24) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_bbne16r ATTRIBUTE_UNUSED = { + 16, 16, 0xff, { { F (F_OPC) }, { F (F_CONDCODE) }, { F (F_SIMM8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_bbne32r ATTRIBUTE_UNUSED = { + 32, 32, 0xff, { { F (F_OPC) }, { F (F_CONDCODE) }, { F (F_SIMM24) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_bblt16r ATTRIBUTE_UNUSED = { + 16, 16, 0xff, { { F (F_OPC) }, { F (F_CONDCODE) }, { F (F_SIMM8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_bblt32r ATTRIBUTE_UNUSED = { + 32, 32, 0xff, { { F (F_OPC) }, { F (F_CONDCODE) }, { F (F_SIMM24) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_bblte16r ATTRIBUTE_UNUSED = { + 16, 16, 0xff, { { F (F_OPC) }, { F (F_CONDCODE) }, { F (F_SIMM8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_bblte32r ATTRIBUTE_UNUSED = { + 32, 32, 0xff, { { F (F_OPC) }, { F (F_CONDCODE) }, { F (F_SIMM24) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_b16r ATTRIBUTE_UNUSED = { + 16, 16, 0xff, { { F (F_OPC) }, { F (F_CONDCODE) }, { F (F_SIMM8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_b32r ATTRIBUTE_UNUSED = { + 32, 32, 0xff, { { F (F_OPC) }, { F (F_CONDCODE) }, { F (F_SIMM24) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_bl16r ATTRIBUTE_UNUSED = { + 16, 16, 0xff, { { F (F_OPC) }, { F (F_CONDCODE) }, { F (F_SIMM8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_blr ATTRIBUTE_UNUSED = { + 32, 32, 0xff, { { F (F_OPC) }, { F (F_CONDCODE) }, { F (F_SIMM24) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_ldrbx ATTRIBUTE_UNUSED = { + 32, 32, 0x6f007f, { { F (F_OPC) }, { F (F_WORDSIZE) }, { F (F_STORE) }, { F (F_OPC_19_4) }, { F (F_DC_22_1) }, { F (F_DC_21_1) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_ADDSUBX) }, { F (F_RM6) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_ldrbp ATTRIBUTE_UNUSED = { + 32, 32, 0x6f007f, { { F (F_OPC) }, { F (F_WORDSIZE) }, { F (F_STORE) }, { F (F_OPC_19_4) }, { F (F_DC_22_2) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_ADDSUBX) }, { F (F_RM6) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_ldrbd ATTRIBUTE_UNUSED = { + 32, 32, 0x200007f, { { F (F_OPC) }, { F (F_WORDSIZE) }, { F (F_STORE) }, { F (F_PM) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_SUBD) }, { F (F_DISP11) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_ldrbdpm ATTRIBUTE_UNUSED = { + 32, 32, 0x200007f, { { F (F_OPC) }, { F (F_WORDSIZE) }, { F (F_STORE) }, { F (F_PM) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_SUBD) }, { F (F_DISP11) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_ldrbds0 ATTRIBUTE_UNUSED = { + 16, 16, 0x3ff, { { F (F_OPC) }, { F (F_WORDSIZE) }, { F (F_STORE) }, { F (F_RD) }, { F (F_RN) }, { F (F_DISP3) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_ldrbdl0 ATTRIBUTE_UNUSED = { + 32, 32, 0x3ff03ff, { { F (F_OPC) }, { F (F_WORDSIZE) }, { F (F_STORE) }, { F (F_PM) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_SUBD) }, { F (F_DISP11) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_ldrbdl0_l ATTRIBUTE_UNUSED = { + 32, 32, 0x3ff03ff, { { F (F_OPC) }, { F (F_WORDSIZE) }, { F (F_STORE) }, { F (F_PM) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_SUBD) }, { F (F_DISP11) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_ldrhx ATTRIBUTE_UNUSED = { + 32, 32, 0x6f007f, { { F (F_OPC) }, { F (F_WORDSIZE) }, { F (F_STORE) }, { F (F_OPC_19_4) }, { F (F_DC_22_1) }, { F (F_DC_21_1) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_ADDSUBX) }, { F (F_RM6) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_ldrhp ATTRIBUTE_UNUSED = { + 32, 32, 0x6f007f, { { F (F_OPC) }, { F (F_WORDSIZE) }, { F (F_STORE) }, { F (F_OPC_19_4) }, { F (F_DC_22_2) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_ADDSUBX) }, { F (F_RM6) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_ldrhd ATTRIBUTE_UNUSED = { + 32, 32, 0x200007f, { { F (F_OPC) }, { F (F_WORDSIZE) }, { F (F_STORE) }, { F (F_PM) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_SUBD) }, { F (F_DISP11) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_ldrhdpm ATTRIBUTE_UNUSED = { + 32, 32, 0x200007f, { { F (F_OPC) }, { F (F_WORDSIZE) }, { F (F_STORE) }, { F (F_PM) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_SUBD) }, { F (F_DISP11) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_ldrhds0 ATTRIBUTE_UNUSED = { + 16, 16, 0x3ff, { { F (F_OPC) }, { F (F_WORDSIZE) }, { F (F_STORE) }, { F (F_RD) }, { F (F_RN) }, { F (F_DISP3) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_ldrhdl0 ATTRIBUTE_UNUSED = { + 32, 32, 0x3ff03ff, { { F (F_OPC) }, { F (F_WORDSIZE) }, { F (F_STORE) }, { F (F_PM) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_SUBD) }, { F (F_DISP11) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_ldrhdl0_l ATTRIBUTE_UNUSED = { + 32, 32, 0x3ff03ff, { { F (F_OPC) }, { F (F_WORDSIZE) }, { F (F_STORE) }, { F (F_PM) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_SUBD) }, { F (F_DISP11) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_ldrx ATTRIBUTE_UNUSED = { + 32, 32, 0x6f007f, { { F (F_OPC) }, { F (F_WORDSIZE) }, { F (F_STORE) }, { F (F_OPC_19_4) }, { F (F_DC_22_1) }, { F (F_DC_21_1) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_ADDSUBX) }, { F (F_RM6) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_ldrp ATTRIBUTE_UNUSED = { + 32, 32, 0x6f007f, { { F (F_OPC) }, { F (F_WORDSIZE) }, { F (F_STORE) }, { F (F_OPC_19_4) }, { F (F_DC_22_2) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_ADDSUBX) }, { F (F_RM6) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_ldrd ATTRIBUTE_UNUSED = { + 32, 32, 0x200007f, { { F (F_OPC) }, { F (F_WORDSIZE) }, { F (F_STORE) }, { F (F_PM) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_SUBD) }, { F (F_DISP11) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_ldrdpm ATTRIBUTE_UNUSED = { + 32, 32, 0x200007f, { { F (F_OPC) }, { F (F_WORDSIZE) }, { F (F_STORE) }, { F (F_PM) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_SUBD) }, { F (F_DISP11) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_ldrds0 ATTRIBUTE_UNUSED = { + 16, 16, 0x3ff, { { F (F_OPC) }, { F (F_WORDSIZE) }, { F (F_STORE) }, { F (F_RD) }, { F (F_RN) }, { F (F_DISP3) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_ldrdl0 ATTRIBUTE_UNUSED = { + 32, 32, 0x3ff03ff, { { F (F_OPC) }, { F (F_WORDSIZE) }, { F (F_STORE) }, { F (F_PM) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_SUBD) }, { F (F_DISP11) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_ldrdl0_l ATTRIBUTE_UNUSED = { + 32, 32, 0x3ff03ff, { { F (F_OPC) }, { F (F_WORDSIZE) }, { F (F_STORE) }, { F (F_PM) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_SUBD) }, { F (F_DISP11) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_ldrdx ATTRIBUTE_UNUSED = { + 32, 32, 0x6f007f, { { F (F_OPC) }, { F (F_WORDSIZE) }, { F (F_STORE) }, { F (F_OPC_19_4) }, { F (F_DC_22_1) }, { F (F_DC_21_1) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_ADDSUBX) }, { F (F_RM6) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_ldrdp ATTRIBUTE_UNUSED = { + 32, 32, 0x6f007f, { { F (F_OPC) }, { F (F_WORDSIZE) }, { F (F_STORE) }, { F (F_OPC_19_4) }, { F (F_DC_22_2) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_ADDSUBX) }, { F (F_RM6) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_ldrdd ATTRIBUTE_UNUSED = { + 32, 32, 0x200007f, { { F (F_OPC) }, { F (F_WORDSIZE) }, { F (F_STORE) }, { F (F_PM) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_SUBD) }, { F (F_DISP11) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_ldrddpm ATTRIBUTE_UNUSED = { + 32, 32, 0x200007f, { { F (F_OPC) }, { F (F_WORDSIZE) }, { F (F_STORE) }, { F (F_PM) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_SUBD) }, { F (F_DISP11) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_ldrdds0 ATTRIBUTE_UNUSED = { + 16, 16, 0x3ff, { { F (F_OPC) }, { F (F_WORDSIZE) }, { F (F_STORE) }, { F (F_RD) }, { F (F_RN) }, { F (F_DISP3) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_ldrddl0 ATTRIBUTE_UNUSED = { + 32, 32, 0x3ff03ff, { { F (F_OPC) }, { F (F_WORDSIZE) }, { F (F_STORE) }, { F (F_PM) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_SUBD) }, { F (F_DISP11) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_ldrddl0_l ATTRIBUTE_UNUSED = { + 32, 32, 0x3ff03ff, { { F (F_OPC) }, { F (F_WORDSIZE) }, { F (F_STORE) }, { F (F_PM) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_SUBD) }, { F (F_DISP11) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_testsetbt_l ATTRIBUTE_UNUSED = { + 32, 32, 0x6f007f, { { F (F_OPC) }, { F (F_WORDSIZE) }, { F (F_STORE) }, { F (F_OPC_19_4) }, { F (F_DC_22_1) }, { F (F_DC_21_1) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_ADDSUBX) }, { F (F_RM6) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_testsetht_l ATTRIBUTE_UNUSED = { + 32, 32, 0x6f007f, { { F (F_OPC) }, { F (F_WORDSIZE) }, { F (F_STORE) }, { F (F_OPC_19_4) }, { F (F_DC_22_1) }, { F (F_DC_21_1) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_ADDSUBX) }, { F (F_RM6) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_testsett_l ATTRIBUTE_UNUSED = { + 32, 32, 0x6f007f, { { F (F_OPC) }, { F (F_WORDSIZE) }, { F (F_STORE) }, { F (F_OPC_19_4) }, { F (F_DC_22_1) }, { F (F_DC_21_1) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_ADDSUBX) }, { F (F_RM6) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_strbx_l ATTRIBUTE_UNUSED = { + 32, 32, 0x6f007f, { { F (F_OPC) }, { F (F_WORDSIZE) }, { F (F_STORE) }, { F (F_OPC_19_4) }, { F (F_DC_22_1) }, { F (F_DC_21_1) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_ADDSUBX) }, { F (F_RM6) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_strbp_l ATTRIBUTE_UNUSED = { + 32, 32, 0x6f007f, { { F (F_OPC) }, { F (F_WORDSIZE) }, { F (F_STORE) }, { F (F_OPC_19_4) }, { F (F_DC_22_2) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_ADDSUBX) }, { F (F_RM6) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_strbd_l ATTRIBUTE_UNUSED = { + 32, 32, 0x200007f, { { F (F_OPC) }, { F (F_WORDSIZE) }, { F (F_STORE) }, { F (F_PM) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_SUBD) }, { F (F_DISP11) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_strbdpm_l ATTRIBUTE_UNUSED = { + 32, 32, 0x200007f, { { F (F_OPC) }, { F (F_WORDSIZE) }, { F (F_STORE) }, { F (F_PM) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_SUBD) }, { F (F_DISP11) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_strbds0 ATTRIBUTE_UNUSED = { + 16, 16, 0x3ff, { { F (F_OPC) }, { F (F_WORDSIZE) }, { F (F_STORE) }, { F (F_RD) }, { F (F_RN) }, { F (F_DISP3) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_strbdl0 ATTRIBUTE_UNUSED = { + 32, 32, 0x3ff03ff, { { F (F_OPC) }, { F (F_WORDSIZE) }, { F (F_STORE) }, { F (F_PM) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_SUBD) }, { F (F_DISP11) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_strbdl0_l ATTRIBUTE_UNUSED = { + 32, 32, 0x3ff03ff, { { F (F_OPC) }, { F (F_WORDSIZE) }, { F (F_STORE) }, { F (F_PM) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_SUBD) }, { F (F_DISP11) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_strhx_l ATTRIBUTE_UNUSED = { + 32, 32, 0x6f007f, { { F (F_OPC) }, { F (F_WORDSIZE) }, { F (F_STORE) }, { F (F_OPC_19_4) }, { F (F_DC_22_1) }, { F (F_DC_21_1) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_ADDSUBX) }, { F (F_RM6) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_strhp_l ATTRIBUTE_UNUSED = { + 32, 32, 0x6f007f, { { F (F_OPC) }, { F (F_WORDSIZE) }, { F (F_STORE) }, { F (F_OPC_19_4) }, { F (F_DC_22_2) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_ADDSUBX) }, { F (F_RM6) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_strhd_l ATTRIBUTE_UNUSED = { + 32, 32, 0x200007f, { { F (F_OPC) }, { F (F_WORDSIZE) }, { F (F_STORE) }, { F (F_PM) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_SUBD) }, { F (F_DISP11) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_strhdpm_l ATTRIBUTE_UNUSED = { + 32, 32, 0x200007f, { { F (F_OPC) }, { F (F_WORDSIZE) }, { F (F_STORE) }, { F (F_PM) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_SUBD) }, { F (F_DISP11) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_strhds0 ATTRIBUTE_UNUSED = { + 16, 16, 0x3ff, { { F (F_OPC) }, { F (F_WORDSIZE) }, { F (F_STORE) }, { F (F_RD) }, { F (F_RN) }, { F (F_DISP3) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_strhdl0 ATTRIBUTE_UNUSED = { + 32, 32, 0x3ff03ff, { { F (F_OPC) }, { F (F_WORDSIZE) }, { F (F_STORE) }, { F (F_PM) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_SUBD) }, { F (F_DISP11) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_strhdl0_l ATTRIBUTE_UNUSED = { + 32, 32, 0x3ff03ff, { { F (F_OPC) }, { F (F_WORDSIZE) }, { F (F_STORE) }, { F (F_PM) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_SUBD) }, { F (F_DISP11) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_strx_l ATTRIBUTE_UNUSED = { + 32, 32, 0x6f007f, { { F (F_OPC) }, { F (F_WORDSIZE) }, { F (F_STORE) }, { F (F_OPC_19_4) }, { F (F_DC_22_1) }, { F (F_DC_21_1) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_ADDSUBX) }, { F (F_RM6) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_strp_l ATTRIBUTE_UNUSED = { + 32, 32, 0x6f007f, { { F (F_OPC) }, { F (F_WORDSIZE) }, { F (F_STORE) }, { F (F_OPC_19_4) }, { F (F_DC_22_2) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_ADDSUBX) }, { F (F_RM6) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_strd_l ATTRIBUTE_UNUSED = { + 32, 32, 0x200007f, { { F (F_OPC) }, { F (F_WORDSIZE) }, { F (F_STORE) }, { F (F_PM) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_SUBD) }, { F (F_DISP11) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_strdpm_l ATTRIBUTE_UNUSED = { + 32, 32, 0x200007f, { { F (F_OPC) }, { F (F_WORDSIZE) }, { F (F_STORE) }, { F (F_PM) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_SUBD) }, { F (F_DISP11) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_strds0 ATTRIBUTE_UNUSED = { + 16, 16, 0x3ff, { { F (F_OPC) }, { F (F_WORDSIZE) }, { F (F_STORE) }, { F (F_RD) }, { F (F_RN) }, { F (F_DISP3) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_strdl0 ATTRIBUTE_UNUSED = { + 32, 32, 0x3ff03ff, { { F (F_OPC) }, { F (F_WORDSIZE) }, { F (F_STORE) }, { F (F_PM) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_SUBD) }, { F (F_DISP11) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_strdl0_l ATTRIBUTE_UNUSED = { + 32, 32, 0x3ff03ff, { { F (F_OPC) }, { F (F_WORDSIZE) }, { F (F_STORE) }, { F (F_PM) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_SUBD) }, { F (F_DISP11) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_strdx_l ATTRIBUTE_UNUSED = { + 32, 32, 0x6f007f, { { F (F_OPC) }, { F (F_WORDSIZE) }, { F (F_STORE) }, { F (F_OPC_19_4) }, { F (F_DC_22_1) }, { F (F_DC_21_1) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_ADDSUBX) }, { F (F_RM6) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_strdp_l ATTRIBUTE_UNUSED = { + 32, 32, 0x6f007f, { { F (F_OPC) }, { F (F_WORDSIZE) }, { F (F_STORE) }, { F (F_OPC_19_4) }, { F (F_DC_22_2) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_ADDSUBX) }, { F (F_RM6) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_strdd_l ATTRIBUTE_UNUSED = { + 32, 32, 0x200007f, { { F (F_OPC) }, { F (F_WORDSIZE) }, { F (F_STORE) }, { F (F_PM) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_SUBD) }, { F (F_DISP11) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_strddpm_l ATTRIBUTE_UNUSED = { + 32, 32, 0x200007f, { { F (F_OPC) }, { F (F_WORDSIZE) }, { F (F_STORE) }, { F (F_PM) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_SUBD) }, { F (F_DISP11) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_strdds0 ATTRIBUTE_UNUSED = { + 16, 16, 0x3ff, { { F (F_OPC) }, { F (F_WORDSIZE) }, { F (F_STORE) }, { F (F_RD) }, { F (F_RN) }, { F (F_DISP3) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_strddl0 ATTRIBUTE_UNUSED = { + 32, 32, 0x3ff03ff, { { F (F_OPC) }, { F (F_WORDSIZE) }, { F (F_STORE) }, { F (F_PM) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_SUBD) }, { F (F_DISP11) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_strddl0_l ATTRIBUTE_UNUSED = { + 32, 32, 0x3ff03ff, { { F (F_OPC) }, { F (F_WORDSIZE) }, { F (F_STORE) }, { F (F_PM) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_SUBD) }, { F (F_DISP11) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_cmov_lEQ ATTRIBUTE_UNUSED = { + 32, 32, 0x3ff03ff, { { F (F_OPC) }, { F (F_CONDCODE) }, { F (F_OPC_8_1) }, { F (F_DC_9_1) }, { F (F_OPC_19_4) }, { F (F_DC_25_6) }, { F (F_RD6) }, { F (F_RN6) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_cmov_lNE ATTRIBUTE_UNUSED = { + 32, 32, 0x3ff03ff, { { F (F_OPC) }, { F (F_CONDCODE) }, { F (F_OPC_8_1) }, { F (F_DC_9_1) }, { F (F_OPC_19_4) }, { F (F_DC_25_6) }, { F (F_RD6) }, { F (F_RN6) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_cmov_lGTU ATTRIBUTE_UNUSED = { + 32, 32, 0x3ff03ff, { { F (F_OPC) }, { F (F_CONDCODE) }, { F (F_OPC_8_1) }, { F (F_DC_9_1) }, { F (F_OPC_19_4) }, { F (F_DC_25_6) }, { F (F_RD6) }, { F (F_RN6) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_cmov_lGTEU ATTRIBUTE_UNUSED = { + 32, 32, 0x3ff03ff, { { F (F_OPC) }, { F (F_CONDCODE) }, { F (F_OPC_8_1) }, { F (F_DC_9_1) }, { F (F_OPC_19_4) }, { F (F_DC_25_6) }, { F (F_RD6) }, { F (F_RN6) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_cmov_lLTEU ATTRIBUTE_UNUSED = { + 32, 32, 0x3ff03ff, { { F (F_OPC) }, { F (F_CONDCODE) }, { F (F_OPC_8_1) }, { F (F_DC_9_1) }, { F (F_OPC_19_4) }, { F (F_DC_25_6) }, { F (F_RD6) }, { F (F_RN6) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_cmov_lLTU ATTRIBUTE_UNUSED = { + 32, 32, 0x3ff03ff, { { F (F_OPC) }, { F (F_CONDCODE) }, { F (F_OPC_8_1) }, { F (F_DC_9_1) }, { F (F_OPC_19_4) }, { F (F_DC_25_6) }, { F (F_RD6) }, { F (F_RN6) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_cmov_lGT ATTRIBUTE_UNUSED = { + 32, 32, 0x3ff03ff, { { F (F_OPC) }, { F (F_CONDCODE) }, { F (F_OPC_8_1) }, { F (F_DC_9_1) }, { F (F_OPC_19_4) }, { F (F_DC_25_6) }, { F (F_RD6) }, { F (F_RN6) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_cmov_lGTE ATTRIBUTE_UNUSED = { + 32, 32, 0x3ff03ff, { { F (F_OPC) }, { F (F_CONDCODE) }, { F (F_OPC_8_1) }, { F (F_DC_9_1) }, { F (F_OPC_19_4) }, { F (F_DC_25_6) }, { F (F_RD6) }, { F (F_RN6) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_cmov_lLT ATTRIBUTE_UNUSED = { + 32, 32, 0x3ff03ff, { { F (F_OPC) }, { F (F_CONDCODE) }, { F (F_OPC_8_1) }, { F (F_DC_9_1) }, { F (F_OPC_19_4) }, { F (F_DC_25_6) }, { F (F_RD6) }, { F (F_RN6) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_cmov_lLTE ATTRIBUTE_UNUSED = { + 32, 32, 0x3ff03ff, { { F (F_OPC) }, { F (F_CONDCODE) }, { F (F_OPC_8_1) }, { F (F_DC_9_1) }, { F (F_OPC_19_4) }, { F (F_DC_25_6) }, { F (F_RD6) }, { F (F_RN6) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_cmov_lB ATTRIBUTE_UNUSED = { + 32, 32, 0x3ff03ff, { { F (F_OPC) }, { F (F_CONDCODE) }, { F (F_OPC_8_1) }, { F (F_DC_9_1) }, { F (F_OPC_19_4) }, { F (F_DC_25_6) }, { F (F_RD6) }, { F (F_RN6) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_cmov_lBEQ ATTRIBUTE_UNUSED = { + 32, 32, 0x3ff03ff, { { F (F_OPC) }, { F (F_CONDCODE) }, { F (F_OPC_8_1) }, { F (F_DC_9_1) }, { F (F_OPC_19_4) }, { F (F_DC_25_6) }, { F (F_RD6) }, { F (F_RN6) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_cmov_lBNE ATTRIBUTE_UNUSED = { + 32, 32, 0x3ff03ff, { { F (F_OPC) }, { F (F_CONDCODE) }, { F (F_OPC_8_1) }, { F (F_DC_9_1) }, { F (F_OPC_19_4) }, { F (F_DC_25_6) }, { F (F_RD6) }, { F (F_RN6) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_cmov_lBLT ATTRIBUTE_UNUSED = { + 32, 32, 0x3ff03ff, { { F (F_OPC) }, { F (F_CONDCODE) }, { F (F_OPC_8_1) }, { F (F_DC_9_1) }, { F (F_OPC_19_4) }, { F (F_DC_25_6) }, { F (F_RD6) }, { F (F_RN6) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_cmov_lBLTE ATTRIBUTE_UNUSED = { + 32, 32, 0x3ff03ff, { { F (F_OPC) }, { F (F_CONDCODE) }, { F (F_OPC_8_1) }, { F (F_DC_9_1) }, { F (F_OPC_19_4) }, { F (F_DC_25_6) }, { F (F_RD6) }, { F (F_RN6) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_movts_l6 ATTRIBUTE_UNUSED = { + 32, 32, 0x3ff03ff, { { F (F_OPC) }, { F (F_DC_7_4) }, { F (F_OPC_8_1) }, { F (F_DC_9_1) }, { F (F_OPC_19_4) }, { F (F_DC_25_4) }, { F (F_DC_21_2) }, { F (F_SN6) }, { F (F_RD6) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_movts_ldma ATTRIBUTE_UNUSED = { + 32, 32, 0x3ff03ff, { { F (F_OPC) }, { F (F_DC_7_4) }, { F (F_OPC_8_1) }, { F (F_DC_9_1) }, { F (F_OPC_19_4) }, { F (F_DC_25_4) }, { F (F_DC_21_2) }, { F (F_SN6) }, { F (F_RD6) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_movts_lmem ATTRIBUTE_UNUSED = { + 32, 32, 0x3ff03ff, { { F (F_OPC) }, { F (F_DC_7_4) }, { F (F_OPC_8_1) }, { F (F_DC_9_1) }, { F (F_OPC_19_4) }, { F (F_DC_25_4) }, { F (F_DC_21_2) }, { F (F_SN6) }, { F (F_RD6) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_movts_lmesh ATTRIBUTE_UNUSED = { + 32, 32, 0x3ff03ff, { { F (F_OPC) }, { F (F_DC_7_4) }, { F (F_OPC_8_1) }, { F (F_DC_9_1) }, { F (F_OPC_19_4) }, { F (F_DC_25_4) }, { F (F_DC_21_2) }, { F (F_SN6) }, { F (F_RD6) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_movfs_l6 ATTRIBUTE_UNUSED = { + 32, 32, 0x3ff03ff, { { F (F_OPC) }, { F (F_DC_7_4) }, { F (F_OPC_8_1) }, { F (F_DC_9_1) }, { F (F_OPC_19_4) }, { F (F_DC_25_4) }, { F (F_DC_21_2) }, { F (F_RD6) }, { F (F_SN6) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_movfs_ldma ATTRIBUTE_UNUSED = { + 32, 32, 0x3ff03ff, { { F (F_OPC) }, { F (F_DC_7_4) }, { F (F_OPC_8_1) }, { F (F_DC_9_1) }, { F (F_OPC_19_4) }, { F (F_DC_25_4) }, { F (F_DC_21_2) }, { F (F_RD6) }, { F (F_SN6) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_movfs_lmem ATTRIBUTE_UNUSED = { + 32, 32, 0x3ff03ff, { { F (F_OPC) }, { F (F_DC_7_4) }, { F (F_OPC_8_1) }, { F (F_DC_9_1) }, { F (F_OPC_19_4) }, { F (F_DC_25_4) }, { F (F_DC_21_2) }, { F (F_RD6) }, { F (F_SN6) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_movfs_lmesh ATTRIBUTE_UNUSED = { + 32, 32, 0x3ff03ff, { { F (F_OPC) }, { F (F_DC_7_4) }, { F (F_OPC_8_1) }, { F (F_DC_9_1) }, { F (F_OPC_19_4) }, { F (F_DC_25_4) }, { F (F_DC_21_2) }, { F (F_RD6) }, { F (F_SN6) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_add_l ATTRIBUTE_UNUSED = { + 32, 32, 0x7f007f, { { F (F_OPC) }, { F (F_OPC_6_3) }, { F (F_OPC_19_4) }, { F (F_DC_22_3) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_RM6) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_sub_l ATTRIBUTE_UNUSED = { + 32, 32, 0x7f007f, { { F (F_OPC) }, { F (F_OPC_6_3) }, { F (F_OPC_19_4) }, { F (F_DC_22_3) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_RM6) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_and_l ATTRIBUTE_UNUSED = { + 32, 32, 0x7f007f, { { F (F_OPC) }, { F (F_OPC_6_3) }, { F (F_OPC_19_4) }, { F (F_DC_22_3) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_RM6) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_orr_l ATTRIBUTE_UNUSED = { + 32, 32, 0x7f007f, { { F (F_OPC) }, { F (F_OPC_6_3) }, { F (F_OPC_19_4) }, { F (F_DC_22_3) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_RM6) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_eor_l ATTRIBUTE_UNUSED = { + 32, 32, 0x7f007f, { { F (F_OPC) }, { F (F_OPC_6_3) }, { F (F_OPC_19_4) }, { F (F_DC_22_3) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_RM6) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_addir ATTRIBUTE_UNUSED = { + 16, 16, 0x7f, { { F (F_OPC) }, { F (F_OPC_6_3) }, { F (F_RD) }, { F (F_RN) }, { F (F_SDISP3) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_addi32r ATTRIBUTE_UNUSED = { + 32, 32, 0x300007f, { { F (F_OPC) }, { F (F_OPC_6_3) }, { F (F_DC_25_2) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_SDISP11) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_addi32m ATTRIBUTE_UNUSED = { + 32, 32, 0x300007f, { { F (F_OPC) }, { F (F_OPC_6_3) }, { F (F_DC_25_2) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_SDISP11) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subir ATTRIBUTE_UNUSED = { + 16, 16, 0x7f, { { F (F_OPC) }, { F (F_OPC_6_3) }, { F (F_RD) }, { F (F_RN) }, { F (F_SDISP3) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subi32r ATTRIBUTE_UNUSED = { + 32, 32, 0x300007f, { { F (F_OPC) }, { F (F_OPC_6_3) }, { F (F_DC_25_2) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_SDISP11) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subi32m ATTRIBUTE_UNUSED = { + 32, 32, 0x300007f, { { F (F_OPC) }, { F (F_OPC_6_3) }, { F (F_DC_25_2) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_SDISP11) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_asr_l ATTRIBUTE_UNUSED = { + 32, 32, 0x7f007f, { { F (F_OPC) }, { F (F_OPC_6_3) }, { F (F_OPC_19_4) }, { F (F_DC_22_3) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_RM6) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_lsr_l ATTRIBUTE_UNUSED = { + 32, 32, 0x7f007f, { { F (F_OPC) }, { F (F_OPC_6_3) }, { F (F_OPC_19_4) }, { F (F_DC_22_3) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_RM6) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_lsl_l ATTRIBUTE_UNUSED = { + 32, 32, 0x7f007f, { { F (F_OPC) }, { F (F_OPC_6_3) }, { F (F_OPC_19_4) }, { F (F_DC_22_3) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_RM6) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_lsri32_l ATTRIBUTE_UNUSED = { + 32, 32, 0x3ff001f, { { F (F_OPC) }, { F (F_OPC_4_1) }, { F (F_OPC_19_4) }, { F (F_DC_25_6) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_SHIFT) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_lsli32_l ATTRIBUTE_UNUSED = { + 32, 32, 0x3ff001f, { { F (F_OPC) }, { F (F_OPC_4_1) }, { F (F_OPC_19_4) }, { F (F_DC_25_6) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_SHIFT) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_asri32_l ATTRIBUTE_UNUSED = { + 32, 32, 0x3ff001f, { { F (F_OPC) }, { F (F_OPC_4_1) }, { F (F_OPC_19_4) }, { F (F_DC_25_6) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_SHIFT) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_bitrl ATTRIBUTE_UNUSED = { + 32, 32, 0x3ff03ff, { { F (F_OPC) }, { F (F_OPC_4_1) }, { F (F_OPC_19_4) }, { F (F_DC_25_6) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_SHIFT) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_fext_l ATTRIBUTE_UNUSED = { + 32, 32, 0x7f007f, { { F (F_OPC) }, { F (F_OPC_6_3) }, { F (F_OPC_19_4) }, { F (F_DC_22_2) }, { F (F_DC_20_1) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_RM6) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_fdep_l ATTRIBUTE_UNUSED = { + 32, 32, 0x7f007f, { { F (F_OPC) }, { F (F_OPC_6_3) }, { F (F_OPC_19_4) }, { F (F_DC_22_2) }, { F (F_DC_20_1) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_RM6) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_lfsr_l ATTRIBUTE_UNUSED = { + 32, 32, 0x7f007f, { { F (F_OPC) }, { F (F_OPC_6_3) }, { F (F_OPC_19_4) }, { F (F_DC_22_2) }, { F (F_DC_20_1) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_RM6) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov8r ATTRIBUTE_UNUSED = { + 16, 16, 0x1f, { { F (F_OPC) }, { F (F_OPC_4_1) }, { F (F_RD) }, { F (F_IMM8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov16r ATTRIBUTE_UNUSED = { + 32, 32, 0x100f001f, { { F (F_OPC) }, { F (F_OPC_4_1) }, { F (F_OPC_19_4) }, { F (F_DC_28_1) }, { F (F_RD6) }, { F (F_IMM16) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_movtl ATTRIBUTE_UNUSED = { + 32, 32, 0x100f001f, { { F (F_OPC) }, { F (F_OPC_4_1) }, { F (F_OPC_19_4) }, { F (F_DC_28_1) }, { F (F_RD6) }, { F (F_IMM16) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_i_addf16 ATTRIBUTE_UNUSED = { + 16, 16, 0x7f, { { F (F_OPC) }, { F (F_OPC_6_3) }, { F (F_RD) }, { F (F_RN) }, { F (F_RM) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_f_addf32_l ATTRIBUTE_UNUSED = { + 32, 32, 0x7f007f, { { F (F_OPC) }, { F (F_OPC_6_3) }, { F (F_OPC_19_4) }, { F (F_DC_22_3) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_RM6) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_i_addf32 ATTRIBUTE_UNUSED = { + 32, 32, 0x7f007f, { { F (F_OPC) }, { F (F_OPC_6_3) }, { F (F_OPC_19_4) }, { F (F_DC_22_3) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_RM6) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_i_addf32_l ATTRIBUTE_UNUSED = { + 32, 32, 0x7f007f, { { F (F_OPC) }, { F (F_OPC_6_3) }, { F (F_OPC_19_4) }, { F (F_DC_22_3) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_RM6) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_i_subf16 ATTRIBUTE_UNUSED = { + 16, 16, 0x7f, { { F (F_OPC) }, { F (F_OPC_6_3) }, { F (F_RD) }, { F (F_RN) }, { F (F_RM) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_f_subf32_l ATTRIBUTE_UNUSED = { + 32, 32, 0x7f007f, { { F (F_OPC) }, { F (F_OPC_6_3) }, { F (F_OPC_19_4) }, { F (F_DC_22_3) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_RM6) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_i_subf32 ATTRIBUTE_UNUSED = { + 32, 32, 0x7f007f, { { F (F_OPC) }, { F (F_OPC_6_3) }, { F (F_OPC_19_4) }, { F (F_DC_22_3) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_RM6) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_i_subf32_l ATTRIBUTE_UNUSED = { + 32, 32, 0x7f007f, { { F (F_OPC) }, { F (F_OPC_6_3) }, { F (F_OPC_19_4) }, { F (F_DC_22_3) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_RM6) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_i_mulf16 ATTRIBUTE_UNUSED = { + 16, 16, 0x7f, { { F (F_OPC) }, { F (F_OPC_6_3) }, { F (F_RD) }, { F (F_RN) }, { F (F_RM) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_f_mulf32_l ATTRIBUTE_UNUSED = { + 32, 32, 0x7f007f, { { F (F_OPC) }, { F (F_OPC_6_3) }, { F (F_OPC_19_4) }, { F (F_DC_22_3) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_RM6) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_i_mulf32 ATTRIBUTE_UNUSED = { + 32, 32, 0x7f007f, { { F (F_OPC) }, { F (F_OPC_6_3) }, { F (F_OPC_19_4) }, { F (F_DC_22_3) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_RM6) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_i_mulf32_l ATTRIBUTE_UNUSED = { + 32, 32, 0x7f007f, { { F (F_OPC) }, { F (F_OPC_6_3) }, { F (F_OPC_19_4) }, { F (F_DC_22_3) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_RM6) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_i_maddf16 ATTRIBUTE_UNUSED = { + 16, 16, 0x7f, { { F (F_OPC) }, { F (F_OPC_6_3) }, { F (F_RD) }, { F (F_RN) }, { F (F_RM) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_f_maddf32_l ATTRIBUTE_UNUSED = { + 32, 32, 0x7f007f, { { F (F_OPC) }, { F (F_OPC_6_3) }, { F (F_OPC_19_4) }, { F (F_DC_22_3) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_RM6) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_i_maddf32 ATTRIBUTE_UNUSED = { + 32, 32, 0x7f007f, { { F (F_OPC) }, { F (F_OPC_6_3) }, { F (F_OPC_19_4) }, { F (F_DC_22_3) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_RM6) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_i_maddf32_l ATTRIBUTE_UNUSED = { + 32, 32, 0x7f007f, { { F (F_OPC) }, { F (F_OPC_6_3) }, { F (F_OPC_19_4) }, { F (F_DC_22_3) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_RM6) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_i_msubf16 ATTRIBUTE_UNUSED = { + 16, 16, 0x7f, { { F (F_OPC) }, { F (F_OPC_6_3) }, { F (F_RD) }, { F (F_RN) }, { F (F_RM) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_f_msubf32_l ATTRIBUTE_UNUSED = { + 32, 32, 0x7f007f, { { F (F_OPC) }, { F (F_OPC_6_3) }, { F (F_OPC_19_4) }, { F (F_DC_22_3) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_RM6) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_i_msubf32 ATTRIBUTE_UNUSED = { + 32, 32, 0x7f007f, { { F (F_OPC) }, { F (F_OPC_6_3) }, { F (F_OPC_19_4) }, { F (F_DC_22_3) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_RM6) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_i_msubf32_l ATTRIBUTE_UNUSED = { + 32, 32, 0x7f007f, { { F (F_OPC) }, { F (F_OPC_6_3) }, { F (F_OPC_19_4) }, { F (F_DC_22_3) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_RM6) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_f_absf32_l ATTRIBUTE_UNUSED = { + 32, 32, 0x7f007f, { { F (F_OPC) }, { F (F_OPC_6_3) }, { F (F_OPC_19_4) }, { F (F_DC_22_3) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_RN6) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_f_loatf32_l ATTRIBUTE_UNUSED = { + 32, 32, 0x7f007f, { { F (F_OPC) }, { F (F_OPC_6_3) }, { F (F_OPC_19_4) }, { F (F_DC_22_3) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_RN6) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_f_ixf32_l ATTRIBUTE_UNUSED = { + 32, 32, 0x7f007f, { { F (F_OPC) }, { F (F_OPC_6_3) }, { F (F_OPC_19_4) }, { F (F_DC_22_3) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_RN6) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_f_recipf32_l ATTRIBUTE_UNUSED = { + 32, 32, 0x7f007f, { { F (F_OPC) }, { F (F_OPC_6_3) }, { F (F_OPC_19_4) }, { F (F_DC_22_2) }, { F (F_DC_20_1) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_RN6) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_f_sqrtf32_l ATTRIBUTE_UNUSED = { + 32, 32, 0x7f007f, { { F (F_OPC) }, { F (F_OPC_6_3) }, { F (F_OPC_19_4) }, { F (F_DC_22_2) }, { F (F_DC_20_1) }, { F (F_RD6) }, { F (F_RN6) }, { F (F_RN6) }, { 0 } } +}; + +#undef F + +/* Each non-simple macro entry points to an array of expansion possibilities. */ + +#define A(a) (1 << CGEN_INSN_##a) +#define OPERAND(op) EPIPHANY_OPERAND_##op +#define MNEM CGEN_SYNTAX_MNEMONIC /* syntax value for mnemonic */ +#define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field)) + +/* The macro instruction table. */ + +static const CGEN_IBASE epiphany_cgen_macro_insn_table[] = +{ +/* beq $simm8 */ + { + -1, "beq16r", "beq", 16, + { 0|A(RELAXABLE)|A(COND_CTI)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } } + }, +/* beq $simm24 */ + { + -1, "beq32r", "beq", 32, + { 0|A(RELAXED)|A(COND_CTI)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } } + }, +/* bne $simm8 */ + { + -1, "bne16r", "bne", 16, + { 0|A(RELAXABLE)|A(COND_CTI)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } } + }, +/* bne $simm24 */ + { + -1, "bne32r", "bne", 32, + { 0|A(RELAXED)|A(COND_CTI)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } } + }, +/* bgtu $simm8 */ + { + -1, "bgtu16r", "bgtu", 16, + { 0|A(RELAXABLE)|A(COND_CTI)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } } + }, +/* bgtu $simm24 */ + { + -1, "bgtu32r", "bgtu", 32, + { 0|A(RELAXED)|A(COND_CTI)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } } + }, +/* bgteu $simm8 */ + { + -1, "bgteu16r", "bgteu", 16, + { 0|A(RELAXABLE)|A(COND_CTI)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } } + }, +/* bgteu $simm24 */ + { + -1, "bgteu32r", "bgteu", 32, + { 0|A(RELAXED)|A(COND_CTI)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } } + }, +/* blteu $simm8 */ + { + -1, "blteu16r", "blteu", 16, + { 0|A(RELAXABLE)|A(COND_CTI)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } } + }, +/* blteu $simm24 */ + { + -1, "blteu32r", "blteu", 32, + { 0|A(RELAXED)|A(COND_CTI)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } } + }, +/* bltu $simm8 */ + { + -1, "bltu16r", "bltu", 16, + { 0|A(RELAXABLE)|A(COND_CTI)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } } + }, +/* bltu $simm24 */ + { + -1, "bltu32r", "bltu", 32, + { 0|A(RELAXED)|A(COND_CTI)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } } + }, +/* bgt $simm8 */ + { + -1, "bgt16r", "bgt", 16, + { 0|A(RELAXABLE)|A(COND_CTI)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } } + }, +/* bgt $simm24 */ + { + -1, "bgt32r", "bgt", 32, + { 0|A(RELAXED)|A(COND_CTI)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } } + }, +/* bgte $simm8 */ + { + -1, "bgte16r", "bgte", 16, + { 0|A(RELAXABLE)|A(COND_CTI)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } } + }, +/* bgte $simm24 */ + { + -1, "bgte32r", "bgte", 32, + { 0|A(RELAXED)|A(COND_CTI)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } } + }, +/* blt $simm8 */ + { + -1, "blt16r", "blt", 16, + { 0|A(RELAXABLE)|A(COND_CTI)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } } + }, +/* blt $simm24 */ + { + -1, "blt32r", "blt", 32, + { 0|A(RELAXED)|A(COND_CTI)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } } + }, +/* blte $simm8 */ + { + -1, "blte16r", "blte", 16, + { 0|A(RELAXABLE)|A(COND_CTI)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } } + }, +/* blte $simm24 */ + { + -1, "blte32r", "blte", 32, + { 0|A(RELAXED)|A(COND_CTI)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } } + }, +/* bbeq $simm8 */ + { + -1, "bbeq16r", "bbeq", 16, + { 0|A(RELAXABLE)|A(COND_CTI)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } } + }, +/* bbeq $simm24 */ + { + -1, "bbeq32r", "bbeq", 32, + { 0|A(RELAXED)|A(COND_CTI)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } } + }, +/* bbne $simm8 */ + { + -1, "bbne16r", "bbne", 16, + { 0|A(RELAXABLE)|A(COND_CTI)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } } + }, +/* bbne $simm24 */ + { + -1, "bbne32r", "bbne", 32, + { 0|A(RELAXED)|A(COND_CTI)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } } + }, +/* bblt $simm8 */ + { + -1, "bblt16r", "bblt", 16, + { 0|A(RELAXABLE)|A(COND_CTI)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } } + }, +/* bblt $simm24 */ + { + -1, "bblt32r", "bblt", 32, + { 0|A(RELAXED)|A(COND_CTI)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } } + }, +/* bblte $simm8 */ + { + -1, "bblte16r", "bblte", 16, + { 0|A(RELAXABLE)|A(COND_CTI)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } } + }, +/* bblte $simm24 */ + { + -1, "bblte32r", "bblte", 32, + { 0|A(RELAXED)|A(COND_CTI)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } } + }, +/* b $simm8 */ + { + -1, "b16r", "b", 16, + { 0|A(RELAXABLE)|A(UNCOND_CTI)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } } + }, +/* b $simm24 */ + { + -1, "b32r", "b", 32, + { 0|A(RELAXED)|A(UNCOND_CTI)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } } + }, +/* bl $simm8 */ + { + -1, "bl16r", "bl", 16, + { 0|A(RELAXABLE)|A(UNCOND_CTI)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } } + }, +/* bl $simm24 */ + { + -1, "blr", "bl", 32, + { 0|A(RELAXED)|A(UNCOND_CTI)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } } + }, +/* ldrb.l $rd6,[$rn6,$direction$rm6] */ + { + -1, "ldrbx", "ldrb.l", 32, + { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } } + }, +/* ldrb.l $rd6,[$rn6],$direction$rm6 */ + { + -1, "ldrbp", "ldrb.l", 32, + { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } } + }, +/* ldrb.l $rd6,[$rn6,$dpmi$disp11] */ + { + -1, "ldrbd", "ldrb.l", 32, + { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } } + }, +/* ldrb.l $rd6,[$rn6],$dpmi$disp11 */ + { + -1, "ldrbdpm", "ldrb.l", 32, + { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } } + }, +/* ldrb $rd,[$rn] */ + { + -1, "ldrbds0", "ldrb", 16, + { 0|A(IMM3)|A(SHORT_INSN)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } } + }, +/* ldrb $rd6,[$rn6] */ + { + -1, "ldrbdl0", "ldrb", 32, + { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } } + }, +/* ldrb.l $rd6,[$rn6] */ + { + -1, "ldrbdl0.l", "ldrb.l", 32, + { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } } + }, +/* ldrh.l $rd6,[$rn6,$direction$rm6] */ + { + -1, "ldrhx", "ldrh.l", 32, + { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } } + }, +/* ldrh.l $rd6,[$rn6],$direction$rm6 */ + { + -1, "ldrhp", "ldrh.l", 32, + { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } } + }, +/* ldrh.l $rd6,[$rn6,$dpmi$disp11] */ + { + -1, "ldrhd", "ldrh.l", 32, + { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } } + }, +/* ldrh.l $rd6,[$rn6],$dpmi$disp11 */ + { + -1, "ldrhdpm", "ldrh.l", 32, + { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } } + }, +/* ldrh $rd,[$rn] */ + { + -1, "ldrhds0", "ldrh", 16, + { 0|A(IMM3)|A(SHORT_INSN)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } } + }, +/* ldrh $rd6,[$rn6] */ + { + -1, "ldrhdl0", "ldrh", 32, + { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } } + }, +/* ldrh.l $rd6,[$rn6] */ + { + -1, "ldrhdl0.l", "ldrh.l", 32, + { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } } + }, +/* ldr.l $rd6,[$rn6,$direction$rm6] */ + { + -1, "ldrx", "ldr.l", 32, + { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } } + }, +/* ldr.l $rd6,[$rn6],$direction$rm6 */ + { + -1, "ldrp", "ldr.l", 32, + { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } } + }, +/* ldr.l $rd6,[$rn6,$dpmi$disp11] */ + { + -1, "ldrd", "ldr.l", 32, + { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } } + }, +/* ldr.l $rd6,[$rn6],$dpmi$disp11 */ + { + -1, "ldrdpm", "ldr.l", 32, + { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } } + }, +/* ldr $rd,[$rn] */ + { + -1, "ldrds0", "ldr", 16, + { 0|A(IMM3)|A(SHORT_INSN)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } } + }, +/* ldr $rd6,[$rn6] */ + { + -1, "ldrdl0", "ldr", 32, + { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } } + }, +/* ldr.l $rd6,[$rn6] */ + { + -1, "ldrdl0.l", "ldr.l", 32, + { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } } + }, +/* ldrd.l $rd6,[$rn6,$direction$rm6] */ + { + -1, "ldrdx", "ldrd.l", 32, + { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } } + }, +/* ldrd.l $rd6,[$rn6],$direction$rm6 */ + { + -1, "ldrdp", "ldrd.l", 32, + { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } } + }, +/* ldrd.l $rd6,[$rn6,$dpmi$disp11] */ + { + -1, "ldrdd", "ldrd.l", 32, + { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } } + }, +/* ldrd.l $rd6,[$rn6],$dpmi$disp11 */ + { + -1, "ldrddpm", "ldrd.l", 32, + { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } } + }, +/* ldrd $rd,[$rn] */ + { + -1, "ldrdds0", "ldrd", 16, + { 0|A(IMM3)|A(SHORT_INSN)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } } + }, +/* ldrd $rd6,[$rn6] */ + { + -1, "ldrddl0", "ldrd", 32, + { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } } + }, +/* ldrd.l $rd6,[$rn6] */ + { + -1, "ldrddl0.l", "ldrd.l", 32, + { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } } + }, +/* testsetb.l $rd6,[$rn6,$direction$rm6] */ + { + -1, "testsetbt.l", "testsetb.l", 32, + { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } } + }, +/* testseth.l $rd6,[$rn6,$direction$rm6] */ + { + -1, "testsetht.l", "testseth.l", 32, + { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } } + }, +/* testset.l $rd6,[$rn6,$direction$rm6] */ + { + -1, "testsett.l", "testset.l", 32, + { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } } + }, +/* strb.l $rd6,[$rn6,$direction$rm6] */ + { + -1, "strbx.l", "strb.l", 32, + { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } } + }, +/* strb.l $rd6,[$rn6],$direction$rm6 */ + { + -1, "strbp.l", "strb.l", 32, + { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } } + }, +/* strb.l $rd6,[$rn6,$dpmi$disp11] */ + { + -1, "strbd.l", "strb.l", 32, + { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } } + }, +/* strb.l $rd6,[$rn6],$dpmi$disp11 */ + { + -1, "strbdpm.l", "strb.l", 32, + { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } } + }, +/* strb $rd,[$rn] */ + { + -1, "strbds0", "strb", 16, + { 0|A(IMM3)|A(SHORT_INSN)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } } + }, +/* strb $rd6,[$rn6] */ + { + -1, "strbdl0", "strb", 32, + { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } } + }, +/* strb.l $rd6,[$rn6] */ + { + -1, "strbdl0.l", "strb.l", 32, + { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } } + }, +/* strh.l $rd6,[$rn6,$direction$rm6] */ + { + -1, "strhx.l", "strh.l", 32, + { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } } + }, +/* strh.l $rd6,[$rn6],$direction$rm6 */ + { + -1, "strhp.l", "strh.l", 32, + { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } } + }, +/* strh.l $rd6,[$rn6,$dpmi$disp11] */ + { + -1, "strhd.l", "strh.l", 32, + { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } } + }, +/* strh.l $rd6,[$rn6],$dpmi$disp11 */ + { + -1, "strhdpm.l", "strh.l", 32, + { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } } + }, +/* strh $rd,[$rn] */ + { + -1, "strhds0", "strh", 16, + { 0|A(IMM3)|A(SHORT_INSN)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } } + }, +/* strh $rd6,[$rn6] */ + { + -1, "strhdl0", "strh", 32, + { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } } + }, +/* strh.l $rd6,[$rn6] */ + { + -1, "strhdl0.l", "strh.l", 32, + { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } } + }, +/* str.l $rd6,[$rn6,$direction$rm6] */ + { + -1, "strx.l", "str.l", 32, + { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } } + }, +/* str.l $rd6,[$rn6],$direction$rm6 */ + { + -1, "strp.l", "str.l", 32, + { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } } + }, +/* str.l $rd6,[$rn6,$dpmi$disp11] */ + { + -1, "strd.l", "str.l", 32, + { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } } + }, +/* str.l $rd6,[$rn6],$dpmi$disp11 */ + { + -1, "strdpm.l", "str.l", 32, + { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } } + }, +/* str $rd,[$rn] */ + { + -1, "strds0", "str", 16, + { 0|A(IMM3)|A(SHORT_INSN)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } } + }, +/* str $rd6,[$rn6] */ + { + -1, "strdl0", "str", 32, + { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } } + }, +/* str.l $rd6,[$rn6] */ + { + -1, "strdl0.l", "str.l", 32, + { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } } + }, +/* strd.l $rd6,[$rn6,$direction$rm6] */ + { + -1, "strdx.l", "strd.l", 32, + { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } } + }, +/* strd.l $rd6,[$rn6],$direction$rm6 */ + { + -1, "strdp.l", "strd.l", 32, + { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } } + }, +/* strd.l $rd6,[$rn6,$dpmi$disp11] */ + { + -1, "strdd.l", "strd.l", 32, + { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } } + }, +/* strd.l $rd6,[$rn6],$dpmi$disp11 */ + { + -1, "strddpm.l", "strd.l", 32, + { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } } + }, +/* strd $rd,[$rn] */ + { + -1, "strdds0", "strd", 16, + { 0|A(IMM3)|A(SHORT_INSN)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } } + }, +/* strd $rd6,[$rn6] */ + { + -1, "strddl0", "strd", 32, + { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } } + }, +/* strd.l $rd6,[$rn6] */ + { + -1, "strddl0.l", "strd.l", 32, + { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } } + }, +/* moveq.l $rd6,$rn6 */ + { + -1, "cmov.lEQ", "moveq.l", 32, + { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } } + }, +/* movne.l $rd6,$rn6 */ + { + -1, "cmov.lNE", "movne.l", 32, + { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } } + }, +/* movgtu.l $rd6,$rn6 */ + { + -1, "cmov.lGTU", "movgtu.l", 32, + { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } } + }, +/* movgteu.l $rd6,$rn6 */ + { + -1, "cmov.lGTEU", "movgteu.l", 32, + { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } } + }, +/* movlteu.l $rd6,$rn6 */ + { + -1, "cmov.lLTEU", "movlteu.l", 32, + { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } } + }, +/* movltu.l $rd6,$rn6 */ + { + -1, "cmov.lLTU", "movltu.l", 32, + { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } } + }, +/* movgt.l $rd6,$rn6 */ + { + -1, "cmov.lGT", "movgt.l", 32, + { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } } + }, +/* movgte.l $rd6,$rn6 */ + { + -1, "cmov.lGTE", "movgte.l", 32, + { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } } + }, +/* movlt.l $rd6,$rn6 */ + { + -1, "cmov.lLT", "movlt.l", 32, + { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } } + }, +/* movlte.l $rd6,$rn6 */ + { + -1, "cmov.lLTE", "movlte.l", 32, + { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } } + }, +/* mov.l $rd6,$rn6 */ + { + -1, "cmov.lB", "mov.l", 32, + { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } } + }, +/* movbeq.l $rd6,$rn6 */ + { + -1, "cmov.lBEQ", "movbeq.l", 32, + { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } } + }, +/* movbne.l $rd6,$rn6 */ + { + -1, "cmov.lBNE", "movbne.l", 32, + { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } } + }, +/* movblt.l $rd6,$rn6 */ + { + -1, "cmov.lBLT", "movblt.l", 32, + { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } } + }, +/* movblte.l $rd6,$rn6 */ + { + -1, "cmov.lBLTE", "movblte.l", 32, + { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } } + }, +/* movts.l $sn6,$rd6 */ + { + -1, "movts.l6", "movts.l", 32, + { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } } + }, +/* movts.l $sndma,$rd6 */ + { + -1, "movts.ldma", "movts.l", 32, + { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } } + }, +/* movts.l $snmem,$rd6 */ + { + -1, "movts.lmem", "movts.l", 32, + { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } } + }, +/* movts.l $snmesh,$rd6 */ + { + -1, "movts.lmesh", "movts.l", 32, + { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } } + }, +/* movfs.l $rd6,$sn6 */ + { + -1, "movfs.l6", "movfs.l", 32, + { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } } + }, +/* movfs.l $rd6,$sndma */ + { + -1, "movfs.ldma", "movfs.l", 32, + { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } } + }, +/* movfs.l $rd6,$snmem */ + { + -1, "movfs.lmem", "movfs.l", 32, + { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } } + }, +/* movfs.l $rd6,$snmesh */ + { + -1, "movfs.lmesh", "movfs.l", 32, + { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } } + }, +/* add.l $rd6,$rn6,$rm6 */ + { + -1, "add.l", "add.l", 32, + { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } } + }, +/* sub.l $rd6,$rn6,$rm6 */ + { + -1, "sub.l", "sub.l", 32, + { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } } + }, +/* and.l $rd6,$rn6,$rm6 */ + { + -1, "and.l", "and.l", 32, + { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } } + }, +/* orr.l $rd6,$rn6,$rm6 */ + { + -1, "orr.l", "orr.l", 32, + { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } } + }, +/* eor.l $rd6,$rn6,$rm6 */ + { + -1, "eor.l", "eor.l", 32, + { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } } + }, +/* add $rd,$rn,$simm3 */ + { + -1, "addir", "add", 16, + { 0|A(IMM3)|A(RELAXABLE)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } } + }, +/* add $rd6,$rn6,$simm11 */ + { + -1, "addi32r", "add", 32, + { 0|A(RELAXED)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } } + }, +/* add $rd6,$rn6,$simm11 */ + { + -1, "addi32m", "add", 32, + { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } } + }, +/* sub $rd,$rn,$simm3 */ + { + -1, "subir", "sub", 16, + { 0|A(IMM3)|A(RELAXABLE)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } } + }, +/* sub $rd6,$rn6,$simm11 */ + { + -1, "subi32r", "sub", 32, + { 0|A(RELAXED)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } } + }, +/* sub $rd6,$rn6,$simm11 */ + { + -1, "subi32m", "sub", 32, + { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } } + }, +/* asr.l $rd6,$rn6,$rm6 */ + { + -1, "asr.l", "asr.l", 32, + { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } } + }, +/* lsr.l $rd6,$rn6,$rm6 */ + { + -1, "lsr.l", "lsr.l", 32, + { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } } + }, +/* lsl.l $rd6,$rn6,$rm6 */ + { + -1, "lsl.l", "lsl.l", 32, + { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } } + }, +/* lsr.l $rd6,$rn6,$shift */ + { + -1, "lsri32.l", "lsr.l", 32, + { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } } + }, +/* lsl.l $rd6,$rn6,$shift */ + { + -1, "lsli32.l", "lsl.l", 32, + { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } } + }, +/* asr.l $rd6,$rn6,$shift */ + { + -1, "asri32.l", "asr.l", 32, + { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } } + }, +/* bitr.l $rd6,$rn6 */ + { + -1, "bitrl", "bitr.l", 32, + { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } } + }, +/* fext.l $rd6,$rn6,$rm6 */ + { + -1, "fext.l", "fext.l", 32, + { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } } + }, +/* fdep.l $rd6,$rn6,$rm6 */ + { + -1, "fdep.l", "fdep.l", 32, + { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } } + }, +/* lfsr.l $rd6,$rn6,$rm6 */ + { + -1, "lfsr.l", "lfsr.l", 32, + { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } } + }, +/* mov $rd,$imm8 */ + { + -1, "mov8r", "mov", 16, + { 0|A(RELAXABLE)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } } + }, +/* mov $rd6,$imm16 */ + { + -1, "mov16r", "mov", 32, + { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } } + }, +/* movt.l $rd6,$imm16 */ + { + -1, "movtl", "movt.l", 32, + { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } } + }, +/* iadd $rd,$rn,$rm */ + { + -1, "i_addf16", "iadd", 16, + { 0|A(NO_DIS)|A(SHORT_INSN)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } } + }, +/* fadd.l $rd6,$rn6,$rm6 */ + { + -1, "f_addf32.l", "fadd.l", 32, + { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } } + }, +/* iadd $rd6,$rn6,$rm6 */ + { + -1, "i_addf32", "iadd", 32, + { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } } + }, +/* iadd.l $rd6,$rn6,$rm6 */ + { + -1, "i_addf32.l", "iadd.l", 32, + { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } } + }, +/* isub $rd,$rn,$rm */ + { + -1, "i_subf16", "isub", 16, + { 0|A(NO_DIS)|A(SHORT_INSN)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } } + }, +/* fsub.l $rd6,$rn6,$rm6 */ + { + -1, "f_subf32.l", "fsub.l", 32, + { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } } + }, +/* isub $rd6,$rn6,$rm6 */ + { + -1, "i_subf32", "isub", 32, + { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } } + }, +/* isub.l $rd6,$rn6,$rm6 */ + { + -1, "i_subf32.l", "isub.l", 32, + { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } } + }, +/* imul $rd,$rn,$rm */ + { + -1, "i_mulf16", "imul", 16, + { 0|A(NO_DIS)|A(SHORT_INSN)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } } + }, +/* fmul.l $rd6,$rn6,$rm6 */ + { + -1, "f_mulf32.l", "fmul.l", 32, + { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } } + }, +/* imul $rd6,$rn6,$rm6 */ + { + -1, "i_mulf32", "imul", 32, + { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } } + }, +/* imul.l $rd6,$rn6,$rm6 */ + { + -1, "i_mulf32.l", "imul.l", 32, + { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } } + }, +/* imadd $rd,$rn,$rm */ + { + -1, "i_maddf16", "imadd", 16, + { 0|A(NO_DIS)|A(SHORT_INSN)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } } + }, +/* fmadd.l $rd6,$rn6,$rm6 */ + { + -1, "f_maddf32.l", "fmadd.l", 32, + { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } } + }, +/* imadd $rd6,$rn6,$rm6 */ + { + -1, "i_maddf32", "imadd", 32, + { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } } + }, +/* imadd.l $rd6,$rn6,$rm6 */ + { + -1, "i_maddf32.l", "imadd.l", 32, + { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } } + }, +/* imsub $rd,$rn,$rm */ + { + -1, "i_msubf16", "imsub", 16, + { 0|A(NO_DIS)|A(SHORT_INSN)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } } + }, +/* fmsub.l $rd6,$rn6,$rm6 */ + { + -1, "f_msubf32.l", "fmsub.l", 32, + { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } } + }, +/* imsub $rd6,$rn6,$rm6 */ + { + -1, "i_msubf32", "imsub", 32, + { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } } + }, +/* imsub.l $rd6,$rn6,$rm6 */ + { + -1, "i_msubf32.l", "imsub.l", 32, + { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } } + }, +/* fabs.l $rd6,$rn6 */ + { + -1, "f_absf32.l", "fabs.l", 32, + { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } } + }, +/* float.l $rd6,$rn6 */ + { + -1, "f_loatf32.l", "float.l", 32, + { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } } + }, +/* fix.l $rd6,$rn6 */ + { + -1, "f_ixf32.l", "fix.l", 32, + { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } } + }, +/* frecip.l $frd6,$frn6 */ + { + -1, "f_recipf32.l", "frecip.l", 32, + { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } } + }, +/* fsqrt.l $frd6,$frn6 */ + { + -1, "f_sqrtf32.l", "fsqrt.l", 32, + { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } } + }, +}; + +/* The macro instruction opcode table. */ + +static const CGEN_OPCODE epiphany_cgen_macro_insn_opcode_table[] = +{ +/* beq $simm8 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (SIMM8), 0 } }, + & ifmt_beq16r, { 0x0 } + }, +/* beq $simm24 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (SIMM24), 0 } }, + & ifmt_beq32r, { 0x8 } + }, +/* bne $simm8 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (SIMM8), 0 } }, + & ifmt_bne16r, { 0x10 } + }, +/* bne $simm24 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (SIMM24), 0 } }, + & ifmt_bne32r, { 0x18 } + }, +/* bgtu $simm8 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (SIMM8), 0 } }, + & ifmt_bgtu16r, { 0x20 } + }, +/* bgtu $simm24 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (SIMM24), 0 } }, + & ifmt_bgtu32r, { 0x28 } + }, +/* bgteu $simm8 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (SIMM8), 0 } }, + & ifmt_bgteu16r, { 0x30 } + }, +/* bgteu $simm24 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (SIMM24), 0 } }, + & ifmt_bgteu32r, { 0x38 } + }, +/* blteu $simm8 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (SIMM8), 0 } }, + & ifmt_blteu16r, { 0x40 } + }, +/* blteu $simm24 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (SIMM24), 0 } }, + & ifmt_blteu32r, { 0x48 } + }, +/* bltu $simm8 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (SIMM8), 0 } }, + & ifmt_bltu16r, { 0x50 } + }, +/* bltu $simm24 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (SIMM24), 0 } }, + & ifmt_bltu32r, { 0x58 } + }, +/* bgt $simm8 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (SIMM8), 0 } }, + & ifmt_bgt16r, { 0x60 } + }, +/* bgt $simm24 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (SIMM24), 0 } }, + & ifmt_bgt32r, { 0x68 } + }, +/* bgte $simm8 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (SIMM8), 0 } }, + & ifmt_bgte16r, { 0x70 } + }, +/* bgte $simm24 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (SIMM24), 0 } }, + & ifmt_bgte32r, { 0x78 } + }, +/* blt $simm8 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (SIMM8), 0 } }, + & ifmt_blt16r, { 0x80 } + }, +/* blt $simm24 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (SIMM24), 0 } }, + & ifmt_blt32r, { 0x88 } + }, +/* blte $simm8 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (SIMM8), 0 } }, + & ifmt_blte16r, { 0x90 } + }, +/* blte $simm24 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (SIMM24), 0 } }, + & ifmt_blte32r, { 0x98 } + }, +/* bbeq $simm8 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (SIMM8), 0 } }, + & ifmt_bbeq16r, { 0xa0 } + }, +/* bbeq $simm24 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (SIMM24), 0 } }, + & ifmt_bbeq32r, { 0xa8 } + }, +/* bbne $simm8 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (SIMM8), 0 } }, + & ifmt_bbne16r, { 0xb0 } + }, +/* bbne $simm24 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (SIMM24), 0 } }, + & ifmt_bbne32r, { 0xb8 } + }, +/* bblt $simm8 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (SIMM8), 0 } }, + & ifmt_bblt16r, { 0xc0 } + }, +/* bblt $simm24 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (SIMM24), 0 } }, + & ifmt_bblt32r, { 0xc8 } + }, +/* bblte $simm8 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (SIMM8), 0 } }, + & ifmt_bblte16r, { 0xd0 } + }, +/* bblte $simm24 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (SIMM24), 0 } }, + & ifmt_bblte32r, { 0xd8 } + }, +/* b $simm8 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (SIMM8), 0 } }, + & ifmt_b16r, { 0xe0 } + }, +/* b $simm24 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (SIMM24), 0 } }, + & ifmt_b32r, { 0xe8 } + }, +/* bl $simm8 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (SIMM8), 0 } }, + & ifmt_bl16r, { 0xf0 } + }, +/* bl $simm24 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (SIMM24), 0 } }, + & ifmt_blr, { 0xf8 } + }, +/* ldrb.l $rd6,[$rn6,$direction$rm6] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD6), ',', '[', OP (RN6), ',', OP (DIRECTION), OP (RM6), ']', 0 } }, + & ifmt_ldrbx, { 0x9 } + }, +/* ldrb.l $rd6,[$rn6],$direction$rm6 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD6), ',', '[', OP (RN6), ']', ',', OP (DIRECTION), OP (RM6), 0 } }, + & ifmt_ldrbp, { 0xd } + }, +/* ldrb.l $rd6,[$rn6,$dpmi$disp11] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD6), ',', '[', OP (RN6), ',', OP (DPMI), OP (DISP11), ']', 0 } }, + & ifmt_ldrbd, { 0xc } + }, +/* ldrb.l $rd6,[$rn6],$dpmi$disp11 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD6), ',', '[', OP (RN6), ']', ',', OP (DPMI), OP (DISP11), 0 } }, + & ifmt_ldrbdpm, { 0x200000c } + }, +/* ldrb $rd,[$rn] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', '[', OP (RN), ']', 0 } }, + & ifmt_ldrbds0, { 0x4 } + }, +/* ldrb $rd6,[$rn6] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD6), ',', '[', OP (RN6), ']', 0 } }, + & ifmt_ldrbdl0, { 0xc } + }, +/* ldrb.l $rd6,[$rn6] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD6), ',', '[', OP (RN6), ']', 0 } }, + & ifmt_ldrbdl0_l, { 0xc } + }, +/* ldrh.l $rd6,[$rn6,$direction$rm6] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD6), ',', '[', OP (RN6), ',', OP (DIRECTION), OP (RM6), ']', 0 } }, + & ifmt_ldrhx, { 0x29 } + }, +/* ldrh.l $rd6,[$rn6],$direction$rm6 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD6), ',', '[', OP (RN6), ']', ',', OP (DIRECTION), OP (RM6), 0 } }, + & ifmt_ldrhp, { 0x2d } + }, +/* ldrh.l $rd6,[$rn6,$dpmi$disp11] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD6), ',', '[', OP (RN6), ',', OP (DPMI), OP (DISP11), ']', 0 } }, + & ifmt_ldrhd, { 0x2c } + }, +/* ldrh.l $rd6,[$rn6],$dpmi$disp11 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD6), ',', '[', OP (RN6), ']', ',', OP (DPMI), OP (DISP11), 0 } }, + & ifmt_ldrhdpm, { 0x200002c } + }, +/* ldrh $rd,[$rn] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', '[', OP (RN), ']', 0 } }, + & ifmt_ldrhds0, { 0x24 } + }, +/* ldrh $rd6,[$rn6] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD6), ',', '[', OP (RN6), ']', 0 } }, + & ifmt_ldrhdl0, { 0x2c } + }, +/* ldrh.l $rd6,[$rn6] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD6), ',', '[', OP (RN6), ']', 0 } }, + & ifmt_ldrhdl0_l, { 0x2c } + }, +/* ldr.l $rd6,[$rn6,$direction$rm6] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD6), ',', '[', OP (RN6), ',', OP (DIRECTION), OP (RM6), ']', 0 } }, + & ifmt_ldrx, { 0x49 } + }, +/* ldr.l $rd6,[$rn6],$direction$rm6 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD6), ',', '[', OP (RN6), ']', ',', OP (DIRECTION), OP (RM6), 0 } }, + & ifmt_ldrp, { 0x4d } + }, +/* ldr.l $rd6,[$rn6,$dpmi$disp11] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD6), ',', '[', OP (RN6), ',', OP (DPMI), OP (DISP11), ']', 0 } }, + & ifmt_ldrd, { 0x4c } + }, +/* ldr.l $rd6,[$rn6],$dpmi$disp11 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD6), ',', '[', OP (RN6), ']', ',', OP (DPMI), OP (DISP11), 0 } }, + & ifmt_ldrdpm, { 0x200004c } + }, +/* ldr $rd,[$rn] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', '[', OP (RN), ']', 0 } }, + & ifmt_ldrds0, { 0x44 } + }, +/* ldr $rd6,[$rn6] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD6), ',', '[', OP (RN6), ']', 0 } }, + & ifmt_ldrdl0, { 0x4c } + }, +/* ldr.l $rd6,[$rn6] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD6), ',', '[', OP (RN6), ']', 0 } }, + & ifmt_ldrdl0_l, { 0x4c } + }, +/* ldrd.l $rd6,[$rn6,$direction$rm6] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD6), ',', '[', OP (RN6), ',', OP (DIRECTION), OP (RM6), ']', 0 } }, + & ifmt_ldrdx, { 0x69 } + }, +/* ldrd.l $rd6,[$rn6],$direction$rm6 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD6), ',', '[', OP (RN6), ']', ',', OP (DIRECTION), OP (RM6), 0 } }, + & ifmt_ldrdp, { 0x6d } + }, +/* ldrd.l $rd6,[$rn6,$dpmi$disp11] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD6), ',', '[', OP (RN6), ',', OP (DPMI), OP (DISP11), ']', 0 } }, + & ifmt_ldrdd, { 0x6c } + }, +/* ldrd.l $rd6,[$rn6],$dpmi$disp11 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD6), ',', '[', OP (RN6), ']', ',', OP (DPMI), OP (DISP11), 0 } }, + & ifmt_ldrddpm, { 0x200006c } + }, +/* ldrd $rd,[$rn] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', '[', OP (RN), ']', 0 } }, + & ifmt_ldrdds0, { 0x64 } + }, +/* ldrd $rd6,[$rn6] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD6), ',', '[', OP (RN6), ']', 0 } }, + & ifmt_ldrddl0, { 0x6c } + }, +/* ldrd.l $rd6,[$rn6] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD6), ',', '[', OP (RN6), ']', 0 } }, + & ifmt_ldrddl0_l, { 0x6c } + }, +/* testsetb.l $rd6,[$rn6,$direction$rm6] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD6), ',', '[', OP (RN6), ',', OP (DIRECTION), OP (RM6), ']', 0 } }, + & ifmt_testsetbt_l, { 0x200009 } + }, +/* testseth.l $rd6,[$rn6,$direction$rm6] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD6), ',', '[', OP (RN6), ',', OP (DIRECTION), OP (RM6), ']', 0 } }, + & ifmt_testsetht_l, { 0x200029 } + }, +/* testset.l $rd6,[$rn6,$direction$rm6] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD6), ',', '[', OP (RN6), ',', OP (DIRECTION), OP (RM6), ']', 0 } }, + & ifmt_testsett_l, { 0x200049 } + }, +/* strb.l $rd6,[$rn6,$direction$rm6] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD6), ',', '[', OP (RN6), ',', OP (DIRECTION), OP (RM6), ']', 0 } }, + & ifmt_strbx_l, { 0x19 } + }, +/* strb.l $rd6,[$rn6],$direction$rm6 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD6), ',', '[', OP (RN6), ']', ',', OP (DIRECTION), OP (RM6), 0 } }, + & ifmt_strbp_l, { 0x1d } + }, +/* strb.l $rd6,[$rn6,$dpmi$disp11] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD6), ',', '[', OP (RN6), ',', OP (DPMI), OP (DISP11), ']', 0 } }, + & ifmt_strbd_l, { 0x1c } + }, +/* strb.l $rd6,[$rn6],$dpmi$disp11 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD6), ',', '[', OP (RN6), ']', ',', OP (DPMI), OP (DISP11), 0 } }, + & ifmt_strbdpm_l, { 0x200001c } + }, +/* strb $rd,[$rn] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', '[', OP (RN), ']', 0 } }, + & ifmt_strbds0, { 0x14 } + }, +/* strb $rd6,[$rn6] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD6), ',', '[', OP (RN6), ']', 0 } }, + & ifmt_strbdl0, { 0x1c } + }, +/* strb.l $rd6,[$rn6] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD6), ',', '[', OP (RN6), ']', 0 } }, + & ifmt_strbdl0_l, { 0x1c } + }, +/* strh.l $rd6,[$rn6,$direction$rm6] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD6), ',', '[', OP (RN6), ',', OP (DIRECTION), OP (RM6), ']', 0 } }, + & ifmt_strhx_l, { 0x39 } + }, +/* strh.l $rd6,[$rn6],$direction$rm6 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD6), ',', '[', OP (RN6), ']', ',', OP (DIRECTION), OP (RM6), 0 } }, + & ifmt_strhp_l, { 0x3d } + }, +/* strh.l $rd6,[$rn6,$dpmi$disp11] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD6), ',', '[', OP (RN6), ',', OP (DPMI), OP (DISP11), ']', 0 } }, + & ifmt_strhd_l, { 0x3c } + }, +/* strh.l $rd6,[$rn6],$dpmi$disp11 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD6), ',', '[', OP (RN6), ']', ',', OP (DPMI), OP (DISP11), 0 } }, + & ifmt_strhdpm_l, { 0x200003c } + }, +/* strh $rd,[$rn] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', '[', OP (RN), ']', 0 } }, + & ifmt_strhds0, { 0x34 } + }, +/* strh $rd6,[$rn6] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD6), ',', '[', OP (RN6), ']', 0 } }, + & ifmt_strhdl0, { 0x3c } + }, +/* strh.l $rd6,[$rn6] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD6), ',', '[', OP (RN6), ']', 0 } }, + & ifmt_strhdl0_l, { 0x3c } + }, +/* str.l $rd6,[$rn6,$direction$rm6] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD6), ',', '[', OP (RN6), ',', OP (DIRECTION), OP (RM6), ']', 0 } }, + & ifmt_strx_l, { 0x59 } + }, +/* str.l $rd6,[$rn6],$direction$rm6 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD6), ',', '[', OP (RN6), ']', ',', OP (DIRECTION), OP (RM6), 0 } }, + & ifmt_strp_l, { 0x5d } + }, +/* str.l $rd6,[$rn6,$dpmi$disp11] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD6), ',', '[', OP (RN6), ',', OP (DPMI), OP (DISP11), ']', 0 } }, + & ifmt_strd_l, { 0x5c } + }, +/* str.l $rd6,[$rn6],$dpmi$disp11 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD6), ',', '[', OP (RN6), ']', ',', OP (DPMI), OP (DISP11), 0 } }, + & ifmt_strdpm_l, { 0x200005c } + }, +/* str $rd,[$rn] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', '[', OP (RN), ']', 0 } }, + & ifmt_strds0, { 0x54 } + }, +/* str $rd6,[$rn6] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD6), ',', '[', OP (RN6), ']', 0 } }, + & ifmt_strdl0, { 0x5c } + }, +/* str.l $rd6,[$rn6] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD6), ',', '[', OP (RN6), ']', 0 } }, + & ifmt_strdl0_l, { 0x5c } + }, +/* strd.l $rd6,[$rn6,$direction$rm6] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD6), ',', '[', OP (RN6), ',', OP (DIRECTION), OP (RM6), ']', 0 } }, + & ifmt_strdx_l, { 0x79 } + }, +/* strd.l $rd6,[$rn6],$direction$rm6 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD6), ',', '[', OP (RN6), ']', ',', OP (DIRECTION), OP (RM6), 0 } }, + & ifmt_strdp_l, { 0x7d } + }, +/* strd.l $rd6,[$rn6,$dpmi$disp11] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD6), ',', '[', OP (RN6), ',', OP (DPMI), OP (DISP11), ']', 0 } }, + & ifmt_strdd_l, { 0x7c } + }, +/* strd.l $rd6,[$rn6],$dpmi$disp11 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD6), ',', '[', OP (RN6), ']', ',', OP (DPMI), OP (DISP11), 0 } }, + & ifmt_strddpm_l, { 0x200007c } + }, +/* strd $rd,[$rn] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', '[', OP (RN), ']', 0 } }, + & ifmt_strdds0, { 0x74 } + }, +/* strd $rd6,[$rn6] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD6), ',', '[', OP (RN6), ']', 0 } }, + & ifmt_strddl0, { 0x7c } + }, +/* strd.l $rd6,[$rn6] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD6), ',', '[', OP (RN6), ']', 0 } }, + & ifmt_strddl0_l, { 0x7c } + }, +/* moveq.l $rd6,$rn6 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD6), ',', OP (RN6), 0 } }, + & ifmt_cmov_lEQ, { 0x2000f } + }, +/* movne.l $rd6,$rn6 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD6), ',', OP (RN6), 0 } }, + & ifmt_cmov_lNE, { 0x2001f } + }, +/* movgtu.l $rd6,$rn6 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD6), ',', OP (RN6), 0 } }, + & ifmt_cmov_lGTU, { 0x2002f } + }, +/* movgteu.l $rd6,$rn6 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD6), ',', OP (RN6), 0 } }, + & ifmt_cmov_lGTEU, { 0x2003f } + }, +/* movlteu.l $rd6,$rn6 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD6), ',', OP (RN6), 0 } }, + & ifmt_cmov_lLTEU, { 0x2004f } + }, +/* movltu.l $rd6,$rn6 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD6), ',', OP (RN6), 0 } }, + & ifmt_cmov_lLTU, { 0x2005f } + }, +/* movgt.l $rd6,$rn6 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD6), ',', OP (RN6), 0 } }, + & ifmt_cmov_lGT, { 0x2006f } + }, +/* movgte.l $rd6,$rn6 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD6), ',', OP (RN6), 0 } }, + & ifmt_cmov_lGTE, { 0x2007f } + }, +/* movlt.l $rd6,$rn6 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD6), ',', OP (RN6), 0 } }, + & ifmt_cmov_lLT, { 0x2008f } + }, +/* movlte.l $rd6,$rn6 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD6), ',', OP (RN6), 0 } }, + & ifmt_cmov_lLTE, { 0x2009f } + }, +/* mov.l $rd6,$rn6 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD6), ',', OP (RN6), 0 } }, + & ifmt_cmov_lB, { 0x200ef } + }, +/* movbeq.l $rd6,$rn6 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD6), ',', OP (RN6), 0 } }, + & ifmt_cmov_lBEQ, { 0x200af } + }, +/* movbne.l $rd6,$rn6 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD6), ',', OP (RN6), 0 } }, + & ifmt_cmov_lBNE, { 0x200bf } + }, +/* movblt.l $rd6,$rn6 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD6), ',', OP (RN6), 0 } }, + & ifmt_cmov_lBLT, { 0x200cf } + }, +/* movblte.l $rd6,$rn6 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD6), ',', OP (RN6), 0 } }, + & ifmt_cmov_lBLTE, { 0x200df } + }, +/* movts.l $sn6,$rd6 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (SN6), ',', OP (RD6), 0 } }, + & ifmt_movts_l6, { 0x2010f } + }, +/* movts.l $sndma,$rd6 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (SNDMA), ',', OP (RD6), 0 } }, + & ifmt_movts_ldma, { 0x12010f } + }, +/* movts.l $snmem,$rd6 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (SNMEM), ',', OP (RD6), 0 } }, + & ifmt_movts_lmem, { 0x22010f } + }, +/* movts.l $snmesh,$rd6 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (SNMESH), ',', OP (RD6), 0 } }, + & ifmt_movts_lmesh, { 0x32010f } + }, +/* movfs.l $rd6,$sn6 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD6), ',', OP (SN6), 0 } }, + & ifmt_movfs_l6, { 0x2011f } + }, +/* movfs.l $rd6,$sndma */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD6), ',', OP (SNDMA), 0 } }, + & ifmt_movfs_ldma, { 0x12011f } + }, +/* movfs.l $rd6,$snmem */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD6), ',', OP (SNMEM), 0 } }, + & ifmt_movfs_lmem, { 0x22011f } + }, +/* movfs.l $rd6,$snmesh */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD6), ',', OP (SNMESH), 0 } }, + & ifmt_movfs_lmesh, { 0x32011f } + }, +/* add.l $rd6,$rn6,$rm6 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD6), ',', OP (RN6), ',', OP (RM6), 0 } }, + & ifmt_add_l, { 0xa001f } + }, +/* sub.l $rd6,$rn6,$rm6 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD6), ',', OP (RN6), ',', OP (RM6), 0 } }, + & ifmt_sub_l, { 0xa003f } + }, +/* and.l $rd6,$rn6,$rm6 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD6), ',', OP (RN6), ',', OP (RM6), 0 } }, + & ifmt_and_l, { 0xa005f } + }, +/* orr.l $rd6,$rn6,$rm6 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD6), ',', OP (RN6), ',', OP (RM6), 0 } }, + & ifmt_orr_l, { 0xa007f } + }, +/* eor.l $rd6,$rn6,$rm6 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD6), ',', OP (RN6), ',', OP (RM6), 0 } }, + & ifmt_eor_l, { 0xa000f } + }, +/* add $rd,$rn,$simm3 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RN), ',', OP (SIMM3), 0 } }, + & ifmt_addir, { 0x13 } + }, +/* add $rd6,$rn6,$simm11 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD6), ',', OP (RN6), ',', OP (SIMM11), 0 } }, + & ifmt_addi32r, { 0x1b } + }, +/* add $rd6,$rn6,$simm11 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD6), ',', OP (RN6), ',', OP (SIMM11), 0 } }, + & ifmt_addi32m, { 0x1b } + }, +/* sub $rd,$rn,$simm3 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RN), ',', OP (SIMM3), 0 } }, + & ifmt_subir, { 0x33 } + }, +/* sub $rd6,$rn6,$simm11 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD6), ',', OP (RN6), ',', OP (SIMM11), 0 } }, + & ifmt_subi32r, { 0x3b } + }, +/* sub $rd6,$rn6,$simm11 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD6), ',', OP (RN6), ',', OP (SIMM11), 0 } }, + & ifmt_subi32m, { 0x3b } + }, +/* asr.l $rd6,$rn6,$rm6 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD6), ',', OP (RN6), ',', OP (RM6), 0 } }, + & ifmt_asr_l, { 0xa006f } + }, +/* lsr.l $rd6,$rn6,$rm6 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD6), ',', OP (RN6), ',', OP (RM6), 0 } }, + & ifmt_lsr_l, { 0xa004f } + }, +/* lsl.l $rd6,$rn6,$rm6 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD6), ',', OP (RN6), ',', OP (RM6), 0 } }, + & ifmt_lsl_l, { 0xa002f } + }, +/* lsr.l $rd6,$rn6,$shift */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD6), ',', OP (RN6), ',', OP (SHIFT), 0 } }, + & ifmt_lsri32_l, { 0x6000f } + }, +/* lsl.l $rd6,$rn6,$shift */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD6), ',', OP (RN6), ',', OP (SHIFT), 0 } }, + & ifmt_lsli32_l, { 0x6001f } + }, +/* asr.l $rd6,$rn6,$shift */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD6), ',', OP (RN6), ',', OP (SHIFT), 0 } }, + & ifmt_asri32_l, { 0xe000f } + }, +/* bitr.l $rd6,$rn6 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD6), ',', OP (RN6), 0 } }, + & ifmt_bitrl, { 0xe001f } + }, +/* fext.l $rd6,$rn6,$rm6 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD6), ',', OP (RN6), ',', OP (RM6), 0 } }, + & ifmt_fext_l, { 0x1a000f } + }, +/* fdep.l $rd6,$rn6,$rm6 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD6), ',', OP (RN6), ',', OP (RM6), 0 } }, + & ifmt_fdep_l, { 0x1a001f } + }, +/* lfsr.l $rd6,$rn6,$rm6 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD6), ',', OP (RN6), ',', OP (RM6), 0 } }, + & ifmt_lfsr_l, { 0x1a002f } + }, +/* mov $rd,$imm8 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (IMM8), 0 } }, + & ifmt_mov8r, { 0x3 } + }, +/* mov $rd6,$imm16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD6), ',', OP (IMM16), 0 } }, + & ifmt_mov16r, { 0x2000b } + }, +/* movt.l $rd6,$imm16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD6), ',', OP (IMM16), 0 } }, + & ifmt_movtl, { 0x1002000b } + }, +/* iadd $rd,$rn,$rm */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RN), ',', OP (RM), 0 } }, + & ifmt_i_addf16, { 0x7 } + }, +/* fadd.l $rd6,$rn6,$rm6 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD6), ',', OP (RN6), ',', OP (RM6), 0 } }, + & ifmt_f_addf32_l, { 0x7000f } + }, +/* iadd $rd6,$rn6,$rm6 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD6), ',', OP (RN6), ',', OP (RM6), 0 } }, + & ifmt_i_addf32, { 0x7000f } + }, +/* iadd.l $rd6,$rn6,$rm6 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD6), ',', OP (RN6), ',', OP (RM6), 0 } }, + & ifmt_i_addf32_l, { 0x7000f } + }, +/* isub $rd,$rn,$rm */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RN), ',', OP (RM), 0 } }, + & ifmt_i_subf16, { 0x17 } + }, +/* fsub.l $rd6,$rn6,$rm6 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD6), ',', OP (RN6), ',', OP (RM6), 0 } }, + & ifmt_f_subf32_l, { 0x7001f } + }, +/* isub $rd6,$rn6,$rm6 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD6), ',', OP (RN6), ',', OP (RM6), 0 } }, + & ifmt_i_subf32, { 0x7001f } + }, +/* isub.l $rd6,$rn6,$rm6 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD6), ',', OP (RN6), ',', OP (RM6), 0 } }, + & ifmt_i_subf32_l, { 0x7001f } + }, +/* imul $rd,$rn,$rm */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RN), ',', OP (RM), 0 } }, + & ifmt_i_mulf16, { 0x27 } + }, +/* fmul.l $rd6,$rn6,$rm6 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD6), ',', OP (RN6), ',', OP (RM6), 0 } }, + & ifmt_f_mulf32_l, { 0x7002f } + }, +/* imul $rd6,$rn6,$rm6 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD6), ',', OP (RN6), ',', OP (RM6), 0 } }, + & ifmt_i_mulf32, { 0x7002f } + }, +/* imul.l $rd6,$rn6,$rm6 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD6), ',', OP (RN6), ',', OP (RM6), 0 } }, + & ifmt_i_mulf32_l, { 0x7002f } + }, +/* imadd $rd,$rn,$rm */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RN), ',', OP (RM), 0 } }, + & ifmt_i_maddf16, { 0x37 } + }, +/* fmadd.l $rd6,$rn6,$rm6 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD6), ',', OP (RN6), ',', OP (RM6), 0 } }, + & ifmt_f_maddf32_l, { 0x7003f } + }, +/* imadd $rd6,$rn6,$rm6 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD6), ',', OP (RN6), ',', OP (RM6), 0 } }, + & ifmt_i_maddf32, { 0x7003f } + }, +/* imadd.l $rd6,$rn6,$rm6 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD6), ',', OP (RN6), ',', OP (RM6), 0 } }, + & ifmt_i_maddf32_l, { 0x7003f } + }, +/* imsub $rd,$rn,$rm */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RN), ',', OP (RM), 0 } }, + & ifmt_i_msubf16, { 0x47 } + }, +/* fmsub.l $rd6,$rn6,$rm6 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD6), ',', OP (RN6), ',', OP (RM6), 0 } }, + & ifmt_f_msubf32_l, { 0x7004f } + }, +/* imsub $rd6,$rn6,$rm6 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD6), ',', OP (RN6), ',', OP (RM6), 0 } }, + & ifmt_i_msubf32, { 0x7004f } + }, +/* imsub.l $rd6,$rn6,$rm6 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD6), ',', OP (RN6), ',', OP (RM6), 0 } }, + & ifmt_i_msubf32_l, { 0x7004f } + }, +/* fabs.l $rd6,$rn6 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD6), ',', OP (RN6), 0 } }, + & ifmt_f_absf32_l, { 0x7007f } + }, +/* float.l $rd6,$rn6 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD6), ',', OP (RN6), 0 } }, + & ifmt_f_loatf32_l, { 0x7005f } + }, +/* fix.l $rd6,$rn6 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD6), ',', OP (RN6), 0 } }, + & ifmt_f_ixf32_l, { 0x7006f } + }, +/* frecip.l $frd6,$frn6 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (FRD6), ',', OP (FRN6), 0 } }, + & ifmt_f_recipf32_l, { 0x17000f } + }, +/* fsqrt.l $frd6,$frn6 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (FRD6), ',', OP (FRN6), 0 } }, + & ifmt_f_sqrtf32_l, { 0x17001f } + }, +}; + +#undef A +#undef OPERAND +#undef MNEM +#undef OP + +#ifndef CGEN_ASM_HASH_P +#define CGEN_ASM_HASH_P(insn) 1 +#endif + +#ifndef CGEN_DIS_HASH_P +#define CGEN_DIS_HASH_P(insn) 1 +#endif + +/* Return non-zero if INSN is to be added to the hash table. + Targets are free to override CGEN_{ASM,DIS}_HASH_P in the .opc file. */ + +static int +asm_hash_insn_p (insn) + const CGEN_INSN *insn ATTRIBUTE_UNUSED; +{ + return CGEN_ASM_HASH_P (insn); +} + +static int +dis_hash_insn_p (insn) + const CGEN_INSN *insn; +{ + /* If building the hash table and the NO-DIS attribute is present, + ignore. */ + if (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_NO_DIS)) + return 0; + return CGEN_DIS_HASH_P (insn); +} + +#ifndef CGEN_ASM_HASH +#define CGEN_ASM_HASH_SIZE 127 +#ifdef CGEN_MNEMONIC_OPERANDS +#define CGEN_ASM_HASH(mnem) (*(unsigned char *) (mnem) % CGEN_ASM_HASH_SIZE) +#else +#define CGEN_ASM_HASH(mnem) (*(unsigned char *) (mnem) % CGEN_ASM_HASH_SIZE) /*FIXME*/ +#endif +#endif + +/* It doesn't make much sense to provide a default here, + but while this is under development we do. + BUFFER is a pointer to the bytes of the insn, target order. + VALUE is the first base_insn_bitsize bits as an int in host order. */ + +#ifndef CGEN_DIS_HASH +#define CGEN_DIS_HASH_SIZE 256 +#define CGEN_DIS_HASH(buf, value) (*(unsigned char *) (buf)) +#endif + +/* The result is the hash value of the insn. + Targets are free to override CGEN_{ASM,DIS}_HASH in the .opc file. */ + +static unsigned int +asm_hash_insn (mnem) + const char * mnem; +{ + return CGEN_ASM_HASH (mnem); +} + +/* BUF is a pointer to the bytes of the insn, target order. + VALUE is the first base_insn_bitsize bits as an int in host order. */ + +static unsigned int +dis_hash_insn (buf, value) + const char * buf ATTRIBUTE_UNUSED; + CGEN_INSN_INT value ATTRIBUTE_UNUSED; +{ + return CGEN_DIS_HASH (buf, value); +} + +/* Set the recorded length of the insn in the CGEN_FIELDS struct. */ + +static void +set_fields_bitsize (CGEN_FIELDS *fields, int size) +{ + CGEN_FIELDS_BITSIZE (fields) = size; +} + +/* Function to call before using the operand instance table. + This plugs the opcode entries and macro instructions into the cpu table. */ + +void +epiphany_cgen_init_opcode_table (CGEN_CPU_DESC cd) +{ + int i; + int num_macros = (sizeof (epiphany_cgen_macro_insn_table) / + sizeof (epiphany_cgen_macro_insn_table[0])); + const CGEN_IBASE *ib = & epiphany_cgen_macro_insn_table[0]; + const CGEN_OPCODE *oc = & epiphany_cgen_macro_insn_opcode_table[0]; + CGEN_INSN *insns = xmalloc (num_macros * sizeof (CGEN_INSN)); + + /* This test has been added to avoid a warning generated + if memset is called with a third argument of value zero. */ + if (num_macros >= 1) + memset (insns, 0, num_macros * sizeof (CGEN_INSN)); + for (i = 0; i < num_macros; ++i) + { + insns[i].base = &ib[i]; + insns[i].opcode = &oc[i]; + epiphany_cgen_build_insn_regex (& insns[i]); + } + cd->macro_insn_table.init_entries = insns; + cd->macro_insn_table.entry_size = sizeof (CGEN_IBASE); + cd->macro_insn_table.num_init_entries = num_macros; + + oc = & epiphany_cgen_insn_opcode_table[0]; + insns = (CGEN_INSN *) cd->insn_table.init_entries; + for (i = 0; i < MAX_INSNS; ++i) + { + insns[i].opcode = &oc[i]; + epiphany_cgen_build_insn_regex (& insns[i]); + } + + cd->sizeof_fields = sizeof (CGEN_FIELDS); + cd->set_fields_bitsize = set_fields_bitsize; + + cd->asm_hash_p = asm_hash_insn_p; + cd->asm_hash = asm_hash_insn; + cd->asm_hash_size = CGEN_ASM_HASH_SIZE; + + cd->dis_hash_p = dis_hash_insn_p; + cd->dis_hash = dis_hash_insn; + cd->dis_hash_size = CGEN_DIS_HASH_SIZE; +} diff --git a/opcodes/epiphany-opc.h b/opcodes/epiphany-opc.h new file mode 100644 index 00000000000..d3f93484d63 --- /dev/null +++ b/opcodes/epiphany-opc.h @@ -0,0 +1,226 @@ +/* Instruction opcode header for epiphany. + +THIS FILE IS MACHINE GENERATED WITH CGEN. + +Copyright 1996-2010 Free Software Foundation, Inc. + +This file is part of the GNU Binutils and/or GDB, the GNU debugger. + + This file is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + It is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License along + with this program; if not, write to the Free Software Foundation, Inc., + 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. + +*/ + +#ifndef EPIPHANY_OPC_H +#define EPIPHANY_OPC_H + +/* -- opc.h */ + +/* enumerate relaxation types for gas. */ +typedef enum epiphany_relax_types +{ + EPIPHANY_RELAX_NONE=0, + EPIPHANY_RELAX_NEED_RELAXING, + + EPIPHANY_RELAX_BRANCH_SHORT, /* Fits into +127..-128 */ + EPIPHANY_RELAX_BRANCH_LONG, /* b/bl/b<cond> +-2*16 */ + + EPIPHANY_RELAX_ARITH_SIMM3, /* add/sub -7..3 */ + EPIPHANY_RELAX_ARITH_SIMM11, /* add/sub -2**11-1 .. 2**10-1 */ + + EPIPHANY_RELAX_MOV_IMM8, /* mov r,imm8 */ + EPIPHANY_RELAX_MOV_IMM16, /* mov r,imm16 */ + + EPIPHANY_RELAX_LDST_IMM3, /* (ldr|str)* r,[r,disp3] */ + EPIPHANY_RELAX_LDST_IMM11 /* (ldr|str)* r,[r,disp11] */ + +} EPIPHANY_RELAX_TYPES; + +/* Override disassembly hashing... */ + +/* Can only depend on instruction having 4 decode bits which gets us to the + major groups of 16/32 instructions. */ +#undef CGEN_DIS_HASH_SIZE +#if 1 + +/* hash code on the 4 LSBs */ +#define CGEN_DIS_HASH_SIZE 16 + +#define CGEN_DIS_HASH(buf, value) ((*buf) & 0xf) +#else +#define CGEN_DIS_HASH_SIZE 1 +#define CGEN_DIS_HASH(buf, value) 0 +#endif + +extern const char * parse_shortregs (CGEN_CPU_DESC cd, + const char ** strp, + CGEN_KEYWORD * keywords, + long * valuep); + +extern const char * parse_branch_addr (CGEN_CPU_DESC cd, + const char ** strp, + int opindex, + int opinfo, + enum cgen_parse_operand_result * resultp, + unsigned long * valuep); + +/* Allows reason codes to be output when assembler errors occur. */ +#define CGEN_VERBOSE_ASSEMBLER_ERRORS + + +/* -- opc.c */ +/* Enum declaration for epiphany instruction types. */ +typedef enum cgen_insn_type { + EPIPHANY_INSN_INVALID, EPIPHANY_INSN_BEQ16, EPIPHANY_INSN_BEQ, EPIPHANY_INSN_BNE16 + , EPIPHANY_INSN_BNE, EPIPHANY_INSN_BGTU16, EPIPHANY_INSN_BGTU, EPIPHANY_INSN_BGTEU16 + , EPIPHANY_INSN_BGTEU, EPIPHANY_INSN_BLTEU16, EPIPHANY_INSN_BLTEU, EPIPHANY_INSN_BLTU16 + , EPIPHANY_INSN_BLTU, EPIPHANY_INSN_BGT16, EPIPHANY_INSN_BGT, EPIPHANY_INSN_BGTE16 + , EPIPHANY_INSN_BGTE, EPIPHANY_INSN_BLT16, EPIPHANY_INSN_BLT, EPIPHANY_INSN_BLTE16 + , EPIPHANY_INSN_BLTE, EPIPHANY_INSN_BBEQ16, EPIPHANY_INSN_BBEQ, EPIPHANY_INSN_BBNE16 + , EPIPHANY_INSN_BBNE, EPIPHANY_INSN_BBLT16, EPIPHANY_INSN_BBLT, EPIPHANY_INSN_BBLTE16 + , EPIPHANY_INSN_BBLTE, EPIPHANY_INSN_B16, EPIPHANY_INSN_B, EPIPHANY_INSN_BL16 + , EPIPHANY_INSN_BL, EPIPHANY_INSN_JR16, EPIPHANY_INSN_RTS, EPIPHANY_INSN_JR + , EPIPHANY_INSN_JALR16, EPIPHANY_INSN_JALR, EPIPHANY_INSN_LDRBX16_S, EPIPHANY_INSN_LDRBP16_S + , EPIPHANY_INSN_LDRBX_L, EPIPHANY_INSN_LDRBP_L, EPIPHANY_INSN_LDRBD16_S, EPIPHANY_INSN_LDRBD_L + , EPIPHANY_INSN_LDRBDPM_L, EPIPHANY_INSN_LDRHX16_S, EPIPHANY_INSN_LDRHP16_S, EPIPHANY_INSN_LDRHX_L + , EPIPHANY_INSN_LDRHP_L, EPIPHANY_INSN_LDRHD16_S, EPIPHANY_INSN_LDRHD_L, EPIPHANY_INSN_LDRHDPM_L + , EPIPHANY_INSN_LDRX16_S, EPIPHANY_INSN_LDRP16_S, EPIPHANY_INSN_LDRX_L, EPIPHANY_INSN_LDRP_L + , EPIPHANY_INSN_LDRD16_S, EPIPHANY_INSN_LDRD_L, EPIPHANY_INSN_LDRDPM_L, EPIPHANY_INSN_LDRDX16_S + , EPIPHANY_INSN_LDRDP16_S, EPIPHANY_INSN_LDRDX_L, EPIPHANY_INSN_LDRDP_L, EPIPHANY_INSN_LDRDD16_S + , EPIPHANY_INSN_LDRDD_L, EPIPHANY_INSN_LDRDDPM_L, EPIPHANY_INSN_TESTSETBT, EPIPHANY_INSN_TESTSETHT + , EPIPHANY_INSN_TESTSETT, EPIPHANY_INSN_STRBX16, EPIPHANY_INSN_STRBX, EPIPHANY_INSN_STRBP16 + , EPIPHANY_INSN_STRBP, EPIPHANY_INSN_STRBD16, EPIPHANY_INSN_STRBD, EPIPHANY_INSN_STRBDPM + , EPIPHANY_INSN_STRHX16, EPIPHANY_INSN_STRHX, EPIPHANY_INSN_STRHP16, EPIPHANY_INSN_STRHP + , EPIPHANY_INSN_STRHD16, EPIPHANY_INSN_STRHD, EPIPHANY_INSN_STRHDPM, EPIPHANY_INSN_STRX16 + , EPIPHANY_INSN_STRX, EPIPHANY_INSN_STRP16, EPIPHANY_INSN_STRP, EPIPHANY_INSN_STRD16 + , EPIPHANY_INSN_STRD, EPIPHANY_INSN_STRDPM, EPIPHANY_INSN_STRDX16, EPIPHANY_INSN_STRDX + , EPIPHANY_INSN_STRDP16, EPIPHANY_INSN_STRDP, EPIPHANY_INSN_STRDD16, EPIPHANY_INSN_STRDD + , EPIPHANY_INSN_STRDDPM, EPIPHANY_INSN_CMOV16EQ, EPIPHANY_INSN_CMOVEQ, EPIPHANY_INSN_CMOV16NE + , EPIPHANY_INSN_CMOVNE, EPIPHANY_INSN_CMOV16GTU, EPIPHANY_INSN_CMOVGTU, EPIPHANY_INSN_CMOV16GTEU + , EPIPHANY_INSN_CMOVGTEU, EPIPHANY_INSN_CMOV16LTEU, EPIPHANY_INSN_CMOVLTEU, EPIPHANY_INSN_CMOV16LTU + , EPIPHANY_INSN_CMOVLTU, EPIPHANY_INSN_CMOV16GT, EPIPHANY_INSN_CMOVGT, EPIPHANY_INSN_CMOV16GTE + , EPIPHANY_INSN_CMOVGTE, EPIPHANY_INSN_CMOV16LT, EPIPHANY_INSN_CMOVLT, EPIPHANY_INSN_CMOV16LTE + , EPIPHANY_INSN_CMOVLTE, EPIPHANY_INSN_CMOV16B, EPIPHANY_INSN_CMOVB, EPIPHANY_INSN_CMOV16BEQ + , EPIPHANY_INSN_CMOVBEQ, EPIPHANY_INSN_CMOV16BNE, EPIPHANY_INSN_CMOVBNE, EPIPHANY_INSN_CMOV16BLT + , EPIPHANY_INSN_CMOVBLT, EPIPHANY_INSN_CMOV16BLTE, EPIPHANY_INSN_CMOVBLTE, EPIPHANY_INSN_MOVTS16 + , EPIPHANY_INSN_MOVTS6, EPIPHANY_INSN_MOVTSDMA, EPIPHANY_INSN_MOVTSMEM, EPIPHANY_INSN_MOVTSMESH + , EPIPHANY_INSN_MOVFS16, EPIPHANY_INSN_MOVFS6, EPIPHANY_INSN_MOVFSDMA, EPIPHANY_INSN_MOVFSMEM + , EPIPHANY_INSN_MOVFSMESH, EPIPHANY_INSN_NOP, EPIPHANY_INSN_SNOP, EPIPHANY_INSN_UNIMPL + , EPIPHANY_INSN_IDLE, EPIPHANY_INSN_BKPT, EPIPHANY_INSN_MBKPT, EPIPHANY_INSN_RTI + , EPIPHANY_INSN_WAND, EPIPHANY_INSN_SYNC, EPIPHANY_INSN_GIEN, EPIPHANY_INSN_GIDIS + , EPIPHANY_INSN_SWI_NUM, EPIPHANY_INSN_SWI, EPIPHANY_INSN_TRAP16, EPIPHANY_INSN_ADD16 + , EPIPHANY_INSN_ADD, EPIPHANY_INSN_SUB16, EPIPHANY_INSN_SUB, EPIPHANY_INSN_AND16 + , EPIPHANY_INSN_AND, EPIPHANY_INSN_ORR16, EPIPHANY_INSN_ORR, EPIPHANY_INSN_EOR16 + , EPIPHANY_INSN_EOR, EPIPHANY_INSN_ADDI16, EPIPHANY_INSN_ADDI, EPIPHANY_INSN_SUBI16 + , EPIPHANY_INSN_SUBI, EPIPHANY_INSN_ASR16, EPIPHANY_INSN_ASR, EPIPHANY_INSN_LSR16 + , EPIPHANY_INSN_LSR, EPIPHANY_INSN_LSL16, EPIPHANY_INSN_LSL, EPIPHANY_INSN_LSRI16 + , EPIPHANY_INSN_LSRI32, EPIPHANY_INSN_LSLI16, EPIPHANY_INSN_LSLI32, EPIPHANY_INSN_ASRI16 + , EPIPHANY_INSN_ASRI32, EPIPHANY_INSN_BITR16, EPIPHANY_INSN_BITR, EPIPHANY_INSN_FEXT + , EPIPHANY_INSN_FDEP, EPIPHANY_INSN_LFSR, EPIPHANY_INSN_MOV8, EPIPHANY_INSN_MOV16 + , EPIPHANY_INSN_MOVT, EPIPHANY_INSN_F_ADDF16, EPIPHANY_INSN_F_ADDF32, EPIPHANY_INSN_F_SUBF16 + , EPIPHANY_INSN_F_SUBF32, EPIPHANY_INSN_F_MULF16, EPIPHANY_INSN_F_MULF32, EPIPHANY_INSN_F_MADDF16 + , EPIPHANY_INSN_F_MADDF32, EPIPHANY_INSN_F_MSUBF16, EPIPHANY_INSN_F_MSUBF32, EPIPHANY_INSN_F_ABSF16 + , EPIPHANY_INSN_F_ABSF32, EPIPHANY_INSN_F_LOATF16, EPIPHANY_INSN_F_LOATF32, EPIPHANY_INSN_F_IXF16 + , EPIPHANY_INSN_F_IXF32, EPIPHANY_INSN_F_RECIPF32, EPIPHANY_INSN_F_SQRTF32 +} CGEN_INSN_TYPE; + +/* Index of `invalid' insn place holder. */ +#define CGEN_INSN_INVALID EPIPHANY_INSN_INVALID + +/* Total number of insns in table. */ +#define MAX_INSNS ((int) EPIPHANY_INSN_F_SQRTF32 + 1) + +/* This struct records data prior to insertion or after extraction. */ +struct cgen_fields +{ + int length; + long f_nil; + long f_anyof; + long f_opc; + long f_opc_4_1; + long f_opc_6_3; + long f_opc_8_5; + long f_opc_19_4; + long f_condcode; + long f_secondary_ccs; + long f_shift; + long f_wordsize; + long f_store; + long f_opc_8_1; + long f_opc_31_32; + long f_simm8; + long f_simm24; + long f_sdisp3; + long f_disp3; + long f_disp8; + long f_imm8; + long f_imm_27_8; + long f_addsubx; + long f_subd; + long f_pm; + long f_rm; + long f_rn; + long f_rd; + long f_rm_x; + long f_rn_x; + long f_rd_x; + long f_dc_9_1; + long f_sn; + long f_sd; + long f_sn_x; + long f_sd_x; + long f_dc_7_4; + long f_trap_swi_9_1; + long f_gien_gidis_9_1; + long f_dc_15_3; + long f_dc_15_7; + long f_dc_15_6; + long f_trap_num; + long f_dc_20_1; + long f_dc_21_1; + long f_dc_21_2; + long f_dc_22_3; + long f_dc_22_2; + long f_dc_22_1; + long f_dc_25_6; + long f_dc_25_4; + long f_dc_25_2; + long f_dc_25_1; + long f_dc_28_1; + long f_dc_31_3; + long f_disp11; + long f_sdisp11; + long f_imm16; + long f_rd6; + long f_rn6; + long f_rm6; + long f_sd6; + long f_sn6; +}; + +#define CGEN_INIT_PARSE(od) \ +{\ +} +#define CGEN_INIT_INSERT(od) \ +{\ +} +#define CGEN_INIT_EXTRACT(od) \ +{\ +} +#define CGEN_INIT_PRINT(od) \ +{\ +} + + +#endif /* EPIPHANY_OPC_H */ diff --git a/opcodes/po/POTFILES.in b/opcodes/po/POTFILES.in index bf9bf046b6b..5c54192c601 100644 --- a/opcodes/po/POTFILES.in +++ b/opcodes/po/POTFILES.in @@ -24,6 +24,13 @@ dis-buf.c dis-init.c disassemble.c dlx-dis.c +epiphany-asm.c +epiphany-desc.c +epiphany-desc.h +epiphany-dis.c +epiphany-ibld.c +epiphany-opc.c +epiphany-opc.h fr30-asm.c fr30-desc.c fr30-desc.h @@ -121,6 +128,7 @@ mep-opc.c mep-opc.h microblaze-dis.c microblaze-opc.h +micromips-opc.c mips-dis.c mips-opc.c mips16-opc.c diff --git a/opcodes/po/opcodes.pot b/opcodes/po/opcodes.pot index ecdb232edd2..90a4bb5e6a6 100644 --- a/opcodes/po/opcodes.pot +++ b/opcodes/po/opcodes.pot @@ -8,7 +8,7 @@ msgid "" msgstr "" "Project-Id-Version: PACKAGE VERSION\n" "Report-Msgid-Bugs-To: bug-binutils@gnu.org\n" -"POT-Creation-Date: 2011-06-02 14:30+0100\n" +"POT-Creation-Date: 2011-10-25 11:34+0100\n" "PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n" "Last-Translator: FULL NAME <EMAIL@ADDRESS>\n" "Language-Team: LANGUAGE <LL@li.org>\n" @@ -111,23 +111,23 @@ msgstr "" msgid "must specify .jd or no nullify suffix" msgstr "" -#: arm-dis.c:1994 +#: arm-dis.c:2000 msgid "<illegal precision>" msgstr "" #. XXX - should break 'option' at following delimiter. -#: arm-dis.c:4376 +#: arm-dis.c:4395 #, c-format msgid "Unrecognised register name set: %s\n" msgstr "" #. XXX - should break 'option' at following delimiter. -#: arm-dis.c:4384 +#: arm-dis.c:4403 #, c-format msgid "Unrecognised disassembler option: %s\n" msgstr "" -#: arm-dis.c:4976 +#: arm-dis.c:4995 #, c-format msgid "" "\n" @@ -135,25 +135,25 @@ msgid "" "the -M switch:\n" msgstr "" -#: avr-dis.c:115 avr-dis.c:135 +#: avr-dis.c:115 avr-dis.c:136 #, c-format msgid "undefined" msgstr "" -#: avr-dis.c:197 +#: avr-dis.c:198 #, c-format msgid "Internal disassembler error" msgstr "" -#: avr-dis.c:250 +#: avr-dis.c:251 #, c-format msgid "unknown constraint `%c'" msgstr "" -#: cgen-asm.c:336 fr30-ibld.c:201 frv-ibld.c:201 ip2k-ibld.c:201 -#: iq2000-ibld.c:201 lm32-ibld.c:201 m32c-ibld.c:201 m32r-ibld.c:201 -#: mep-ibld.c:201 mt-ibld.c:201 openrisc-ibld.c:201 xc16x-ibld.c:201 -#: xstormy16-ibld.c:201 +#: cgen-asm.c:336 epiphany-ibld.c:201 fr30-ibld.c:201 frv-ibld.c:201 +#: ip2k-ibld.c:201 iq2000-ibld.c:201 lm32-ibld.c:201 m32c-ibld.c:201 +#: m32r-ibld.c:201 mep-ibld.c:201 mt-ibld.c:201 openrisc-ibld.c:201 +#: xc16x-ibld.c:201 xstormy16-ibld.c:201 #, c-format msgid "operand out of range (%ld not between %ld and %ld)" msgstr "" @@ -179,36 +179,58 @@ msgstr "" msgid "Address 0x%s is out of bounds.\n" msgstr "" -#: fr30-asm.c:93 m32c-asm.c:872 m32c-asm.c:879 -msgid "Register number is not valid" +#: epiphany-asm.c:68 +msgid "register unavailable for short instructions" msgstr "" -#: fr30-asm.c:95 -msgid "Register must be between r0 and r7" +#: epiphany-asm.c:115 +msgid "register name used as immediate value" msgstr "" -#: fr30-asm.c:97 -msgid "Register must be between r8 and r15" +#. Don't treat "mov ip,ip" as a move-immediate. +#: epiphany-asm.c:178 epiphany-asm.c:234 +msgid "register source in immediate move" msgstr "" -#: fr30-asm.c:116 m32c-asm.c:910 -msgid "Register list is not valid" +#: epiphany-asm.c:187 +msgid "byte relocation unsupported" +msgstr "" + +#. -- assembler routines inserted here. +#. -- asm.c +#: epiphany-asm.c:193 frv-asm.c:972 iq2000-asm.c:56 lm32-asm.c:95 +#: lm32-asm.c:127 lm32-asm.c:157 lm32-asm.c:187 lm32-asm.c:217 lm32-asm.c:247 +#: m32c-asm.c:140 m32c-asm.c:235 m32c-asm.c:276 m32c-asm.c:334 m32c-asm.c:355 +#: m32r-asm.c:53 mep-asm.c:241 mep-asm.c:259 mep-asm.c:274 mep-asm.c:289 +#: mep-asm.c:301 openrisc-asm.c:54 +msgid "missing `)'" msgstr "" -#: fr30-asm.c:310 frv-asm.c:1263 ip2k-asm.c:511 iq2000-asm.c:459 -#: lm32-asm.c:349 m32c-asm.c:1584 m32r-asm.c:328 mep-asm.c:1286 mt-asm.c:595 -#: openrisc-asm.c:241 xc16x-asm.c:376 xstormy16-asm.c:276 +#: epiphany-asm.c:270 +msgid "ABORT: unknown operand" +msgstr "" + +#: epiphany-asm.c:296 +msgid "Not a pc-relative address." +msgstr "" + +#: epiphany-asm.c:455 fr30-asm.c:310 frv-asm.c:1263 ip2k-asm.c:511 +#: iq2000-asm.c:459 lm32-asm.c:349 m32c-asm.c:1584 m32r-asm.c:328 +#: mep-asm.c:1286 mt-asm.c:595 openrisc-asm.c:241 xc16x-asm.c:376 +#: xstormy16-asm.c:276 #, c-format msgid "Unrecognized field %d while parsing.\n" msgstr "" -#: fr30-asm.c:361 frv-asm.c:1314 ip2k-asm.c:562 iq2000-asm.c:510 -#: lm32-asm.c:400 m32c-asm.c:1635 m32r-asm.c:379 mep-asm.c:1337 mt-asm.c:646 -#: openrisc-asm.c:292 xc16x-asm.c:427 xstormy16-asm.c:327 +#: epiphany-asm.c:506 fr30-asm.c:361 frv-asm.c:1314 ip2k-asm.c:562 +#: iq2000-asm.c:510 lm32-asm.c:400 m32c-asm.c:1635 m32r-asm.c:379 +#: mep-asm.c:1337 mt-asm.c:646 openrisc-asm.c:292 xc16x-asm.c:427 +#: xstormy16-asm.c:327 msgid "missing mnemonic in syntax string" msgstr "" #. We couldn't parse it. +#: epiphany-asm.c:641 epiphany-asm.c:645 epiphany-asm.c:734 epiphany-asm.c:841 #: fr30-asm.c:496 fr30-asm.c:500 fr30-asm.c:589 fr30-asm.c:696 frv-asm.c:1449 #: frv-asm.c:1453 frv-asm.c:1542 frv-asm.c:1649 ip2k-asm.c:697 ip2k-asm.c:701 #: ip2k-asm.c:790 ip2k-asm.c:897 iq2000-asm.c:645 iq2000-asm.c:649 @@ -224,116 +246,147 @@ msgstr "" msgid "unrecognized instruction" msgstr "" -#: fr30-asm.c:543 frv-asm.c:1496 ip2k-asm.c:744 iq2000-asm.c:692 -#: lm32-asm.c:582 m32c-asm.c:1817 m32r-asm.c:561 mep-asm.c:1519 mt-asm.c:828 -#: openrisc-asm.c:474 xc16x-asm.c:609 xstormy16-asm.c:509 +#: epiphany-asm.c:688 fr30-asm.c:543 frv-asm.c:1496 ip2k-asm.c:744 +#: iq2000-asm.c:692 lm32-asm.c:582 m32c-asm.c:1817 m32r-asm.c:561 +#: mep-asm.c:1519 mt-asm.c:828 openrisc-asm.c:474 xc16x-asm.c:609 +#: xstormy16-asm.c:509 #, c-format msgid "syntax error (expected char `%c', found `%c')" msgstr "" -#: fr30-asm.c:553 frv-asm.c:1506 ip2k-asm.c:754 iq2000-asm.c:702 -#: lm32-asm.c:592 m32c-asm.c:1827 m32r-asm.c:571 mep-asm.c:1529 mt-asm.c:838 -#: openrisc-asm.c:484 xc16x-asm.c:619 xstormy16-asm.c:519 +#: epiphany-asm.c:698 fr30-asm.c:553 frv-asm.c:1506 ip2k-asm.c:754 +#: iq2000-asm.c:702 lm32-asm.c:592 m32c-asm.c:1827 m32r-asm.c:571 +#: mep-asm.c:1529 mt-asm.c:838 openrisc-asm.c:484 xc16x-asm.c:619 +#: xstormy16-asm.c:519 #, c-format msgid "syntax error (expected char `%c', found end of instruction)" msgstr "" -#: fr30-asm.c:583 frv-asm.c:1536 ip2k-asm.c:784 iq2000-asm.c:732 -#: lm32-asm.c:622 m32c-asm.c:1857 m32r-asm.c:601 mep-asm.c:1559 mt-asm.c:868 -#: openrisc-asm.c:514 xc16x-asm.c:649 xstormy16-asm.c:549 +#: epiphany-asm.c:728 fr30-asm.c:583 frv-asm.c:1536 ip2k-asm.c:784 +#: iq2000-asm.c:732 lm32-asm.c:622 m32c-asm.c:1857 m32r-asm.c:601 +#: mep-asm.c:1559 mt-asm.c:868 openrisc-asm.c:514 xc16x-asm.c:649 +#: xstormy16-asm.c:549 msgid "junk at end of line" msgstr "" -#: fr30-asm.c:695 frv-asm.c:1648 ip2k-asm.c:896 iq2000-asm.c:844 -#: lm32-asm.c:734 m32c-asm.c:1969 m32r-asm.c:713 mep-asm.c:1671 mt-asm.c:980 -#: openrisc-asm.c:626 xc16x-asm.c:761 xstormy16-asm.c:661 +#: epiphany-asm.c:840 fr30-asm.c:695 frv-asm.c:1648 ip2k-asm.c:896 +#: iq2000-asm.c:844 lm32-asm.c:734 m32c-asm.c:1969 m32r-asm.c:713 +#: mep-asm.c:1671 mt-asm.c:980 openrisc-asm.c:626 xc16x-asm.c:761 +#: xstormy16-asm.c:661 msgid "unrecognized form of instruction" msgstr "" -#: fr30-asm.c:709 frv-asm.c:1662 ip2k-asm.c:910 iq2000-asm.c:858 -#: lm32-asm.c:748 m32c-asm.c:1983 m32r-asm.c:727 mep-asm.c:1685 mt-asm.c:994 -#: openrisc-asm.c:640 xc16x-asm.c:775 xstormy16-asm.c:675 +#: epiphany-asm.c:854 fr30-asm.c:709 frv-asm.c:1662 ip2k-asm.c:910 +#: iq2000-asm.c:858 lm32-asm.c:748 m32c-asm.c:1983 m32r-asm.c:727 +#: mep-asm.c:1685 mt-asm.c:994 openrisc-asm.c:640 xc16x-asm.c:775 +#: xstormy16-asm.c:675 #, c-format msgid "bad instruction `%.50s...'" msgstr "" -#: fr30-asm.c:712 frv-asm.c:1665 ip2k-asm.c:913 iq2000-asm.c:861 -#: lm32-asm.c:751 m32c-asm.c:1986 m32r-asm.c:730 mep-asm.c:1688 mt-asm.c:997 -#: openrisc-asm.c:643 xc16x-asm.c:778 xstormy16-asm.c:678 +#: epiphany-asm.c:857 fr30-asm.c:712 frv-asm.c:1665 ip2k-asm.c:913 +#: iq2000-asm.c:861 lm32-asm.c:751 m32c-asm.c:1986 m32r-asm.c:730 +#: mep-asm.c:1688 mt-asm.c:997 openrisc-asm.c:643 xc16x-asm.c:778 +#: xstormy16-asm.c:678 #, c-format msgid "bad instruction `%.50s'" msgstr "" #. Default text to print if an instruction isn't recognized. -#: fr30-dis.c:41 frv-dis.c:41 ip2k-dis.c:41 iq2000-dis.c:41 lm32-dis.c:41 -#: m32c-dis.c:41 m32r-dis.c:41 mep-dis.c:41 mmix-dis.c:277 mt-dis.c:41 -#: openrisc-dis.c:41 xc16x-dis.c:41 xstormy16-dis.c:41 +#: epiphany-dis.c:41 fr30-dis.c:41 frv-dis.c:41 ip2k-dis.c:41 iq2000-dis.c:41 +#: lm32-dis.c:41 m32c-dis.c:41 m32r-dis.c:41 mep-dis.c:41 mmix-dis.c:277 +#: mt-dis.c:41 openrisc-dis.c:41 xc16x-dis.c:41 xstormy16-dis.c:41 msgid "*unknown*" msgstr "" -#: fr30-dis.c:299 frv-dis.c:396 ip2k-dis.c:288 iq2000-dis.c:189 lm32-dis.c:147 -#: m32c-dis.c:891 m32r-dis.c:279 mep-dis.c:1187 mt-dis.c:290 -#: openrisc-dis.c:135 xc16x-dis.c:420 xstormy16-dis.c:168 +#: epiphany-dis.c:277 fr30-dis.c:299 frv-dis.c:396 ip2k-dis.c:288 +#: iq2000-dis.c:189 lm32-dis.c:147 m32c-dis.c:891 m32r-dis.c:279 +#: mep-dis.c:1187 mt-dis.c:290 openrisc-dis.c:135 xc16x-dis.c:420 +#: xstormy16-dis.c:168 #, c-format msgid "Unrecognized field %d while printing insn.\n" msgstr "" -#: fr30-ibld.c:164 frv-ibld.c:164 ip2k-ibld.c:164 iq2000-ibld.c:164 -#: lm32-ibld.c:164 m32c-ibld.c:164 m32r-ibld.c:164 mep-ibld.c:164 -#: mt-ibld.c:164 openrisc-ibld.c:164 xc16x-ibld.c:164 xstormy16-ibld.c:164 +#: epiphany-ibld.c:164 fr30-ibld.c:164 frv-ibld.c:164 ip2k-ibld.c:164 +#: iq2000-ibld.c:164 lm32-ibld.c:164 m32c-ibld.c:164 m32r-ibld.c:164 +#: mep-ibld.c:164 mt-ibld.c:164 openrisc-ibld.c:164 xc16x-ibld.c:164 +#: xstormy16-ibld.c:164 #, c-format msgid "operand out of range (%ld not between %ld and %lu)" msgstr "" -#: fr30-ibld.c:185 frv-ibld.c:185 ip2k-ibld.c:185 iq2000-ibld.c:185 -#: lm32-ibld.c:185 m32c-ibld.c:185 m32r-ibld.c:185 mep-ibld.c:185 -#: mt-ibld.c:185 openrisc-ibld.c:185 xc16x-ibld.c:185 xstormy16-ibld.c:185 +#: epiphany-ibld.c:185 fr30-ibld.c:185 frv-ibld.c:185 ip2k-ibld.c:185 +#: iq2000-ibld.c:185 lm32-ibld.c:185 m32c-ibld.c:185 m32r-ibld.c:185 +#: mep-ibld.c:185 mt-ibld.c:185 openrisc-ibld.c:185 xc16x-ibld.c:185 +#: xstormy16-ibld.c:185 #, c-format msgid "operand out of range (0x%lx not between 0 and 0x%lx)" msgstr "" -#: fr30-ibld.c:727 frv-ibld.c:853 ip2k-ibld.c:604 iq2000-ibld.c:710 -#: lm32-ibld.c:631 m32c-ibld.c:1728 m32r-ibld.c:662 mep-ibld.c:1205 -#: mt-ibld.c:746 openrisc-ibld.c:630 xc16x-ibld.c:749 xstormy16-ibld.c:675 +#: epiphany-ibld.c:872 fr30-ibld.c:727 frv-ibld.c:853 ip2k-ibld.c:604 +#: iq2000-ibld.c:710 lm32-ibld.c:631 m32c-ibld.c:1728 m32r-ibld.c:662 +#: mep-ibld.c:1205 mt-ibld.c:746 openrisc-ibld.c:630 xc16x-ibld.c:749 +#: xstormy16-ibld.c:675 #, c-format msgid "Unrecognized field %d while building insn.\n" msgstr "" -#: fr30-ibld.c:932 frv-ibld.c:1170 ip2k-ibld.c:679 iq2000-ibld.c:885 -#: lm32-ibld.c:735 m32c-ibld.c:2889 m32r-ibld.c:799 mep-ibld.c:1804 -#: mt-ibld.c:966 openrisc-ibld.c:730 xc16x-ibld.c:969 xstormy16-ibld.c:821 +#: epiphany-ibld.c:1166 fr30-ibld.c:932 frv-ibld.c:1170 ip2k-ibld.c:679 +#: iq2000-ibld.c:885 lm32-ibld.c:735 m32c-ibld.c:2889 m32r-ibld.c:799 +#: mep-ibld.c:1804 mt-ibld.c:966 openrisc-ibld.c:730 xc16x-ibld.c:969 +#: xstormy16-ibld.c:821 #, c-format msgid "Unrecognized field %d while decoding insn.\n" msgstr "" -#: fr30-ibld.c:1078 frv-ibld.c:1448 ip2k-ibld.c:753 iq2000-ibld.c:1016 -#: lm32-ibld.c:824 m32c-ibld.c:3506 m32r-ibld.c:912 mep-ibld.c:2274 -#: mt-ibld.c:1166 openrisc-ibld.c:807 xc16x-ibld.c:1190 xstormy16-ibld.c:931 +#: epiphany-ibld.c:1309 fr30-ibld.c:1078 frv-ibld.c:1448 ip2k-ibld.c:753 +#: iq2000-ibld.c:1016 lm32-ibld.c:824 m32c-ibld.c:3506 m32r-ibld.c:912 +#: mep-ibld.c:2274 mt-ibld.c:1166 openrisc-ibld.c:807 xc16x-ibld.c:1190 +#: xstormy16-ibld.c:931 #, c-format msgid "Unrecognized field %d while getting int operand.\n" msgstr "" -#: fr30-ibld.c:1206 frv-ibld.c:1708 ip2k-ibld.c:809 iq2000-ibld.c:1129 -#: lm32-ibld.c:895 m32c-ibld.c:4105 m32r-ibld.c:1007 mep-ibld.c:2726 -#: mt-ibld.c:1348 openrisc-ibld.c:866 xc16x-ibld.c:1393 xstormy16-ibld.c:1023 +#: epiphany-ibld.c:1434 fr30-ibld.c:1206 frv-ibld.c:1708 ip2k-ibld.c:809 +#: iq2000-ibld.c:1129 lm32-ibld.c:895 m32c-ibld.c:4105 m32r-ibld.c:1007 +#: mep-ibld.c:2726 mt-ibld.c:1348 openrisc-ibld.c:866 xc16x-ibld.c:1393 +#: xstormy16-ibld.c:1023 #, c-format msgid "Unrecognized field %d while getting vma operand.\n" msgstr "" -#: fr30-ibld.c:1337 frv-ibld.c:1975 ip2k-ibld.c:868 iq2000-ibld.c:1249 -#: lm32-ibld.c:973 m32c-ibld.c:4692 m32r-ibld.c:1108 mep-ibld.c:3139 -#: mt-ibld.c:1537 openrisc-ibld.c:932 xc16x-ibld.c:1597 xstormy16-ibld.c:1122 +#: epiphany-ibld.c:1566 fr30-ibld.c:1337 frv-ibld.c:1975 ip2k-ibld.c:868 +#: iq2000-ibld.c:1249 lm32-ibld.c:973 m32c-ibld.c:4692 m32r-ibld.c:1108 +#: mep-ibld.c:3139 mt-ibld.c:1537 openrisc-ibld.c:932 xc16x-ibld.c:1597 +#: xstormy16-ibld.c:1122 #, c-format msgid "Unrecognized field %d while setting int operand.\n" msgstr "" -#: fr30-ibld.c:1458 frv-ibld.c:2232 ip2k-ibld.c:917 iq2000-ibld.c:1359 -#: lm32-ibld.c:1041 m32c-ibld.c:5269 m32r-ibld.c:1199 mep-ibld.c:3542 -#: mt-ibld.c:1716 openrisc-ibld.c:988 xc16x-ibld.c:1791 xstormy16-ibld.c:1211 +#: epiphany-ibld.c:1688 fr30-ibld.c:1458 frv-ibld.c:2232 ip2k-ibld.c:917 +#: iq2000-ibld.c:1359 lm32-ibld.c:1041 m32c-ibld.c:5269 m32r-ibld.c:1199 +#: mep-ibld.c:3542 mt-ibld.c:1716 openrisc-ibld.c:988 xc16x-ibld.c:1791 +#: xstormy16-ibld.c:1211 #, c-format msgid "Unrecognized field %d while setting vma operand.\n" msgstr "" +#: fr30-asm.c:93 m32c-asm.c:872 m32c-asm.c:879 +msgid "Register number is not valid" +msgstr "" + +#: fr30-asm.c:95 +msgid "Register must be between r0 and r7" +msgstr "" + +#: fr30-asm.c:97 +msgid "Register must be between r8 and r15" +msgstr "" + +#: fr30-asm.c:116 m32c-asm.c:910 +msgid "Register list is not valid" +msgstr "" + #: frv-asm.c:608 msgid "missing `]'" msgstr "" @@ -350,15 +403,6 @@ msgstr "" msgid "register number must be even" msgstr "" -#. -- assembler routines inserted here. -#. -- asm.c -#: frv-asm.c:972 iq2000-asm.c:56 lm32-asm.c:95 lm32-asm.c:127 lm32-asm.c:157 -#: lm32-asm.c:187 lm32-asm.c:217 lm32-asm.c:247 m32c-asm.c:140 m32c-asm.c:235 -#: m32c-asm.c:276 m32c-asm.c:334 m32c-asm.c:355 m32r-asm.c:53 mep-asm.c:241 -#: mep-asm.c:259 mep-asm.c:274 mep-asm.c:289 mep-asm.c:301 openrisc-asm.c:54 -msgid "missing `)'" -msgstr "" - #: h8300-dis.c:314 #, c-format msgid "Hmmmm 0x%x" @@ -380,11 +424,11 @@ msgstr "" msgid "%02x\t\t*unknown*" msgstr "" -#: i386-dis.c:10774 +#: i386-dis.c:10504 msgid "<internal disassembler error>" msgstr "" -#: i386-dis.c:11071 +#: i386-dis.c:10801 #, c-format msgid "" "\n" @@ -393,126 +437,126 @@ msgid "" "with the -M switch (multiple options should be separated by commas):\n" msgstr "" -#: i386-dis.c:11075 +#: i386-dis.c:10805 #, c-format msgid " x86-64 Disassemble in 64bit mode\n" msgstr "" -#: i386-dis.c:11076 +#: i386-dis.c:10806 #, c-format msgid " i386 Disassemble in 32bit mode\n" msgstr "" -#: i386-dis.c:11077 +#: i386-dis.c:10807 #, c-format msgid " i8086 Disassemble in 16bit mode\n" msgstr "" -#: i386-dis.c:11078 +#: i386-dis.c:10808 #, c-format msgid " att Display instruction in AT&T syntax\n" msgstr "" -#: i386-dis.c:11079 +#: i386-dis.c:10809 #, c-format msgid " intel Display instruction in Intel syntax\n" msgstr "" -#: i386-dis.c:11080 +#: i386-dis.c:10810 #, c-format msgid "" " att-mnemonic\n" " Display instruction in AT&T mnemonic\n" msgstr "" -#: i386-dis.c:11082 +#: i386-dis.c:10812 #, c-format msgid "" " intel-mnemonic\n" " Display instruction in Intel mnemonic\n" msgstr "" -#: i386-dis.c:11084 +#: i386-dis.c:10814 #, c-format msgid " addr64 Assume 64bit address size\n" msgstr "" -#: i386-dis.c:11085 +#: i386-dis.c:10815 #, c-format msgid " addr32 Assume 32bit address size\n" msgstr "" -#: i386-dis.c:11086 +#: i386-dis.c:10816 #, c-format msgid " addr16 Assume 16bit address size\n" msgstr "" -#: i386-dis.c:11087 +#: i386-dis.c:10817 #, c-format msgid " data32 Assume 32bit data size\n" msgstr "" -#: i386-dis.c:11088 +#: i386-dis.c:10818 #, c-format msgid " data16 Assume 16bit data size\n" msgstr "" -#: i386-dis.c:11089 +#: i386-dis.c:10819 #, c-format msgid " suffix Always display instruction suffix in AT&T syntax\n" msgstr "" -#: i386-gen.c:467 ia64-gen.c:307 +#: i386-gen.c:483 ia64-gen.c:307 #, c-format msgid "%s: Error: " msgstr "" -#: i386-gen.c:599 +#: i386-gen.c:615 #, c-format msgid "%s: %d: Unknown bitfield: %s\n" msgstr "" -#: i386-gen.c:601 +#: i386-gen.c:617 #, c-format msgid "Unknown bitfield: %s\n" msgstr "" -#: i386-gen.c:657 +#: i386-gen.c:673 #, c-format msgid "%s: %d: Missing `)' in bitfield: %s\n" msgstr "" -#: i386-gen.c:922 +#: i386-gen.c:938 #, c-format msgid "can't find i386-opc.tbl for reading, errno = %s\n" msgstr "" -#: i386-gen.c:1053 +#: i386-gen.c:1069 #, c-format msgid "can't find i386-reg.tbl for reading, errno = %s\n" msgstr "" -#: i386-gen.c:1130 +#: i386-gen.c:1146 #, c-format msgid "can't create i386-init.h, errno = %s\n" msgstr "" -#: i386-gen.c:1219 ia64-gen.c:2820 +#: i386-gen.c:1235 ia64-gen.c:2820 #, c-format msgid "unable to change directory to \"%s\", errno = %s\n" msgstr "" -#: i386-gen.c:1226 +#: i386-gen.c:1242 #, c-format msgid "%d unused bits in i386_cpu_flags.\n" msgstr "" -#: i386-gen.c:1233 +#: i386-gen.c:1249 #, c-format msgid "%d unused bits in i386_operand_type.\n" msgstr "" -#: i386-gen.c:1247 +#: i386-gen.c:1263 #, c-format msgid "can't create i386-tbl.h, errno = %s\n" msgstr "" @@ -830,26 +874,41 @@ msgstr "" msgid "Value is not aligned enough" msgstr "" -#: mips-dis.c:845 +#: mips-dis.c:947 msgid "# internal error, incomplete extension sequence (+)" msgstr "" -#: mips-dis.c:1011 +#: mips-dis.c:1113 #, c-format msgid "# internal error, undefined extension sequence (+%c)" msgstr "" -#: mips-dis.c:1371 +#: mips-dis.c:1485 #, c-format msgid "# internal error, undefined modifier (%c)" msgstr "" -#: mips-dis.c:1975 +#: mips-dis.c:2089 #, c-format msgid "# internal disassembler error, unrecognised modifier (%c)" msgstr "" -#: mips-dis.c:2213 +#: mips-dis.c:2664 +#, c-format +msgid "# internal disassembler error, unrecognized modifier (+%c)" +msgstr "" + +#: mips-dis.c:2894 +#, c-format +msgid "# internal disassembler error, unrecognized modifier (m%c)" +msgstr "" + +#: mips-dis.c:2904 +#, c-format +msgid "# internal disassembler error, unrecognized modifier (%c)" +msgstr "" + +#: mips-dis.c:3052 #, c-format msgid "" "\n" @@ -857,7 +916,7 @@ msgid "" "with the -M switch (multiple options should be separated by commas):\n" msgstr "" -#: mips-dis.c:2217 +#: mips-dis.c:3056 #, c-format msgid "" "\n" @@ -865,7 +924,7 @@ msgid "" " Default: based on binary being disassembled.\n" msgstr "" -#: mips-dis.c:2221 +#: mips-dis.c:3060 #, c-format msgid "" "\n" @@ -873,7 +932,7 @@ msgid "" " Default: numeric.\n" msgstr "" -#: mips-dis.c:2225 +#: mips-dis.c:3064 #, c-format msgid "" "\n" @@ -882,7 +941,7 @@ msgid "" " Default: based on binary being disassembled.\n" msgstr "" -#: mips-dis.c:2230 +#: mips-dis.c:3069 #, c-format msgid "" "\n" @@ -891,7 +950,7 @@ msgid "" " Default: based on binary being disassembled.\n" msgstr "" -#: mips-dis.c:2235 +#: mips-dis.c:3074 #, c-format msgid "" "\n" @@ -899,7 +958,7 @@ msgid "" " specified ABI.\n" msgstr "" -#: mips-dis.c:2239 +#: mips-dis.c:3078 #, c-format msgid "" "\n" @@ -907,7 +966,7 @@ msgid "" " specified architecture.\n" msgstr "" -#: mips-dis.c:2243 +#: mips-dis.c:3082 #, c-format msgid "" "\n" @@ -915,12 +974,12 @@ msgid "" " " msgstr "" -#: mips-dis.c:2248 mips-dis.c:2256 mips-dis.c:2258 +#: mips-dis.c:3087 mips-dis.c:3095 mips-dis.c:3097 #, c-format msgid "\n" msgstr "" -#: mips-dis.c:2250 +#: mips-dis.c:3089 #, c-format msgid "" "\n" @@ -995,43 +1054,51 @@ msgid "" "the -M switch:\n" msgstr "" -#: ppc-opc.c:879 ppc-opc.c:907 +#: ppc-opc.c:906 ppc-opc.c:936 msgid "invalid conditional option" msgstr "" -#: ppc-opc.c:909 +#: ppc-opc.c:908 ppc-opc.c:938 +msgid "invalid counter access" +msgstr "" + +#: ppc-opc.c:940 msgid "attempt to set y bit when using + or - modifier" msgstr "" -#: ppc-opc.c:941 +#: ppc-opc.c:972 msgid "invalid mask field" msgstr "" -#: ppc-opc.c:967 +#: ppc-opc.c:998 msgid "ignoring invalid mfcr mask" msgstr "" -#: ppc-opc.c:1017 ppc-opc.c:1052 +#: ppc-opc.c:1048 ppc-opc.c:1083 msgid "illegal bitmask" msgstr "" -#: ppc-opc.c:1172 +#: ppc-opc.c:1170 +msgid "address register in load range" +msgstr "" + +#: ppc-opc.c:1223 msgid "index register in load range" msgstr "" -#: ppc-opc.c:1188 +#: ppc-opc.c:1239 ppc-opc.c:1295 msgid "source and target register operands must be different" msgstr "" -#: ppc-opc.c:1203 +#: ppc-opc.c:1254 msgid "invalid register operand when updating" msgstr "" -#: ppc-opc.c:1282 +#: ppc-opc.c:1349 msgid "invalid sprg number" msgstr "" -#: ppc-opc.c:1452 +#: ppc-opc.c:1519 msgid "invalid constant" msgstr "" @@ -1058,23 +1125,23 @@ msgstr "" msgid "<illegal instruction>" msgstr "" -#: sparc-dis.c:283 +#: sparc-dis.c:285 #, c-format msgid "Internal error: bad sparc-opcode.h: \"%s\", %#.8lx, %#.8lx\n" msgstr "" -#: sparc-dis.c:294 +#: sparc-dis.c:296 #, c-format msgid "Internal error: bad sparc-opcode.h: \"%s\", %#.8lx, %#.8lx\n" msgstr "" -#: sparc-dis.c:344 +#: sparc-dis.c:346 #, c-format msgid "Internal error: bad sparc-opcode.h: \"%s\" == \"%s\"\n" msgstr "" #. Mark as non-valid instruction. -#: sparc-dis.c:1015 +#: sparc-dis.c:1028 msgid "unknown" msgstr "" |