diff options
| -rw-r--r-- | bfd/ChangeLog | 7 | ||||
| -rw-r--r-- | bfd/bfdio.c | 6 | ||||
| -rw-r--r-- | bfd/elf32-spu.c | 5 | ||||
| -rw-r--r-- | bfd/elfnn-aarch64.c | 2 | ||||
| -rw-r--r-- | include/opcode/ChangeLog | 7 | ||||
| -rw-r--r-- | include/opcode/i960.h | 4 | ||||
| -rw-r--r-- | opcodes/ChangeLog | 7 | ||||
| -rw-r--r-- | opcodes/aarch64-asm.c | 4 | ||||
| -rw-r--r-- | opcodes/aarch64-dis.c | 4 | ||||
| -rw-r--r-- | opcodes/msp430-dis.c | 2 |
10 files changed, 32 insertions, 16 deletions
diff --git a/bfd/ChangeLog b/bfd/ChangeLog index 824c1716d09..0b07c5ef5ac 100644 --- a/bfd/ChangeLog +++ b/bfd/ChangeLog @@ -1,3 +1,10 @@ +2013-08-23 Yuri Chornoivan <yurchor@ukr.net> + + PR binutils/15834 + * bfdio.c: Fix typos. + * elf32-spu.c: Likewise. + * elfnn-aarch64.c: Likewise. + 2013-08-21 Tristan Gingold <gingold@adacore.com> * coff-rs6000.c (_bfd_xcoff_sizeof_headers): Also count diff --git a/bfd/bfdio.c b/bfd/bfdio.c index be05581aeb4..363402e91fe 100644 --- a/bfd/bfdio.c +++ b/bfd/bfdio.c @@ -1,8 +1,6 @@ /* Low-level I/O routines for BFDs. - Copyright 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, - 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2011 - Free Software Foundation, Inc. + Copyright 1990-2013 Free Software Foundation, Inc. Written by Cygnus Support. @@ -89,7 +87,7 @@ real_fopen (const char *filename, const char *modes) #ifdef VMS char *vms_attr; - /* On VMS, fopen allows file attributes as optionnal arguments. + /* On VMS, fopen allows file attributes as optional arguments. We need to use them but we'd better to use the common prototype. In fopen-vms.h, they are separated from the mode with a comma. Split here. */ diff --git a/bfd/elf32-spu.c b/bfd/elf32-spu.c index c72bbfb1b04..86fb33cfec3 100644 --- a/bfd/elf32-spu.c +++ b/bfd/elf32-spu.c @@ -1,7 +1,6 @@ /* SPU specific support for 32-bit ELF - Copyright 2006, 2007, 2008, 2009, 2010, 2011, 2012 - Free Software Foundation, Inc. + Copyright 2006-2013 Free Software Foundation, Inc. This file is part of BFD, the Binary File Descriptor library. @@ -1143,7 +1142,7 @@ count_stub (struct spu_link_hash_table *htab, } /* Support two sizes of overlay stubs, a slower more compact stub of two - intructions, and a faster stub of four instructions. + instructions, and a faster stub of four instructions. Soft-icache stubs are four or eight words. */ static unsigned int diff --git a/bfd/elfnn-aarch64.c b/bfd/elfnn-aarch64.c index 4e6b1adb05a..bd5f0bf695b 100644 --- a/bfd/elfnn-aarch64.c +++ b/bfd/elfnn-aarch64.c @@ -6176,7 +6176,7 @@ elfNN_aarch64_create_small_pltn_entry (struct elf_link_hash_entry *h, plt_entry + 4, PG_OFFSET (gotplt_entry_address)); - /* Fill in the the lo12 bits for the add from the pltgot entry. */ + /* Fill in the lo12 bits for the add from the pltgot entry. */ elf_aarch64_update_plt_entry (output_bfd, BFD_RELOC_AARCH64_ADD_LO12, plt_entry + 8, PG_OFFSET (gotplt_entry_address)); diff --git a/include/opcode/ChangeLog b/include/opcode/ChangeLog index e842f5da21e..caf7aee83ca 100644 --- a/include/opcode/ChangeLog +++ b/include/opcode/ChangeLog @@ -1,3 +1,8 @@ +2013-08-23 Yuri Chornoivan <yurchor@ukr.net> + + PR binutils/15834 + * i960.h: Fix typos. + 2013-08-19 Richard Sandiford <rdsandiford@googlemail.com> * mips.h: Remove references to "+I" and imm2_expr. @@ -1110,7 +1115,7 @@ 2008-04-28 Adam Nemet <anemet@caviumnetworks.com> - * mips.h (INSN_MACRO): Move it up to the the pinfo macros. + * mips.h (INSN_MACRO): Move it up to the pinfo macros. (INSN2_M_FP_S, INSN2_M_FP_D): New pinfo2 macros. 2008-04-14 Edmar Wienskoski <edmar@freescale.com> diff --git a/include/opcode/i960.h b/include/opcode/i960.h index dc0e78f88a1..7b8e1f5d5fa 100644 --- a/include/opcode/i960.h +++ b/include/opcode/i960.h @@ -1,6 +1,6 @@ /* Basic 80960 instruction formats. - Copyright 2001, 2010 Free Software Foundation, Inc. + Copyright 2001-2013 Free Software Foundation, Inc. This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by @@ -141,7 +141,7 @@ struct i960_opcode { char operand[3];/* Operand descriptors; same order as assembler instr */ }; -/* Classes of 960 intructions: +/* Classes of 960 instructions: * - each instruction falls into one class. * - each target architecture supports one or more classes. * diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index af6ba2be956..7427f14fba7 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,10 @@ +2013-08-23 Yuri Chornoivan <yurchor@ukr.net> + + PR binutils/15834 + * aarch64-asm.c: Fix typos. + * aarch64-dis.c: Likewise. + * msp430-dis.c: Likewise. + 2013-08-19 Richard Sandiford <rdsandiford@googlemail.com> * micromips-opc.c (micromips_opcodes): Replace "dext" and "dins" diff --git a/opcodes/aarch64-asm.c b/opcodes/aarch64-asm.c index 96396e87d48..27a4def173d 100644 --- a/opcodes/aarch64-asm.c +++ b/opcodes/aarch64-asm.c @@ -1,5 +1,5 @@ /* aarch64-asm.c -- AArch64 assembler support. - Copyright 2012, 2013 Free Software Foundation, Inc. + Copyright 2012-2013 Free Software Foundation, Inc. Contributed by ARM Ltd. This file is part of the GNU opcodes library. @@ -31,7 +31,7 @@ N.B. the fields are required to be in such an order than the least signficant field for VALUE comes the first, e.g. the <index> in SQDMLAL <Va><d>, <Vb><n>, <Vm>.<Ts>[<index>] - is encoded in H:L:M in some cases, the the fields H:L:M should be passed in + is encoded in H:L:M in some cases, the fields H:L:M should be passed in the order of M, L, H. */ static inline void diff --git a/opcodes/aarch64-dis.c b/opcodes/aarch64-dis.c index c757316dfb6..c403be85ca9 100644 --- a/opcodes/aarch64-dis.c +++ b/opcodes/aarch64-dis.c @@ -1,5 +1,5 @@ /* aarch64-dis.c -- AArch64 disassembler. - Copyright 2009, 2010, 2011, 2012, 2013 Free Software Foundation, Inc. + Copyright 2009-2013 Free Software Foundation, Inc. Contributed by ARM Ltd. This file is part of the GNU opcodes library. @@ -120,7 +120,7 @@ parse_aarch64_dis_options (const char *options) N.B. the fields are required to be in such an order than the most signficant field for VALUE comes the first, e.g. the <index> in SQDMLAL <Va><d>, <Vb><n>, <Vm>.<Ts>[<index>] - is encoded in H:L:M in some cases, the the fields H:L:M should be passed in + is encoded in H:L:M in some cases, the fields H:L:M should be passed in the order of H, L, M. */ static inline aarch64_insn diff --git a/opcodes/msp430-dis.c b/opcodes/msp430-dis.c index 46da3ccc653..c31463881ec 100644 --- a/opcodes/msp430-dis.c +++ b/opcodes/msp430-dis.c @@ -836,7 +836,7 @@ msp430x_calla_instr (disassemble_info * info, break; default: - strcpy (comm1, _("unercognised CALLA addressing mode")); + strcpy (comm1, _("unrecognised CALLA addressing mode")); return -1; } |