diff options
Diffstat (limited to 'opcodes')
| -rw-r--r-- | opcodes/ChangeLog | 14 | ||||
| -rw-r--r-- | opcodes/i386-gen.c | 6 | ||||
| -rw-r--r-- | opcodes/i386-init.h | 2 | ||||
| -rw-r--r-- | opcodes/i386-opc.h | 8 | ||||
| -rw-r--r-- | opcodes/i386-opc.tbl | 12 |
5 files changed, 28 insertions, 14 deletions
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 0c1be77b69a..9e89ebcafd6 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,17 @@ +2008-04-04 H.J. Lu <hongjiu.lu@intel.com> + + * i386-gen.c (cpu_flag_init): Replace CPU_CLMUL_FLAGS/CpuCLMUL + with CPU_PCLMUL_FLAGS/CpuPCLMUL. + (cpu_flags): Replace CpuCLMUL with CpuPCLMUL. + * i386-opc.tbl: Likewise. + + * i386-opc.h (CpuCLMUL): Renamed to ... + (CpuPCLMUL): This. + (CpuFMA): Updated. + (i386_cpu_flags): Replace cpuclmul with cpupclmul. + + * i386-init.h: Regenerated. + 2008-04-03 H.J. Lu <hongjiu.lu@intel.com> * i386-dis.c (OP_E_register): New. diff --git a/opcodes/i386-gen.c b/opcodes/i386-gen.c index b225e0653e7..12c8bb90ec3 100644 --- a/opcodes/i386-gen.c +++ b/opcodes/i386-gen.c @@ -104,8 +104,8 @@ static initializer cpu_flag_init [] = "CpuXsave" }, { "CPU_AES_FLAGS", "CpuMMX|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3|CpuSSE4_1|CpuSSE4_2|CpuAES" }, - { "CPU_CLMUL_FLAGS", - "CpuMMX|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3|CpuSSE4_1|CpuSSE4_2|CpuCLMUL" }, + { "CPU_PCLMUL_FLAGS", + "CpuMMX|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3|CpuSSE4_1|CpuSSE4_2|CpuPCLMUL" }, { "CPU_FMA_FLAGS", "CpuMMX|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3|CpuSSE4_1|CpuSSE4_2|CpuAVX|CpuFMA" }, { "CPU_3DNOW_FLAGS", @@ -263,7 +263,7 @@ static bitfield cpu_flags[] = BITFIELD (CpuABM), BITFIELD (CpuXsave), BITFIELD (CpuAES), - BITFIELD (CpuCLMUL), + BITFIELD (CpuPCLMUL), BITFIELD (CpuFMA), BITFIELD (CpuLM), BITFIELD (Cpu64), diff --git a/opcodes/i386-init.h b/opcodes/i386-init.h index 11a88aa74b5..b6e7cfa4821 100644 --- a/opcodes/i386-init.h +++ b/opcodes/i386-init.h @@ -146,7 +146,7 @@ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, 0, 0, 0, 0, 1, \ 0, 0, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0 } } -#define CPU_CLMUL_FLAGS \ +#define CPU_PCLMUL_FLAGS \ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, 0, 0, 0, 0, 1, \ 0, 0, 1, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 } } diff --git a/opcodes/i386-opc.h b/opcodes/i386-opc.h index 4ea2ec453b2..a3dd8637759 100644 --- a/opcodes/i386-opc.h +++ b/opcodes/i386-opc.h @@ -86,10 +86,10 @@ #define CpuXsave (CpuAVX + 1) /* AES support required */ #define CpuAES (CpuXsave + 1) -/* CLMUL support required */ -#define CpuCLMUL (CpuAES + 1) +/* PCLMUL support required */ +#define CpuPCLMUL (CpuAES + 1) /* FMA support required */ -#define CpuFMA (CpuCLMUL + 1) +#define CpuFMA (CpuPCLMUL + 1) /* 64bit support available, used by -march= in assembler. */ #define CpuLM (CpuFMA + 1) /* 64bit support required */ @@ -142,7 +142,7 @@ typedef union i386_cpu_flags unsigned int cpuavx:1; unsigned int cpuxsave:1; unsigned int cpuaes:1; - unsigned int cpuclmul:1; + unsigned int cpupclmul:1; unsigned int cpufma:1; unsigned int cpulm:1; unsigned int cpu64:1; diff --git a/opcodes/i386-opc.tbl b/opcodes/i386-opc.tbl index dc71cf3a262..411db32dab7 100644 --- a/opcodes/i386-opc.tbl +++ b/opcodes/i386-opc.tbl @@ -1722,13 +1722,13 @@ aesenclast, 2, 0x660f38dd, None, 3, CpuAES, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_ aesimc, 2, 0x660f38db, None, 3, CpuAES, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } aeskeygenassist, 3, 0x660f3adf, None, 3, CpuAES, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } -// CLMUL +// PCLMUL -pclmulqdq, 3, 0x660f3a44, None, 3, CpuCLMUL, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } -pclmullqlqdq, 2, 0x660f3a44, 0x0, 3, CpuCLMUL, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } -pclmulhqlqdq, 2, 0x660f3a44, 0x1, 3, CpuCLMUL, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } -pclmullqhqdq, 2, 0x660f3a44, 0x10, 3, CpuCLMUL, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } -pclmulhqhqdq, 2, 0x660f3a44, 0x11, 3, CpuCLMUL, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +pclmulqdq, 3, 0x660f3a44, None, 3, CpuPCLMUL, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +pclmullqlqdq, 2, 0x660f3a44, 0x0, 3, CpuPCLMUL, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +pclmulhqlqdq, 2, 0x660f3a44, 0x1, 3, CpuPCLMUL, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +pclmullqhqdq, 2, 0x660f3a44, 0x10, 3, CpuPCLMUL, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +pclmulhqhqdq, 2, 0x660f3a44, 0x11, 3, CpuPCLMUL, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } // AVX instructions. |