diff options
Diffstat (limited to 'sim/testsuite/sim')
214 files changed, 9451 insertions, 0 deletions
diff --git a/sim/testsuite/sim/fr30/add.cgs b/sim/testsuite/sim/fr30/add.cgs new file mode 100644 index 00000000000..1409df1b6fe --- /dev/null +++ b/sim/testsuite/sim/fr30/add.cgs @@ -0,0 +1,55 @@ +# fr30 testcase for add $Rj,$Ri, add $u4,$Rj +# mach(): fr30 + + .include "testutils.inc" + + START + + .text + .global add +add: + ; Test add $Rj,$Ri + mvi_h_gr 1,r7 + mvi_h_gr 2,r8 + set_cc 0x0f ; Set mask opposite of expected + add r7,r8 + test_cc 0 0 0 0 + test_h_gr 3,r8 + + mvi_h_gr 0x7fffffff,r7 + mvi_h_gr 1,r8 + set_cc 0x05 ; Set mask opposite of expected + add r7,r8 + test_cc 1 0 1 0 + test_h_gr 0x80000000,r8 + + set_cc 0x08 ; Set mask opposite of expected + add r8,r8 + test_cc 0 1 1 1 + test_h_gr 0,r8 + + ; Test add $u4Ri + mvi_h_gr 4,r8 + set_cc 0x0f ; Set mask opposite of expected + add 0,r8 + test_cc 0 0 0 0 + test_h_gr 4,r8 + set_cc 0x0f ; Set mask opposite of expected + add 1,r8 + test_cc 0 0 0 0 + test_h_gr 5,r8 + set_cc 0x0f ; Set mask opposite of expected + add 15,r8 + test_cc 0 0 0 0 + test_h_gr 20,r8 + mvi_h_gr 0x7fffffff,r8 ; test neg and overflow bits + set_cc 0x05 ; Set mask opposite of expected + add 1,r8 + test_cc 1 0 1 0 + test_h_gr 0x80000000,r8 + set_cc 0x08 ; Set mask opposite of expected + add r8,r8 ; test zero, carry and overflow bits + test_cc 0 1 1 1; + test_h_gr 0,r8 + + pass diff --git a/sim/testsuite/sim/fr30/add.ms b/sim/testsuite/sim/fr30/add.ms new file mode 100644 index 00000000000..9da6868a110 --- /dev/null +++ b/sim/testsuite/sim/fr30/add.ms @@ -0,0 +1,13 @@ +# fr30 testcase for add $Rj,$Ri +# cpu {} + + .include "testutils.inc" + + START + + .text + .global add +add: + add ac,ac + fail + EXIT 0 diff --git a/sim/testsuite/sim/fr30/add2.cgs b/sim/testsuite/sim/fr30/add2.cgs new file mode 100644 index 00000000000..856acde6fe8 --- /dev/null +++ b/sim/testsuite/sim/fr30/add2.cgs @@ -0,0 +1,43 @@ +# fr30 testcase for add2 $m4,$Ri +# mach(): fr30 + + .include "testutils.inc" + + START + + .text + .global add +add: + mvi_h_gr 30,r8 + set_cc 0x0e ; Set mask opposite of expected + add2 -16,r8 ; Max value of immediate field + test_cc 0 0 0 1 + test_h_gr 14,r8 + + set_cc 0x0e ; Set mask opposite of expected + add2 -3,r8 ; Mid value of immediate field + test_cc 0 0 0 1 + test_h_gr 11,r8 + + set_cc 0x0e ; Set mask opposite of expected + add2 -1,r8 ; Min value of immediate field + test_cc 0 0 0 1 + test_h_gr 10,r8 + + set_cc 0x0a ; Set mask opposite of expected + add2 -10,r8 ; Test zero and carry bits + test_cc 0 1 0 1 + test_h_gr 0,r8 + + set_cc 0x07 ; Set mask opposite of expected + add2 -16,r8 ; Test negative bit + test_cc 1 0 0 0 + test_h_gr -16,r8 + + mvi_h_gr 0x80000000,r8 + set_cc 0x0c ; Set mask opposite of expected + add2 -1,r8 ; Test overflow bit + test_cc 0 0 1 1 + test_h_gr 0x7fffffff,r8 + + pass diff --git a/sim/testsuite/sim/fr30/addc.cgs b/sim/testsuite/sim/fr30/addc.cgs new file mode 100644 index 00000000000..e13547894b6 --- /dev/null +++ b/sim/testsuite/sim/fr30/addc.cgs @@ -0,0 +1,50 @@ +# fr30 testcase for addc $Rj,$Ri +# mach(): fr30 + + .include "testutils.inc" + + START + + .text + .global add +add: + mvi_h_gr 1,r7 + mvi_h_gr 2,r8 + set_cc 0x0e ; Make sure carry bit is off + addc r7,r8 + test_cc 0 0 0 0 + test_h_gr 3,r8 + + mvi_h_gr 0x7fffffff,r7 + mvi_h_gr 1,r8 + set_cc 0x04 ; Make sure carry bit is off + addc r7,r8 + test_cc 1 0 1 0 + test_h_gr 0x80000000,r8 + + set_cc 0x08 ; Make sure carry bit is off + addc r8,r8 + test_cc 0 1 1 1 + test_h_gr 0,r8 + + mvi_h_gr 1,r7 + mvi_h_gr 2,r8 + set_cc 0x0f ; Make sure carry bit is on + addc r7,r8 + test_cc 0 0 0 0 + test_h_gr 4,r8 + + mvi_h_gr 0x7fffffff,r7 + mvi_h_gr 0,r8 + set_cc 0x05 ; Make sure carry bit is on + addc r7,r8 + test_cc 1 0 1 0 + test_h_gr 0x80000000,r8 + + mvi_h_gr 0x7fffffff,r7 + set_cc 0x0b ; Make sure carry bit is on + addc r7,r8 + test_cc 0 1 0 1; + test_h_gr 0,r8 + + pass diff --git a/sim/testsuite/sim/fr30/addn.cgs b/sim/testsuite/sim/fr30/addn.cgs new file mode 100644 index 00000000000..b7638d61995 --- /dev/null +++ b/sim/testsuite/sim/fr30/addn.cgs @@ -0,0 +1,55 @@ +# fr30 testcase for addn $Rj,$Ri, addn $u4,$Rj +# mach(): fr30 + + .include "testutils.inc" + + START + + .text + .global addn +addn: + ; Test addn $Rj,$Ri + mvi_h_gr 1,r7 + mvi_h_gr 2,r8 + set_cc 0x0f ; Set mask opposite of normal result + addn r7,r8 + test_cc 1 1 1 1 + test_h_gr 3,r8 + + mvi_h_gr 0x7fffffff,r7 + mvi_h_gr 1,r8 + set_cc 0x05 ; Set mask opposite of normal result + addn r7,r8 + test_cc 0 1 0 1 + test_h_gr 0x80000000,r8 + + set_cc 0x08 ; Set mask opposite of normal result + addn r8,r8 + test_cc 1 0 0 0 + test_h_gr 0,r8 + + ; Test addn $u4Ri + mvi_h_gr 4,r8 + set_cc 0x0f ; Set mask opposite of normal result + addn 0,r8 + test_cc 1 1 1 1 + test_h_gr 4,r8 + set_cc 0x0f ; Set mask opposite of normal result + addn 1,r8 + test_cc 1 1 1 1 + test_h_gr 5,r8 + set_cc 0x0f ; Set mask opposite of normal result + addn 15,r8 + test_cc 1 1 1 1 + test_h_gr 20,r8 + mvi_h_gr 0x7fffffff,r8 ; test neg and overflow bits + set_cc 0x05 ; Set mask opposite of normal result + addn 1,r8 + test_cc 0 1 0 1 + test_h_gr 0x80000000,r8 + set_cc 0x08 ; Set mask opposite of normal result + addn r8,r8 ; test zero, carry and overflow bits + test_cc 1 0 0 0; + test_h_gr 0,r8 + + pass diff --git a/sim/testsuite/sim/fr30/addn2.cgs b/sim/testsuite/sim/fr30/addn2.cgs new file mode 100644 index 00000000000..9525baf4502 --- /dev/null +++ b/sim/testsuite/sim/fr30/addn2.cgs @@ -0,0 +1,43 @@ +# fr30 testcase for addn2 $m4,$Ri +# mach(): fr30 + + .include "testutils.inc" + + START + + .text + .global add +add: + mvi_h_gr 30,r8 + set_cc 0x0e ; Set mask opposite of normal result + addn2 -16,r8 ; Max value of immediate field + test_cc 1 1 1 0 + test_h_gr 14,r8 + + set_cc 0x0e ; Set mask opposite of normal result + addn2 -3,r8 ; Mid value of immediate field + test_cc 1 1 1 0 + test_h_gr 11,r8 + + set_cc 0x0e ; Set mask opposite of normal result + addn2 -1,r8 ; Min value of immediate field + test_cc 1 1 1 0 + test_h_gr 10,r8 + + set_cc 0x0a ; Set mask opposite of normal result + addn2 -10,r8 ; Test zero and carry bits + test_cc 1 0 1 0 + test_h_gr 0,r8 + + set_cc 0x07 ; Set mask opposite of normal result + addn2 -16,r8 ; Test negative bit + test_cc 0 1 1 1 + test_h_gr -16,r8 + + mvi_h_gr 0x80000000,r8 + set_cc 0x0c ; Set mask opposite of normal result + addn2 -1,r8 ; Test overflow bit + test_cc 1 1 0 0 + test_h_gr 0x7fffffff,r8 + + pass diff --git a/sim/testsuite/sim/fr30/addsp.cgs b/sim/testsuite/sim/fr30/addsp.cgs new file mode 100644 index 00000000000..da5bc36b86a --- /dev/null +++ b/sim/testsuite/sim/fr30/addsp.cgs @@ -0,0 +1,31 @@ +# fr30 testcase for addsp $s10 +# mach(): fr30 + + .include "testutils.inc" + + START + + .text + .global addsp +addsp: + ; Test addsp $s10 + mvr_h_gr sp,r7 ; save stack pointer permanently + mvr_h_gr sp,r8 ; Shadow updated sp + set_cc 0x0f ; Condition codes are irrelevent + addsp 508 + test_cc 1 1 1 1 + inci_h_gr 508,r8 + testr_h_gr r8,sp + + set_cc 0x0e ; Condition codes are irrelevent + addsp 0 + test_cc 1 1 1 0 + testr_h_gr r8,sp + + set_cc 0x0d ; Condition codes are irrelevent + addsp -512 + test_cc 1 1 0 1 + inci_h_gr -512,r8 + testr_h_gr r8,sp + + pass diff --git a/sim/testsuite/sim/fr30/allinsn.exp b/sim/testsuite/sim/fr30/allinsn.exp new file mode 100644 index 00000000000..8c3d5121113 --- /dev/null +++ b/sim/testsuite/sim/fr30/allinsn.exp @@ -0,0 +1,19 @@ +# FR30 simulator testsuite. + +if [istarget fr30*-*-*] { + # load support procs + # load_lib cgen.exp + + # all machines + set all_machs "fr30" + + foreach src [lsort [glob -nocomplain $srcdir/$subdir/*.cgs]] { + # If we're only testing specific files and this isn't one of them, + # skip it. + if ![runtest_file_p $runtests $src] { + continue + } + + run_sim_test $src $all_machs + } +} diff --git a/sim/testsuite/sim/fr30/and.cgs b/sim/testsuite/sim/fr30/and.cgs new file mode 100644 index 00000000000..49db6fd2ee1 --- /dev/null +++ b/sim/testsuite/sim/fr30/and.cgs @@ -0,0 +1,51 @@ +# fr30 testcase for and $Rj,$Ri, and $Rj,@$Ri +# mach(): fr30 + + .include "testutils.inc" + + START + + .text + .global and +and: + ; Test and $Rj,$Ri + mvi_h_gr 0xaaaaaaaa,r7 + mvi_h_gr 0x55555555,r8 + set_cc 0x0b ; Set mask opposite of expected + and r7,r8 + test_cc 0 1 1 1 + test_h_gr 0,r8 + + mvi_h_gr 0xffff0000,r8 + set_cc 0x04 ; Set mask opposite of expected + and r7,r8 + test_cc 1 0 0 0 + test_h_gr 0xaaaa0000,r8 + + mvi_h_gr 0xffff,r8 + set_cc 0x0d ; Set mask opposite of expected + and r7,r8 + test_cc 0 0 0 1 + test_h_gr 0xaaaa,r8 + + ; Test and $Rj,@$Ri + mvi_h_gr 0xaaaaaaaa,r7 + mvi_h_mem 0x55555555,sp + set_cc 0x0b ; Set mask opposite of expected + and r7,@sp + test_cc 0 1 1 1 + test_h_mem 0,sp + + mvi_h_mem 0xffff0000,sp + set_cc 0x04 ; Set mask opposite of expected + and r7,@sp + test_cc 1 0 0 0 + test_h_mem 0xaaaa0000,sp + + mvi_h_mem 0xffff,sp + set_cc 0x0d ; Set mask opposite of expected + and r7,@sp + test_cc 0 0 0 1 + test_h_mem 0xaaaa,sp + + pass diff --git a/sim/testsuite/sim/fr30/andb.cgs b/sim/testsuite/sim/fr30/andb.cgs new file mode 100644 index 00000000000..c01d49d276b --- /dev/null +++ b/sim/testsuite/sim/fr30/andb.cgs @@ -0,0 +1,31 @@ +# fr30 testcase for andb $Rj,@$Ri +# mach(): fr30 + + .include "testutils.inc" + + START + + .text + .global andb +andb: + ; Test andb $Rj,@$Ri + mvi_h_gr 0xaaaaaaaa,r7 + mvi_h_mem 0x55555555,sp + set_cc 0x0b ; Set mask opposite of expected + andb r7,@sp + test_cc 0 1 1 1 + test_h_mem 0x00555555,sp + + mvi_h_mem 0xffffffff,sp + set_cc 0x04 ; Set mask opposite of expected + andb r7,@sp + test_cc 1 0 0 0 + test_h_mem 0xaaffffff,sp + + mvi_h_mem 0x0fffffff,sp + set_cc 0x0d ; Set mask opposite of expected + andb r7,@sp + test_cc 0 0 0 1 + test_h_mem 0x0affffff,sp + + pass diff --git a/sim/testsuite/sim/fr30/andccr.cgs b/sim/testsuite/sim/fr30/andccr.cgs new file mode 100644 index 00000000000..7f8f99e25f5 --- /dev/null +++ b/sim/testsuite/sim/fr30/andccr.cgs @@ -0,0 +1,51 @@ +# fr30 testcase for andccr $u8 +# mach(): fr30 + + .include "testutils.inc" + + START + + .text + .global andccr +andccr: + set_cc 0x00 + set_i 0 + set_s_system + andccr 0xff + test_cc 0 0 0 0 + test_i 0 + test_s_system + + set_cc 0x0f + set_i 1 + set_s_user + andccr 0xff + test_cc 1 1 1 1 + test_i 1 + test_s_user + + set_cc 0x0f + set_i 1 + set_s_user + andccr 0xaa + test_cc 1 0 1 0 + test_i 0 + test_s_user + + set_cc 0x0f + set_i 1 + set_s_user + andccr 0xc0 + test_cc 0 0 0 0 + test_i 0 + test_s_system + + set_cc 0x0f + set_i 1 + set_s_user + andccr 0x3f ; no effect + test_cc 1 1 1 1 + test_i 1 + test_s_user + + pass diff --git a/sim/testsuite/sim/fr30/andh.cgs b/sim/testsuite/sim/fr30/andh.cgs new file mode 100644 index 00000000000..a172fc764f2 --- /dev/null +++ b/sim/testsuite/sim/fr30/andh.cgs @@ -0,0 +1,31 @@ +# fr30 testcase for andh $Rj,@$Ri +# mach(): fr30 + + .include "testutils.inc" + + START + + .text + .global andh +andh: + ; Test andh $Rj,@$Ri + mvi_h_gr 0xaaaaaaaa,r7 + mvi_h_mem 0x55555555,sp + set_cc 0x0b ; Set mask opposite of expected + andh r7,@sp + test_cc 0 1 1 1 + test_h_mem 0x00005555,sp + + mvi_h_mem 0xffffffff,sp + set_cc 0x04 ; Set mask opposite of expected + andh r7,@sp + test_cc 1 0 0 0 + test_h_mem 0xaaaaffff,sp + + mvi_h_mem 0x00ffffff,sp + set_cc 0x0d ; Set mask opposite of expected + andh r7,@sp + test_cc 0 0 0 1 + test_h_mem 0x00aaffff,sp + + pass diff --git a/sim/testsuite/sim/fr30/asr.cgs b/sim/testsuite/sim/fr30/asr.cgs new file mode 100644 index 00000000000..f783d41ba3d --- /dev/null +++ b/sim/testsuite/sim/fr30/asr.cgs @@ -0,0 +1,65 @@ +# fr30 testcase for asr $Rj,$Ri, asr $u4,$Rj +# mach(): fr30 + + .include "testutils.inc" + + START + + .text + .global asr +asr: + ; Test asr $Rj,$Ri + mvi_h_gr 0xdeadbee0,r7 ; Shift by 0 + mvi_h_gr 0x80000000,r8 + set_cc 0x05 ; Set mask opposite of expected + asr r7,r8 + test_cc 1 0 0 0 + test_h_gr 0x80000000,r8 + + mvi_h_gr 0xdeadbee1,r7 ; Shift by 1 + mvi_h_gr 0x80000000,r8 + set_cc 0x07 ; Set mask opposite of expected + asr r7,r8 + test_cc 1 0 1 0 + test_h_gr 0xc0000000,r8 + + mvi_h_gr 0xdeadbeff,r7 ; Shift by 31 + mvi_h_gr 0x80000000,r8 + set_cc 0x07 ; Set mask opposite of expected + asr r7,r8 + test_cc 1 0 1 0 + test_h_gr -1,r8 + + mvi_h_gr 0xdeadbeff,r7 ; clear register + mvi_h_gr 0x40000000,r8 + set_cc 0x0a ; Set mask opposite of expected + asr r7,r8 + test_cc 0 1 1 1 + test_h_gr 0x00000000,r8 + + ; Test asr $u4Ri + mvi_h_gr 0x80000000,r8 + set_cc 0x05 ; Set mask opposite of expected + asr 0,r8 + test_cc 1 0 0 0 + test_h_gr 0x80000000,r8 + + mvi_h_gr 0x80000000,r8 + set_cc 0x07 ; Set mask opposite of expected + asr 1,r8 + test_cc 1 0 1 0 + test_h_gr 0xc0000000,r8 + + mvi_h_gr 0x80000000,r8 + set_cc 0x07 ; Set mask opposite of expected + asr 15,r8 + test_cc 1 0 1 0 + test_h_gr 0xffff0000,r8 + + mvi_h_gr 0x00004000,r8 + set_cc 0x0a ; Set mask opposite of expected + asr 15,r8 + test_cc 0 1 1 1 + test_h_gr 0x00000000,r8 + + pass diff --git a/sim/testsuite/sim/fr30/asr2.cgs b/sim/testsuite/sim/fr30/asr2.cgs new file mode 100644 index 00000000000..884e40d5c84 --- /dev/null +++ b/sim/testsuite/sim/fr30/asr2.cgs @@ -0,0 +1,36 @@ +# fr30 testcase for asr2 $u4,$Rj +# mach(): fr30 + + .include "testutils.inc" + + START + + .text + .global asr2 +asr2: + ; Test asr2 $u4Ri + mvi_h_gr 0x80000000,r8 + set_cc 0x05 ; Set mask opposite of expected + asr2 0,r8 + test_cc 1 0 0 0 + test_h_gr 0xffff8000,r8 + + mvi_h_gr 0x80000000,r8 + set_cc 0x07 ; Set mask opposite of expected + asr2 1,r8 + test_cc 1 0 1 0 + test_h_gr 0xffffc000,r8 + + mvi_h_gr 0x80000000,r8 + set_cc 0x07 ; Set mask opposite of expected + asr2 15,r8 + test_cc 1 0 1 0 + test_h_gr -1,r8 + + mvi_h_gr 0x40000000,r8 + set_cc 0x0a ; Set mask opposite of expected + asr2 15,r8 + test_cc 0 1 1 1 + test_h_gr 0x00000000,r8 + + pass diff --git a/sim/testsuite/sim/fr30/bandh.cgs b/sim/testsuite/sim/fr30/bandh.cgs new file mode 100644 index 00000000000..45ab5e59f3a --- /dev/null +++ b/sim/testsuite/sim/fr30/bandh.cgs @@ -0,0 +1,30 @@ +# fr30 testcase for bandh $Rj,@$Ri +# mach(): fr30 + + .include "testutils.inc" + + START + + .text + .global bandh +bandh: + ; Test bandh $Rj,@$Ri + mvi_h_mem 0x55555555,sp + set_cc 0x0f ; Condition codes should not change + bandh 0x0a,@sp + test_cc 1 1 1 1 + test_h_mem 0x05555555,sp + + mvi_h_mem 0xffffffff,sp + set_cc 0x04 ; Condition codes should not change + bandh 0x0a,@sp + test_cc 0 1 0 0 + test_h_mem 0xafffffff,sp + + mvi_h_mem 0xe5ffffff,sp + set_cc 0x0a ; Condition codes should not change + bandh 0x07,@sp + test_cc 1 0 1 0 + test_h_mem 0x65ffffff,sp + + pass diff --git a/sim/testsuite/sim/fr30/bandl.cgs b/sim/testsuite/sim/fr30/bandl.cgs new file mode 100644 index 00000000000..9cd4825965a --- /dev/null +++ b/sim/testsuite/sim/fr30/bandl.cgs @@ -0,0 +1,30 @@ +# fr30 testcase for bandl $Rj,@$Ri +# mach(): fr30 + + .include "testutils.inc" + + START + + .text + .global bandl +bandl: + ; Test bandl $Rj,@$Ri + mvi_h_mem 0x55555555,sp + set_cc 0x0f ; Condition codes should not change + bandl 0x0a,@sp + test_cc 1 1 1 1 + test_h_mem 0x50555555,sp + + mvi_h_mem 0xffffffff,sp + set_cc 0x04 ; Condition codes should not change + bandl 0x0a,@sp + test_cc 0 1 0 0 + test_h_mem 0xfaffffff,sp + + mvi_h_mem 0x5effffff,sp + set_cc 0x0a ; Condition codes should not change + bandl 0x07,@sp + test_cc 1 0 1 0 + test_h_mem 0x56ffffff,sp + + pass diff --git a/sim/testsuite/sim/fr30/bc.cgs b/sim/testsuite/sim/fr30/bc.cgs new file mode 100644 index 00000000000..0502625d32e --- /dev/null +++ b/sim/testsuite/sim/fr30/bc.cgs @@ -0,0 +1,109 @@ +# fr30 testcase for bc $label9 +# mach(): fr30 + + .include "testutils.inc" + + START + + .text + .global bc +bc: + ; Test bc $label9 + set_cc 0x0f ; condition codes are irrelevent + take_branch bc + + set_cc 0x0e ; condition codes are irrelevent + no_branch bc + + set_cc 0x0d ; condition codes are irrelevent + take_branch bc + + set_cc 0x0c ; condition codes are irrelevent + no_branch bc + + set_cc 0x0b ; condition codes are irrelevent + take_branch bc + + set_cc 0x0a ; condition codes are irrelevent + no_branch bc + + set_cc 0x09 ; condition codes are irrelevent + take_branch bc + + set_cc 0x08 ; condition codes are irrelevent + no_branch bc + + set_cc 0x07 ; condition codes are irrelevent + take_branch bc + + set_cc 0x06 ; condition codes are irrelevent + no_branch bc + + set_cc 0x05 ; condition codes are irrelevent + take_branch bc + + set_cc 0x04 ; condition codes are irrelevent + no_branch bc + + set_cc 0x03 ; condition codes are irrelevent + take_branch bc + + set_cc 0x02 ; condition codes are irrelevent + no_branch bc + + set_cc 0x01 ; condition codes are irrelevent + take_branch bc + + set_cc 0x00 ; condition codes are irrelevent + no_branch bc + + ; Test bc:d label9 + set_cc 0x0f ; condition codes are irrelevent + take_branch_d bc:d 0xf + + set_cc 0x0e ; condition codes are irrelevent + no_branch_d bc:d 0xe + + set_cc 0x0d ; condition codes are irrelevent + take_branch_d bc:d 0xd + + set_cc 0x0c ; condition codes are irrelevent + no_branch_d bc:d 0xc + + set_cc 0x0b ; condition codes are irrelevent + take_branch_d bc:d 0xb + + set_cc 0x0a ; condition codes are irrelevent + no_branch_d bc:d 0xa + + set_cc 0x09 ; condition codes are irrelevent + take_branch_d bc:d 0x9 + + set_cc 0x08 ; condition codes are irrelevent + no_branch_d bc:d 0x8 + + set_cc 0x07 ; condition codes are irrelevent + take_branch_d bc:d 0x7 + + set_cc 0x06 ; condition codes are irrelevent + no_branch_d bc:d 0x6 + + set_cc 0x05 ; condition codes are irrelevent + take_branch_d bc:d 0x5 + + set_cc 0x04 ; condition codes are irrelevent + no_branch_d bc:d 0x4 + + set_cc 0x03 ; condition codes are irrelevent + take_branch_d bc:d 0x3 + + set_cc 0x02 ; condition codes are irrelevent + no_branch_d bc:d 0x2 + + set_cc 0x01 ; condition codes are irrelevent + take_branch_d bc:d 0x1 + + set_cc 0x00 ; condition codes are irrelevent + no_branch_d bc:d 0x0 + + pass diff --git a/sim/testsuite/sim/fr30/beorh.cgs b/sim/testsuite/sim/fr30/beorh.cgs new file mode 100644 index 00000000000..6d07f1af788 --- /dev/null +++ b/sim/testsuite/sim/fr30/beorh.cgs @@ -0,0 +1,36 @@ +# fr30 testcase for beorh $Rj,@$Ri +# mach(): fr30 + + .include "testutils.inc" + + START + + .text + .global beorh +beorh: + ; Test beorh $Rj,@$Ri + mvi_h_mem 0x55555555,sp + set_cc 0x0f ; Condition codes should not change + beorh 0x0a,@sp + test_cc 1 1 1 1 + test_h_mem 0xf5555555,sp + + mvi_h_mem 0x0fffffff,sp + set_cc 0x04 ; Condition codes should not change + beorh 0x00,@sp + test_cc 0 1 0 0 + test_h_mem 0x0fffffff,sp + + mvi_h_mem 0xffffffff,sp + set_cc 0x0a ; Condition codes should not change + beorh 0x0f,@sp + test_cc 1 0 1 0 + test_h_mem 0x0fffffff,sp + + mvi_h_mem 0x9eadbeef,sp + set_cc 0x09 ; Condition codes should not change + beorh 0x04,@sp + test_cc 1 0 0 1 + test_h_mem 0xdeadbeef,sp + + pass diff --git a/sim/testsuite/sim/fr30/beorl.cgs b/sim/testsuite/sim/fr30/beorl.cgs new file mode 100644 index 00000000000..f7ea05347b3 --- /dev/null +++ b/sim/testsuite/sim/fr30/beorl.cgs @@ -0,0 +1,36 @@ +# fr30 testcase for beorl $Rj,@$Ri +# mach(): fr30 + + .include "testutils.inc" + + START + + .text + .global beorl +beorl: + ; Test beorl $Rj,@$Ri + mvi_h_mem 0x55555555,sp + set_cc 0x0f ; Condition codes should not change + beorl 0x0a,@sp + test_cc 1 1 1 1 + test_h_mem 0x5f555555,sp + + mvi_h_mem 0xf0ffffff,sp + set_cc 0x04 ; Condition codes should not change + beorl 0x00,@sp + test_cc 0 1 0 0 + test_h_mem 0xf0ffffff,sp + + mvi_h_mem 0xffffffff,sp + set_cc 0x0a ; Condition codes should not change + beorl 0x0f,@sp + test_cc 1 0 1 0 + test_h_mem 0xf0ffffff,sp + + mvi_h_mem 0xddadbeef,sp + set_cc 0x09 ; Condition codes should not change + beorl 0x03,@sp + test_cc 1 0 0 1 + test_h_mem 0xdeadbeef,sp + + pass diff --git a/sim/testsuite/sim/fr30/beq.cgs b/sim/testsuite/sim/fr30/beq.cgs new file mode 100644 index 00000000000..edd797e4ed2 --- /dev/null +++ b/sim/testsuite/sim/fr30/beq.cgs @@ -0,0 +1,109 @@ +# fr30 testcase for beq $label9 +# mach(): fr30 + + .include "testutils.inc" + + START + + .text + .global beq +beq: + ; Test beq $label9 + set_cc 0x0f ; condition codes are irrelevent + take_branch beq + + set_cc 0x0e ; condition codes are irrelevent + take_branch beq + + set_cc 0x0d ; condition codes are irrelevent + take_branch beq + + set_cc 0x0c ; condition codes are irrelevent + take_branch beq + + set_cc 0x0b ; condition codes are irrelevent + no_branch beq + + set_cc 0x0a ; condition codes are irrelevent + no_branch beq + + set_cc 0x09 ; condition codes are irrelevent + no_branch beq + + set_cc 0x08 ; condition codes are irrelevent + no_branch beq + + set_cc 0x07 ; condition codes are irrelevent + take_branch beq + + set_cc 0x06 ; condition codes are irrelevent + take_branch beq + + set_cc 0x05 ; condition codes are irrelevent + take_branch beq + + set_cc 0x04 ; condition codes are irrelevent + take_branch beq + + set_cc 0x03 ; condition codes are irrelevent + no_branch beq + + set_cc 0x02 ; condition codes are irrelevent + no_branch beq + + set_cc 0x01 ; condition codes are irrelevent + no_branch beq + + set_cc 0x00 ; condition codes are irrelevent + no_branch beq + + ; Test beq:d label9 + set_cc 0x0f ; condition codes are irrelevent + take_branch_d beq:d 0xf + + set_cc 0x0e ; condition codes are irrelevent + take_branch_d beq:d 0xe + + set_cc 0x0d ; condition codes are irrelevent + take_branch_d beq:d 0xd + + set_cc 0x0c ; condition codes are irrelevent + take_branch_d beq:d 0xc + + set_cc 0x0b ; condition codes are irrelevent + no_branch_d beq:d 0xb + + set_cc 0x0a ; condition codes are irrelevent + no_branch_d beq:d 0xa + + set_cc 0x09 ; condition codes are irrelevent + no_branch_d beq:d 0x9 + + set_cc 0x08 ; condition codes are irrelevent + no_branch_d beq:d 0x8 + + set_cc 0x07 ; condition codes are irrelevent + take_branch_d beq:d 0x7 + + set_cc 0x06 ; condition codes are irrelevent + take_branch_d beq:d 0x6 + + set_cc 0x05 ; condition codes are irrelevent + take_branch_d beq:d 0x5 + + set_cc 0x04 ; condition codes are irrelevent + take_branch_d beq:d 0x4 + + set_cc 0x03 ; condition codes are irrelevent + no_branch_d beq:d 0x3 + + set_cc 0x02 ; condition codes are irrelevent + no_branch_d beq:d 0x2 + + set_cc 0x01 ; condition codes are irrelevent + no_branch_d beq:d 0x1 + + set_cc 0x00 ; condition codes are irrelevent + no_branch_d beq:d 0x0 + + pass diff --git a/sim/testsuite/sim/fr30/bge.cgs b/sim/testsuite/sim/fr30/bge.cgs new file mode 100644 index 00000000000..dd7796ccd94 --- /dev/null +++ b/sim/testsuite/sim/fr30/bge.cgs @@ -0,0 +1,109 @@ +# fr30 testcase for bge $label9 +# mach(): fr30 + + .include "testutils.inc" + + START + + .text + .global bge +bge: + ; Test bge $label9 + set_cc 0x0f ; condition codes are irrelevent + take_branch bge + + set_cc 0x0e ; condition codes are irrelevent + take_branch bge + + set_cc 0x0d ; condition codes are irrelevent + no_branch bge + + set_cc 0x0c ; condition codes are irrelevent + no_branch bge + + set_cc 0x0b ; condition codes are irrelevent + take_branch bge + + set_cc 0x0a ; condition codes are irrelevent + take_branch bge + + set_cc 0x09 ; condition codes are irrelevent + no_branch bge + + set_cc 0x08 ; condition codes are irrelevent + no_branch bge + + set_cc 0x07 ; condition codes are irrelevent + no_branch bge + + set_cc 0x06 ; condition codes are irrelevent + no_branch bge + + set_cc 0x05 ; condition codes are irrelevent + take_branch bge + + set_cc 0x04 ; condition codes are irrelevent + take_branch bge + + set_cc 0x03 ; condition codes are irrelevent + no_branch bge + + set_cc 0x02 ; condition codes are irrelevent + no_branch bge + + set_cc 0x01 ; condition codes are irrelevent + take_branch bge + + set_cc 0x00 ; condition codes are irrelevent + take_branch bge + + ; Test bge:d label9 + set_cc 0x0f ; condition codes are irrelevent + take_branch_d bge:d 0xf + + set_cc 0x0e ; condition codes are irrelevent + take_branch_d bge:d 0xe + + set_cc 0x0d ; condition codes are irrelevent + no_branch_d bge:d 0xd + + set_cc 0x0c ; condition codes are irrelevent + no_branch_d bge:d 0xc + + set_cc 0x0b ; condition codes are irrelevent + take_branch_d bge:d 0xb + + set_cc 0x0a ; condition codes are irrelevent + take_branch_d bge:d 0xa + + set_cc 0x09 ; condition codes are irrelevent + no_branch_d bge:d 0x9 + + set_cc 0x08 ; condition codes are irrelevent + no_branch_d bge:d 0x8 + + set_cc 0x07 ; condition codes are irrelevent + no_branch_d bge:d 0x7 + + set_cc 0x06 ; condition codes are irrelevent + no_branch_d bge:d 0x6 + + set_cc 0x05 ; condition codes are irrelevent + take_branch_d bge:d 0x5 + + set_cc 0x04 ; condition codes are irrelevent + take_branch_d bge:d 0x4 + + set_cc 0x03 ; condition codes are irrelevent + no_branch_d bge:d 0x3 + + set_cc 0x02 ; condition codes are irrelevent + no_branch_d bge:d 0x2 + + set_cc 0x01 ; condition codes are irrelevent + take_branch_d bge:d 0x1 + + set_cc 0x00 ; condition codes are irrelevent + take_branch_d bge:d 0x0 + + pass diff --git a/sim/testsuite/sim/fr30/bgt.cgs b/sim/testsuite/sim/fr30/bgt.cgs new file mode 100644 index 00000000000..525ac2e8f32 --- /dev/null +++ b/sim/testsuite/sim/fr30/bgt.cgs @@ -0,0 +1,109 @@ +# fr30 testcase for bgt $label9 +# mach(): fr30 + + .include "testutils.inc" + + START + + .text + .global bgt +bgt: + ; Test bgt $label9 + set_cc 0x0f ; condition codes are irrelevent + no_branch bgt + + set_cc 0x0e ; condition codes are irrelevent + no_branch bgt + + set_cc 0x0d ; condition codes are irrelevent + no_branch bgt + + set_cc 0x0c ; condition codes are irrelevent + no_branch bgt + + set_cc 0x0b ; condition codes are irrelevent + take_branch bgt + + set_cc 0x0a ; condition codes are irrelevent + take_branch bgt + + set_cc 0x09 ; condition codes are irrelevent + no_branch bgt + + set_cc 0x08 ; condition codes are irrelevent + no_branch bgt + + set_cc 0x07 ; condition codes are irrelevent + no_branch bgt + + set_cc 0x06 ; condition codes are irrelevent + no_branch bgt + + set_cc 0x05 ; condition codes are irrelevent + no_branch bgt + + set_cc 0x04 ; condition codes are irrelevent + no_branch bgt + + set_cc 0x03 ; condition codes are irrelevent + no_branch bgt + + set_cc 0x02 ; condition codes are irrelevent + no_branch bgt + + set_cc 0x01 ; condition codes are irrelevent + take_branch bgt + + set_cc 0x00 ; condition codes are irrelevent + take_branch bgt + + ; Test bgt:d label9 + set_cc 0x0f ; condition codes are irrelevent + no_branch_d bgt:d 0xf + + set_cc 0x0e ; condition codes are irrelevent + no_branch_d bgt:d 0xe + + set_cc 0x0d ; condition codes are irrelevent + no_branch_d bgt:d 0xd + + set_cc 0x0c ; condition codes are irrelevent + no_branch_d bgt:d 0xc + + set_cc 0x0b ; condition codes are irrelevent + take_branch_d bgt:d 0xb + + set_cc 0x0a ; condition codes are irrelevent + take_branch_d bgt:d 0xa + + set_cc 0x09 ; condition codes are irrelevent + no_branch_d bgt:d 0x9 + + set_cc 0x08 ; condition codes are irrelevent + no_branch_d bgt:d 0x8 + + set_cc 0x07 ; condition codes are irrelevent + no_branch_d bgt:d 0x7 + + set_cc 0x06 ; condition codes are irrelevent + no_branch_d bgt:d 0x6 + + set_cc 0x05 ; condition codes are irrelevent + no_branch_d bgt:d 0x5 + + set_cc 0x04 ; condition codes are irrelevent + no_branch_d bgt:d 0x4 + + set_cc 0x03 ; condition codes are irrelevent + no_branch_d bgt:d 0x3 + + set_cc 0x02 ; condition codes are irrelevent + no_branch_d bgt:d 0x2 + + set_cc 0x01 ; condition codes are irrelevent + take_branch_d bgt:d 0x1 + + set_cc 0x00 ; condition codes are irrelevent + take_branch_d bgt:d 0x0 + + pass diff --git a/sim/testsuite/sim/fr30/bhi.cgs b/sim/testsuite/sim/fr30/bhi.cgs new file mode 100644 index 00000000000..f5a15492063 --- /dev/null +++ b/sim/testsuite/sim/fr30/bhi.cgs @@ -0,0 +1,109 @@ +# fr30 testcase for bhi $label9 +# mach(): fr30 + + .include "testutils.inc" + + START + + .text + .global bhi +bhi: + ; Test bhi $label9 + set_cc 0x0f ; condition codes are irrelevent + no_branch bhi + + set_cc 0x0e ; condition codes are irrelevent + no_branch bhi + + set_cc 0x0d ; condition codes are irrelevent + no_branch bhi + + set_cc 0x0c ; condition codes are irrelevent + no_branch bhi + + set_cc 0x0b ; condition codes are irrelevent + no_branch bhi + + set_cc 0x0a ; condition codes are irrelevent + take_branch bhi + + set_cc 0x09 ; condition codes are irrelevent + no_branch bhi + + set_cc 0x08 ; condition codes are irrelevent + take_branch bhi + + set_cc 0x07 ; condition codes are irrelevent + no_branch bhi + + set_cc 0x06 ; condition codes are irrelevent + no_branch bhi + + set_cc 0x05 ; condition codes are irrelevent + no_branch bhi + + set_cc 0x04 ; condition codes are irrelevent + no_branch bhi + + set_cc 0x03 ; condition codes are irrelevent + no_branch bhi + + set_cc 0x02 ; condition codes are irrelevent + take_branch bhi + + set_cc 0x01 ; condition codes are irrelevent + no_branch bhi + + set_cc 0x00 ; condition codes are irrelevent + take_branch bhi + + ; Test bhi:d label9 + set_cc 0x0f ; condition codes are irrelevent + no_branch_d bhi:d 0xf + + set_cc 0x0e ; condition codes are irrelevent + no_branch_d bhi:d 0xe + + set_cc 0x0d ; condition codes are irrelevent + no_branch_d bhi:d 0xd + + set_cc 0x0c ; condition codes are irrelevent + no_branch_d bhi:d 0xc + + set_cc 0x0b ; condition codes are irrelevent + no_branch_d bhi:d 0xb + + set_cc 0x0a ; condition codes are irrelevent + take_branch_d bhi:d 0xa + + set_cc 0x09 ; condition codes are irrelevent + no_branch_d bhi:d 0x9 + + set_cc 0x08 ; condition codes are irrelevent + take_branch_d bhi:d 0x8 + + set_cc 0x07 ; condition codes are irrelevent + no_branch_d bhi:d 0x7 + + set_cc 0x06 ; condition codes are irrelevent + no_branch_d bhi:d 0x6 + + set_cc 0x05 ; condition codes are irrelevent + no_branch_d bhi:d 0x5 + + set_cc 0x04 ; condition codes are irrelevent + no_branch_d bhi:d 0x4 + + set_cc 0x03 ; condition codes are irrelevent + no_branch_d bhi:d 0x3 + + set_cc 0x02 ; condition codes are irrelevent + take_branch_d bhi:d 0x2 + + set_cc 0x01 ; condition codes are irrelevent + no_branch_d bhi:d 0x1 + + set_cc 0x00 ; condition codes are irrelevent + take_branch_d bhi:d 0x0 + + pass diff --git a/sim/testsuite/sim/fr30/ble.cgs b/sim/testsuite/sim/fr30/ble.cgs new file mode 100644 index 00000000000..1a33f783ce3 --- /dev/null +++ b/sim/testsuite/sim/fr30/ble.cgs @@ -0,0 +1,109 @@ +# fr30 testcase for ble $label9 +# mach(): fr30 + + .include "testutils.inc" + + START + + .text + .global ble +ble: + ; Test ble $label9 + set_cc 0x0f ; condition codes are irrelevent + take_branch ble + + set_cc 0x0e ; condition codes are irrelevent + take_branch ble + + set_cc 0x0d ; condition codes are irrelevent + take_branch ble + + set_cc 0x0c ; condition codes are irrelevent + take_branch ble + + set_cc 0x0b ; condition codes are irrelevent + no_branch ble + + set_cc 0x0a ; condition codes are irrelevent + no_branch ble + + set_cc 0x09 ; condition codes are irrelevent + take_branch ble + + set_cc 0x08 ; condition codes are irrelevent + take_branch ble + + set_cc 0x07 ; condition codes are irrelevent + take_branch ble + + set_cc 0x06 ; condition codes are irrelevent + take_branch ble + + set_cc 0x05 ; condition codes are irrelevent + take_branch ble + + set_cc 0x04 ; condition codes are irrelevent + take_branch ble + + set_cc 0x03 ; condition codes are irrelevent + take_branch ble + + set_cc 0x02 ; condition codes are irrelevent + take_branch ble + + set_cc 0x01 ; condition codes are irrelevent + no_branch ble + + set_cc 0x00 ; condition codes are irrelevent + no_branch ble + + ; Test ble:d label9 + set_cc 0x0f ; condition codes are irrelevent + take_branch_d ble:d 0xf + + set_cc 0x0e ; condition codes are irrelevent + take_branch_d ble:d 0xe + + set_cc 0x0d ; condition codes are irrelevent + take_branch_d ble:d 0xd + + set_cc 0x0c ; condition codes are irrelevent + take_branch_d ble:d 0xc + + set_cc 0x0b ; condition codes are irrelevent + no_branch_d ble:d 0xb + + set_cc 0x0a ; condition codes are irrelevent + no_branch_d ble:d 0xa + + set_cc 0x09 ; condition codes are irrelevent + take_branch_d ble:d 0x9 + + set_cc 0x08 ; condition codes are irrelevent + take_branch_d ble:d 0x8 + + set_cc 0x07 ; condition codes are irrelevent + take_branch_d ble:d 0x7 + + set_cc 0x06 ; condition codes are irrelevent + take_branch_d ble:d 0x6 + + set_cc 0x05 ; condition codes are irrelevent + take_branch_d ble:d 0x5 + + set_cc 0x04 ; condition codes are irrelevent + take_branch_d ble:d 0x4 + + set_cc 0x03 ; condition codes are irrelevent + take_branch_d ble:d 0x3 + + set_cc 0x02 ; condition codes are irrelevent + take_branch_d ble:d 0x2 + + set_cc 0x01 ; condition codes are irrelevent + no_branch_d ble:d 0x1 + + set_cc 0x00 ; condition codes are irrelevent + no_branch_d ble:d 0x0 + + pass diff --git a/sim/testsuite/sim/fr30/bls.cgs b/sim/testsuite/sim/fr30/bls.cgs new file mode 100644 index 00000000000..c0148b7b901 --- /dev/null +++ b/sim/testsuite/sim/fr30/bls.cgs @@ -0,0 +1,109 @@ +# fr30 testcase for bls $label9 +# mach(): fr30 + + .include "testutils.inc" + + START + + .text + .global bls +bls: + ; Test bls $label9 + set_cc 0x0f ; condition codes are irrelevent + take_branch bls + + set_cc 0x0e ; condition codes are irrelevent + take_branch bls + + set_cc 0x0d ; condition codes are irrelevent + take_branch bls + + set_cc 0x0c ; condition codes are irrelevent + take_branch bls + + set_cc 0x0b ; condition codes are irrelevent + take_branch bls + + set_cc 0x0a ; condition codes are irrelevent + no_branch bls + + set_cc 0x09 ; condition codes are irrelevent + take_branch bls + + set_cc 0x08 ; condition codes are irrelevent + no_branch bls + + set_cc 0x07 ; condition codes are irrelevent + take_branch bls + + set_cc 0x06 ; condition codes are irrelevent + take_branch bls + + set_cc 0x05 ; condition codes are irrelevent + take_branch bls + + set_cc 0x04 ; condition codes are irrelevent + take_branch bls + + set_cc 0x03 ; condition codes are irrelevent + take_branch bls + + set_cc 0x02 ; condition codes are irrelevent + no_branch bls + + set_cc 0x01 ; condition codes are irrelevent + take_branch bls + + set_cc 0x00 ; condition codes are irrelevent + no_branch bls + + ; Test bls:d label9 + set_cc 0x0f ; condition codes are irrelevent + take_branch_d bls:d 0xf + + set_cc 0x0e ; condition codes are irrelevent + take_branch_d bls:d 0xe + + set_cc 0x0d ; condition codes are irrelevent + take_branch_d bls:d 0xd + + set_cc 0x0c ; condition codes are irrelevent + take_branch_d bls:d 0xc + + set_cc 0x0b ; condition codes are irrelevent + take_branch_d bls:d 0xb + + set_cc 0x0a ; condition codes are irrelevent + no_branch_d bls:d 0xa + + set_cc 0x09 ; condition codes are irrelevent + take_branch_d bls:d 0x9 + + set_cc 0x08 ; condition codes are irrelevent + no_branch_d bls:d 0x8 + + set_cc 0x07 ; condition codes are irrelevent + take_branch_d bls:d 0x7 + + set_cc 0x06 ; condition codes are irrelevent + take_branch_d bls:d 0x6 + + set_cc 0x05 ; condition codes are irrelevent + take_branch_d bls:d 0x5 + + set_cc 0x04 ; condition codes are irrelevent + take_branch_d bls:d 0x4 + + set_cc 0x03 ; condition codes are irrelevent + take_branch_d bls:d 0x3 + + set_cc 0x02 ; condition codes are irrelevent + no_branch_d bls:d 0x2 + + set_cc 0x01 ; condition codes are irrelevent + take_branch_d bls:d 0x1 + + set_cc 0x00 ; condition codes are irrelevent + no_branch_d bls:d 0x0 + + pass diff --git a/sim/testsuite/sim/fr30/blt.cgs b/sim/testsuite/sim/fr30/blt.cgs new file mode 100644 index 00000000000..f7b6ff114bf --- /dev/null +++ b/sim/testsuite/sim/fr30/blt.cgs @@ -0,0 +1,109 @@ +# fr30 testcase for blt $label9 +# mach(): fr30 + + .include "testutils.inc" + + START + + .text + .global blt +blt: + ; Test blt $label9 + set_cc 0x0f ; condition codes are irrelevent + no_branch blt + + set_cc 0x0e ; condition codes are irrelevent + no_branch blt + + set_cc 0x0d ; condition codes are irrelevent + take_branch blt + + set_cc 0x0c ; condition codes are irrelevent + take_branch blt + + set_cc 0x0b ; condition codes are irrelevent + no_branch blt + + set_cc 0x0a ; condition codes are irrelevent + no_branch blt + + set_cc 0x09 ; condition codes are irrelevent + take_branch blt + + set_cc 0x08 ; condition codes are irrelevent + take_branch blt + + set_cc 0x07 ; condition codes are irrelevent + take_branch blt + + set_cc 0x06 ; condition codes are irrelevent + take_branch blt + + set_cc 0x05 ; condition codes are irrelevent + no_branch blt + + set_cc 0x04 ; condition codes are irrelevent + no_branch blt + + set_cc 0x03 ; condition codes are irrelevent + take_branch blt + + set_cc 0x02 ; condition codes are irrelevent + take_branch blt + + set_cc 0x01 ; condition codes are irrelevent + no_branch blt + + set_cc 0x00 ; condition codes are irrelevent + no_branch blt + + ; Test blt:d label9 + set_cc 0x0f ; condition codes are irrelevent + no_branch_d blt:d 0xf + + set_cc 0x0e ; condition codes are irrelevent + no_branch_d blt:d 0xe + + set_cc 0x0d ; condition codes are irrelevent + take_branch_d blt:d 0xd + + set_cc 0x0c ; condition codes are irrelevent + take_branch_d blt:d 0xc + + set_cc 0x0b ; condition codes are irrelevent + no_branch_d blt:d 0xb + + set_cc 0x0a ; condition codes are irrelevent + no_branch_d blt:d 0xa + + set_cc 0x09 ; condition codes are irrelevent + take_branch_d blt:d 0x9 + + set_cc 0x08 ; condition codes are irrelevent + take_branch_d blt:d 0x8 + + set_cc 0x07 ; condition codes are irrelevent + take_branch_d blt:d 0x7 + + set_cc 0x06 ; condition codes are irrelevent + take_branch_d blt:d 0x6 + + set_cc 0x05 ; condition codes are irrelevent + no_branch_d blt:d 0x5 + + set_cc 0x04 ; condition codes are irrelevent + no_branch_d blt:d 0x4 + + set_cc 0x03 ; condition codes are irrelevent + take_branch_d blt:d 0x3 + + set_cc 0x02 ; condition codes are irrelevent + take_branch_d blt:d 0x2 + + set_cc 0x01 ; condition codes are irrelevent + no_branch_d blt:d 0x1 + + set_cc 0x00 ; condition codes are irrelevent + no_branch_d blt:d 0x0 + + pass diff --git a/sim/testsuite/sim/fr30/bn.cgs b/sim/testsuite/sim/fr30/bn.cgs new file mode 100644 index 00000000000..45858fc97ee --- /dev/null +++ b/sim/testsuite/sim/fr30/bn.cgs @@ -0,0 +1,109 @@ +# fr30 testcase for bn $label9 +# mach(): fr30 + + .include "testutils.inc" + + START + + .text + .global bn +bn: + ; Test bn $label9 + set_cc 0x0f ; condition codes are irrelevent + take_branch bn + + set_cc 0x0e ; condition codes are irrelevent + take_branch bn + + set_cc 0x0d ; condition codes are irrelevent + take_branch bn + + set_cc 0x0c ; condition codes are irrelevent + take_branch bn + + set_cc 0x0b ; condition codes are irrelevent + take_branch bn + + set_cc 0x0a ; condition codes are irrelevent + take_branch bn + + set_cc 0x09 ; condition codes are irrelevent + take_branch bn + + set_cc 0x08 ; condition codes are irrelevent + take_branch bn + + set_cc 0x07 ; condition codes are irrelevent + no_branch bn + + set_cc 0x06 ; condition codes are irrelevent + no_branch bn + + set_cc 0x05 ; condition codes are irrelevent + no_branch bn + + set_cc 0x04 ; condition codes are irrelevent + no_branch bn + + set_cc 0x03 ; condition codes are irrelevent + no_branch bn + + set_cc 0x02 ; condition codes are irrelevent + no_branch bn + + set_cc 0x01 ; condition codes are irrelevent + no_branch bn + + set_cc 0x00 ; condition codes are irrelevent + no_branch bn + + ; Test bn:d label9 + set_cc 0x0f ; condition codes are irrelevent + take_branch_d bn:d 0xf + + set_cc 0x0e ; condition codes are irrelevent + take_branch_d bn:d 0xe + + set_cc 0x0d ; condition codes are irrelevent + take_branch_d bn:d 0xd + + set_cc 0x0c ; condition codes are irrelevent + take_branch_d bn:d 0xc + + set_cc 0x0b ; condition codes are irrelevent + take_branch_d bn:d 0xb + + set_cc 0x0a ; condition codes are irrelevent + take_branch_d bn:d 0xa + + set_cc 0x09 ; condition codes are irrelevent + take_branch_d bn:d 0x9 + + set_cc 0x08 ; condition codes are irrelevent + take_branch_d bn:d 0x8 + + set_cc 0x07 ; condition codes are irrelevent + no_branch_d bn:d 0x7 + + set_cc 0x06 ; condition codes are irrelevent + no_branch_d bn:d 0x6 + + set_cc 0x05 ; condition codes are irrelevent + no_branch_d bn:d 0x5 + + set_cc 0x04 ; condition codes are irrelevent + no_branch_d bn:d 0x4 + + set_cc 0x03 ; condition codes are irrelevent + no_branch_d bn:d 0x3 + + set_cc 0x02 ; condition codes are irrelevent + no_branch_d bn:d 0x2 + + set_cc 0x01 ; condition codes are irrelevent + no_branch_d bn:d 0x1 + + set_cc 0x00 ; condition codes are irrelevent + no_branch_d bn:d 0x0 + + pass diff --git a/sim/testsuite/sim/fr30/bnc.cgs b/sim/testsuite/sim/fr30/bnc.cgs new file mode 100644 index 00000000000..9968c43737c --- /dev/null +++ b/sim/testsuite/sim/fr30/bnc.cgs @@ -0,0 +1,109 @@ +# fr30 testcase for bnc $label9 +# mach(): fr30 + + .include "testutils.inc" + + START + + .text + .global bnc +bc: + ; Test bnc $label9 + set_cc 0x0f ; condition codes are irrelevent + no_branch bnc + + set_cc 0x0e ; condition codes are irrelevent + take_branch bnc + + set_cc 0x0d ; condition codes are irrelevent + no_branch bnc + + set_cc 0x0c ; condition codes are irrelevent + take_branch bnc + + set_cc 0x0b ; condition codes are irrelevent + no_branch bnc + + set_cc 0x0a ; condition codes are irrelevent + take_branch bnc + + set_cc 0x09 ; condition codes are irrelevent + no_branch bnc + + set_cc 0x08 ; condition codes are irrelevent + take_branch bnc + + set_cc 0x07 ; condition codes are irrelevent + no_branch bnc + + set_cc 0x06 ; condition codes are irrelevent + take_branch bnc + + set_cc 0x05 ; condition codes are irrelevent + no_branch bnc + + set_cc 0x04 ; condition codes are irrelevent + take_branch bnc + + set_cc 0x03 ; condition codes are irrelevent + no_branch bnc + + set_cc 0x02 ; condition codes are irrelevent + take_branch bnc + + set_cc 0x01 ; condition codes are irrelevent + no_branch bnc + + set_cc 0x00 ; condition codes are irrelevent + take_branch bnc + + ; Test bnc:d label9 + set_cc 0x0f ; condition codes are irrelevent + no_branch_d bnc:d 0xf + + set_cc 0x0e ; condition codes are irrelevent + take_branch_d bnc:d 0xe + + set_cc 0x0d ; condition codes are irrelevent + no_branch_d bnc:d 0xd + + set_cc 0x0c ; condition codes are irrelevent + take_branch_d bnc:d 0xc + + set_cc 0x0b ; condition codes are irrelevent + no_branch_d bnc:d 0xb + + set_cc 0x0a ; condition codes are irrelevent + take_branch_d bnc:d 0xa + + set_cc 0x09 ; condition codes are irrelevent + no_branch_d bnc:d 0x9 + + set_cc 0x08 ; condition codes are irrelevent + take_branch_d bnc:d 0x8 + + set_cc 0x07 ; condition codes are irrelevent + no_branch_d bnc:d 0x7 + + set_cc 0x06 ; condition codes are irrelevent + take_branch_d bnc:d 0x6 + + set_cc 0x05 ; condition codes are irrelevent + no_branch_d bnc:d 0x5 + + set_cc 0x04 ; condition codes are irrelevent + take_branch_d bnc:d 0x4 + + set_cc 0x03 ; condition codes are irrelevent + no_branch_d bnc:d 0x3 + + set_cc 0x02 ; condition codes are irrelevent + take_branch_d bnc:d 0x2 + + set_cc 0x01 ; condition codes are irrelevent + no_branch_d bnc:d 0x1 + + set_cc 0x00 ; condition codes are irrelevent + take_branch_d bnc:d 0x0 + + pass diff --git a/sim/testsuite/sim/fr30/bne.cgs b/sim/testsuite/sim/fr30/bne.cgs new file mode 100644 index 00000000000..58971de1326 --- /dev/null +++ b/sim/testsuite/sim/fr30/bne.cgs @@ -0,0 +1,109 @@ +# fr30 testcase for bne $label9 +# mach(): fr30 + + .include "testutils.inc" + + START + + .text + .global bne +bne: + ; Test bne $label9 + set_cc 0x0f ; condition codes are irrelevent + no_branch bne + + set_cc 0x0e ; condition codes are irrelevent + no_branch bne + + set_cc 0x0d ; condition codes are irrelevent + no_branch bne + + set_cc 0x0c ; condition codes are irrelevent + no_branch bne + + set_cc 0x0b ; condition codes are irrelevent + take_branch bne + + set_cc 0x0a ; condition codes are irrelevent + take_branch bne + + set_cc 0x09 ; condition codes are irrelevent + take_branch bne + + set_cc 0x08 ; condition codes are irrelevent + take_branch bne + + set_cc 0x07 ; condition codes are irrelevent + no_branch bne + + set_cc 0x06 ; condition codes are irrelevent + no_branch bne + + set_cc 0x05 ; condition codes are irrelevent + no_branch bne + + set_cc 0x04 ; condition codes are irrelevent + no_branch bne + + set_cc 0x03 ; condition codes are irrelevent + take_branch bne + + set_cc 0x02 ; condition codes are irrelevent + take_branch bne + + set_cc 0x01 ; condition codes are irrelevent + take_branch bne + + set_cc 0x00 ; condition codes are irrelevent + take_branch bne + + ; Test bne:d label9 + set_cc 0x0f ; condition codes are irrelevent + no_branch_d bne:d 0xf + + set_cc 0x0e ; condition codes are irrelevent + no_branch_d bne:d 0xe + + set_cc 0x0d ; condition codes are irrelevent + no_branch_d bne:d 0xd + + set_cc 0x0c ; condition codes are irrelevent + no_branch_d bne:d 0xc + + set_cc 0x0b ; condition codes are irrelevent + take_branch_d bne:d 0xb + + set_cc 0x0a ; condition codes are irrelevent + take_branch_d bne:d 0xa + + set_cc 0x09 ; condition codes are irrelevent + take_branch_d bne:d 0x9 + + set_cc 0x08 ; condition codes are irrelevent + take_branch_d bne:d 0x8 + + set_cc 0x07 ; condition codes are irrelevent + no_branch_d bne:d 0x7 + + set_cc 0x06 ; condition codes are irrelevent + no_branch_d bne:d 0x6 + + set_cc 0x05 ; condition codes are irrelevent + no_branch_d bne:d 0x5 + + set_cc 0x04 ; condition codes are irrelevent + no_branch_d bne:d 0x4 + + set_cc 0x03 ; condition codes are irrelevent + take_branch_d bne:d 0x3 + + set_cc 0x02 ; condition codes are irrelevent + take_branch_d bne:d 0x2 + + set_cc 0x01 ; condition codes are irrelevent + take_branch_d bne:d 0x1 + + set_cc 0x00 ; condition codes are irrelevent + take_branch_d bne:d 0x0 + + pass diff --git a/sim/testsuite/sim/fr30/bno.cgs b/sim/testsuite/sim/fr30/bno.cgs new file mode 100644 index 00000000000..faef9ba0380 --- /dev/null +++ b/sim/testsuite/sim/fr30/bno.cgs @@ -0,0 +1,109 @@ +# fr30 testcase for bno $label9 +# mach(): fr30 + + .include "testutils.inc" + + START + + .text + .global bno +bno: + ; Test bno $label9 + set_cc 0x0f ; condition codes are irrelevent + no_branch bno + + set_cc 0x0e ; condition codes are irrelevent + no_branch bno + + set_cc 0x0d ; condition codes are irrelevent + no_branch bno + + set_cc 0x0c ; condition codes are irrelevent + no_branch bno + + set_cc 0x0b ; condition codes are irrelevent + no_branch bno + + set_cc 0x0a ; condition codes are irrelevent + no_branch bno + + set_cc 0x09 ; condition codes are irrelevent + no_branch bno + + set_cc 0x08 ; condition codes are irrelevent + no_branch bno + + set_cc 0x07 ; condition codes are irrelevent + no_branch bno + + set_cc 0x06 ; condition codes are irrelevent + no_branch bno + + set_cc 0x05 ; condition codes are irrelevent + no_branch bno + + set_cc 0x04 ; condition codes are irrelevent + no_branch bno + + set_cc 0x03 ; condition codes are irrelevent + no_branch bno + + set_cc 0x02 ; condition codes are irrelevent + no_branch bno + + set_cc 0x01 ; condition codes are irrelevent + no_branch bno + + set_cc 0x00 ; condition codes are irrelevent + no_branch bno + + ; Test bno:d label9 + set_cc 0x0f ; condition codes are irrelevent + no_branch_d bno:d 0xf + + set_cc 0x0e ; condition codes are irrelevent + no_branch_d bno:d 0xe + + set_cc 0x0d ; condition codes are irrelevent + no_branch_d bno:d 0xd + + set_cc 0x0c ; condition codes are irrelevent + no_branch_d bno:d 0xc + + set_cc 0x0b ; condition codes are irrelevent + no_branch_d bno:d 0xb + + set_cc 0x0a ; condition codes are irrelevent + no_branch_d bno:d 0xa + + set_cc 0x09 ; condition codes are irrelevent + no_branch_d bno:d 0x9 + + set_cc 0x08 ; condition codes are irrelevent + no_branch_d bno:d 0x8 + + set_cc 0x07 ; condition codes are irrelevent + no_branch_d bno:d 0x7 + + set_cc 0x06 ; condition codes are irrelevent + no_branch_d bno:d 0x6 + + set_cc 0x05 ; condition codes are irrelevent + no_branch_d bno:d 0x5 + + set_cc 0x04 ; condition codes are irrelevent + no_branch_d bno:d 0x4 + + set_cc 0x03 ; condition codes are irrelevent + no_branch_d bno:d 0x3 + + set_cc 0x02 ; condition codes are irrelevent + no_branch_d bno:d 0x2 + + set_cc 0x01 ; condition codes are irrelevent + no_branch_d bno:d 0x1 + + set_cc 0x00 ; condition codes are irrelevent + no_branch_d bno:d 0x0 + + pass diff --git a/sim/testsuite/sim/fr30/bnv.cgs b/sim/testsuite/sim/fr30/bnv.cgs new file mode 100644 index 00000000000..7615abd6c7d --- /dev/null +++ b/sim/testsuite/sim/fr30/bnv.cgs @@ -0,0 +1,109 @@ +# fr30 testcase for bnv $label9 +# mach(): fr30 + + .include "testutils.inc" + + START + + .text + .global bnv +bnv: + ; Test bnv $label9 + set_cc 0x0f ; condition codes are irrelevent + no_branch bnv + + set_cc 0x0e ; condition codes are irrelevent + no_branch bnv + + set_cc 0x0d ; condition codes are irrelevent + take_branch bnv + + set_cc 0x0c ; condition codes are irrelevent + take_branch bnv + + set_cc 0x0b ; condition codes are irrelevent + no_branch bnv + + set_cc 0x0a ; condition codes are irrelevent + no_branch bnv + + set_cc 0x09 ; condition codes are irrelevent + take_branch bnv + + set_cc 0x08 ; condition codes are irrelevent + take_branch bnv + + set_cc 0x07 ; condition codes are irrelevent + no_branch bnv + + set_cc 0x06 ; condition codes are irrelevent + no_branch bnv + + set_cc 0x05 ; condition codes are irrelevent + take_branch bnv + + set_cc 0x04 ; condition codes are irrelevent + take_branch bnv + + set_cc 0x03 ; condition codes are irrelevent + no_branch bnv + + set_cc 0x02 ; condition codes are irrelevent + no_branch bnv + + set_cc 0x01 ; condition codes are irrelevent + take_branch bnv + + set_cc 0x00 ; condition codes are irrelevent + take_branch bnv + + ; Test bnv:d label9 + set_cc 0x0f ; condition codes are irrelevent + no_branch_d bnv:d 0xf + + set_cc 0x0e ; condition codes are irrelevent + no_branch_d bnv:d 0xe + + set_cc 0x0d ; condition codes are irrelevent + take_branch_d bnv:d 0xd + + set_cc 0x0c ; condition codes are irrelevent + take_branch_d bnv:d 0xc + + set_cc 0x0b ; condition codes are irrelevent + no_branch_d bnv:d 0xb + + set_cc 0x0a ; condition codes are irrelevent + no_branch_d bnv:d 0xa + + set_cc 0x09 ; condition codes are irrelevent + take_branch_d bnv:d 0x9 + + set_cc 0x08 ; condition codes are irrelevent + take_branch_d bnv:d 0x8 + + set_cc 0x07 ; condition codes are irrelevent + no_branch_d bnv:d 0x7 + + set_cc 0x06 ; condition codes are irrelevent + no_branch_d bnv:d 0x6 + + set_cc 0x05 ; condition codes are irrelevent + take_branch_d bnv:d 0x5 + + set_cc 0x04 ; condition codes are irrelevent + take_branch_d bnv:d 0x4 + + set_cc 0x03 ; condition codes are irrelevent + no_branch_d bnv:d 0x3 + + set_cc 0x02 ; condition codes are irrelevent + no_branch_d bnv:d 0x2 + + set_cc 0x01 ; condition codes are irrelevent + take_branch_d bnv:d 0x1 + + set_cc 0x00 ; condition codes are irrelevent + take_branch_d bnv:d 0x0 + + pass diff --git a/sim/testsuite/sim/fr30/borh.cgs b/sim/testsuite/sim/fr30/borh.cgs new file mode 100644 index 00000000000..039f18a37e2 --- /dev/null +++ b/sim/testsuite/sim/fr30/borh.cgs @@ -0,0 +1,30 @@ +# fr30 testcase for borh $Rj,@$Ri +# mach(): fr30 + + .include "testutils.inc" + + START + + .text + .global borh +borh: + ; Test borh $Rj,@$Ri + mvi_h_mem 0x55555555,sp + set_cc 0x0f ; Condition codes should not change + borh 0x0a,@sp + test_cc 1 1 1 1 + test_h_mem 0xf5555555,sp + + mvi_h_mem 0x0fffffff,sp + set_cc 0x04 ; Condition codes should not change + borh 0x00,@sp + test_cc 0 1 0 0 + test_h_mem 0x0fffffff,sp + + mvi_h_mem 0xceadbeef,sp + set_cc 0x09 ; Condition codes should not change + borh 0x01,@sp + test_cc 1 0 0 1 + test_h_mem 0xdeadbeef,sp + + pass diff --git a/sim/testsuite/sim/fr30/borl.cgs b/sim/testsuite/sim/fr30/borl.cgs new file mode 100644 index 00000000000..beb2bbbaa2d --- /dev/null +++ b/sim/testsuite/sim/fr30/borl.cgs @@ -0,0 +1,30 @@ +# fr30 testcase for borl $Rj,@$Ri +# mach(): fr30 + + .include "testutils.inc" + + START + + .text + .global borl +borl: + ; Test borl $Rj,@$Ri + mvi_h_mem 0x55555555,sp + set_cc 0x0f ; Condition codes should not change + borl 0x0a,@sp + test_cc 1 1 1 1 + test_h_mem 0x5f555555,sp + + mvi_h_mem 0xf0ffffff,sp + set_cc 0x04 ; Condition codes should not change + borl 0x00,@sp + test_cc 0 1 0 0 + test_h_mem 0xf0ffffff,sp + + mvi_h_mem 0xdcadbeef,sp + set_cc 0x09 ; Condition codes should not change + borl 0x02,@sp + test_cc 1 0 0 1 + test_h_mem 0xdeadbeef,sp + + pass diff --git a/sim/testsuite/sim/fr30/bp.cgs b/sim/testsuite/sim/fr30/bp.cgs new file mode 100644 index 00000000000..375328305e0 --- /dev/null +++ b/sim/testsuite/sim/fr30/bp.cgs @@ -0,0 +1,109 @@ +# fr30 testcase for bp $label9 +# mach(): fr30 + + .include "testutils.inc" + + START + + .text + .global bp +bp: + ; Test bp $label9 + set_cc 0x0f ; condition codes are irrelevent + no_branch bp + + set_cc 0x0e ; condition codes are irrelevent + no_branch bp + + set_cc 0x0d ; condition codes are irrelevent + no_branch bp + + set_cc 0x0c ; condition codes are irrelevent + no_branch bp + + set_cc 0x0b ; condition codes are irrelevent + no_branch bp + + set_cc 0x0a ; condition codes are irrelevent + no_branch bp + + set_cc 0x09 ; condition codes are irrelevent + no_branch bp + + set_cc 0x08 ; condition codes are irrelevent + no_branch bp + + set_cc 0x07 ; condition codes are irrelevent + take_branch bp + + set_cc 0x06 ; condition codes are irrelevent + take_branch bp + + set_cc 0x05 ; condition codes are irrelevent + take_branch bp + + set_cc 0x04 ; condition codes are irrelevent + take_branch bp + + set_cc 0x03 ; condition codes are irrelevent + take_branch bp + + set_cc 0x02 ; condition codes are irrelevent + take_branch bp + + set_cc 0x01 ; condition codes are irrelevent + take_branch bp + + set_cc 0x00 ; condition codes are irrelevent + take_branch bp + + ; Test bp:d label9 + set_cc 0x0f ; condition codes are irrelevent + no_branch_d bp:d 0xf + + set_cc 0x0e ; condition codes are irrelevent + no_branch_d bp:d 0xe + + set_cc 0x0d ; condition codes are irrelevent + no_branch_d bp:d 0xd + + set_cc 0x0c ; condition codes are irrelevent + no_branch_d bp:d 0xc + + set_cc 0x0b ; condition codes are irrelevent + no_branch_d bp:d 0xb + + set_cc 0x0a ; condition codes are irrelevent + no_branch_d bp:d 0xa + + set_cc 0x09 ; condition codes are irrelevent + no_branch_d bp:d 0x9 + + set_cc 0x08 ; condition codes are irrelevent + no_branch_d bp:d 0x8 + + set_cc 0x07 ; condition codes are irrelevent + take_branch_d bp:d 0x7 + + set_cc 0x06 ; condition codes are irrelevent + take_branch_d bp:d 0x6 + + set_cc 0x05 ; condition codes are irrelevent + take_branch_d bp:d 0x5 + + set_cc 0x04 ; condition codes are irrelevent + take_branch_d bp:d 0x4 + + set_cc 0x03 ; condition codes are irrelevent + take_branch_d bp:d 0x3 + + set_cc 0x02 ; condition codes are irrelevent + take_branch_d bp:d 0x2 + + set_cc 0x01 ; condition codes are irrelevent + take_branch_d bp:d 0x1 + + set_cc 0x00 ; condition codes are irrelevent + take_branch_d bp:d 0x0 + + pass diff --git a/sim/testsuite/sim/fr30/bra.cgs b/sim/testsuite/sim/fr30/bra.cgs new file mode 100644 index 00000000000..3732f74a3ed --- /dev/null +++ b/sim/testsuite/sim/fr30/bra.cgs @@ -0,0 +1,109 @@ +# fr30 testcase for bra $label9 +# mach(): fr30 + + .include "testutils.inc" + + START + + .text + .global bra +bra: + ; Test bra $label9 + set_cc 0x0f ; condition codes are irrelevent + take_branch bra + + set_cc 0x0e ; condition codes are irrelevent + take_branch bra + + set_cc 0x0d ; condition codes are irrelevent + take_branch bra + + set_cc 0x0c ; condition codes are irrelevent + take_branch bra + + set_cc 0x0b ; condition codes are irrelevent + take_branch bra + + set_cc 0x0a ; condition codes are irrelevent + take_branch bra + + set_cc 0x09 ; condition codes are irrelevent + take_branch bra + + set_cc 0x08 ; condition codes are irrelevent + take_branch bra + + set_cc 0x07 ; condition codes are irrelevent + take_branch bra + + set_cc 0x06 ; condition codes are irrelevent + take_branch bra + + set_cc 0x05 ; condition codes are irrelevent + take_branch bra + + set_cc 0x04 ; condition codes are irrelevent + take_branch bra + + set_cc 0x03 ; condition codes are irrelevent + take_branch bra + + set_cc 0x02 ; condition codes are irrelevent + take_branch bra + + set_cc 0x01 ; condition codes are irrelevent + take_branch bra + + set_cc 0x00 ; condition codes are irrelevent + take_branch bra + + ; Test bra:d label9 + set_cc 0x0f ; condition codes are irrelevent + take_branch_d bra:d 0xf + + set_cc 0x0e ; condition codes are irrelevent + take_branch_d bra:d 0xe + + set_cc 0x0d ; condition codes are irrelevent + take_branch_d bra:d 0xd + + set_cc 0x0c ; condition codes are irrelevent + take_branch_d bra:d 0xc + + set_cc 0x0b ; condition codes are irrelevent + take_branch_d bra:d 0xb + + set_cc 0x0a ; condition codes are irrelevent + take_branch_d bra:d 0xa + + set_cc 0x09 ; condition codes are irrelevent + take_branch_d bra:d 0x9 + + set_cc 0x08 ; condition codes are irrelevent + take_branch_d bra:d 0x8 + + set_cc 0x07 ; condition codes are irrelevent + take_branch_d bra:d 0x7 + + set_cc 0x06 ; condition codes are irrelevent + take_branch_d bra:d 0x6 + + set_cc 0x05 ; condition codes are irrelevent + take_branch_d bra:d 0x5 + + set_cc 0x04 ; condition codes are irrelevent + take_branch_d bra:d 0x4 + + set_cc 0x03 ; condition codes are irrelevent + take_branch_d bra:d 0x3 + + set_cc 0x02 ; condition codes are irrelevent + take_branch_d bra:d 0x2 + + set_cc 0x01 ; condition codes are irrelevent + take_branch_d bra:d 0x1 + + set_cc 0x00 ; condition codes are irrelevent + take_branch_d bra:d 0x0 + + pass diff --git a/sim/testsuite/sim/fr30/btsth.cgs b/sim/testsuite/sim/fr30/btsth.cgs new file mode 100644 index 00000000000..2897c340555 --- /dev/null +++ b/sim/testsuite/sim/fr30/btsth.cgs @@ -0,0 +1,30 @@ +# fr30 testcase for btsth $Rj,@$Ri +# mach(): fr30 + + .include "testutils.inc" + + START + + .text + .global btsth +btsth: + ; Test btsth $Rj,@$Ri + mvi_h_mem 0x55555555,sp + set_cc 0x0b ; Set mask opposite of expected + btsth 0x0a,@sp + test_cc 0 1 1 1 + test_h_mem 0x55555555,sp + + mvi_h_mem 0xffffffff,sp + set_cc 0x04 ; Set mask opposite of expected + btsth 0x0a,@sp + test_cc 1 0 0 0 + test_h_mem 0xffffffff,sp + + mvi_h_mem 0xe5ffffff,sp + set_cc 0x0e ; Set mask opposite of expected + btsth 0x07,@sp + test_cc 0 0 1 0 + test_h_mem 0xe5ffffff,sp + + pass diff --git a/sim/testsuite/sim/fr30/btstl.cgs b/sim/testsuite/sim/fr30/btstl.cgs new file mode 100644 index 00000000000..cef5a927190 --- /dev/null +++ b/sim/testsuite/sim/fr30/btstl.cgs @@ -0,0 +1,30 @@ +# fr30 testcase for btstl $Rj,@$Ri +# mach(): fr30 + + .include "testutils.inc" + + START + + .text + .global btstl +btstl: + ; Test btstl $Rj,@$Ri + mvi_h_mem 0x55555555,sp + set_cc 0x0b ; Set mask opposite of expected + btstl 0x0a,@sp + test_cc 0 1 1 1 + test_h_mem 0x55555555,sp + + mvi_h_mem 0xffffffff,sp + set_cc 0x0c ; Set mask opposite of expected + btstl 0x0a,@sp + test_cc 0 0 0 0 + test_h_mem 0xffffffff,sp + + mvi_h_mem 0x5effffff,sp + set_cc 0x0e ; Set mask opposite of expected + btstl 0x07,@sp + test_cc 0 0 1 0 + test_h_mem 0x5effffff,sp + + pass diff --git a/sim/testsuite/sim/fr30/bv.cgs b/sim/testsuite/sim/fr30/bv.cgs new file mode 100644 index 00000000000..68cb9acf165 --- /dev/null +++ b/sim/testsuite/sim/fr30/bv.cgs @@ -0,0 +1,109 @@ +# fr30 testcase for bv $label9 +# mach(): fr30 + + .include "testutils.inc" + + START + + .text + .global bv +bv: + ; Test bv $label9 + set_cc 0x0f ; condition codes are irrelevent + take_branch bv + + set_cc 0x0e ; condition codes are irrelevent + take_branch bv + + set_cc 0x0d ; condition codes are irrelevent + no_branch bv + + set_cc 0x0c ; condition codes are irrelevent + no_branch bv + + set_cc 0x0b ; condition codes are irrelevent + take_branch bv + + set_cc 0x0a ; condition codes are irrelevent + take_branch bv + + set_cc 0x09 ; condition codes are irrelevent + no_branch bv + + set_cc 0x08 ; condition codes are irrelevent + no_branch bv + + set_cc 0x07 ; condition codes are irrelevent + take_branch bv + + set_cc 0x06 ; condition codes are irrelevent + take_branch bv + + set_cc 0x05 ; condition codes are irrelevent + no_branch bv + + set_cc 0x04 ; condition codes are irrelevent + no_branch bv + + set_cc 0x03 ; condition codes are irrelevent + take_branch bv + + set_cc 0x02 ; condition codes are irrelevent + take_branch bv + + set_cc 0x01 ; condition codes are irrelevent + no_branch bv + + set_cc 0x00 ; condition codes are irrelevent + no_branch bv + + ; Test bv:d label9 + set_cc 0x0f ; condition codes are irrelevent + take_branch_d bv:d 0xf + + set_cc 0x0e ; condition codes are irrelevent + take_branch_d bv:d 0xe + + set_cc 0x0d ; condition codes are irrelevent + no_branch_d bv:d 0xd + + set_cc 0x0c ; condition codes are irrelevent + no_branch_d bv:d 0xc + + set_cc 0x0b ; condition codes are irrelevent + take_branch_d bv:d 0xb + + set_cc 0x0a ; condition codes are irrelevent + take_branch_d bv:d 0xa + + set_cc 0x09 ; condition codes are irrelevent + no_branch_d bv:d 0x9 + + set_cc 0x08 ; condition codes are irrelevent + no_branch_d bv:d 0x8 + + set_cc 0x07 ; condition codes are irrelevent + take_branch_d bv:d 0x7 + + set_cc 0x06 ; condition codes are irrelevent + take_branch_d bv:d 0x6 + + set_cc 0x05 ; condition codes are irrelevent + no_branch_d bv:d 0x5 + + set_cc 0x04 ; condition codes are irrelevent + no_branch_d bv:d 0x4 + + set_cc 0x03 ; condition codes are irrelevent + take_branch_d bv:d 0x3 + + set_cc 0x02 ; condition codes are irrelevent + take_branch_d bv:d 0x2 + + set_cc 0x01 ; condition codes are irrelevent + no_branch_d bv:d 0x1 + + set_cc 0x00 ; condition codes are irrelevent + no_branch_d bv:d 0x0 + + pass diff --git a/sim/testsuite/sim/fr30/call.cgs b/sim/testsuite/sim/fr30/call.cgs new file mode 100644 index 00000000000..413840ed350 --- /dev/null +++ b/sim/testsuite/sim/fr30/call.cgs @@ -0,0 +1,69 @@ +# fr30 testcase for call @$Ri +# mach(): fr30 + + .include "testutils.inc" + + START + + .text + .global call + + ; Test call $Ri + mvi_h_gr 0xdeadbeef,r9 + mvi_h_gr #func1,r0 + set_cc 0x0f ; condition codes shouldn't change +call1: + call @r0 + test_h_gr 0xbeefdead,r9 + pass + +func1: + test_cc 1 1 1 1 + mvi_h_gr #call1,r7 + inci_h_gr 2,r7 + testr_h_dr r7,rp + save_rp + + mvi_h_gr #func2,r0 + set_cc 0x0f ; condition codes shouldn't change +call2: + call:d @r0 + ldi:8 1,r0 ; Must assume this works + restore_rp + ret +func2: + test_cc 1 1 1 1 + mvi_h_gr #call2,r7 + inci_h_gr 4,r7 + testr_h_dr r7,rp + testr_h_gr 1,r0 + save_rp + + set_cc 0x0f ; condition codes shouldn't change +call3: + call func3 + restore_rp + ret +func3: + test_cc 1 1 1 1 + mvi_h_gr #call3,r7 + inci_h_gr 2,r7 + testr_h_dr r7,rp + save_rp + + set_cc 0x0f ; condition codes shouldn't change +call4: + call:d func4 + ldi:8 1,r0 ; Must assume this works + restore_rp + ret +func4: + test_cc 1 1 1 1 + mvi_h_gr #call4,r7 + inci_h_gr 4,r7 + testr_h_dr r7,rp + testr_h_gr 1,r0 + mvi_h_gr 0xbeefdead,r9 + ret + + fail diff --git a/sim/testsuite/sim/fr30/cmp.cgs b/sim/testsuite/sim/fr30/cmp.cgs new file mode 100644 index 00000000000..7bfbbf8f1c9 --- /dev/null +++ b/sim/testsuite/sim/fr30/cmp.cgs @@ -0,0 +1,53 @@ +# fr30 testcase for cmp $Rj,$Ri, cmp $u4,$Ri +# mach(): fr30 + + .include "testutils.inc" + + START + + .text + .global cmp +cmp: + ; Test cmp $Rj,$Ri + mvi_h_gr 1,r7 + mvi_h_gr 2,r8 + set_cc 0x0f ; Set mask opposite of expected + cmp r7,r8 + test_cc 0 0 0 0 + + mvi_h_gr 1,r7 + mvi_h_gr 0x80000000,r8 + set_cc 0x0d ; Set mask opposite of expected + cmp r7,r8 + test_cc 0 0 1 0 + + set_cc 0x0b ; Set mask opposite of expected + cmp r8,r8 + test_cc 0 1 0 0 + + mvi_h_gr 0,r8 + set_cc 0x06 ; Set mask opposite of expected + cmp r7,r8 + test_cc 1 0 0 1 + + ; Test cmp $u4,$Ri + mvi_h_gr 2,r8 + set_cc 0x0f ; Set mask opposite of expected + cmp 1,r8 + test_cc 0 0 0 0 + + mvi_h_gr 0x80000000,r8 + set_cc 0x0d ; Set mask opposite of expected + cmp 1,r8 + test_cc 0 0 1 0 + + mvi_h_gr 0,r8 + set_cc 0x0b ; Set mask opposite of expected + cmp 0,r8 + test_cc 0 1 0 0 + + set_cc 0x06 ; Set mask opposite of expected + cmp 15,r8 + test_cc 1 0 0 1 + + pass diff --git a/sim/testsuite/sim/fr30/cmp2.cgs b/sim/testsuite/sim/fr30/cmp2.cgs new file mode 100644 index 00000000000..7ba62013cad --- /dev/null +++ b/sim/testsuite/sim/fr30/cmp2.cgs @@ -0,0 +1,27 @@ +# fr30 testcase for cmp2 $u4,$Ri +# mach(): fr30 + + .include "testutils.inc" + + START + + .text + .global cmp2 +cmp2: + ; Test cmp2 $u4,$Ri + mvi_h_gr 2,r8 + set_cc 0x0e ; Set mask opposite of expected + cmp2 -1,r8 + test_cc 0 0 0 1 + + mvi_h_gr 0x7ffffffe,r8 + set_cc 0x04 ; Set mask opposite of expected + cmp2 -2,r8 + test_cc 1 0 1 1 + + mvi_h_gr -16,r8 + set_cc 0x0b ; Set mask opposite of expected + cmp2 -16,r8 + test_cc 0 1 0 0 + + pass diff --git a/sim/testsuite/sim/fr30/copld.cgs b/sim/testsuite/sim/fr30/copld.cgs new file mode 100644 index 00000000000..e0ababb0e85 --- /dev/null +++ b/sim/testsuite/sim/fr30/copld.cgs @@ -0,0 +1,21 @@ +# fr30 testcase for copld $u4,$cc,$Rj,CRi +# mach(): fr30 + + .include "testutils.inc" + + START + + .text + .global copld +copld: + ; Test copld copld $u4,$cc,$Rj,CRi + ; The current implementation is a noop + set_cc 0x0f ; Condition codes are irrelevent + copld 0,0,r0,cr15 + test_cc 1 1 1 1 + + set_cc 0x0e ; Condition codes are irrelevent + copld 15,255,r15,cr0 + test_cc 1 1 1 0 + + pass diff --git a/sim/testsuite/sim/fr30/copop.cgs b/sim/testsuite/sim/fr30/copop.cgs new file mode 100644 index 00000000000..b0afd77005b --- /dev/null +++ b/sim/testsuite/sim/fr30/copop.cgs @@ -0,0 +1,21 @@ +# fr30 testcase for copop $u4,$cc,$CRj,CRi +# mach(): fr30 + + .include "testutils.inc" + + START + + .text + .global copop +copop: + ; Test copop copop $u4,$cc,$CRj,CRi + ; The current implementation is a noop + set_cc 0x0f ; Condition codes are irrelevent + copop 0,0,cr0,cr15 + test_cc 1 1 1 1 + + set_cc 0x0e ; Condition codes are irrelevent + copop 15,255,cr0,cr15 + test_cc 1 1 1 0 + + pass diff --git a/sim/testsuite/sim/fr30/copst.cgs b/sim/testsuite/sim/fr30/copst.cgs new file mode 100644 index 00000000000..00120b2096c --- /dev/null +++ b/sim/testsuite/sim/fr30/copst.cgs @@ -0,0 +1,21 @@ +# fr30 testcase for copst $u4,$cc,$CRj,Ri +# mach(): fr30 + + .include "testutils.inc" + + START + + .text + .global copst +copst: + ; Test copst copst $u4,$cc,$CRj,Ri + ; The current implementation is a noop + set_cc 0x0f ; Condition codes are irrelevent + copst 0,0,cr0,r15 + test_cc 1 1 1 1 + + set_cc 0x0e ; Condition codes are irrelevent + copst 15,255,cr15,r0 + test_cc 1 1 1 0 + + pass diff --git a/sim/testsuite/sim/fr30/copsv.cgs b/sim/testsuite/sim/fr30/copsv.cgs new file mode 100644 index 00000000000..e00a4f5315c --- /dev/null +++ b/sim/testsuite/sim/fr30/copsv.cgs @@ -0,0 +1,21 @@ +# fr30 testcase for copsv $u4,$cc,$CRj,Ri +# mach(): fr30 + + .include "testutils.inc" + + START + + .text + .global copsv +copsv: + ; Test copsv copsv $u4,$cc,$CRj,Ri + ; The current implementation is a noop + set_cc 0x0f ; Condition codes are irrelevent + copsv 0,0,cr0,r15 + test_cc 1 1 1 1 + + set_cc 0x0e ; Condition codes are irrelevent + copsv 15,255,cr15,r0 + test_cc 1 1 1 0 + + pass diff --git a/sim/testsuite/sim/fr30/div.ms b/sim/testsuite/sim/fr30/div.ms new file mode 100644 index 00000000000..7e3aaf20ae0 --- /dev/null +++ b/sim/testsuite/sim/fr30/div.ms @@ -0,0 +1,176 @@ +# fr30 testcase for division +# mach(): fr30 + + .include "testutils.inc" + + START + + .text + .global div +div: + ; simple division 12 / 3 + mvi_h_gr 0x00000003,r2 + mvi_h_dr 0xdeadbeef,mdh + mvi_h_dr 0x0000000c,mdl + div0s r2 + div1 r2 + div1 r2 + div1 r2 + div1 r2 + div1 r2 + div1 r2 + div1 r2 + div1 r2 + div1 r2 + div1 r2 + div1 r2 + div1 r2 + div1 r2 + div1 r2 + div1 r2 + div1 r2 + div1 r2 + div1 r2 + div1 r2 + div1 r2 + div1 r2 + div1 r2 + div1 r2 + div1 r2 + div1 r2 + div1 r2 + div1 r2 + div1 r2 + div1 r2 + div1 r2 + div1 r2 + div1 r2 + div2 r2 + div3 + div4s + test_h_gr 0x00000003,r2 + test_h_dr 0x00000000,mdh + test_h_dr 0x00000004,mdl + test_dbits 0x0 + + ; example 1 from div0s the manual + mvi_h_gr 0x01234567,r2 + mvi_h_dr 0xdeadbeef,mdh + mvi_h_dr 0xfedcba98,mdl + div0s r2 + div1 r2 + div1 r2 + div1 r2 + div1 r2 + div1 r2 + div1 r2 + div1 r2 + div1 r2 + div1 r2 + div1 r2 + div1 r2 + div1 r2 + div1 r2 + div1 r2 + div1 r2 + div1 r2 + div1 r2 + div1 r2 + div1 r2 + div1 r2 + div1 r2 + div1 r2 + div1 r2 + div1 r2 + div1 r2 + div1 r2 + div1 r2 + div1 r2 + div1 r2 + div1 r2 + div1 r2 + div1 r2 + div2 r2 + div3 + div4s + test_h_gr 0x01234567,r2 + test_h_dr 0xffffffff,mdh + test_h_dr 0xffffffff,mdl + test_dbits 0x3 + + ; example 2 from div0s the manual + mvi_h_dr 0xdeadbeef,mdh + mvi_h_dr 0xfedcba98,mdl + mvi_h_gr 0x1234567,r2 + mvi_h_gr 1,r0 + mvi_h_gr 32,r1 + div0s r2 +loop1: sub r0,r1 + bne:d loop1 + div1 r2 + div2 r2 + div3 + div4s + test_h_gr 0x01234567,r2 + test_h_dr 0xffffffff,mdh + test_h_dr 0xffffffff,mdl + test_dbits 0x3 + + ; example 1 from div0u in the manual + mvi_h_gr 0x01234567,r2 + mvi_h_dr 0xdeadbeef,mdh + mvi_h_dr 0xfedcba98,mdl + div0u r2 + div1 r2 + div1 r2 + div1 r2 + div1 r2 + div1 r2 + div1 r2 + div1 r2 + div1 r2 + div1 r2 + div1 r2 + div1 r2 + div1 r2 + div1 r2 + div1 r2 + div1 r2 + div1 r2 + div1 r2 + div1 r2 + div1 r2 + div1 r2 + div1 r2 + div1 r2 + div1 r2 + div1 r2 + div1 r2 + div1 r2 + div1 r2 + div1 r2 + div1 r2 + div1 r2 + div1 r2 + div1 r2 + test_h_gr 0x01234567,r2 + test_h_dr 0x00000078,mdh + test_h_dr 0x000000e0,mdl + test_dbits 0x0 + + ; example 2 from div0u in the manual + mvi_h_dr 0xdeadbeef,mdh + mvi_h_dr 0xfedcba98,mdl + mvi_h_gr 0x1234567,r2 + mvi_h_gr 1,r0 + mvi_h_gr 32,r1 + div0u r2 +loop2: sub r0,r1 + bne:d loop2 + div1 r2 + test_h_gr 0x01234567,r2 + test_h_dr 0x00000078,mdh + test_h_dr 0x000000e0,mdl + test_dbits 0x0 + + pass diff --git a/sim/testsuite/sim/fr30/div0s.cgs b/sim/testsuite/sim/fr30/div0s.cgs new file mode 100644 index 00000000000..84d76c4bfb9 --- /dev/null +++ b/sim/testsuite/sim/fr30/div0s.cgs @@ -0,0 +1,64 @@ +# fr30 testcase for div0s $Ri +# mach(): fr30 + + .include "testutils.inc" + + START + + .text + .global div0s +div0s: + ; Test div0s $Rj,$Ri + ; example from the manual - negative dividend + mvi_h_gr 0x0fffffff,r2 + mvi_h_dr 0x00000000,mdh + mvi_h_dr 0xfffffff0,mdl + set_dbits 0x0 ; Set opposite of expected + set_cc 0x0f ; Condition codes should not change + div0s r2 + test_cc 1 1 1 1 + test_h_gr 0x0fffffff,r2 + test_h_dr 0xffffffff,mdh + test_h_dr 0xfffffff0,mdl + test_dbits 0x3 + + ; negative divisor + mvi_h_gr 0xffffffff,r2 + mvi_h_dr 0xffffffff,mdh + mvi_h_dr 0x7fffffff,mdl + set_dbits 0x1 ; Set opposite of expected + set_cc 0x0f ; Condition codes should not change + div0s r2 + test_cc 1 1 1 1 + test_h_gr 0xffffffff,r2 + test_h_dr 0x00000000,mdh + test_h_dr 0x7fffffff,mdl + test_dbits 0x2 + + ; Both sign bits 0 + mvi_h_gr 0x0fffffff,r2 + mvi_h_dr 0xffffffff,mdh + mvi_h_dr 0x7ffffff0,mdl + set_dbits 0x3 ; Set opposite of expected + set_cc 0x0f ; Condition codes should not change + div0s r2 + test_cc 1 1 1 1 + test_h_gr 0x0fffffff,r2 + test_h_dr 0x00000000,mdh + test_h_dr 0x7ffffff0,mdl + test_dbits 0x0 + + ; Both sign bits 1 + mvi_h_gr 0xffffffff,r2 + mvi_h_dr 0x00000000,mdh + mvi_h_dr 0xffffffff,mdl + set_dbits 0x2 ; Set opposite of expected + set_cc 0x0f ; Condition codes should not change + div0s r2 + test_cc 1 1 1 1 + test_h_gr 0xffffffff,r2 + test_h_dr 0xffffffff,mdh + test_h_dr 0xffffffff,mdl + test_dbits 0x1 + + pass diff --git a/sim/testsuite/sim/fr30/div0u.cgs b/sim/testsuite/sim/fr30/div0u.cgs new file mode 100644 index 00000000000..8fd84a6c22b --- /dev/null +++ b/sim/testsuite/sim/fr30/div0u.cgs @@ -0,0 +1,25 @@ +# fr30 testcase for div0u $Ri +# mach(): fr30 + + .include "testutils.inc" + + START + + .text + .global div0u +div0u: + ; Test div0u $Rj,$Ri + ; operand register has no effect + mvi_h_gr 0xdeadbeef,r2 + mvi_h_dr 0xdeadbeef,mdh + mvi_h_dr 0x0ffffff0,mdl + set_dbits 0x3 ; Set opposite of expected + set_cc 0x0f ; Condition codes should not change + div0u r2 + test_cc 1 1 1 1 + test_h_gr 0xdeadbeef,r2 + test_h_dr 0x00000000,mdh + test_h_dr 0x0ffffff0,mdl + test_dbits 0x0 + + pass diff --git a/sim/testsuite/sim/fr30/div1.cgs b/sim/testsuite/sim/fr30/div1.cgs new file mode 100644 index 00000000000..dac35fe15c4 --- /dev/null +++ b/sim/testsuite/sim/fr30/div1.cgs @@ -0,0 +1,113 @@ +# fr30 testcase for div1 $Ri +# mach(): fr30 + + .include "testutils.inc" + + START + + .text + .global div1 +div1: + ; Test div1 $Ri + ; example from the manual -- all status bits 0 + mvi_h_gr 0x00ffffff,r2 + mvi_h_dr 0x00ffffff,mdh + mvi_h_dr 0x00000000,mdl + set_dbits 0x0 + set_cc 0x00 + div1 r2 + test_cc 0 0 0 0 + test_dbits 0x0 + test_h_gr 0x00ffffff,r2 + test_h_dr 0x00ffffff,mdh ; misprinted in manual? + test_h_dr 0x00000001,mdl + + ; D0 == 1 + set_dbits 0x1 + set_cc 0x00 + div1 r2 + test_cc 0 0 0 0 + test_dbits 0x1 + test_h_gr 0x00ffffff,r2 + test_h_dr 0x01fffffe,mdh + test_h_dr 0x00000002,mdl + + ; D1 == 1 + set_dbits 0x2 + set_cc 0x00 + div1 r2 + test_cc 0 0 0 0 + test_dbits 0x2 + test_h_gr 0x00ffffff,r2 + test_h_dr 0x03fffffc,mdh + test_h_dr 0x00000004,mdl + + ; D0 == 1, D1 == 1 + set_dbits 0x3 + set_cc 0x00 + div1 r2 + test_cc 0 0 0 0 + test_dbits 0x3 + test_h_gr 0x00ffffff,r2 + test_h_dr 0x08fffff7,mdh + test_h_dr 0x00000009,mdl + + ; C == 1 + mvi_h_gr 0x11ffffef,r2 + set_dbits 0x0 + set_cc 0x00 + div1 r2 + test_cc 0 0 0 1 + test_dbits 0x0 + test_h_gr 0x11ffffef,r2 + test_h_dr 0x11ffffee,mdh + test_h_dr 0x00000012,mdl + + ; D0 == 1, C == 1 + mvi_h_gr 0x23ffffdd,r2 + set_dbits 0x1 + set_cc 0x00 + div1 r2 + test_cc 0 0 0 1 + test_dbits 0x1 + test_h_gr 0x23ffffdd,r2 + test_h_dr 0xffffffff,mdh + test_h_dr 0x00000025,mdl + + ; D1 == 1, C == 1 + mvi_h_gr 0x00000003,r2 + set_dbits 0x2 + set_cc 0x00 + div1 r2 + test_cc 0 0 0 1 + test_dbits 0x2 + test_h_gr 0x00000003,r2 + test_h_dr 0x00000001,mdh + test_h_dr 0x0000004b,mdl + + ; D0 == 1, D1 == 1, C == 1 + mvi_h_gr 0xfffffffe,r2 + set_dbits 0x3 + set_cc 0x00 + div1 r2 + test_cc 0 0 0 1 + test_dbits 0x3 + test_h_gr 0xfffffffe,r2 + test_h_dr 0x00000002,mdh + test_h_dr 0x00000096,mdl + + ; remainder is zero + mvi_h_gr 0x00000004,r2 + set_dbits 0x0 + set_cc 0x00 + div1 r2 + test_cc 0 1 0 0 + test_dbits 0x0 + test_h_gr 0x00000004,r2 + test_h_dr 0x00000000,mdh + test_h_dr 0x0000012d,mdl + + pass + + + diff --git a/sim/testsuite/sim/fr30/div2.cgs b/sim/testsuite/sim/fr30/div2.cgs new file mode 100644 index 00000000000..03000a24242 --- /dev/null +++ b/sim/testsuite/sim/fr30/div2.cgs @@ -0,0 +1,120 @@ +# fr30 testcase for div2 $Ri +# mach(): fr30 + + .include "testutils.inc" + + START + + .text + .global div2 +div2: + ; Test div2 $Ri + ; example from the manual -- all status bits 0 + mvi_h_gr 0x00ffffff,r2 + mvi_h_dr 0x00ffffff,mdh + mvi_h_dr 0x0000000f,mdl + set_dbits 0x0 + set_cc 0x00 + div2 r2 + test_cc 0 1 0 0 + test_dbits 0x0 + test_h_gr 0x00ffffff,r2 + test_h_dr 0x00000000,mdh + test_h_dr 0x0000000f,mdl + + ; D0 == 1 + mvi_h_dr 0x00ffffff,mdh + set_dbits 0x1 + set_cc 0x00 + div2 r2 + test_cc 0 1 0 0 + test_dbits 0x1 + test_h_gr 0x00ffffff,r2 + test_h_dr 0x00000000,mdh + test_h_dr 0x0000000f,mdl + + ; D1 == 1 + mvi_h_dr 0x00ffffff,mdh + set_dbits 0x2 + set_cc 0x00 + div2 r2 + test_cc 0 0 0 0 + test_dbits 0x2 + test_h_gr 0x00ffffff,r2 + test_h_dr 0x00ffffff,mdh + test_h_dr 0x0000000f,mdl + + ; D0 == 1, D1 == 1 + set_dbits 0x3 + set_cc 0x00 + div2 r2 + test_cc 0 0 0 0 + test_dbits 0x3 + test_h_gr 0x00ffffff,r2 + test_h_dr 0x00ffffff,mdh + test_h_dr 0x0000000f,mdl + + ; C == 1 + mvi_h_dr 0x11ffffee,mdh + mvi_h_gr 0x11ffffef,r2 + set_dbits 0x0 + set_cc 0x00 + div2 r2 + test_cc 0 0 0 1 + test_dbits 0x0 + test_h_gr 0x11ffffef,r2 + test_h_dr 0x11ffffee,mdh + test_h_dr 0x0000000f,mdl + + ; D0 == 1, C == 1 + mvi_h_dr 0x23ffffdc,mdh + mvi_h_gr 0x23ffffdd,r2 + set_dbits 0x1 + set_cc 0x00 + div2 r2 + test_cc 0 0 0 1 + test_dbits 0x1 + test_h_gr 0x23ffffdd,r2 + test_h_dr 0x23ffffdc,mdh + test_h_dr 0x0000000f,mdl + + ; D1 == 1, C == 1 + mvi_h_dr 0xfffffffd,mdh + mvi_h_gr 0x00000004,r2 + set_dbits 0x2 + set_cc 0x00 + div2 r2 + test_cc 0 0 0 1 + test_dbits 0x2 + test_h_gr 0x00000004,r2 + test_h_dr 0xfffffffd,mdh + test_h_dr 0x0000000f,mdl + + ; D0 == 1, D1 == 1, C == 1 + mvi_h_dr 0x00000002,mdh + mvi_h_gr 0xffffffff,r2 + set_dbits 0x3 + set_cc 0x00 + div2 r2 + test_cc 0 0 0 1 + test_dbits 0x3 + test_h_gr 0xffffffff,r2 + test_h_dr 0x00000002,mdh + test_h_dr 0x0000000f,mdl + + ; remainder is zero + mvi_h_dr 0x00000004,mdh + mvi_h_gr 0x00000004,r2 + set_dbits 0x0 + set_cc 0x00 + div2 r2 + test_cc 0 1 0 0 + test_dbits 0x0 + test_h_gr 0x00000004,r2 + test_h_dr 0x00000000,mdh + test_h_dr 0x0000000f,mdl + + pass + + + diff --git a/sim/testsuite/sim/fr30/div3.cgs b/sim/testsuite/sim/fr30/div3.cgs new file mode 100644 index 00000000000..ee7da1a8042 --- /dev/null +++ b/sim/testsuite/sim/fr30/div3.cgs @@ -0,0 +1,34 @@ +# fr30 testcase for div3 +# mach(): fr30 + + .include "testutils.inc" + + START + + .text + .global div3 +div3: + ; Test div3 + ; example from the manual + mvi_h_gr 0x00ffffff,r2 + mvi_h_dr 0x00000000,mdh + mvi_h_dr 0x0000000f,mdl + set_dbits 0x0 + set_cc 0x04 + div3 + test_cc 0 1 0 0 + test_dbits 0x0 + test_h_gr 0x00ffffff,r2 + test_h_dr 0x00000000,mdh + test_h_dr 0x00000010,mdl + + set_dbits 0x0 + set_cc 0x00 + div3 + test_cc 0 0 0 0 + test_dbits 0x0 + test_h_gr 0x00ffffff,r2 + test_h_dr 0x00000000,mdh + test_h_dr 0x00000010,mdl + + pass diff --git a/sim/testsuite/sim/fr30/div4s.cgs b/sim/testsuite/sim/fr30/div4s.cgs new file mode 100644 index 00000000000..3b98ecaf1c3 --- /dev/null +++ b/sim/testsuite/sim/fr30/div4s.cgs @@ -0,0 +1,34 @@ +# fr30 testcase for div4s +# mach(): fr30 + + .include "testutils.inc" + + START + + .text + .global div4s +div4s: + ; Test div4s + ; example from the manual + mvi_h_gr 0x00ffffff,r2 + mvi_h_dr 0x00000000,mdh + mvi_h_dr 0x0000000f,mdl + set_dbits 0x3 + set_cc 0x0f + div4s + test_cc 1 1 1 1 + test_dbits 0x3 + test_h_gr 0x00ffffff,r2 + test_h_dr 0x00000000,mdh + test_h_dr 0xfffffff1,mdl + + set_dbits 0x0 + set_cc 0x00 + div4s + test_cc 0 0 0 0 + test_dbits 0x0 + test_h_gr 0x00ffffff,r2 + test_h_dr 0x00000000,mdh + test_h_dr 0xfffffff1,mdl + + pass diff --git a/sim/testsuite/sim/fr30/dmov.cgs b/sim/testsuite/sim/fr30/dmov.cgs new file mode 100644 index 00000000000..bd2e5cc45ff --- /dev/null +++ b/sim/testsuite/sim/fr30/dmov.cgs @@ -0,0 +1,73 @@ +# fr30 testcase for dmov +# mach(): fr30 + + .include "testutils.inc" + START + + .text + .global dmov +dmov: + ; Test dmov @$dir10,$R13 + mvi_h_gr 0xdeadbeef,r1 + mvi_h_gr 0x200,r2 + mvr_h_mem r1,r2 + set_cc 0x0f ; Condition codes shouldn't change + dmov @0x200,r13 + test_cc 1 1 1 1 + test_h_gr 0xdeadbeef,r13 + + ; Test dmov $R13,@$dir10 + mvi_h_gr 0xbeefdead,r13 + set_cc 0x0e ; Condition codes shouldn't change + dmov r13,@0x200 + test_cc 1 1 1 0 + test_h_mem 0xbeefdead,r2 + + ; Test dmov @$dir10,@R13+ + mvi_h_gr 0x1fc,r13 + set_cc 0x0d ; Condition codes shouldn't change + dmov @0x200,@r13+ + test_cc 1 1 0 1 + mvi_h_gr 0x1fc,r2 + test_h_mem 0xbeefdead,r2 + inci_h_gr 4,r2 + test_h_mem 0xbeefdead,r2 + test_h_gr 0x200,r13 + + ; Test dmov @$R13+,@$dir10 + mvi_h_gr 0x1fc,r13 + mvi_h_mem 0xdeadbeef,r13 + set_cc 0x0c ; Condition codes shouldn't change + dmov @r13+,@0x200 + test_cc 1 1 0 0 + mvi_h_gr 0x1fc,r2 + test_h_mem 0xdeadbeef,r2 + inci_h_gr 4,r2 + test_h_mem 0xdeadbeef,r2 + test_h_gr 0x200,r13 + + ; Test dmov @$dir10,@-R15 + mvi_h_gr 0x200,r15 + mvi_h_mem 0xdeadbeef,r15 + set_cc 0x0b ; Condition codes shouldn't change + dmov @0x200,@-r15 + test_cc 1 0 1 1 + mvi_h_gr 0x1fc,r2 + test_h_mem 0xdeadbeef,r2 + inci_h_gr 4,r2 + test_h_mem 0xdeadbeef,r2 + test_h_gr 0x1fc,r15 + + ; Test dmov @$R15+,@$dir10 + mvi_h_gr 0x1fc,r15 + mvi_h_mem 0xbeefdead,r15 + set_cc 0x0a ; Condition codes shouldn't change + dmov @r15+,@0x200 + test_cc 1 0 1 0 + mvi_h_gr 0x1fc,r2 + test_h_mem 0xbeefdead,r2 + inci_h_gr 4,r2 + test_h_mem 0xbeefdead,r2 + test_h_gr 0x200,r15 + + pass diff --git a/sim/testsuite/sim/fr30/dmovb.cgs b/sim/testsuite/sim/fr30/dmovb.cgs new file mode 100644 index 00000000000..96cfb9d3e08 --- /dev/null +++ b/sim/testsuite/sim/fr30/dmovb.cgs @@ -0,0 +1,46 @@ +# fr30 testcase for dmovb +# mach(): fr30 + + .include "testutils.inc" + START + + .text + .global dmovb +dmovb: + ; Test dmovb @$dir8,$R13 + mvi_h_gr 0xdeadbeef,r1 + mvi_h_gr 0x80,r2 + mvr_h_mem r1,r2 + set_cc 0x0f ; Condition codes shouldn't change + dmovb @0x80,r13 + test_cc 1 1 1 1 + test_h_gr 0xffffffde,r13 + + ; Test dmovb $R13,@$dir8 + mvi_h_gr 0xbeefdead,r13 + set_cc 0x0e ; Condition codes shouldn't change + dmovb r13,@0x80 + test_cc 1 1 1 0 + test_h_mem 0xadadbeef,r2 + + ; Test dmovb @$dir8,@R13+ + mvi_h_gr 0x7c,r13 + mvi_h_mem 0xdeadbeef,r13 + set_cc 0x0d ; Condition codes shouldn't change + dmovb @0x7f,@r13+ + test_cc 1 1 0 1 + mvi_h_gr 0x7c,r2 + test_h_mem 0xefadbeef,r2 + test_h_gr 0x7d,r13 + + ; Test dmovb @$R13+,@$dir8 + mvi_h_gr 0x7c,r13 + mvi_h_mem 0xbeefdead,r13 + set_cc 0x0c ; Condition codes shouldn't change + dmovb @r13+,@0x7f + test_cc 1 1 0 0 + mvi_h_gr 0x7c,r2 + test_h_mem 0xbeefdebe,r2 + test_h_gr 0x7d,r13 + + pass diff --git a/sim/testsuite/sim/fr30/dmovh.cgs b/sim/testsuite/sim/fr30/dmovh.cgs new file mode 100644 index 00000000000..86afb44f411 --- /dev/null +++ b/sim/testsuite/sim/fr30/dmovh.cgs @@ -0,0 +1,46 @@ +# fr30 testcase for dmovh +# mach(): fr30 + + .include "testutils.inc" + START + + .text + .global dmovh +dmovh: + ; Test dmovh @$dir9,$R13 + mvi_h_gr 0xdeadbeef,r1 + mvi_h_gr 0x100,r2 + mvr_h_mem r1,r2 + set_cc 0x0f ; Condition codes shouldn't change + dmovh @0x100,r13 + test_cc 1 1 1 1 + test_h_gr 0xffffdead,r13 + + ; Test dmovh $R13,@$dir9 + mvi_h_gr 0xdeadbeef,r13 + set_cc 0x0e ; Condition codes shouldn't change + dmovh r13,@0x100 + test_cc 1 1 1 0 + test_h_mem 0xbeefbeef,r2 + + ; Test dmovh @$dir9,@R13+ + mvi_h_gr 0x1fc,r13 + mvi_h_mem 0xdeadbeef,r13 + set_cc 0x0d ; Condition codes shouldn't change + dmovh @0x1fe,@r13+ + test_cc 1 1 0 1 + mvi_h_gr 0x1fc,r2 + test_h_mem 0xbeefbeef,r2 + test_h_gr 0x1fe,r13 + + ; Test dmovh @$R13+,@$dir9 + mvi_h_gr 0x1fc,r13 + mvi_h_mem 0xbeefdead,r13 + set_cc 0x0c ; Condition codes shouldn't change + dmovh @r13+,@0x1fe + test_cc 1 1 0 0 + mvi_h_gr 0x1fc,r2 + test_h_mem 0xbeefbeef,r2 + test_h_gr 0x1fe,r13 + + pass diff --git a/sim/testsuite/sim/fr30/enter.cgs b/sim/testsuite/sim/fr30/enter.cgs new file mode 100644 index 00000000000..ae75e16a2e1 --- /dev/null +++ b/sim/testsuite/sim/fr30/enter.cgs @@ -0,0 +1,34 @@ +# fr30 testcase for enter $u10 +# mach(): fr30 + + .include "testutils.inc" + + START + + .text + .global enter +enter: + ; Test enter $u10 + mvr_h_gr sp,r7 ; save stack pointer + mvr_h_gr sp,r8 ; shadow stack pointer + mvr_h_gr sp,r14 ; Initialize + set_cc 0x0f ; Condition codes are irrelevent + enter 0 + test_cc 1 1 1 1 + testr_h_gr r8,sp + inci_h_gr -4,r8 + testr_h_gr r14,r8 + testr_h_mem r7,r14 + + mvr_h_gr sp,r8 ; shadow stack pointer + mvr_h_gr r14,r9 ; save + set_cc 0x0e ; Condition codes are irrelevent + enter 0x3fc + test_cc 1 1 1 0 + inci_h_gr -4,r8 + testr_h_gr r14,r8 + testr_h_mem r9,r14 + inci_h_gr -0x3f8,r8 + testr_h_gr r8,sp + + pass diff --git a/sim/testsuite/sim/fr30/eor.cgs b/sim/testsuite/sim/fr30/eor.cgs new file mode 100644 index 00000000000..a87076151cf --- /dev/null +++ b/sim/testsuite/sim/fr30/eor.cgs @@ -0,0 +1,69 @@ +# fr30 testcase for eor $Rj,$Ri, eor $Rj,@$Ri +# mach(): fr30 + + .include "testutils.inc" + + START + + .text + .global eor +eor: + ; Test eor $Rj,$Ri + mvi_h_gr 0xaaaaaaaa,r7 + mvi_h_gr 0x55555555,r8 + set_cc 0x07 ; Set mask opposite of expected + eor r7,r8 + test_cc 1 0 1 1 + test_h_gr 0xffffffff,r8 + + mvi_h_gr 0x00000000,r7 + mvi_h_gr 0x00000000,r8 + set_cc 0x08 ; Set mask opposite of expected + eor r7,r8 + test_cc 0 1 0 0 + test_h_gr 0x00000000,r8 + + mvi_h_gr 0xaaaaaaaa,r7 + mvi_h_gr 0xaaaaaaaa,r8 + set_cc 0x0b ; Set mask opposite of expected + eor r7,r8 + test_cc 0 1 1 1 + test_h_gr 0x00000000,r8 + + mvi_h_gr 0xdead0000,r7 + mvi_h_gr 0x0000beef,r8 + set_cc 0x05 ; Set mask opposite of expected + eor r7,r8 + test_cc 1 0 0 1 + test_h_gr 0xdeadbeef,r8 + + ; Test eor $Rj,@$Ri + mvi_h_gr 0xaaaaaaaa,r7 + mvi_h_mem 0x55555555,sp + set_cc 0x07 ; Set mask opposite of expected + eor r7,@sp + test_cc 1 0 1 1 + test_h_mem 0xffffffff,sp + + mvi_h_gr 0x00000000,r7 + mvi_h_mem 0x00000000,sp + set_cc 0x08 ; Set mask opposite of expected + eor r7,@sp + test_cc 0 1 0 0 + test_h_mem 0x00000000,sp + + mvi_h_gr 0xaaaaaaaa,r7 + mvi_h_mem 0xaaaaaaaa,sp + set_cc 0x0b ; Set mask opposite of expected + eor r7,@sp + test_cc 0 1 1 1 + test_h_mem 0x00000000,sp + + mvi_h_gr 0xdead0000,r7 + mvi_h_mem 0x0000beef,sp + set_cc 0x05 ; Set mask opposite of expected + eor r7,@sp + test_cc 1 0 0 1 + test_h_mem 0xdeadbeef,sp + + pass diff --git a/sim/testsuite/sim/fr30/eorb.cgs b/sim/testsuite/sim/fr30/eorb.cgs new file mode 100644 index 00000000000..540f3f7aa1f --- /dev/null +++ b/sim/testsuite/sim/fr30/eorb.cgs @@ -0,0 +1,40 @@ +# fr30 testcase for eorb $Rj,$Ri, eorb $Rj,@$Ri +# mach(): fr30 + + .include "testutils.inc" + + START + + .text + .global eorb +eorb: + ; Test eorb $Rj,@$Ri + mvi_h_gr 0xaaaaaaaa,r7 + mvi_h_mem 0x55555555,sp + set_cc 0x07 ; Set mask opposite of expected + eorb r7,@sp + test_cc 1 0 1 1 + test_h_mem 0xff555555,sp + + mvi_h_gr 0xaaaaaa00,r7 + mvi_h_mem 0x00555555,sp + set_cc 0x08 ; Set mask opposite of expected + eorb r7,@sp + test_cc 0 1 0 0 + test_h_mem 0x00555555,sp + + mvi_h_gr 0xaaaaaa55,r7 + mvi_h_mem 0x55aaaaaa,sp + set_cc 0x0b ; Set mask opposite of expected + eorb r7,@sp + test_cc 0 1 1 1 + test_h_mem 0x00aaaaaa,sp + + mvi_h_gr 0x000000d0,r7 + mvi_h_mem 0x0eadbeef,sp + set_cc 0x05 ; Set mask opposite of expected + eorb r7,@sp + test_cc 1 0 0 1 + test_h_mem 0xdeadbeef,sp + + pass diff --git a/sim/testsuite/sim/fr30/eorh.cgs b/sim/testsuite/sim/fr30/eorh.cgs new file mode 100644 index 00000000000..7cf84735959 --- /dev/null +++ b/sim/testsuite/sim/fr30/eorh.cgs @@ -0,0 +1,40 @@ +# fr30 testcase for eorh $Rj,$Ri, eorh $Rj,@$Ri +# mach(): fr30 + + .include "testutils.inc" + + START + + .text + .global eorh +eorh: + ; Test eorh $Rj,@$Ri + mvi_h_gr 0xaaaaaaaa,r7 + mvi_h_mem 0x55555555,sp + set_cc 0x07 ; Set mask opposite of expected + eorh r7,@sp + test_cc 1 0 1 1 + test_h_mem 0xffff5555,sp + + mvi_h_gr 0xaaaa0000,r7 + mvi_h_mem 0x00005555,sp + set_cc 0x08 ; Set mask opposite of expected + eorh r7,@sp + test_cc 0 1 0 0 + test_h_mem 0x00005555,sp + + mvi_h_gr 0xaaaa5555,r7 + mvi_h_mem 0x5555aaaa,sp + set_cc 0x0b ; Set mask opposite of expected + eorh r7,@sp + test_cc 0 1 1 1 + test_h_mem 0x0000aaaa,sp + + mvi_h_gr 0x0000de00,r7 + mvi_h_mem 0x00adbeef,sp + set_cc 0x05 ; Set mask opposite of expected + eorh r7,@sp + test_cc 1 0 0 1 + test_h_mem 0xdeadbeef,sp + + pass diff --git a/sim/testsuite/sim/fr30/extsb.cgs b/sim/testsuite/sim/fr30/extsb.cgs new file mode 100644 index 00000000000..6a18d7e7dae --- /dev/null +++ b/sim/testsuite/sim/fr30/extsb.cgs @@ -0,0 +1,36 @@ +# fr30 testcase for extsb $Ri +# mach(): fr30 + + .include "testutils.inc" + + START + + .text + .global extsb +extsb: + ; Test extsb $Ri + mvi_h_gr 0,r7 + set_cc 0x0f ; Condition codes are irrelevent + extsb r7 + test_cc 1 1 1 1 + test_h_gr 0,r7 + + mvi_h_gr 0x7f,r7 + set_cc 0x0e ; Condition codes are irrelevent + extsb r7 + test_cc 1 1 1 0 + test_h_gr 0x7f,r7 + + mvi_h_gr 0x80,r7 + set_cc 0x0d ; Condition codes are irrelevent + extsb r7 + test_cc 1 1 0 1 + test_h_gr 0xffffff80,r7 + + mvi_h_gr 0xffffff7f,r7 + set_cc 0x0c ; Condition codes are irrelevent + extsb r7 + test_cc 1 1 0 0 + test_h_gr 0x7f,r7 + + pass diff --git a/sim/testsuite/sim/fr30/extsh.cgs b/sim/testsuite/sim/fr30/extsh.cgs new file mode 100644 index 00000000000..eb12fd0aae8 --- /dev/null +++ b/sim/testsuite/sim/fr30/extsh.cgs @@ -0,0 +1,48 @@ +# fr30 testcase for extsh $Ri +# mach(): fr30 + + .include "testutils.inc" + + START + + .text + .global extsh +extsh: + ; Test extsh $Ri + mvi_h_gr 0,r7 + set_cc 0x0f ; Condition codes are irrelevent + extsh r7 + test_cc 1 1 1 1 + test_h_gr 0,r7 + + mvi_h_gr 0x7f,r7 + set_cc 0x0e ; Condition codes are irrelevent + extsh r7 + test_cc 1 1 1 0 + test_h_gr 0x7f,r7 + + mvi_h_gr 0x80,r7 + set_cc 0x0d ; Condition codes are irrelevent + extsh r7 + test_cc 1 1 0 1 + test_h_gr 0x80,r7 + + mvi_h_gr 0x7fff,r7 + set_cc 0x0c ; Condition codes are irrelevent + extsh r7 + test_cc 1 1 0 0 + test_h_gr 0x7fff,r7 + + mvi_h_gr 0x8000,r7 + set_cc 0x0b ; Condition codes are irrelevent + extsh r7 + test_cc 1 0 1 1 + test_h_gr 0xffff8000,r7 + + mvi_h_gr 0xffff7fff,r7 + set_cc 0x0a ; Condition codes are irrelevent + extsh r7 + test_cc 1 0 1 0 + test_h_gr 0x7fff,r7 + + pass diff --git a/sim/testsuite/sim/fr30/extub.cgs b/sim/testsuite/sim/fr30/extub.cgs new file mode 100644 index 00000000000..ddcc68361cc --- /dev/null +++ b/sim/testsuite/sim/fr30/extub.cgs @@ -0,0 +1,42 @@ +# fr30 testcase for extub $Ri +# mach(): fr30 + + .include "testutils.inc" + + START + + .text + .global extub +extub: + ; Test extub $Ri + mvi_h_gr 0,r7 + set_cc 0x0f ; Condition codes are irrelevent + extub r7 + test_cc 1 1 1 1 + test_h_gr 0,r7 + + mvi_h_gr 0x7f,r7 + set_cc 0x0e ; Condition codes are irrelevent + extub r7 + test_cc 1 1 1 0 + test_h_gr 0x7f,r7 + + mvi_h_gr 0x80,r7 + set_cc 0x0d ; Condition codes are irrelevent + extub r7 + test_cc 1 1 0 1 + test_h_gr 0x80,r7 + + mvi_h_gr 0xffffff7f,r7 + set_cc 0x0c ; Condition codes are irrelevent + extub r7 + test_cc 1 1 0 0 + test_h_gr 0x7f,r7 + + mvi_h_gr 0xffffff80,r7 + set_cc 0x0b ; Condition codes are irrelevent + extub r7 + test_cc 1 0 1 1 + test_h_gr 0x80,r7 + + pass diff --git a/sim/testsuite/sim/fr30/extuh.cgs b/sim/testsuite/sim/fr30/extuh.cgs new file mode 100644 index 00000000000..fa2579e469f --- /dev/null +++ b/sim/testsuite/sim/fr30/extuh.cgs @@ -0,0 +1,54 @@ +# fr30 testcase for extuh $Ri +# mach(): fr30 + + .include "testutils.inc" + + START + + .text + .global extuh +extuh: + ; Test extuh $Ri + mvi_h_gr 0,r7 + set_cc 0x0f ; Condition codes are irrelevent + extuh r7 + test_cc 1 1 1 1 + test_h_gr 0,r7 + + mvi_h_gr 0x7f,r7 + set_cc 0x0e ; Condition codes are irrelevent + extuh r7 + test_cc 1 1 1 0 + test_h_gr 0x7f,r7 + + mvi_h_gr 0x80,r7 + set_cc 0x0d ; Condition codes are irrelevent + extuh r7 + test_cc 1 1 0 1 + test_h_gr 0x80,r7 + + mvi_h_gr 0x7fff,r7 + set_cc 0x0e ; Condition codes are irrelevent + extuh r7 + test_cc 1 1 1 0 + test_h_gr 0x7fff,r7 + + mvi_h_gr 0x8000,r7 + set_cc 0x0d ; Condition codes are irrelevent + extuh r7 + test_cc 1 1 0 1 + test_h_gr 0x8000,r7 + + mvi_h_gr 0xffff7fff,r7 + set_cc 0x0c ; Condition codes are irrelevent + extuh r7 + test_cc 1 1 0 0 + test_h_gr 0x7fff,r7 + + mvi_h_gr 0xffff8000,r7 + set_cc 0x0b ; Condition codes are irrelevent + extuh r7 + test_cc 1 0 1 1 + test_h_gr 0x8000,r7 + + pass diff --git a/sim/testsuite/sim/fr30/hello.ms b/sim/testsuite/sim/fr30/hello.ms new file mode 100644 index 00000000000..0f208dfb927 --- /dev/null +++ b/sim/testsuite/sim/fr30/hello.ms @@ -0,0 +1,19 @@ +# mach: fr30 +# output: Hello world!\n + + .global _start +_start: + +; write (hello world) + ldi32 #14,r6 + ldi32 #hello,r5 + ldi32 #1,r4 + ldi32 #5,r0 + int #10 +; exit (0) + ldi32 #0,r4 + ldi32 #1,r0 + int #10 + +length: .long 14 +hello: .ascii "Hello world!\r\n" diff --git a/sim/testsuite/sim/fr30/int.cgs b/sim/testsuite/sim/fr30/int.cgs new file mode 100644 index 00000000000..7cdca7b8c9b --- /dev/null +++ b/sim/testsuite/sim/fr30/int.cgs @@ -0,0 +1,35 @@ +# fr30 testcase for int $u8 +# mach(): fr30 + + .include "testutils.inc" + + START + + .text + .global int +int: + ; Test int $u8 - setup and test an interrupt #0xfd (randomly chosen) + mvr_h_gr tbr,r7 + inci_h_gr 8,r7 + mvi_h_mem pass,r7 + mvi_h_gr doint,r9 + inci_h_gr 2,r9 + mvr_h_gr ssp,r10 + set_cc 0x0f ; Condition codes should not change + set_s_user ; Set opposite of expected + set_i 1 ; Set opposite of expected + mvr_h_gr ps,r8 +doint: int 0xfd + fail + +pass: + test_cc 1 1 1 1 + test_s_system + test_i 0 + inci_h_gr -4,r10 + testr_h_mem r8,r10 + inci_h_gr -4,r10 + testr_h_mem r9,r10 + testr_h_dr r10,ssp + + pass diff --git a/sim/testsuite/sim/fr30/inte.cgs b/sim/testsuite/sim/fr30/inte.cgs new file mode 100644 index 00000000000..a15bfd978a2 --- /dev/null +++ b/sim/testsuite/sim/fr30/inte.cgs @@ -0,0 +1,36 @@ +# fr30 testcase for inte +# mach(): fr30 + + .include "testutils.inc" + + START + + .text + .global inte +inte: + ; Test inte which is essentially int #9 + mvr_h_gr tbr,r7 + inci_h_gr 0x3d8,r7 + mvi_h_mem pass,r7 + mvi_h_gr doint,r9 + inci_h_gr 2,r9 + mvr_h_gr ssp,r10 + set_cc 0x0f ; Condition codes should not change + set_s_user ; Set opposite of expected + set_i 1 ; Should not change + mvr_h_gr ps,r8 +doint: inte + fail + +pass: + test_cc 1 1 1 1 + test_ilm 4 + test_s_system + test_i 1 + inci_h_gr -4,r10 + testr_h_mem r8,r10 + inci_h_gr -4,r10 + testr_h_mem r9,r10 + testr_h_dr r10,ssp + + pass diff --git a/sim/testsuite/sim/fr30/jmp.cgs b/sim/testsuite/sim/fr30/jmp.cgs new file mode 100644 index 00000000000..db4af220d36 --- /dev/null +++ b/sim/testsuite/sim/fr30/jmp.cgs @@ -0,0 +1,29 @@ +# fr30 testcase for jmp @$Ri +# mach(): fr30 + + .include "testutils.inc" + + START + + .text + .global jmp + + ; Test jmp $Ri + mvi_h_gr #func1,r0 + set_cc 0x0f ; condition codes shouldn't change +jmp1: + jmp @r0 + fail +func1: + test_cc 1 1 1 1 + mvi_h_gr #func2,r0 + set_cc 0x0f ; condition codes shouldn't change +jmp2: + jmp:d @r0 + ldi:8 1,r0 ; Must assume this works + fail +func2: + test_cc 1 1 1 1 + testr_h_gr 1,r0 + + pass diff --git a/sim/testsuite/sim/fr30/ld.cgs b/sim/testsuite/sim/fr30/ld.cgs new file mode 100644 index 00000000000..3f2d30bb023 --- /dev/null +++ b/sim/testsuite/sim/fr30/ld.cgs @@ -0,0 +1,219 @@ +# fr30 testcase for +# mach(): fr30 +# ld $Rj,$Ri +# ld @($R13,$Rj),$Ri +# ld @($R14,$disp10),$Ri +# ld @($R15,$udisp6),$Ri +# ld @$R15+,$Ri +# ld @$R15+,$Rs + + .include "testutils.inc" + + START + + .text + .global ld +ld: + ; Test ld $Rj,$Ri + mvi_h_mem #0x00000000,sp + set_cc 0x0f ; condition codes should not change + ld @sp,r7 + test_cc 1 1 1 1 + test_h_gr 0,r7 + + mvi_h_mem #0x00000001,sp + set_cc 0x07 ; condition codes should not change + ld @sp,r7 + test_cc 0 1 1 1 + test_h_gr 1,r7 + + mvi_h_mem #0x7fffffff,sp + set_cc 0x0b ; condition codes should not change + ld @sp,r7 + test_cc 1 0 1 1 + test_h_gr 0x7fffffff,r7 + + mvi_h_mem #0x80000000,sp + set_cc 0x0d ; condition codes should not change + ld @sp,r7 + test_cc 1 1 0 1 + test_h_gr 0x80000000,r7 + + mvi_h_mem #0xffffffff,sp + set_cc 0x0e ; condition codes should not change + ld @sp,r7 + test_cc 1 1 1 0 + test_h_gr -1,r7 + + ; Test ld @($R13,$Rj),$Ri + mvr_h_gr sp,r13 + inci_h_gr -8,r13 + mvi_h_gr 8,r8 + + mvi_h_mem #0x00000000,sp + set_cc 0x0f ; condition codes should not change + ld @(r13,r8),r7 + test_cc 1 1 1 1 + test_h_gr 0,r7 + + mvi_h_mem #0x00000001,sp + set_cc 0x07 ; condition codes should not change + ld @(r13,r8),r7 + test_cc 0 1 1 1 + test_h_gr 1,r7 + + mvi_h_mem #0x7fffffff,sp + set_cc 0x0b ; condition codes should not change + ld @(r13,r8),r7 + test_cc 1 0 1 1 + test_h_gr 0x7fffffff,r7 + + mvi_h_mem #0x80000000,sp + set_cc 0x0d ; condition codes should not change + ld @(r13,r8),r7 + test_cc 1 1 0 1 + test_h_gr 0x80000000,r7 + + mvi_h_mem #0xffffffff,sp + set_cc 0x0e ; condition codes should not change + ld @(r13,r8),r7 + test_cc 1 1 1 0 + test_h_gr -1,r7 + + ; Test ld @($R14,$disp10),$Ri + mvi_h_mem #0xdeadbeef,sp + mvr_h_gr sp,r14 + mvi_h_gr -0x1fc,r8 + add_h_gr r8,r14 + + set_cc 0x0f ; condition codes should not change + ld @(r14,0x1fc),r7 + test_cc 1 1 1 1 + test_h_gr 0xdeadbeef,r7 + + inci_h_gr 0xfc,r14 + set_cc 0x07 ; condition codes should not change + ld @(r14,0x100),r7 + test_cc 0 1 1 1 + test_h_gr 0xdeadbeef,r7 + + inci_h_gr 0x100,r14 + set_cc 0x0b ; condition codes should not change + ld @(r14,0x0),r7 + test_cc 1 0 1 1 + test_h_gr 0xdeadbeef,r7 + + inci_h_gr 0x100,r14 + set_cc 0x0d ; condition codes should not change + ld @(r14,-0x100),r7 + test_cc 1 1 0 1 + test_h_gr 0xdeadbeef,r7 + + inci_h_gr 0x100,r14 + set_cc 0x0e ; condition codes should not change + ld @(r14,-0x200),r7 + test_cc 1 1 1 0 + test_h_gr 0xdeadbeef,r7 + + ; Test ld @($R15,$udisp6),$Ri + mvi_h_mem #0xdeadbeef,sp + mvr_h_gr sp,r14 + mvi_h_gr -0x3c,r8 + add_h_gr r8,r14 + + set_cc 0x0f ; condition codes should not change + ld @(r14,0x3c),r7 + test_cc 1 1 1 1 + test_h_gr 0xdeadbeef,r7 + + inci_h_gr 0x1c,r14 + set_cc 0x07 ; condition codes should not change + ld @(r14,0x20),r7 + test_cc 0 1 1 1 + test_h_gr 0xdeadbeef,r7 + + inci_h_gr 0x20,r14 + set_cc 0x0b ; condition codes should not change + ld @(r14,0x0),r7 + test_cc 1 0 1 1 + test_h_gr 0xdeadbeef,r7 + + ; Test ld @$R15+,$Ri + mvr_h_gr sp,r8 ; save original stack pointer + mvr_h_gr r8,r9 + inci_h_gr 4,r9 ; original stack pointer + 4 + mvi_h_mem #0xdeadbeef,sp ; prime memory + + mvr_h_gr r8,sp ; restore original stack pointer + set_cc 0x0f ; condition codes should not change + ld @r15+,r7 + test_cc 1 1 1 1 + test_h_gr 0xdeadbeef,r7 + testr_h_gr sp,r9 ; should have been incremented + + mvr_h_gr r8,sp ; restore original stack pointer + set_cc 0x0f ; condition codes should not change + ld @r15+,sp + test_cc 1 1 1 1 + test_h_gr 0xdeadbeef,sp ; should not have been incremented + + ; Test ld @$R15+,$Rs + mvr_h_gr r8,sp ; restore original stack pointer + set_cc 0x0f ; condition codes should not change + ld @r15+,tbr + test_cc 1 1 1 1 + test_h_dr 0xdeadbeef,tbr + testr_h_gr sp,r9 ; should have been incremented + + mvr_h_gr r8,sp ; restore original stack pointer + set_cc 0x0f ; condition codes should not change + ld @r15+,rp + test_cc 1 1 1 1 + test_h_dr 0xdeadbeef,rp + testr_h_gr sp,r9 ; should have been incremented + + mvr_h_gr r8,sp ; restore original stack pointer + set_cc 0x0f ; condition codes should not change + ld @r15+,mdh + test_cc 1 1 1 1 + test_h_dr 0xdeadbeef,mdh + testr_h_gr sp,r9 ; should have been incremented + + mvr_h_gr r8,sp ; restore original stack pointer + set_cc 0x0f ; condition codes should not change + ld @r15+,mdl + test_cc 1 1 1 1 + test_h_dr 0xdeadbeef,mdl + testr_h_gr sp,r9 ; should have been incremented + + set_s_user + mvr_h_gr r8,sp ; restore original stack pointer + set_cc 0x0f ; condition codes should not change + ld @r15+,ssp + test_cc 1 1 1 1 + test_h_dr 0xdeadbeef,ssp + testr_h_gr sp,r9 ; should have been incremented + + mvr_h_gr r8,sp ; restore original stack pointer + set_cc 0x0f ; condition codes should not change + ld @r15+,usp + test_cc 1 1 1 1 + test_h_dr 0xdeadbeef,usp + test_h_gr 0xdeadbeef,sp ; should not have been incremented + + set_s_system + mvr_h_gr r8,sp ; restore original stack pointer + set_cc 0x0f ; condition codes should not change + ld @r15+,usp + test_cc 1 1 1 1 + test_h_dr 0xdeadbeef,usp + testr_h_gr sp,r9 ; should have been incremented + + mvr_h_gr r8,sp ; restore original stack pointer + set_cc 0x0f ; condition codes should not change + ld @r15+,ssp + test_cc 1 1 1 1 + test_h_dr 0xdeadbeef,ssp + test_h_gr 0xdeadbeef,sp ; should not have been incremented + + pass diff --git a/sim/testsuite/sim/fr30/ldi20.cgs b/sim/testsuite/sim/fr30/ldi20.cgs new file mode 100644 index 00000000000..c7a4ef4165f --- /dev/null +++ b/sim/testsuite/sim/fr30/ldi20.cgs @@ -0,0 +1,37 @@ +# fr30 testcase for ldi20 $i20,$Ri +# mach(): fr30 + + .include "testutils.inc" + + START + + .text + .global ldi20 +ldi20: + ; Test ldi20 $i20,$Ri + set_cc 0x0f ; condition codes should not change + ldi20 #0x00000000,r7 + test_cc 1 1 1 1 + test_h_gr 0,r7 + + set_cc 0x07 ; condition codes should not change + ldi:20 1,r7 + test_cc 0 1 1 1 + test_h_gr 1,r7 + + set_cc 0x0b ; condition codes should not change + ldi20 0x7ffff,r7 + test_cc 1 0 1 1 + test_h_gr 0x0007ffff,r7 + + set_cc 0x0d ; condition codes should not change + ldi:20 0x80000,r7 + test_cc 1 1 0 1 + test_h_gr 0x00080000,r7 + + set_cc 0x0e ; condition codes should not change + ldi20 0xfffff,r7 + test_cc 1 1 1 0 + test_h_gr 0x000fffff,r7 + + pass diff --git a/sim/testsuite/sim/fr30/ldi32.cgs b/sim/testsuite/sim/fr30/ldi32.cgs new file mode 100644 index 00000000000..3e56db741e3 --- /dev/null +++ b/sim/testsuite/sim/fr30/ldi32.cgs @@ -0,0 +1,37 @@ +# fr30 testcase for ldi32 $i32,$Ri +# mach(): fr30 + + .include "testutils.inc" + + START + + .text + .global ldi32 +ldi32: + ; Test ldi32 $i32,$Ri + set_cc 0x0f ; condition codes should not change + ldi32 #0x00000000,r7 + test_cc 1 1 1 1 + test_h_gr 0,r7 + + set_cc 0x07 ; condition codes should not change + ldi:32 1,r7 + test_cc 0 1 1 1 + test_h_gr 1,r7 + + set_cc 0x0b ; condition codes should not change + ldi32 0x7fffffff,r7 + test_cc 1 0 1 1 + test_h_gr 0x7fffffff,r7 + + set_cc 0x0d ; condition codes should not change + ldi:32 0x80000000,r7 + test_cc 1 1 0 1 + test_h_gr 0x80000000,r7 + + set_cc 0x0e ; condition codes should not change + ldi32 0xffffffff,r7 + test_cc 1 1 1 0 + test_h_gr -1,r7 + + pass diff --git a/sim/testsuite/sim/fr30/ldi8.cgs b/sim/testsuite/sim/fr30/ldi8.cgs new file mode 100644 index 00000000000..9b15edead0c --- /dev/null +++ b/sim/testsuite/sim/fr30/ldi8.cgs @@ -0,0 +1,37 @@ +# fr30 testcase for ldi8 $i8,$Ri +# mach(): fr30 + + .include "testutils.inc" + + START + + .text + .global ldi8 +ldi8: + ; Test ldi8 $i8,$Ri + set_cc 0x0f ; condition codes should not change + ldi8 #0x00000000,r7 + test_cc 1 1 1 1 + test_h_gr 0,r7 + + set_cc 0x07 ; condition codes should not change + ldi:20 1,r7 + test_cc 0 1 1 1 + test_h_gr 1,r7 + + set_cc 0x0b ; condition codes should not change + ldi8 0x7f,r7 + test_cc 1 0 1 1 + test_h_gr 0x0000007f,r7 + + set_cc 0x0d ; condition codes should not change + ldi:20 0x80,r7 + test_cc 1 1 0 1 + test_h_gr 0x00000080,r7 + + set_cc 0x0e ; condition codes should not change + ldi8 0xff,r7 + test_cc 1 1 1 0 + test_h_gr 0x000000ff,r7 + + pass diff --git a/sim/testsuite/sim/fr30/ldm0.cgs b/sim/testsuite/sim/fr30/ldm0.cgs new file mode 100644 index 00000000000..9deb5642544 --- /dev/null +++ b/sim/testsuite/sim/fr30/ldm0.cgs @@ -0,0 +1,60 @@ +# fr30 testcase for ldm0 ($reglist_low) +# mach(): fr30 + + .include "testutils.inc" + + START + + .text + .global ldm0 +ldm0: + ; Test ldm0 ($reglist_low) + mvr_h_gr sp,r9 ; save stack pointer permanently + inci_h_gr -4,sp + mvi_h_mem 3,sp + inci_h_gr -4,sp + mvi_h_mem 2,sp + inci_h_gr -4,sp + mvi_h_mem 1,sp + inci_h_gr -4,sp + mvi_h_mem 0,sp + + set_cc 0x0f ; Condition codes should not change + ldm0 (r0,r2,r4,r6) + test_cc 1 1 1 1 + testr_h_gr sp,r9 + test_h_gr 0,r0 + test_h_gr 1,r2 + test_h_gr 2,r4 + test_h_gr 3,r6 + + inci_h_gr -16,sp + set_cc 0x0f ; Condition codes should not change + ldm0 (r1,r3,r5,r7) + test_cc 1 1 1 1 + testr_h_gr sp,r9 + test_h_gr 0,r1 + test_h_gr 1,r3 + test_h_gr 2,r5 + test_h_gr 3,r7 + + inci_h_gr -16,sp + set_cc 0x0f ; Condition codes should not change + ldm0 (r1,r5,r7,r3) ; Order speficied should not matter + test_cc 1 1 1 1 + testr_h_gr sp,r9 + test_h_gr 0,r1 + test_h_gr 1,r3 + test_h_gr 2,r5 + test_h_gr 3,r7 + + set_cc 0x0f ; Condition codes should not change + ldm0 () ; Nothing should happen + test_cc 1 1 1 1 + testr_h_gr sp,r9 + test_h_gr 0,r1 + test_h_gr 1,r3 + test_h_gr 2,r5 + test_h_gr 3,r7 + + pass diff --git a/sim/testsuite/sim/fr30/ldm1.cgs b/sim/testsuite/sim/fr30/ldm1.cgs new file mode 100644 index 00000000000..33cfcdba770 --- /dev/null +++ b/sim/testsuite/sim/fr30/ldm1.cgs @@ -0,0 +1,59 @@ +# fr30 testcase for ldm1 ($reglist_low) +# mach(): fr30 + + .include "testutils.inc" + + START + + .text + .global ldm1 +ldm1: + ; Test ldm1 ($reglist_low) + mvr_h_gr sp,r1 ; save stack pointer permanently + inci_h_gr -4,sp + mvi_h_mem 3,sp + inci_h_gr -4,sp + mvi_h_mem 2,sp + inci_h_gr -4,sp + mvi_h_mem 1,sp + inci_h_gr -4,sp + mvi_h_mem 0,sp + + set_cc 0x0f ; Condition codes should not change + ldm1 (r8,r10,r12,r14) + test_cc 1 1 1 1 + testr_h_gr sp,r1 + test_h_gr 0,r8 + test_h_gr 1,r10 + test_h_gr 2,r12 + test_h_gr 3,r14 + + inci_h_gr -16,sp + set_cc 0x0f ; Condition codes should not change + ldm1 (r9,r11,r13,r15) + test_cc 1 1 1 1 + test_h_gr 0,r9 + test_h_gr 1,r11 + test_h_gr 2,r13 + test_h_gr 3,r15 + + mvr_h_gr r1,sp ; restore stack pointer + inci_h_gr -16,sp + set_cc 0x0f ; Condition codes should not change + ldm1 (r9,r13,r15,r11); Order speficied should not matter + test_cc 1 1 1 1 + test_h_gr 0,r9 + test_h_gr 1,r11 + test_h_gr 2,r13 + test_h_gr 3,r15 + + mvr_h_gr r1,sp ; restore stack pointer + set_cc 0x0f ; Condition codes should not change + ldm1 () ; Nothing should happen + test_cc 1 1 1 1 + testr_h_gr sp,r1 + test_h_gr 0,r9 + test_h_gr 1,r11 + test_h_gr 2,r13 + + pass diff --git a/sim/testsuite/sim/fr30/ldres.cgs b/sim/testsuite/sim/fr30/ldres.cgs new file mode 100644 index 00000000000..008348992d2 --- /dev/null +++ b/sim/testsuite/sim/fr30/ldres.cgs @@ -0,0 +1,25 @@ +# fr30 testcase for ldres $@Ri+,$u4 +# mach(): fr30 + + .include "testutils.inc" + + START + + .text + .global ldres +ldres: + ; Test ldres $@Ri+,$u4 + ; The current implementation simply increments Ri + mvi_h_gr 0x1000,r7 + set_cc 0x0f ; Condition codes are irrelevent + ldres @r7+,0 + test_cc 1 1 1 1 + test_h_gr 0x1004,r7 + + mvi_h_gr 0x1000,r7 + set_cc 0x0f ; Condition codes are irrelevent + ldres @r7+,0xf + test_cc 1 1 1 1 + test_h_gr 0x1004,r7 + + pass diff --git a/sim/testsuite/sim/fr30/ldub.cgs b/sim/testsuite/sim/fr30/ldub.cgs new file mode 100644 index 00000000000..97e00d9e00a --- /dev/null +++ b/sim/testsuite/sim/fr30/ldub.cgs @@ -0,0 +1,115 @@ +# fr30 testcase for +# mach(): fr30 +# ldub $Rj,$Ri +# ldub @($R13,$Rj),$Ri +# ldub @($R14,$disp8),$Ri + + .include "testutils.inc" + + START + + .text + .global ldub +ldub: + ; Test ldub $Rj,$Ri + mvi_h_mem #0x00adbeef,sp + set_cc 0x0f ; condition codes should not change + ldub @sp,r7 + test_cc 1 1 1 1 + test_h_gr 0,r7 + + mvi_h_mem #0x01adbeef,sp + set_cc 0x07 ; condition codes should not change + ldub @sp,r7 + test_cc 0 1 1 1 + test_h_gr 1,r7 + + mvi_h_mem #0x7fadbeef,sp + set_cc 0x0b ; condition codes should not change + ldub @sp,r7 + test_cc 1 0 1 1 + test_h_gr 0x7f,r7 + + mvi_h_mem #0x80adbeef,sp + set_cc 0x0d ; condition codes should not change + ldub @sp,r7 + test_cc 1 1 0 1 + test_h_gr 0x80,r7 + + mvi_h_mem #0xffadbeef,sp + set_cc 0x0e ; condition codes should not change + ldub @sp,r7 + test_cc 1 1 1 0 + test_h_gr 0xff,r7 + + ; Test ldub @($R13,$Rj),$Ri + mvr_h_gr sp,r13 + inci_h_gr -8,r13 + mvi_h_gr 8,r8 + + mvi_h_mem #0x00adbeef,sp + set_cc 0x0f ; condition codes should not change + ldub @(r13,r8),r7 + test_cc 1 1 1 1 + test_h_gr 0,r7 + + mvi_h_mem #0x01adbeef,sp + set_cc 0x07 ; condition codes should not change + ldub @(r13,r8),r7 + test_cc 0 1 1 1 + test_h_gr 1,r7 + + mvi_h_mem #0x7fadbeef,sp + set_cc 0x0b ; condition codes should not change + ldub @(r13,r8),r7 + test_cc 1 0 1 1 + test_h_gr 0x7f,r7 + + mvi_h_mem #0x80adbeef,sp + set_cc 0x0d ; condition codes should not change + ldub @(r13,r8),r7 + test_cc 1 1 0 1 + test_h_gr 0x80,r7 + + mvi_h_mem #0xffadbeef,sp + set_cc 0x0e ; condition codes should not change + ldub @(r13,r8),r7 + test_cc 1 1 1 0 + test_h_gr 0xff,r7 + + ; Test ldub @($R14,$disp8),$Ri + mvi_h_mem #0xdeadbeef,sp + mvr_h_gr sp,r14 + mvi_h_gr -0x7f,r8 + add_h_gr r8,r14 + + set_cc 0x0f ; condition codes should not change + lduh @(r14,0x7f),r7 + test_cc 1 1 1 1 + test_h_gr 0xde,r7 + + inci_h_gr 0x3e,r14 + set_cc 0x07 ; condition codes should not change + lduh @(r14,0x40),r7 + test_cc 0 1 1 1 + test_h_gr 0xde,r7 + + inci_h_gr 0x40,r14 + set_cc 0x0b ; condition codes should not change + lduh @(r14,0x0),r7 + test_cc 1 0 1 1 + test_h_gr 0xde,r7 + + inci_h_gr 0x40,r14 + set_cc 0x0d ; condition codes should not change + lduh @(r14,-0x40),r7 + test_cc 1 1 0 1 + test_h_gr 0xde,r7 + + inci_h_gr 0x40,r14 + set_cc 0x0e ; condition codes should not change + lduh @(r14,-0x80),r7 + test_cc 1 1 1 0 + test_h_gr 0xde,r7 + + pass diff --git a/sim/testsuite/sim/fr30/lduh.cgs b/sim/testsuite/sim/fr30/lduh.cgs new file mode 100644 index 00000000000..7d36b75cbcc --- /dev/null +++ b/sim/testsuite/sim/fr30/lduh.cgs @@ -0,0 +1,115 @@ +# fr30 testcase for +# mach(): fr30 +# lduh $Rj,$Ri +# lduh @($R13,$Rj),$Ri +# lduh @($R14,$disp9),$Ri + + .include "testutils.inc" + + START + + .text + .global lduh +lduh: + ; Test lduh $Rj,$Ri + mvi_h_mem #0x0000beef,sp + set_cc 0x0f ; condition codes should not change + lduh @sp,r7 + test_cc 1 1 1 1 + test_h_gr 0,r7 + + mvi_h_mem #0x0001beef,sp + set_cc 0x07 ; condition codes should not change + lduh @sp,r7 + test_cc 0 1 1 1 + test_h_gr 1,r7 + + mvi_h_mem #0x7fffbeef,sp + set_cc 0x0b ; condition codes should not change + lduh @sp,r7 + test_cc 1 0 1 1 + test_h_gr 0x7fff,r7 + + mvi_h_mem #0x8000beef,sp + set_cc 0x0d ; condition codes should not change + lduh @sp,r7 + test_cc 1 1 0 1 + test_h_gr 0x8000,r7 + + mvi_h_mem #0xffffbeef,sp + set_cc 0x0e ; condition codes should not change + lduh @sp,r7 + test_cc 1 1 1 0 + test_h_gr 0xffff,r7 + + ; Test lduh @($R13,$Rj),$Ri + mvr_h_gr sp,r13 + inci_h_gr -8,r13 + mvi_h_gr 8,r8 + + mvi_h_mem #0x0000beef,sp + set_cc 0x0f ; condition codes should not change + lduh @(r13,r8),r7 + test_cc 1 1 1 1 + test_h_gr 0,r7 + + mvi_h_mem #0x0001beef,sp + set_cc 0x07 ; condition codes should not change + lduh @(r13,r8),r7 + test_cc 0 1 1 1 + test_h_gr 1,r7 + + mvi_h_mem #0x7fffbeef,sp + set_cc 0x0b ; condition codes should not change + lduh @(r13,r8),r7 + test_cc 1 0 1 1 + test_h_gr 0x7fff,r7 + + mvi_h_mem #0x8000beef,sp + set_cc 0x0d ; condition codes should not change + lduh @(r13,r8),r7 + test_cc 1 1 0 1 + test_h_gr 0x8000,r7 + + mvi_h_mem #0xffffbeef,sp + set_cc 0x0e ; condition codes should not change + lduh @(r13,r8),r7 + test_cc 1 1 1 0 + test_h_gr 0xffff,r7 + + ; Test lduh @($R14,$disp9),$Ri + mvi_h_mem #0xdeadbeef,sp + mvr_h_gr sp,r14 + mvi_h_gr -0xfe,r8 + add_h_gr r8,r14 + + set_cc 0x0f ; condition codes should not change + lduh @(r14,0xfe),r7 + test_cc 1 1 1 1 + test_h_gr 0xdead,r7 + + inci_h_gr 0x7e,r14 + set_cc 0x07 ; condition codes should not change + lduh @(r14,0x80),r7 + test_cc 0 1 1 1 + test_h_gr 0xdead,r7 + + inci_h_gr 0x80,r14 + set_cc 0x0b ; condition codes should not change + lduh @(r14,0x0),r7 + test_cc 1 0 1 1 + test_h_gr 0xdead,r7 + + inci_h_gr 0x80,r14 + set_cc 0x0d ; condition codes should not change + lduh @(r14,-0x80),r7 + test_cc 1 1 0 1 + test_h_gr 0xdead,r7 + + inci_h_gr 0x80,r14 + set_cc 0x0e ; condition codes should not change + lduh @(r14,-0x100),r7 + test_cc 1 1 1 0 + test_h_gr 0xdead,r7 + + pass diff --git a/sim/testsuite/sim/fr30/leave.cgs b/sim/testsuite/sim/fr30/leave.cgs new file mode 100644 index 00000000000..4d3dd70100e --- /dev/null +++ b/sim/testsuite/sim/fr30/leave.cgs @@ -0,0 +1,23 @@ +# fr30 testcase for leave +# mach(): fr30 + + .include "testutils.inc" + + START + + .text + .global leave +leave: + ; Test leave $u10 + mvr_h_gr sp,r7 ; save Stack pointer + mvr_h_gr sp,r14 + inci_h_gr -4,r14 + mvi_h_mem 0xdeadbeef,r14 + mvi_h_gr 0xbeefdead,r15 + set_cc 0x0f ; Condition codes are irrelevent + leave + test_cc 1 1 1 1 + testr_h_gr sp,r7 + test_h_gr 0xdeadbeef,r14 + + pass diff --git a/sim/testsuite/sim/fr30/lsl.cgs b/sim/testsuite/sim/fr30/lsl.cgs new file mode 100644 index 00000000000..ead749fbbb5 --- /dev/null +++ b/sim/testsuite/sim/fr30/lsl.cgs @@ -0,0 +1,65 @@ +# fr30 testcase for lsl $Rj,$Ri, lsl $u4,$Rj +# mach(): fr30 + + .include "testutils.inc" + + START + + .text + .global lsl +lsl: + ; Test lsl $Rj,$Ri + mvi_h_gr 0xdeadbee0,r7 ; Shift by 0 + mvi_h_gr 2,r8 + set_cc 0x0d ; Set mask opposite of expected + lsl r7,r8 + test_cc 0 0 0 0 + test_h_gr 2,r8 + + mvi_h_gr 0xdeadbee1,r7 ; Shift by 1 + mvi_h_gr 2,r8 + set_cc 0x0f ; Set mask opposite of expected + lsl r7,r8 + test_cc 0 0 1 0 + test_h_gr 4,r8 + + mvi_h_gr 0xdeadbeff,r7 ; Shift by 31 + mvi_h_gr 1,r8 + set_cc 0x07 ; Set mask opposite of expected + lsl r7,r8 + test_cc 1 0 1 0 + test_h_gr 0x80000000,r8 + + mvi_h_gr 0xdeadbeff,r7 ; clear register + mvi_h_gr 2,r8 + set_cc 0x0a ; Set mask opposite of expected + lsl r7,r8 + test_cc 0 1 1 1 + test_h_gr 0x00000000,r8 + + ; Test lsl $u4Ri + mvi_h_gr 2,r8 + set_cc 0x0d ; Set mask opposite of expected + lsl 0,r8 + test_cc 0 0 0 0 + test_h_gr 2,r8 + + mvi_h_gr 2,r8 + set_cc 0x0f ; Set mask opposite of expected + lsl 1,r8 + test_cc 0 0 1 0 + test_h_gr 4,r8 + + mvi_h_gr 1,r8 + set_cc 0x0e ; Set mask opposite of expected + lsl 15,r8 + test_cc 0 0 1 0 + test_h_gr 0x00008000,r8 + + mvi_h_gr 0x00020000,r8 + set_cc 0x0a ; Set mask opposite of expected + lsl 15,r8 + test_cc 0 1 1 1 + test_h_gr 0x00000000,r8 + + pass diff --git a/sim/testsuite/sim/fr30/lsl2.cgs b/sim/testsuite/sim/fr30/lsl2.cgs new file mode 100644 index 00000000000..58acf84ef2c --- /dev/null +++ b/sim/testsuite/sim/fr30/lsl2.cgs @@ -0,0 +1,36 @@ +# fr30 testcase for lsl2 $Rj,$Ri, lsl2 $u4,$Rj +# mach(): fr30 + + .include "testutils.inc" + + START + + .text + .global lsl2 +lsl2: + ; Test lsl2 $u4Ri + mvi_h_gr 2,r8 + set_cc 0x0d ; Set mask opposite of expected + lsl2 0,r8 + test_cc 0 0 0 0 + test_h_gr 0x20000,r8 + + mvi_h_gr 2,r8 + set_cc 0x0f ; Set mask opposite of expected + lsl2 1,r8 + test_cc 0 0 1 0 + test_h_gr 0x40000,r8 + + mvi_h_gr 1,r8 + set_cc 0x07 ; Set mask opposite of expected + lsl2 15,r8 + test_cc 1 0 1 0 + test_h_gr 0x80000000,r8 + + mvi_h_gr 2,r8 + set_cc 0x0a ; Set mask opposite of expected + lsl2 15,r8 + test_cc 0 1 1 1 + test_h_gr 0x00000000,r8 + + pass diff --git a/sim/testsuite/sim/fr30/lsr.cgs b/sim/testsuite/sim/fr30/lsr.cgs new file mode 100644 index 00000000000..5b9587fe71f --- /dev/null +++ b/sim/testsuite/sim/fr30/lsr.cgs @@ -0,0 +1,65 @@ +# fr30 testcase for lsr $Rj,$Ri, lsr $u4,$Rj +# mach(): fr30 + + .include "testutils.inc" + + START + + .text + .global lsr +lsr: + ; Test lsr $Rj,$Ri + mvi_h_gr 0xdeadbee0,r7 ; Shift by 0 + mvi_h_gr 0x80000000,r8 + set_cc 0x05 ; Set mask opposite of expected + lsr r7,r8 + test_cc 1 0 0 0 + test_h_gr 0x80000000,r8 + + mvi_h_gr 0xdeadbee1,r7 ; Shift by 1 + mvi_h_gr 0x80000000,r8 + set_cc 0x0f ; Set mask opposite of expected + lsr r7,r8 + test_cc 0 0 1 0 + test_h_gr 0x40000000,r8 + + mvi_h_gr 0xdeadbeff,r7 ; Shift by 31 + mvi_h_gr 0x80000000,r8 + set_cc 0x0f ; Set mask opposite of expected + lsr r7,r8 + test_cc 0 0 1 0 + test_h_gr 1,r8 + + mvi_h_gr 0xdeadbeff,r7 ; clear register + mvi_h_gr 0x40000000,r8 + set_cc 0x0a ; Set mask opposite of expected + lsr r7,r8 + test_cc 0 1 1 1 + test_h_gr 0x00000000,r8 + + ; Test lsr $u4Ri + mvi_h_gr 0x80000000,r8 + set_cc 0x05 ; Set mask opposite of expected + lsr 0,r8 + test_cc 1 0 0 0 + test_h_gr 0x80000000,r8 + + mvi_h_gr 0x80000000,r8 + set_cc 0x0f ; Set mask opposite of expected + lsr 1,r8 + test_cc 0 0 1 0 + test_h_gr 0x40000000,r8 + + mvi_h_gr 0x80000000,r8 + set_cc 0x0e ; Set mask opposite of expected + lsr 15,r8 + test_cc 0 0 1 0 + test_h_gr 0x00010000,r8 + + mvi_h_gr 0x00004000,r8 + set_cc 0x0a ; Set mask opposite of expected + lsr 15,r8 + test_cc 0 1 1 1 + test_h_gr 0x00000000,r8 + + pass diff --git a/sim/testsuite/sim/fr30/lsr2.cgs b/sim/testsuite/sim/fr30/lsr2.cgs new file mode 100644 index 00000000000..fd6ceaa9ff7 --- /dev/null +++ b/sim/testsuite/sim/fr30/lsr2.cgs @@ -0,0 +1,36 @@ +# fr30 testcase for lsr2 $u4,$Rj +# mach(): fr30 + + .include "testutils.inc" + + START + + .text + .global lsr2 +lsr2: + ; Test lsr2 $u4Ri + mvi_h_gr 0x80000000,r8 + set_cc 0x0d ; Set mask opposite of expected + lsr2 0,r8 + test_cc 0 0 0 0 + test_h_gr 0x00008000,r8 + + mvi_h_gr 0x80000000,r8 + set_cc 0x0f ; Set mask opposite of expected + lsr2 1,r8 + test_cc 0 0 1 0 + test_h_gr 0x00004000,r8 + + mvi_h_gr 0x80000000,r8 + set_cc 0x0e ; Set mask opposite of expected + lsr2 15,r8 + test_cc 0 0 1 0 + test_h_gr 1,r8 + + mvi_h_gr 0x40000000,r8 + set_cc 0x0a ; Set mask opposite of expected + lsr2 15,r8 + test_cc 0 1 1 1 + test_h_gr 0x00000000,r8 + + pass diff --git a/sim/testsuite/sim/fr30/misc.exp b/sim/testsuite/sim/fr30/misc.exp new file mode 100644 index 00000000000..da1490dd9e4 --- /dev/null +++ b/sim/testsuite/sim/fr30/misc.exp @@ -0,0 +1,20 @@ +# Miscellaneous FR30 simulator testcases + +if [istarget fr30*-*-*] { + # load support procs + # load_lib cgen.exp + + # all machines + set all_machs "fr30" + + # The .ms suffix is for "miscellaneous .s". + foreach src [lsort [glob -nocomplain $srcdir/$subdir/*.ms]] { + # If we're only testing specific files and this isn't one of them, + # skip it. + if ![runtest_file_p $runtests $src] { + continue + } + + run_sim_test $src $all_machs + } +} diff --git a/sim/testsuite/sim/fr30/mov.cgs b/sim/testsuite/sim/fr30/mov.cgs new file mode 100644 index 00000000000..bf99252f061 --- /dev/null +++ b/sim/testsuite/sim/fr30/mov.cgs @@ -0,0 +1,108 @@ +# fr30 testcase for mov $Rj,$Ri +# mach(): fr30 + + .include "testutils.inc" + + START + + .text + .global mov +mov: + ; Test mov $Rj,$Ri + mvi_h_gr 1,r7 + mvi_h_dr 0xa,tbr + mvi_h_dr 0xb,rp + mvi_h_dr 0xc,mdh + mvi_h_dr 0xd,mdl + mvr_h_gr sp,ssp + mvr_h_gr sp,usp + + mov r7,r7 + set_cc 0x0f ; Condition codes should not change + test_cc 1 1 1 1 + test_h_gr 1,r7 + + mov r7,r8 + set_cc 0x0e ; Condition codes should not change + test_cc 1 1 1 0 + test_h_gr 1,r7 + test_h_gr 1,r8 + + ; Test mov $Rs,$Ri + set_cc 0x0d ; Condition codes should not change + mov tbr,r7 + test_cc 1 1 0 1 + test_h_gr 0xa,r7 + + set_cc 0x0c ; Condition codes should not change + mov rp,r7 + test_cc 1 1 0 0 + test_h_gr 0xb,r7 + + set_cc 0x0b ; Condition codes should not change + mov mdh,r7 + test_cc 1 0 1 1 + test_h_gr 0xc,r7 + + set_cc 0x0a ; Condition codes should not change + mov mdl,r7 + test_cc 1 0 1 0 + test_h_gr 0xd,r7 + + set_cc 0x09 ; Condition codes should not change + mov usp,r7 + test_cc 1 0 0 1 + testr_h_gr sp,r7 + + set_cc 0x08 ; Condition codes should not change + mov ssp,r7 + test_cc 1 0 0 0 + testr_h_gr sp,r7 + + ; Test mov $Ri,$Rs + set_cc 0x07 ; Condition codes should not change + mov r8,tbr + test_cc 0 1 1 1 + test_h_dr 0x1,tbr + + set_cc 0x06 ; Condition codes should not change + mov r8,rp + test_cc 0 1 1 0 + test_h_dr 0x1,rp + + set_cc 0x05 ; Condition codes should not change + mov r8,mdh + test_cc 0 1 0 1 + test_h_dr 0x1,mdh + + set_cc 0x04 ; Condition codes should not change + mov r8,mdl + test_cc 0 1 0 0 + test_h_dr 0x1,mdl + + set_cc 0x03 ; Condition codes should not change + mov r8,ssp + test_cc 0 0 1 1 + test_h_dr 0x1,ssp + + set_cc 0x02 ; Condition codes should not change + mov r8,usp + test_cc 0 0 1 0 + test_h_dr 0x1,usp + + ; Test mov $PS,$Ri + set_cc 0x01 ; Condition codes affect result + set_dbits 0x3 + mov ps,r7 + test_cc 0 0 0 1 + test_h_gr 0x00000601,r7 + + ; Test mov $Ri,PS + set_cc 0x01 ; Set opposite of expected + set_dbits 0x1 ; Set opposite of expected + mvi_h_gr 0x0000040e,r7 + mov r7,PS + test_cc 1 1 1 0 + test_dbits 0x2 + + pass diff --git a/sim/testsuite/sim/fr30/mul.cgs b/sim/testsuite/sim/fr30/mul.cgs new file mode 100644 index 00000000000..f7cbf58e50e --- /dev/null +++ b/sim/testsuite/sim/fr30/mul.cgs @@ -0,0 +1,240 @@ +# fr30 testcase for mul $Rj,$Ri +# mach(): fr30 + + .include "testutils.inc" + + START + + .text + .global mul +mul: + ; Test mul $Rj,$Ri + ; Positive operands + mvi_h_gr 3,r7 ; multiply small numbers + mvi_h_gr 2,r8 + set_cc 0x0f ; Set mask opposite of expected + mul r7,r8 + test_cc 0 0 0 1 + test_h_dr 0,mdh + test_h_dr 6,mdl + + mvi_h_gr 1,r7 ; multiply by 1 + mvi_h_gr 2,r8 + set_cc 0x0e ; Set mask opposite of expected + mul r7,r8 + test_cc 0 0 0 0 + test_h_dr 0,mdh + test_h_dr 2,mdl + + mvi_h_gr 2,r7 ; multiply by 1 + mvi_h_gr 1,r8 + set_cc 0x0f ; Set mask opposite of expected + mul r7,r8 + test_cc 0 0 0 1 + test_h_dr 0,mdh + test_h_dr 2,mdl + + mvi_h_gr 0,r7 ; multiply by 0 + mvi_h_gr 2,r8 + set_cc 0x0b ; Set mask opposite of expected + mul r7,r8 + test_cc 0 1 0 1 + test_h_dr 0,mdh + test_h_dr 0,mdl + + mvi_h_gr 2,r7 ; multiply by 0 + mvi_h_gr 0,r8 + set_cc 0x0a ; Set mask opposite of expected + mul r7,r8 + test_cc 0 1 0 0 + test_h_dr 0,mdh + test_h_dr 0,mdl + + mvi_h_gr 0x3fffffff,r7 ; 31 bit result + mvi_h_gr 2,r8 + set_cc 0x0f ; Set mask opposite of expected + mul r7,r8 + test_cc 0 0 0 1 + test_h_dr 0,mdh + test_h_dr 0x7ffffffe,mdl + + mvi_h_gr 0x40000000,r7 ; 32 bit result + mvi_h_gr 2,r8 + set_cc 0x04 ; Set mask opposite of expected + mul r7,r8 + test_cc 1 0 1 0 + test_h_dr 0,mdh + test_h_dr 0x80000000,mdl + + mvi_h_gr 0x40000000,r7 ; 33 bit result + mvi_h_gr 4,r8 + set_cc 0x0d ; Set mask opposite of expected + mul r7,r8 + test_cc 0 0 1 1 + test_h_dr 1,mdh + test_h_dr 0x00000000,mdl + + mvi_h_gr 0x7fffffff,r7 ; max positive result + mvi_h_gr 0x7fffffff,r8 + set_cc 0x0d ; Set mask opposite of expected + mul r7,r8 + test_cc 0 0 1 1 + test_h_dr 0x3fffffff,mdh + test_h_dr 0x00000001,mdl + + ; Mixed operands + mvi_h_gr -3,r7 ; multiply small numbers + mvi_h_gr 2,r8 + set_cc 0x07 ; Set mask opposite of expected + mul r7,r8 + test_cc 1 0 0 1 + test_h_dr -1,mdh + test_h_dr -6,mdl + + mvi_h_gr 3,r7 ; multiply small numbers + mvi_h_gr -2,r8 + set_cc 0x07 ; Set mask opposite of expected + mul r7,r8 + test_cc 1 0 0 1 + test_h_dr -1,mdh + test_h_dr -6,mdl + + mvi_h_gr 1,r7 ; multiply by 1 + mvi_h_gr -2,r8 + set_cc 0x06 ; Set mask opposite of expected + mul r7,r8 + test_cc 1 0 0 0 + test_h_dr -1,mdh + test_h_dr -2,mdl + + mvi_h_gr -2,r7 ; multiply by 1 + mvi_h_gr 1,r8 + set_cc 0x07 ; Set mask opposite of expected + mul r7,r8 + test_cc 1 0 0 1 + test_h_dr -1,mdh + test_h_dr -2,mdl + + mvi_h_gr 0,r7 ; multiply by 0 + mvi_h_gr -2,r8 + set_cc 0x0b ; Set mask opposite of expected + mul r7,r8 + test_cc 0 1 0 1 + test_h_dr 0,mdh + test_h_dr 0,mdl + + mvi_h_gr -2,r7 ; multiply by 0 + mvi_h_gr 0,r8 + set_cc 0x0a ; Set mask opposite of expected + mul r7,r8 + test_cc 0 1 0 0 + test_h_dr 0,mdh + test_h_dr 0,mdl + + mvi_h_gr 0x20000001,r7 ; 31 bit result + mvi_h_gr -2,r8 + set_cc 0x07 ; Set mask opposite of expected + mul r7,r8 + test_cc 1 0 0 1 + test_h_dr 0xffffffff,mdh + test_h_dr 0xbffffffe,mdl + + mvi_h_gr 0x40000000,r7 ; 32 bit result + mvi_h_gr -2,r8 + set_cc 0x06 ; Set mask opposite of expected + mul r7,r8 + test_cc 1 0 0 0 + test_h_dr 0xffffffff,mdh + test_h_dr 0x80000000,mdl + + mvi_h_gr 0x40000001,r7 ; 32 bit result + mvi_h_gr -2,r8 + set_cc 0x0c ; Set mask opposite of expected + mul r7,r8 + test_cc 0 0 1 0 + test_h_dr 0xffffffff,mdh + test_h_dr 0x7ffffffe,mdl + + mvi_h_gr 0x40000000,r7 ; 33 bit result + mvi_h_gr -4,r8 + set_cc 0x0d ; Set mask opposite of expected + mul r7,r8 + test_cc 0 0 1 1 + test_h_dr 0xffffffff,mdh + test_h_dr 0x00000000,mdl + + mvi_h_gr 0x7fffffff,r7 ; max negative result + mvi_h_gr 0x80000000,r8 + set_cc 0x05 ; Set mask opposite of expected + mul r7,r8 + test_cc 1 0 1 1 + test_h_dr 0xc0000000,mdh + test_h_dr 0x80000000,mdl + + ; Negative operands + mvi_h_gr -3,r7 ; multiply small numbers + mvi_h_gr -2,r8 + set_cc 0x0f ; Set mask opposite of expected + mul r7,r8 + test_cc 0 0 0 1 + test_h_dr 0,mdh + test_h_dr 6,mdl + + mvi_h_gr -1,r7 ; multiply by 1 + mvi_h_gr -2,r8 + set_cc 0x0e ; Set mask opposite of expected + mul r7,r8 + test_cc 0 0 0 0 + test_h_dr 0,mdh + test_h_dr 2,mdl + + mvi_h_gr -2,r7 ; multiply by 1 + mvi_h_gr -1,r8 + set_cc 0x0f ; Set mask opposite of expected + mul r7,r8 + test_cc 0 0 0 1 + test_h_dr 0,mdh + test_h_dr 2,mdl + + mvi_h_gr 0xc0000001,r7 ; 31 bit result + mvi_h_gr -2,r8 + set_cc 0x0f ; Set mask opposite of expected + mul r7,r8 + test_cc 0 0 0 1 + test_h_dr 0,mdh + test_h_dr 0x7ffffffe,mdl + + mvi_h_gr 0xc0000000,r7 ; 32 bit result + mvi_h_gr -2,r8 + set_cc 0x04 ; Set mask opposite of expected + mul r7,r8 + test_cc 1 0 1 0 + test_h_dr 0,mdh + test_h_dr 0x80000000,mdl + + mvi_h_gr 0xc0000000,r7 ; 33 bit result + mvi_h_gr -4,r8 + set_cc 0x0d ; Set mask opposite of expected + mul r7,r8 + test_cc 0 0 1 1 + test_h_dr 1,mdh + test_h_dr 0x00000000,mdl + + mvi_h_gr 0x80000001,r7 ; almost max positive result + mvi_h_gr 0x80000001,r8 + set_cc 0x0d ; Set mask opposite of expected + mul r7,r8 + test_cc 0 0 1 1 + test_h_dr 0x3fffffff,mdh + test_h_dr 0x00000001,mdl + + + mvi_h_gr 0x80000000,r7 ; max positive result + mvi_h_gr 0x80000000,r8 + set_cc 0x0d ; Set mask opposite of expected + mul r7,r8 + test_cc 0 0 1 1 + test_h_dr 0x40000000,mdh + test_h_dr 0x00000000,mdl + + pass diff --git a/sim/testsuite/sim/fr30/mulh.cgs b/sim/testsuite/sim/fr30/mulh.cgs new file mode 100644 index 00000000000..1421f07b31a --- /dev/null +++ b/sim/testsuite/sim/fr30/mulh.cgs @@ -0,0 +1,211 @@ +# fr30 testcase for mulh $Rj,$Ri +# mach(): fr30 + + .include "testutils.inc" + + START + + .text + .global mulh +mulh: + ; Test mulh $Rj,$Ri + ; Positive operands + mvi_h_gr 0xdead0003,r7 ; multiply small numbers + mvi_h_gr 0xbeef0002,r8 + set_cc 0x09 ; Set mask opposite of expected + mulh r7,r8 + test_cc 0 1 0 1 + test_h_dr 6,mdl + + mvi_h_gr 0xdead0001,r7 ; multiply by 1 + mvi_h_gr 0xbeef0002,r8 + set_cc 0x08 ; Set mask opposite of expected + mulh r7,r8 + test_cc 0 1 0 0 + test_h_dr 2,mdl + + mvi_h_gr 0xdead0002,r7 ; multiply by 1 + mvi_h_gr 0xbeef0001,r8 + set_cc 0x09 ; Set mask opposite of expected + mulh r7,r8 + test_cc 0 1 0 1 + test_h_dr 2,mdl + + mvi_h_gr 0xdead0000,r7 ; multiply by 0 + mvi_h_gr 0xbeef0002,r8 + set_cc 0x09 ; Set mask opposite of expected + mulh r7,r8 + test_cc 0 1 0 1 + test_h_dr 0,mdl + + mvi_h_gr 0xdead0002,r7 ; multiply by 0 + mvi_h_gr 0xbeef0000,r8 + set_cc 0x08 ; Set mask opposite of expected + mulh r7,r8 + test_cc 0 1 0 0 + test_h_dr 0,mdl + + mvi_h_gr 0xdead3fff,r7 ; 15 bit result + mvi_h_gr 0xbeef0002,r8 + set_cc 0x09 ; Set mask opposite of expected + mulh r7,r8 + test_cc 0 1 0 1 + test_h_dr 0x00007ffe,mdl + + mvi_h_gr 0xdead4000,r7 ; 16 bit result + mvi_h_gr 0xbeef0002,r8 + set_cc 0x0a ; Set mask opposite of expected + mulh r7,r8 + test_cc 0 1 1 0 + test_h_dr 0x00008000,mdl + + mvi_h_gr 0xdead4000,r7 ; 17 bit result + mvi_h_gr 0xbeef0004,r8 + set_cc 0x0b ; Set mask opposite of expected + mulh r7,r8 + test_cc 0 1 1 1 + test_h_dr 0x00010000,mdl + + mvi_h_gr 0xdead7fff,r7 ; max positive result + mvi_h_gr 0xbeef7fff,r8 + set_cc 0x0b ; Set mask opposite of expected + mulh r7,r8 + test_cc 0 1 1 1 + test_h_dr 0x3fff0001,mdl + + ; Mixed operands + mvi_h_gr -3,r7 ; multiply small numbers + mvi_h_gr 2,r8 + set_cc 0x05 ; Set mask opposite of expected + mulh r7,r8 + test_cc 1 0 0 1 + test_h_dr -6,mdl + + mvi_h_gr 3,r7 ; multiply small numbers + mvi_h_gr -2,r8 + set_cc 0x05 ; Set mask opposite of expected + mulh r7,r8 + test_cc 1 0 0 1 + test_h_dr -6,mdl + + mvi_h_gr 1,r7 ; multiply by 1 + mvi_h_gr -2,r8 + set_cc 0x04 ; Set mask opposite of expected + mulh r7,r8 + test_cc 1 0 0 0 + test_h_dr -2,mdl + + mvi_h_gr -2,r7 ; multiply by 1 + mvi_h_gr 1,r8 + set_cc 0x05 ; Set mask opposite of expected + mulh r7,r8 + test_cc 1 0 0 1 + test_h_dr -2,mdl + + mvi_h_gr 0,r7 ; multiply by 0 + mvi_h_gr -2,r8 + set_cc 0x09 ; Set mask opposite of expected + mulh r7,r8 + test_cc 0 1 0 1 + test_h_dr 0,mdl + + mvi_h_gr -2,r7 ; multiply by 0 + mvi_h_gr 0,r8 + set_cc 0x08 ; Set mask opposite of expected + mulh r7,r8 + test_cc 0 1 0 0 + test_h_dr 0,mdl + + mvi_h_gr 0xdead2001,r7 ; 15 bit result + mvi_h_gr -2,r8 + set_cc 0x05 ; Set mask opposite of expected + mulh r7,r8 + test_cc 1 0 0 1 + test_h_dr 0xffffbffe,mdl + + mvi_h_gr 0xdead4000,r7 ; 16 bit result + mvi_h_gr -2,r8 + set_cc 0x04 ; Set mask opposite of expected + mulh r7,r8 + test_cc 1 0 0 0 + test_h_dr 0xffff8000,mdl + + mvi_h_gr 0xdead4001,r7 ; 16 bit result + mvi_h_gr -2,r8 + set_cc 0x06 ; Set mask opposite of expected + mulh r7,r8 + test_cc 1 0 1 0 + test_h_dr 0xffff7ffe,mdl + + mvi_h_gr 0xdead4000,r7 ; 17 bit result + mvi_h_gr -4,r8 + set_cc 0x07 ; Set mask opposite of expected + mulh r7,r8 + test_cc 1 0 1 1 + test_h_dr 0xffff0000,mdl + + mvi_h_gr 0xdead7fff,r7 ; max negative result + mvi_h_gr 0xbeef8000,r8 + set_cc 0x07 ; Set mask opposite of expected + mulh r7,r8 + test_cc 1 0 1 1 + test_h_dr 0xc0008000,mdl + + ; Negative operands + mvi_h_gr -3,r7 ; multiply small numbers + mvi_h_gr -2,r8 + set_cc 0x09 ; Set mask opposite of expected + mulh r7,r8 + test_cc 0 1 0 1 + test_h_dr 6,mdl + + mvi_h_gr -1,r7 ; multiply by 1 + mvi_h_gr -2,r8 + set_cc 0x08 ; Set mask opposite of expected + mulh r7,r8 + test_cc 0 1 0 0 + test_h_dr 2,mdl + + mvi_h_gr -2,r7 ; multiply by 1 + mvi_h_gr -1,r8 + set_cc 0x09 ; Set mask opposite of expected + mulh r7,r8 + test_cc 0 1 0 1 + test_h_dr 2,mdl + + mvi_h_gr 0xdeadc001,r7 ; 15 bit result + mvi_h_gr -2,r8 + set_cc 0x09 ; Set mask opposite of expected + mulh r7,r8 + test_cc 0 1 0 1 + test_h_dr 0x00007ffe,mdl + + mvi_h_gr 0xdeadc000,r7 ; 16 bit result + mvi_h_gr -2,r8 + set_cc 0x0a ; Set mask opposite of expected + mulh r7,r8 + test_cc 0 1 1 0 + test_h_dr 0x00008000,mdl + + mvi_h_gr 0xdeadc000,r7 ; 17 bit result + mvi_h_gr -4,r8 + set_cc 0x0b ; Set mask opposite of expected + mulh r7,r8 + test_cc 0 1 1 1 + test_h_dr 0x00010000,mdl + + mvi_h_gr 0xdead8001,r7 ; almost max positive result + mvi_h_gr 0xbeef8001,r8 + set_cc 0x0b ; Set mask opposite of expected + mulh r7,r8 + test_cc 0 1 1 1 + test_h_dr 0x3fff0001,mdl + + mvi_h_gr 0xdead8000,r7 ; max positive result + mvi_h_gr 0xbeef8000,r8 + set_cc 0x0b ; Set mask opposite of expected + mulh r7,r8 + test_cc 0 1 1 1 + test_h_dr 0x40000000,mdl + + pass diff --git a/sim/testsuite/sim/fr30/mulu.cgs b/sim/testsuite/sim/fr30/mulu.cgs new file mode 100644 index 00000000000..477583b224d --- /dev/null +++ b/sim/testsuite/sim/fr30/mulu.cgs @@ -0,0 +1,101 @@ +# fr30 testcase for mulu $Rj,$Ri +# mach(): fr30 + + .include "testutils.inc" + + START + + .text + .global mulu +mulu: + ; Test mulu $Rj,$Ri + ; Positive operands + mvi_h_gr 3,r7 ; multiply small numbers + mvi_h_gr 2,r8 + set_cc 0x0f ; Set mask opposite of expected + mulu r7,r8 + test_cc 0 0 0 1 + test_h_dr 0,mdh + test_h_dr 6,mdl + + mvi_h_gr 1,r7 ; multiply by 1 + mvi_h_gr 2,r8 + set_cc 0x0e ; Set mask opposite of expected + mulu r7,r8 + test_cc 0 0 0 0 + test_h_dr 0,mdh + test_h_dr 2,mdl + + mvi_h_gr 2,r7 ; multiply by 1 + mvi_h_gr 1,r8 + set_cc 0x0f ; Set mask opposite of expected + mulu r7,r8 + test_cc 0 0 0 1 + test_h_dr 0,mdh + test_h_dr 2,mdl + + mvi_h_gr 0,r7 ; multiply by 0 + mvi_h_gr 2,r8 + set_cc 0x0b ; Set mask opposite of expected + mulu r7,r8 + test_cc 0 1 0 1 + test_h_dr 0,mdh + test_h_dr 0,mdl + + mvi_h_gr 2,r7 ; multiply by 0 + mvi_h_gr 0,r8 + set_cc 0x0a ; Set mask opposite of expected + mulu r7,r8 + test_cc 0 1 0 0 + test_h_dr 0,mdh + test_h_dr 0,mdl + + mvi_h_gr 0x3fffffff,r7 ; 31 bit result + mvi_h_gr 2,r8 + set_cc 0x0f ; Set mask opposite of expected + mulu r7,r8 + test_cc 0 0 0 1 + test_h_dr 0,mdh + test_h_dr 0x7ffffffe,mdl + + mvi_h_gr 0x40000000,r7 ; 32 bit result + mvi_h_gr 2,r8 + set_cc 0x0e ; Set mask opposite of expected + mulu r7,r8 + test_cc 0 0 0 0 + test_h_dr 0,mdh + test_h_dr 0x80000000,mdl + + mvi_h_gr 0x80000000,r7 ; 33 bit result + mvi_h_gr 2,r8 + set_cc 0x09 ; Set mask opposite of expected + mulu r7,r8 + test_cc 0 1 1 1 + test_h_dr 1,mdh + test_h_dr 0x00000000,mdl + + mvi_h_gr 0x7fffffff,r7 ; max positive result + mvi_h_gr 0x7fffffff,r8 + set_cc 0x0d ; Set mask opposite of expected + mulu r7,r8 + test_cc 0 0 1 1 + test_h_dr 0x3fffffff,mdh + test_h_dr 0x00000001,mdl + + mvi_h_gr 0x80000000,r7 ; max positive result + mvi_h_gr 0x80000000,r8 + set_cc 0x09 ; Set mask opposite of expected + mulu r7,r8 + test_cc 0 1 1 1 + test_h_dr 0x40000000,mdh + test_h_dr 0x00000000,mdl + + mvi_h_gr 0xffffffff,r7 ; max positive result + mvi_h_gr 0xffffffff,r8 + set_cc 0x05 ; Set mask opposite of expected + mulu r7,r8 + test_cc 1 0 1 1 + test_h_dr 0xfffffffe,mdh + test_h_dr 0x00000001,mdl + + pass diff --git a/sim/testsuite/sim/fr30/muluh.cgs b/sim/testsuite/sim/fr30/muluh.cgs new file mode 100644 index 00000000000..b0c847e1b97 --- /dev/null +++ b/sim/testsuite/sim/fr30/muluh.cgs @@ -0,0 +1,90 @@ +# fr30 testcase for muluh $Rj,$Ri +# mach(): fr30 + + .include "testutils.inc" + + START + + .text + .global muluh +muluh: + ; Test muluh $Rj,$Ri + ; Positive operands + mvi_h_gr 0xdead0003,r7 ; multiply small numbers + mvi_h_gr 0xbeef0002,r8 + set_cc 0x09 ; Set mask opposite of expected + muluh r7,r8 + test_cc 0 1 0 1 + test_h_dr 6,mdl + + mvi_h_gr 0xdead0001,r7 ; multiply by 1 + mvi_h_gr 0xbeef0002,r8 + set_cc 0x08 ; Set mask opposite of expected + muluh r7,r8 + test_cc 0 1 0 0 + test_h_dr 2,mdl + + mvi_h_gr 0xdead0002,r7 ; multiply by 1 + mvi_h_gr 0xbeef0001,r8 + set_cc 0x09 ; Set mask opposite of expected + muluh r7,r8 + test_cc 0 1 0 1 + test_h_dr 2,mdl + + mvi_h_gr 0xdead0000,r7 ; multiply by 0 + mvi_h_gr 0xbeef0002,r8 + set_cc 0x09 ; Set mask opposite of expected + muluh r7,r8 + test_cc 0 1 0 1 + test_h_dr 0,mdl + + mvi_h_gr 0xdead0002,r7 ; multiply by 0 + mvi_h_gr 0xbeef0000,r8 + set_cc 0x08 ; Set mask opposite of expected + muluh r7,r8 + test_cc 0 1 0 0 + test_h_dr 0,mdl + + mvi_h_gr 0xdead3fff,r7 ; 15 bit result + mvi_h_gr 0xbeef0002,r8 + set_cc 0x09 ; Set mask opposite of expected + muluh r7,r8 + test_cc 0 1 0 1 + test_h_dr 0x00007ffe,mdl + + mvi_h_gr 0xdead4000,r7 ; 16 bit result + mvi_h_gr 0xbeef0002,r8 + set_cc 0x08 ; Set mask opposite of expected + muluh r7,r8 + test_cc 0 1 0 0 + test_h_dr 0x00008000,mdl + + mvi_h_gr 0xdead8000,r7 ; 17 bit result + mvi_h_gr 0xbeef0002,r8 + set_cc 0x0b ; Set mask opposite of expected + muluh r7,r8 + test_cc 0 1 1 1 + test_h_dr 0x00010000,mdl + + mvi_h_gr 0xdead7fff,r7 ; max positive result + mvi_h_gr 0xbeef7fff,r8 + set_cc 0x0b ; Set mask opposite of expected + muluh r7,r8 + test_cc 0 1 1 1 + test_h_dr 0x3fff0001,mdl + + mvi_h_gr 0xdead8000,r7 ; max positive result + mvi_h_gr 0xbeef8000,r8 + set_cc 0x0b ; Set mask opposite of expected + muluh r7,r8 + test_cc 0 1 1 1 + test_h_dr 0x40000000,mdl + + mvi_h_gr 0xdeadffff,r7 ; max positive result + mvi_h_gr 0xbeefffff,r8 + set_cc 0x07 ; Set mask opposite of expected + muluh r7,r8 + test_cc 1 0 1 1 + test_h_dr 0xfffe0001,mdl + + pass diff --git a/sim/testsuite/sim/fr30/nop.cgs b/sim/testsuite/sim/fr30/nop.cgs new file mode 100644 index 00000000000..885c55cfd1a --- /dev/null +++ b/sim/testsuite/sim/fr30/nop.cgs @@ -0,0 +1,16 @@ +# fr30 testcase for nop +# mach(): fr30 + + .include "testutils.inc" + + START + + .text + .global nop +nop: + ; Test nop + set_cc 0x0f ; Condition codes are irrelevent + nop + test_cc 1 1 1 1 + + pass diff --git a/sim/testsuite/sim/fr30/or.cgs b/sim/testsuite/sim/fr30/or.cgs new file mode 100644 index 00000000000..8acb9702000 --- /dev/null +++ b/sim/testsuite/sim/fr30/or.cgs @@ -0,0 +1,55 @@ +# fr30 testcase for or $Rj,$Ri, or $Rj,@$Ri +# mach(): fr30 + + .include "testutils.inc" + + START + + .text + .global or +or: + ; Test or $Rj,$Ri + mvi_h_gr 0xaaaaaaaa,r7 + mvi_h_gr 0x55555555,r8 + set_cc 0x07 ; Set mask opposite of expected + or r7,r8 + test_cc 1 0 1 1 + test_h_gr 0xffffffff,r8 + + mvi_h_gr 0x00000000,r7 + mvi_h_gr 0x00000000,r8 + set_cc 0x08 ; Set mask opposite of expected + or r7,r8 + test_cc 0 1 0 0 + test_h_gr 0x00000000,r8 + + mvi_h_gr 0xdead0000,r7 + mvi_h_gr 0x0000beef,r8 + set_cc 0x05 ; Set mask opposite of expected + or r7,r8 + test_cc 1 0 0 1 + test_h_gr 0xdeadbeef,r8 + + ; Test or $Rj,@$Ri + mvi_h_gr 0xaaaaaaaa,r7 + mvi_h_mem 0x55555555,sp + set_cc 0x07 ; Set mask opposite of expected + or r7,@sp + test_cc 1 0 1 1 + test_h_mem 0xffffffff,sp + + mvi_h_gr 0x00000000,r7 + mvi_h_mem 0x00000000,sp + set_cc 0x08 ; Set mask opposite of expected + or r7,@sp + test_cc 0 1 0 0 + test_h_mem 0x00000000,sp + + mvi_h_gr 0xdead0000,r7 + mvi_h_mem 0x0000beef,sp + set_cc 0x05 ; Set mask opposite of expected + or r7,@sp + test_cc 1 0 0 1 + test_h_mem 0xdeadbeef,sp + + pass diff --git a/sim/testsuite/sim/fr30/orb.cgs b/sim/testsuite/sim/fr30/orb.cgs new file mode 100644 index 00000000000..a7b36bf5284 --- /dev/null +++ b/sim/testsuite/sim/fr30/orb.cgs @@ -0,0 +1,33 @@ +# fr30 testcase for orb $Rj,$Ri, orb $Rj,@$Ri +# mach(): fr30 + + .include "testutils.inc" + + START + + .text + .global orb +orb: + ; Test orb $Rj,@$Ri + mvi_h_gr 0xaaaaaaaa,r7 + mvi_h_mem 0x55555555,sp + set_cc 0x07 ; Set mask opposite of expected + orb r7,@sp + test_cc 1 0 1 1 + test_h_mem 0xff555555,sp + + mvi_h_gr 0xffffff00,r7 + mvi_h_mem 0x00ffffff,sp + set_cc 0x08 ; Set mask opposite of expected + orb r7,@sp + test_cc 0 1 0 0 + test_h_mem 0x00ffffff,sp + + mvi_h_gr 0x000000d0,r7 + mvi_h_mem 0x0eadbeef,sp + set_cc 0x05 ; Set mask opposite of expected + orb r7,@sp + test_cc 1 0 0 1 + test_h_mem 0xdeadbeef,sp + + pass diff --git a/sim/testsuite/sim/fr30/orccr.cgs b/sim/testsuite/sim/fr30/orccr.cgs new file mode 100644 index 00000000000..3bc55a84570 --- /dev/null +++ b/sim/testsuite/sim/fr30/orccr.cgs @@ -0,0 +1,38 @@ +# fr30 testcase for orccr $u8 +# mach(): fr30 + + .include "testutils.inc" + + START + + .text + .global orccr +orccr: + orccr 0xff + test_cc 1 1 1 1 + test_i 1 + test_s_user + + set_cc 0x0f + orccr 0x00 + test_cc 1 1 1 1 + test_i 1 + test_s_user + + set_cc 0x00 + set_i 0 + set_s_system + orccr 0xaa + test_cc 1 0 1 0 + test_i 0 + test_s_user + + set_cc 0x00 + set_i 0 + set_s_system + orccr 0xc0 + test_cc 0 0 0 0 + test_i 0 + test_s_system + + pass diff --git a/sim/testsuite/sim/fr30/orh.cgs b/sim/testsuite/sim/fr30/orh.cgs new file mode 100644 index 00000000000..b30b4028e85 --- /dev/null +++ b/sim/testsuite/sim/fr30/orh.cgs @@ -0,0 +1,33 @@ +# fr30 testcase for orh $Rj,$Ri, orh $Rj,@$Ri +# mach(): fr30 + + .include "testutils.inc" + + START + + .text + .global orh +orh: + ; Test orh $Rj,@$Ri + mvi_h_gr 0xaaaaaaaa,r7 + mvi_h_mem 0x55555555,sp + set_cc 0x07 ; Set mask opposite of expected + orh r7,@sp + test_cc 1 0 1 1 + test_h_mem 0xffff5555,sp + + mvi_h_gr 0xffff0000,r7 + mvi_h_mem 0x0000ffff,sp + set_cc 0x08 ; Set mask opposite of expected + orh r7,@sp + test_cc 0 1 0 0 + test_h_mem 0x0000ffff,sp + + mvi_h_gr 0x0000de00,r7 + mvi_h_mem 0x00adbeef,sp + set_cc 0x05 ; Set mask opposite of expected + orh r7,@sp + test_cc 1 0 0 1 + test_h_mem 0xdeadbeef,sp + + pass diff --git a/sim/testsuite/sim/fr30/ret.cgs b/sim/testsuite/sim/fr30/ret.cgs new file mode 100644 index 00000000000..7bfa0b230f9 --- /dev/null +++ b/sim/testsuite/sim/fr30/ret.cgs @@ -0,0 +1,75 @@ +# fr30 testcase for ret +# mach(): fr30 + + .include "testutils.inc" + + START + + .text + .global ret + + ; Test ret + mvi_h_gr 0xdeadbeef,r9 + mvi_h_gr #func1,r0 + set_cc 0x0f ; condition codes shouldn't change +call1: + call @r0 + testr_h_gr 2,r0 + test_h_gr 0xbeefdead,r9 + pass + +func1: + test_cc 1 1 1 1 + mvi_h_gr #call1,r7 + inci_h_gr 2,r7 + testr_h_dr r7,rp + save_rp + + mvi_h_gr #func2,r0 + set_cc 0x0f ; condition codes shouldn't change +call2: + call:d @r0 + ldi:8 1,r0 ; Must assume this works + testr_h_gr 2,r0 + restore_rp + ret +func2: + test_cc 1 1 1 1 + mvi_h_gr #call2,r7 + inci_h_gr 4,r7 + testr_h_dr r7,rp + testr_h_gr 1,r0 + save_rp + + set_cc 0x0f ; condition codes shouldn't change +call3: + call func3 + testr_h_gr 2,r0 + restore_rp + ret +func3: + test_cc 1 1 1 1 + mvi_h_gr #call3,r7 + inci_h_gr 2,r7 + testr_h_dr r7,rp + save_rp + + set_cc 0x0f ; condition codes shouldn't change +call4: + call:d func4 + ldi:8 1,r0 ; Must assume this works + testr_h_gr 3,r0 + restore_rp + ret:d + ldi:8 2,r0 ; Must assume this works +func4: + test_cc 1 1 1 1 + mvi_h_gr #call4,r7 + inci_h_gr 4,r7 + testr_h_dr r7,rp + testr_h_gr 1,r0 + mvi_h_gr 0xbeefdead,r9 + ret:d + ldi:8 3,r0 ; Must assume this works + + fail diff --git a/sim/testsuite/sim/fr30/reti.cgs b/sim/testsuite/sim/fr30/reti.cgs new file mode 100644 index 00000000000..76a1af0bb82 --- /dev/null +++ b/sim/testsuite/sim/fr30/reti.cgs @@ -0,0 +1,57 @@ +# fr30 testcase for reti +# mach(): fr30 + + .include "testutils.inc" + + START + + .text + .global reti +reti: + ; Test reti with low reset of ilm allowed + mvr_h_gr sp,r8 ; Save stack pointer + set_s_system + set_i 1 + set_ilm 15 ; attempt reset of low range + set_cc 0x0f ; Condition codes should not change + save_ps + inci_h_gr -4,sp + mvi_h_mem ret1,sp + set_i 0 ; Set opposite of expected + set_ilm 0 ; attempt reset of low range + set_cc 0x00 ; Set opposite of expected + + reti + fail + +ret1: + test_cc 1 1 1 1 + test_s_system + test_i 1 + test_ilm 15 + testr_h_gr r8,sp + + ; Test reti with low reset of ilm not allowed + mvr_h_gr sp,r8 ; Save stack pointer + set_s_system + set_i 0 + set_ilm 15 ; attempt reset of low range + set_cc 0x0f ; Condition codes should not change + save_ps + inci_h_gr -4,sp + mvi_h_mem ret2,sp + set_i 0 ; Set opposite of expected + set_ilm 16 ; disallow reset of low range + set_cc 0x00 ; Set opposite of expected + + reti + fail + +ret2: + test_cc 1 1 1 1 + test_s_system + test_i 0 + test_ilm 31 + testr_h_gr r8,sp + + pass diff --git a/sim/testsuite/sim/fr30/st.cgs b/sim/testsuite/sim/fr30/st.cgs new file mode 100644 index 00000000000..e458d14001b --- /dev/null +++ b/sim/testsuite/sim/fr30/st.cgs @@ -0,0 +1,194 @@ +# fr30 testcase for +# mach(): fr30 +# st $Ri,@$Rj + + .include "testutils.inc" + + START + + .text + .global st +st: + mvr_h_gr sp,r9 ; Save stack pointer + ; Test st $Ri,@Rj + mvi_h_gr 0xdeadbeef,r8 + set_cc 0x0f ; Condition codes should not change + st r8,@sp + test_cc 1 1 1 1 + test_h_mem 0xdeadbeef,sp + test_h_gr 0xdeadbeef,r8 + + ; Test st $Ri,@(R13,Rj) + mvi_h_gr 0xbeefdead,r8 + mvr_h_gr sp,r1 + inci_h_gr -8,sp + mvr_h_gr sp,r2 + inci_h_gr 4,sp + + mvi_h_gr 4,r13 + set_cc 0x0e ; Condition codes should not change + st r8,@(r13,sp) + test_cc 1 1 1 0 + test_h_mem 0xbeefdead,r1 + test_h_gr 0xbeefdead,r8 + + mvi_h_gr 0,r13 + set_cc 0x0d ; Condition codes should not change + st r8,@(r13,sp) + test_cc 1 1 0 1 + test_h_mem 0xbeefdead,sp + test_h_gr 0xbeefdead,r8 + + mvi_h_gr -4,r13 + set_cc 0x0c ; Condition codes should not change + st r8,@(r13,sp) + test_cc 1 1 0 0 + test_h_mem 0xbeefdead,r2 + test_h_gr 0xbeefdead,r8 + + ; Test st $Ri,@(R14,$disp10) + mvi_h_gr 0xdeadbeef,r8 + mvr_h_gr r9,sp ; Restore stack pointer + mvr_h_gr sp,r14 + inci_h_gr -508,r14 + mvr_h_gr r14,r2 + inci_h_gr -512,r14 + mvr_h_gr r14,r3 + inci_h_gr 512,r14 + + set_cc 0x0b ; Condition codes should not change + st r8,@(r14,508) + test_cc 1 0 1 1 + test_h_mem 0xdeadbeef,r1 + test_h_gr 0xdeadbeef,r8 + + set_cc 0x0a ; Condition codes should not change + st r8,@(r14,0) + test_cc 1 0 1 0 + test_h_mem 0xdeadbeef,r2 + test_h_gr 0xdeadbeef,r8 + + set_cc 0x09 ; Condition codes should not change + st r8,@(r14,-512) + test_cc 1 0 0 1 + test_h_mem 0xdeadbeef,r3 + test_h_gr 0xdeadbeef,r8 + + ; Test st $Ri,@(R15,$udisp6) + mvi_h_gr 0xbeefdead,r8 + mvr_h_gr r9,sp ; Restore stack pointer + inci_h_gr -60,sp + + set_cc 0x08 ; Condition codes should not change + st r8,@(r15,60) + test_cc 1 0 0 0 + test_h_mem 0xbeefdead,r9 + test_h_gr 0xbeefdead,r8 + + set_cc 0x07 ; Condition codes should not change + st r8,@(r15,0) + test_cc 0 1 1 1 + test_h_mem 0xbeefdead,r9 + test_h_gr 0xbeefdead,r8 + + ; Test st $Ri,@-R15 + mvr_h_gr r9,sp ; Restore stack pointer + mvr_h_gr r9,r10 + + set_cc 0x06 ; Condition codes should not change + st r15,@-r15 + test_cc 0 1 1 0 + testr_h_mem r9,sp ; original value stored + inci_h_gr -4,r10 + testr_h_gr r10,sp ; was decremented + + mvi_h_gr 0xdeadbeef,r8 + set_cc 0x05 ; Condition codes should not change + st r8,@-r15 + test_cc 0 1 0 1 + test_h_mem 0xdeadbeef,sp + test_h_gr 0xdeadbeef,r8 + inci_h_gr -4,r10 + testr_h_gr r10,sp ; was decremented + + ; Test st $Rs,@-R15 + mvr_h_gr r9,sp ; Restore stack pointer + mvr_h_gr r9,r10 + mvi_h_dr 0xbeefdead,tbr + mvi_h_dr 0xdeadbeef,rp + mvi_h_dr 0x0000dead,mdh + mvi_h_dr 0xbeef0000,mdl + + set_cc 0x04 ; Condition codes should not change + st tbr,@-r15 + test_cc 0 1 0 0 + test_h_mem 0xbeefdead,sp + inci_h_gr -4,r10 + testr_h_gr r10,sp ; was decremented + + set_cc 0x03 ; Condition codes should not change + st rp,@-r15 + test_cc 0 0 1 1 + test_h_mem 0xdeadbeef,sp + inci_h_gr -4,r10 + testr_h_gr r10,sp ; was decremented + + set_cc 0x02 ; Condition codes should not change + st mdh,@-r15 + test_cc 0 0 1 0 + test_h_mem 0x0000dead,sp + inci_h_gr -4,r10 + testr_h_gr r10,sp ; was decremented + + set_cc 0x01 ; Condition codes should not change + st mdl,@-r15 + test_cc 0 0 0 1 + test_h_mem 0xbeef0000,sp + inci_h_gr -4,r10 + testr_h_gr r10,sp ; was decremented + + mvr_h_gr sp,usp + set_s_user + set_cc 0x00 ; Condition codes should not change + st ssp,@-r15 + test_cc 0 0 0 0 + testr_h_mem r10,sp + inci_h_gr -4,r10 + testr_h_gr r10,sp ; was decremented + + set_cc 0x00 ; Condition codes should not change + st usp,@-r15 + test_cc 0 0 0 0 + testr_h_mem r10,sp ; original value stored + inci_h_gr -4,r10 + testr_h_gr r10,sp ; was decremented + + mvr_h_gr sp,ssp + set_s_system + set_cc 0x00 ; Condition codes should not change + st usp,@-r15 + test_cc 0 0 0 0 + testr_h_mem r10,sp + inci_h_gr -4,r10 + testr_h_gr r10,sp ; was decremented + + set_cc 0x00 ; Condition codes should not change + st ssp,@-r15 + test_cc 0 0 0 0 + testr_h_mem r10,sp ; original value stored + inci_h_gr -4,r10 + testr_h_gr r10,sp ; was decremented + + ; Test st $PS,@-R15 + mvr_h_gr r9,sp ; Restore stack pointer + mvr_h_gr r9,r10 + + set_cc 0x0f ; Condition codes affect result + set_dbits 3 ; Division bits affect result + st ps,@-r15 + test_cc 1 1 1 1 + test_h_mem 0x0000060f,sp + inci_h_gr -4,r10 + testr_h_gr r10,sp ; was decremented + + pass diff --git a/sim/testsuite/sim/fr30/stb.cgs b/sim/testsuite/sim/fr30/stb.cgs new file mode 100644 index 00000000000..d9d4fd00aed --- /dev/null +++ b/sim/testsuite/sim/fr30/stb.cgs @@ -0,0 +1,84 @@ +# fr30 testcase for +# mach(): fr30 +# stb $Ri,@$Rj + + .include "testutils.inc" + + START + + .text + .global stb +stb: + mvr_h_gr sp,r9 ; Save stack pointer + ; Test stb $Ri,@Rj + mvi_h_mem 0xdeadbeef,sp + mvi_h_gr 0xaaaaaafe,r8 + set_cc 0x0f ; Condition codes should not change + stb r8,@sp + test_cc 1 1 1 1 + test_h_mem 0xfeadbeef,sp + test_h_gr 0xaaaaaafe,r8 + + ; Test stb $Ri,@(R13,Rj) + mvi_h_mem 0xbeefdead,sp + mvi_h_gr 0xaaaaaade,r8 + mvr_h_gr sp,r1 + inci_h_gr -8,sp + mvr_h_gr sp,r2 + mvi_h_mem 0xbeefdead,sp + inci_h_gr 4,sp + mvi_h_mem 0xbeefdead,sp + + mvi_h_gr 4,r13 + set_cc 0x0e ; Condition codes should not change + stb r8,@(r13,sp) + test_cc 1 1 1 0 + test_h_mem 0xdeefdead,r1 + test_h_gr 0xaaaaaade,r8 + + mvi_h_gr 0,r13 + set_cc 0x0d ; Condition codes should not change + stb r8,@(r13,sp) + test_cc 1 1 0 1 + test_h_mem 0xdeefdead,sp + test_h_gr 0xaaaaaade,r8 + + mvi_h_gr -4,r13 + set_cc 0x0c ; Condition codes should not change + stb r8,@(r13,sp) + test_cc 1 1 0 0 + test_h_mem 0xdeefdead,r2 + test_h_gr 0xaaaaaade,r8 + + ; Test stb $Ri,@(R14,$disp8 + mvr_h_gr r9,sp ; Restore stack pointer + mvi_h_gr 0xaaaaaafe,r8 + mvi_h_mem 0xdeadbeef,sp + mvr_h_gr sp,r14 + inci_h_gr -127,r14 + mvr_h_gr r14,r2 + mvi_h_mem 0xdeadbeef,r14 + inci_h_gr -128,r14 + mvr_h_gr r14,r3 + mvi_h_mem 0xdeadbeef,r14 + inci_h_gr 128,r14 + + set_cc 0x0b ; Condition codes should not change + stb r8,@(r14,127) + test_cc 1 0 1 1 + test_h_mem 0xfeadbeef,r1 + test_h_gr 0xaaaaaafe,r8 + + set_cc 0x0a ; Condition codes should not change + stb r8,@(r14,0) + test_cc 1 0 1 0 + test_h_mem 0xfeadbeef,r2 + test_h_gr 0xaaaaaafe,r8 + + set_cc 0x09 ; Condition codes should not change + stb r8,@(r14,-128) + test_cc 1 0 0 1 + test_h_mem 0xfeadbeef,r3 + test_h_gr 0xaaaaaafe,r8 + + pass diff --git a/sim/testsuite/sim/fr30/sth.cgs b/sim/testsuite/sim/fr30/sth.cgs new file mode 100644 index 00000000000..64c83e6072f --- /dev/null +++ b/sim/testsuite/sim/fr30/sth.cgs @@ -0,0 +1,84 @@ +# fr30 testcase for +# mach(): fr30 +# sth $Ri,@$Rj + + .include "testutils.inc" + + START + + .text + .global sth +sth: + mvr_h_gr sp,r9 ; Save stack pointer + ; Test sth $Ri,@Rj + mvi_h_mem 0xdeadbeef,sp + mvi_h_gr 0xaaaabeef,r8 + set_cc 0x0f ; Condition codes should not change + sth r8,@sp + test_cc 1 1 1 1 + test_h_mem 0xbeefbeef,sp + test_h_gr 0xaaaabeef,r8 + + ; Test sth $Ri,@(R13,Rj) + mvi_h_mem 0xbeefdead,sp + mvi_h_gr 0xaaaadead,r8 + mvr_h_gr sp,r1 + inci_h_gr -8,sp + mvr_h_gr sp,r2 + mvi_h_mem 0xbeefdead,sp + inci_h_gr 4,sp + mvi_h_mem 0xbeefdead,sp + + mvi_h_gr 4,r13 + set_cc 0x0e ; Condition codes should not change + sth r8,@(r13,sp) + test_cc 1 1 1 0 + test_h_mem 0xdeaddead,r1 + test_h_gr 0xaaaadead,r8 + + mvi_h_gr 0,r13 + set_cc 0x0d ; Condition codes should not change + sth r8,@(r13,sp) + test_cc 1 1 0 1 + test_h_mem 0xdeaddead,sp + test_h_gr 0xaaaadead,r8 + + mvi_h_gr -4,r13 + set_cc 0x0c ; Condition codes should not change + sth r8,@(r13,sp) + test_cc 1 1 0 0 + test_h_mem 0xdeaddead,r2 + test_h_gr 0xaaaadead,r8 + + ; Test sth $Ri,@(R14,$disp9) + mvr_h_gr r9,sp ; Restore stack pointer + mvi_h_gr 0xaaaabeef,r8 + mvi_h_mem 0xdeadbeef,sp + mvr_h_gr sp,r14 + inci_h_gr -254,r14 + mvr_h_gr r14,r2 + mvi_h_mem 0xdeadbeef,r14 + inci_h_gr -256,r14 + mvr_h_gr r14,r3 + mvi_h_mem 0xdeadbeef,r14 + inci_h_gr 256,r14 + + set_cc 0x0b ; Condition codes should not change + sth r8,@(r14,254) + test_cc 1 0 1 1 + test_h_mem 0xbeefbeef,r1 + test_h_gr 0xaaaabeef,r8 + + set_cc 0x0a ; Condition codes should not change + sth r8,@(r14,0) + test_cc 1 0 1 0 + test_h_mem 0xbeefbeef,r2 + test_h_gr 0xaaaabeef,r8 + + set_cc 0x09 ; Condition codes should not change + sth r8,@(r14,-256) + test_cc 1 0 0 1 + test_h_mem 0xbeefbeef,r3 + test_h_gr 0xaaaabeef,r8 + + pass diff --git a/sim/testsuite/sim/fr30/stilm.cgs b/sim/testsuite/sim/fr30/stilm.cgs new file mode 100644 index 00000000000..197940bbf4f --- /dev/null +++ b/sim/testsuite/sim/fr30/stilm.cgs @@ -0,0 +1,41 @@ +# fr30 testcase for stilm $i8 +# mach(): fr30 + + .include "testutils.inc" + + START + + .text + .global stilm +stilm: + stilm 0 + test_ilm 0 + + stilm 0xe0 + test_ilm 0 + + stilm 1 + test_ilm 1 + + stilm 15 + test_ilm 15 + + stilm 16 + test_ilm 16 + + stilm 0 + test_ilm 16 + + stilm 1 + test_ilm 17 + + stilm 18 + test_ilm 18 + + stilm 31 + test_ilm 31 + + stilm 0xff + test_ilm 31 + + pass diff --git a/sim/testsuite/sim/fr30/stm0.cgs b/sim/testsuite/sim/fr30/stm0.cgs new file mode 100644 index 00000000000..5cc162c1a31 --- /dev/null +++ b/sim/testsuite/sim/fr30/stm0.cgs @@ -0,0 +1,101 @@ +# fr30 testcase for stm0 ($reglist_low) +# mach(): fr30 + + .include "testutils.inc" + + START + + .text + .global stm0 +stm0: + ; Test stm0 ($reglist_low) + mvr_h_gr sp,r8 ; save stack pointer temporarily + mvr_h_gr sp,r9 ; save stack pointer permanently + mvi_h_gr 0,r0 + mvi_h_gr 1,r1 + mvi_h_gr 2,r2 + mvi_h_gr 3,r3 + mvi_h_gr 4,r4 + mvi_h_gr 5,r5 + mvi_h_gr 6,r6 + mvi_h_gr 7,r7 + set_cc 0x0f ; Condition codes should not change + stm0 (r0,r2,r4,r6) + test_cc 1 1 1 1 + inci_h_gr -4,r8 + test_h_mem 6,r8 + inci_h_gr -4,r8 + test_h_mem 4,r8 + inci_h_gr -4,r8 + test_h_mem 2,r8 + inci_h_gr -4,r8 + test_h_mem 0,r8 + + mvr_h_gr r9,sp ; restore stack pointer + mvr_h_gr r9,r8 ; save stack pointer temporarily + mvi_h_gr 0,r0 + mvi_h_gr 1,r1 + mvi_h_gr 2,r2 + mvi_h_gr 3,r3 + mvi_h_gr 4,r4 + mvi_h_gr 5,r5 + mvi_h_gr 6,r6 + mvi_h_gr 7,r7 + set_cc 0x0f ; Condition codes should not change + stm0 (r1,r3,r5,r7) + test_cc 1 1 1 1 + inci_h_gr -4,r8 + test_h_mem 7,r8 + inci_h_gr -4,r8 + test_h_mem 5,r8 + inci_h_gr -4,r8 + test_h_mem 3,r8 + inci_h_gr -4,r8 + test_h_mem 1,r8 + + mvr_h_gr r9,sp ; restore stack pointer + mvr_h_gr r9,r8 ; save stack pointer temporarily + mvi_h_gr 0,r0 + mvi_h_gr 1,r1 + mvi_h_gr 2,r2 + mvi_h_gr 3,r3 + mvi_h_gr 4,r4 + mvi_h_gr 5,r5 + mvi_h_gr 6,r6 + mvi_h_gr 7,r7 + set_cc 0x0f ; Condition codes should not change + stm0 (r1,r5,r7,r3) ; Order specified should not matter + test_cc 1 1 1 1 + inci_h_gr -4,r8 + test_h_mem 7,r8 + inci_h_gr -4,r8 + test_h_mem 5,r8 + inci_h_gr -4,r8 + test_h_mem 3,r8 + inci_h_gr -4,r8 + test_h_mem 1,r8 + + mvr_h_gr r9,sp ; restore stack pointer + mvr_h_gr r9,r8 ; save stack pointer temporarily + mvi_h_gr 9,r0 + mvi_h_gr 9,r1 + mvi_h_gr 9,r2 + mvi_h_gr 9,r3 + mvi_h_gr 9,r4 + mvi_h_gr 9,r5 + mvi_h_gr 9,r6 + mvi_h_gr 9,r7 + set_cc 0x0f ; Condition codes should not change + stm0 () ; should do nothing + test_cc 1 1 1 1 + testr_h_gr r9,sp + inci_h_gr -4,r8 + test_h_mem 7,r8 + inci_h_gr -4,r8 + test_h_mem 5,r8 + inci_h_gr -4,r8 + test_h_mem 3,r8 + inci_h_gr -4,r8 + test_h_mem 1,r8 + + pass diff --git a/sim/testsuite/sim/fr30/stm1.cgs b/sim/testsuite/sim/fr30/stm1.cgs new file mode 100644 index 00000000000..2ac373d3544 --- /dev/null +++ b/sim/testsuite/sim/fr30/stm1.cgs @@ -0,0 +1,97 @@ +# fr30 testcase for stm1 ($reglist_low) +# mach(): fr30 + + .include "testutils.inc" + + START + + .text + .global stm1 +stm1: + ; Test stm1 ($reglist_low) + mvr_h_gr sp,r1 ; save stack pointer temporarily + mvr_h_gr sp,r2 ; save stack pointer permanently + mvi_h_gr 8,r8 + mvi_h_gr 9,r9 + mvi_h_gr 10,r10 + mvi_h_gr 11,r11 + mvi_h_gr 12,r12 + mvi_h_gr 13,r13 + mvi_h_gr 14,r14 + set_cc 0x0f ; Condition codes should not change + stm1 (r8,r10,r12,r14) + test_cc 1 1 1 1 + inci_h_gr -4,r1 + test_h_mem 14,r1 + inci_h_gr -4,r1 + test_h_mem 12,r1 + inci_h_gr -4,r1 + test_h_mem 10,r1 + inci_h_gr -4,r1 + testr_h_mem 8,r1 + + mvr_h_gr r2,sp ; restore stack pointer + mvr_h_gr r2,r1 ; save stack pointer temporarily + mvi_h_gr 8,r8 + mvi_h_gr 9,r9 + mvi_h_gr 10,r10 + mvi_h_gr 11,r11 + mvi_h_gr 12,r12 + mvi_h_gr 13,r13 + mvi_h_gr 14,r14 + set_cc 0x0f ; Condition codes should not change + stm1 (r9,r11,r13,r15) + test_cc 1 1 1 1 + inci_h_gr -4,r1 + testr_h_mem r2,r1 + inci_h_gr -4,r1 + test_h_mem 13,r1 + inci_h_gr -4,r1 + test_h_mem 11,r1 + inci_h_gr -4,r1 + test_h_mem 9,r1 ; saved r15 is from before stm1 + + mvr_h_gr r2,sp ; restore stack pointer + mvr_h_gr r2,r1 ; save stack pointer temporarily + mvi_h_gr 8,r8 + mvi_h_gr 9,r9 + mvi_h_gr 10,r10 + mvi_h_gr 11,r11 + mvi_h_gr 12,r12 + mvi_h_gr 13,r13 + mvi_h_gr 14,r14 + set_cc 0x0f ; Condition codes should not change + stm1 (r9,r13,r15,r11); Order specified should not matter + test_cc 1 1 1 1 + inci_h_gr -4,r1 + testr_h_mem r2,r1 + inci_h_gr -4,r1 + test_h_mem 13,r1 + inci_h_gr -4,r1 + test_h_mem 11,r1 + inci_h_gr -4,r1 + test_h_mem 9,r1 ; saved r15 is from before stm1 + + mvr_h_gr r2,sp ; restore stack pointer + mvr_h_gr r2,r1 ; save stack pointer temporarily + mvi_h_gr 9,r8 + mvi_h_gr 9,r9 + mvi_h_gr 9,r10 + mvi_h_gr 9,r11 + mvi_h_gr 9,r12 + mvi_h_gr 9,r13 + mvi_h_gr 9,r14 + set_cc 0x0f ; Condition codes should not change + stm1 () ; should do nothing + test_cc 1 1 1 1 + testr_h_gr r2,sp + inci_h_gr -4,r1 + testr_h_mem r2,r1 + inci_h_gr -4,r1 + test_h_mem 13,r1 + inci_h_gr -4,r1 + test_h_mem 11,r1 + inci_h_gr -4,r1 + test_h_mem 9,r1 + + pass diff --git a/sim/testsuite/sim/fr30/stres.cgs b/sim/testsuite/sim/fr30/stres.cgs new file mode 100644 index 00000000000..a85fdf3f9f4 --- /dev/null +++ b/sim/testsuite/sim/fr30/stres.cgs @@ -0,0 +1,25 @@ +# fr30 testcase for stres $@Ri+,$u4 +# mach(): fr30 + + .include "testutils.inc" + + START + + .text + .global stres +stres: + ; Test stres $@Ri+,$u4 + ; The current implementation simply increments Ri + mvi_h_gr 0x1000,r7 + set_cc 0x0f ; Condition codes are irrelevent + stres 0,@r7+ + test_cc 1 1 1 1 + test_h_gr 0x1004,r7 + + mvi_h_gr 0x1000,r7 + set_cc 0x0f ; Condition codes are irrelevent + stres 0xf,@r7+ + test_cc 1 1 1 1 + test_h_gr 0x1004,r7 + + pass diff --git a/sim/testsuite/sim/fr30/sub.cgs b/sim/testsuite/sim/fr30/sub.cgs new file mode 100644 index 00000000000..eceaa79c5c6 --- /dev/null +++ b/sim/testsuite/sim/fr30/sub.cgs @@ -0,0 +1,36 @@ +# fr30 testcase for sub $Rj,$Ri +# mach(): fr30 + + .include "testutils.inc" + + START + + .text + .global sub +sub: + ; Test sub $Rj,$Ri + mvi_h_gr 1,r7 + mvi_h_gr 2,r8 + set_cc 0x0f ; Set mask opposite of expected + sub r7,r8 + test_cc 0 0 0 0 + test_h_gr 1,r8 + + mvi_h_gr 1,r7 + mvi_h_gr 0x80000000,r8 + set_cc 0x0d ; Set mask opposite of expected + sub r7,r8 + test_cc 0 0 1 0 + test_h_gr 0x7fffffff,r8 + + set_cc 0x0b ; Set mask opposite of expected + sub r8,r8 + test_cc 0 1 0 0 + test_h_gr 0,r8 + + set_cc 0x06 ; Set mask opposite of expected + sub r7,r8 + test_cc 1 0 0 1 + test_h_gr 0xffffffff,r8 + + pass diff --git a/sim/testsuite/sim/fr30/subc.cgs b/sim/testsuite/sim/fr30/subc.cgs new file mode 100644 index 00000000000..2978e40c38d --- /dev/null +++ b/sim/testsuite/sim/fr30/subc.cgs @@ -0,0 +1,62 @@ +# fr30 testcase for subc $Rj,$Ri +# mach(): fr30 + + .include "testutils.inc" + + START + + .text + .global subc +subc: + ; Test subc $Rj,$Ri + mvi_h_gr 1,r7 + mvi_h_gr 2,r8 + set_cc 0x0e ; Make sure carry is off + subc r7,r8 + test_cc 0 0 0 0 + test_h_gr 1,r8 + + mvi_h_gr 1,r7 + mvi_h_gr 0x80000000,r8 + set_cc 0x0c ; Make sure carry is off + subc r7,r8 + test_cc 0 0 1 0 + test_h_gr 0x7fffffff,r8 + + set_cc 0x0a ; Make sure carry is off + subc r8,r8 + test_cc 0 1 0 0 + test_h_gr 0,r8 + + set_cc 0x06 ; Make sure carry is off + subc r7,r8 + test_cc 1 0 0 1 + test_h_gr 0xffffffff,r8 + + mvi_h_gr 1,r7 + mvi_h_gr 3,r8 + set_cc 0x0f ; Make sure carry is on + subc r7,r8 + test_cc 0 0 0 0 + test_h_gr 1,r8 + + mvi_h_gr 0,r7 + mvi_h_gr 0x80000000,r8 + set_cc 0x0d ; Make sure carry is on + subc r7,r8 + test_cc 0 0 1 0 + test_h_gr 0x7fffffff,r8 + + mvi_h_gr 0x7ffffffe,r7 + set_cc 0x0b ; Make sure carry is on + subc r7,r8 + test_cc 0 1 0 0 + test_h_gr 0,r8 + + mvi_h_gr 0,r7 + set_cc 0x07 ; Make sure carry is on + subc r7,r8 + test_cc 1 0 0 1 + test_h_gr 0xffffffff,r8 + + pass diff --git a/sim/testsuite/sim/fr30/subn.cgs b/sim/testsuite/sim/fr30/subn.cgs new file mode 100644 index 00000000000..c4830468d22 --- /dev/null +++ b/sim/testsuite/sim/fr30/subn.cgs @@ -0,0 +1,36 @@ +# fr30 testcase for subn $Rj,$Ri +# mach(): fr30 + + .include "testutils.inc" + + START + + .text + .global subn +subn: + ; Test subn $Rj,$Ri + mvi_h_gr 1,r7 + mvi_h_gr 2,r8 + set_cc 0x0f ; Set mask opposite of usual result + subn r7,r8 + test_cc 1 1 1 1 + test_h_gr 1,r8 + + mvi_h_gr 1,r7 + mvi_h_gr 0x80000000,r8 + set_cc 0x0d ; Set mask opposite of usual result + subn r7,r8 + test_cc 1 1 0 1 + test_h_gr 0x7fffffff,r8 + + set_cc 0x0b ; Set mask opposite of usual result + subn r8,r8 + test_cc 1 0 1 1 + test_h_gr 0,r8 + + set_cc 0x06 ; Set mask opposite of usual result + subn r7,r8 + test_cc 0 1 1 0 + test_h_gr 0xffffffff,r8 + + pass diff --git a/sim/testsuite/sim/fr30/testutils.inc b/sim/testsuite/sim/fr30/testutils.inc new file mode 100644 index 00000000000..7523d6f6aa5 --- /dev/null +++ b/sim/testsuite/sim/fr30/testutils.inc @@ -0,0 +1,306 @@ +# r0, r4-r6 are used as tmps, consider them call clobbered by these macros. + + .macro start + .data +failmsg: + .ascii "fail\n" +passmsg: + .ascii "pass\n" + .text + .global _start +_start: + ldi32 0x7fffc,sp ; TODO -- what's a good value for this? + ldi32 0xffc00,r0 + mov r0,tbr ; defined in manual + mov sp,usp + mov sp,ssp + .endm + +; Exit with return code + .macro exit rc + ldi32 \rc,r4 + ldi32 #1,r0 + int #10 + .endm + +; Pass the test case + .macro pass + ldi32 #5,r6 + ldi32 #passmsg,r5 + ldi32 #1,r4 + ldi32 #5,r0 + int #10 + exit #0 + .endm + +; Fail the testcase + .macro fail + ldi32 #5,r6 + ldi32 #failmsg,r5 + ldi32 #1,r4 + ldi32 #5,r0 + int #10 + exit #1 + .endm + +; Load an immediate value into a general register +; TODO: use minimal sized insn + .macro mvi_h_gr val reg + ldi32 \val,\reg + .endm + +; Load an immediate value into a dedicated register + .macro mvi_h_dr val reg + ldi32 \val,r0 + mov r0,\reg + .endm + +; Load a general register into another general register + .macro mvr_h_gr src targ + mov \src,\targ + .endm + +; Store an immediate into a word in memory + .macro mvi_h_mem val addr + mvi_h_gr \val r4 + mvr_h_mem r4,\addr + .endm + +; Store a register into a word in memory + .macro mvr_h_mem reg addr + st \reg,@\addr + .endm + +; Store the current ps on the stack + .macro save_ps + st ps,@-r15 + .endm + +; Load a word value from memory + .macro ldmem_h_gr addr reg + ld @\addr,\reg + .endm + +; Add 2 general registers + .macro add_h_gr reg1 reg2 + add \reg1,\reg2 + .endm + +; Increment a register by and immediate + .macro inci_h_gr inc reg + mvi_h_gr \inc,r4 + add r4,\reg + .endm + +; Test the value of an immediate against a general register + .macro test_h_gr val reg + .if (\val >= 0) && (\val <= 15) + cmp \val,\reg + .else + .if (\val < 0) && (\val >= -16) + cmp2 \val,\reg + .else + ldi32 \val,r4 + cmp r4,\reg + .endif + .endif + beq test_gr\@ + fail +test_gr\@: + .endm + +; compare two general registers + .macro testr_h_gr reg1 reg2 + cmp \reg1,\reg2 + beq testr_gr\@ + fail +testr_gr\@: + .endm + +; Test the value of an immediate against a dedicated register + .macro test_h_dr val reg + mov \reg,r5 + test_h_gr \val r5 + .endm + +; Test the value of an general register against a dedicated register + .macro testr_h_dr gr dr + mov \dr,r5 + testr_h_gr \gr r5 + .endm + +; Compare an immediate with word in memory + .macro test_h_mem val addr + ldmem_h_gr \addr r5 + test_h_gr \val r5 + .endm + +; Compare a general register with word in memory + .macro testr_h_mem reg addr + ldmem_h_gr \addr r5 + testr_h_gr \reg r5 + .endm + +; Set the condition codes + .macro set_cc mask + andccr 0xf0 + orccr \mask + .endm + +; Set the stack mode + .macro set_s_user + orccr 0x20 + .endm + + .macro set_s_system + andccr 0x1f + .endm + +; Test the stack mode + .macro test_s_user + mvr_h_gr ps,r0 + mvi_h_gr 0x20,r4 + and r4,r0 + test_h_gr 0x20,r0 + .endm + + .macro test_s_system + mvr_h_gr ps,r0 + mvi_h_gr 0x20,r4 + and r4,r0 + test_h_gr 0x0,r0 + .endm + +; Set the interrupt bit + .macro set_i val + .if (\val == 1) + orccr 0x10 + .else + andccr 0x2f + .endif + .endm + +; Test the stack mode + .macro test_i val + mvr_h_gr ps,r0 + mvi_h_gr 0x10,r4 + and r4,r0 + .if (\val == 1) + test_h_gr 0x10,r0 + .else + test_h_gr 0x0,r0 + .endif + .endm + +; Set the ilm + .macro set_ilm val + stilm \val + .endm + +; Test the ilm + .macro test_ilm val + mvr_h_gr ps,r0 + mvi_h_gr 0x1f0000,r4 + and r4,r0 + mvi_h_gr \val,r5 + mvi_h_gr 0x1f,r4 + and r4,r5 + lsl 15,r5 + lsl 1,r5 + testr_h_gr r0,r5 + .endm + +; Test the condition codes + .macro test_cc N Z V C + .if (\N == 1) + bp fail\@ + .else + bn fail\@ + .endif + .if (\Z == 1) + bne fail\@ + .else + beq fail\@ + .endif + .if (\V == 1) + bnv fail\@ + .else + bv fail\@ + .endif + .if (\C == 1) + bnc fail\@ + .else + bc fail\@ + .endif + bra test_cc\@ +fail\@: + fail +test_cc\@: + .endm + +; Set the division bits + .macro set_dbits val + mvr_h_gr ps,r5 + mvi_h_gr 0xfffff8ff,r4 + and r4,r5 + mvi_h_gr \val,r0 + mvi_h_gr 3,r4 + and r4,r0 + lsl 9,r0 + or r0,r5 + mvr_h_gr r5,ps + .endm + +; Test the division bits + .macro test_dbits val + mvr_h_gr ps,r0 + lsr 9,r0 + mvi_h_gr 3,r4 + and r4,r0 + test_h_gr \val,r0 + .endm + +; Save the return pointer + .macro save_rp + st rp,@-R15 + .ENDM + +; restore the return pointer + .macro restore_rp + ld @R15+,rp + .endm + +; Ensure branch taken + .macro take_branch opcode + \opcode take_br\@ + fail +take_br\@: + .endm + + .macro take_branch_d opcode val + \opcode take_brd\@ + ldi:8 \val,r0 + fail +take_brd\@: + test_h_gr \val,r0 + .endm + +; Ensure branch not taken + .macro no_branch opcode + \opcode no_brf\@ + bra no_brs\@ +no_brf\@: + fail +no_brs\@: + .endm + + .macro no_branch_d opcode val + \opcode no_brdf\@ + ldi:8 \val,r0 + bra no_brds\@ +no_brdf\@: + fail +no_brds\@: + test_h_gr \val,r0 + .endm + diff --git a/sim/testsuite/sim/fr30/xchb.cgs b/sim/testsuite/sim/fr30/xchb.cgs new file mode 100644 index 00000000000..3450a2e34cd --- /dev/null +++ b/sim/testsuite/sim/fr30/xchb.cgs @@ -0,0 +1,20 @@ +# fr30 testcase for xchb @$Rj,Ri +# mach(): fr30 + + .include "testutils.inc" + + START + + .text + .global xchb +xchb: + ; Test xchb @$Rj,Ri + mvi_h_mem 0xdeadbeef,sp + mvi_h_gr 0xbeefdead,r0 + set_cc 0x0f ; Condition codes are irrelevent + xchb @sp,r0 + test_cc 1 1 1 1 + test_h_gr 0xde,r0 + test_h_mem 0xadadbeef,sp + + pass diff --git a/sim/testsuite/sim/m32r/add.cgs b/sim/testsuite/sim/m32r/add.cgs new file mode 100644 index 00000000000..8ed2b3a2ad3 --- /dev/null +++ b/sim/testsuite/sim/m32r/add.cgs @@ -0,0 +1,16 @@ +# m32r testcase for add $dr,$sr +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global add +add: + + mvi_h_gr r4, 1 + mvi_h_gr r5, 2 + add r4, r5 + test_h_gr r4, 3 + + pass diff --git a/sim/testsuite/sim/m32r/add3.cgs b/sim/testsuite/sim/m32r/add3.cgs new file mode 100644 index 00000000000..d1cc8480ad4 --- /dev/null +++ b/sim/testsuite/sim/m32r/add3.cgs @@ -0,0 +1,15 @@ +# m32r testcase for add3 $dr,$sr,#$slo16 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global add3 +add3: + + mvi_h_gr r5, 1 + add3 r4, r5, 2 + test_h_gr r4, 3 + + pass diff --git a/sim/testsuite/sim/m32r/addi.cgs b/sim/testsuite/sim/m32r/addi.cgs new file mode 100644 index 00000000000..1448d0d2e2b --- /dev/null +++ b/sim/testsuite/sim/m32r/addi.cgs @@ -0,0 +1,16 @@ +# m32r testcase for addi $dr,#$simm8 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global addi +addi: + + mvi_h_gr r5, 1 + addi r5, 2 + test_h_gr r5, 3 + + pass + diff --git a/sim/testsuite/sim/m32r/addv.cgs b/sim/testsuite/sim/m32r/addv.cgs new file mode 100644 index 00000000000..704be83c914 --- /dev/null +++ b/sim/testsuite/sim/m32r/addv.cgs @@ -0,0 +1,21 @@ +# m32r testcase for addv $dr,$sr +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global addv +addv: + mvi_h_condbit 0 + mvi_h_gr r4, 0x80000000 + mvi_h_gr r5, 0x80000000 + + addv r4, r5 + + bnc not_ok + test_h_gr r4, 0 + + pass +not_ok: + fail diff --git a/sim/testsuite/sim/m32r/addv3.cgs b/sim/testsuite/sim/m32r/addv3.cgs new file mode 100644 index 00000000000..a8c0a108561 --- /dev/null +++ b/sim/testsuite/sim/m32r/addv3.cgs @@ -0,0 +1,28 @@ +# m32r testcase for addv3 $dr,$sr,#$simm16 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global addv3 +addv3: + mvi_h_condbit 0 + mvi_h_gr r4, 1 + mvi_h_gr r5, 1 + + addv3 r4, r5, #2 + + bc not_ok + + test_h_gr r4, 3 + + mvi_h_gr r5, 0x7fff8001 + + addv3 r4, r5, #0x7fff + + bnc not_ok + + pass +not_ok: + fail diff --git a/sim/testsuite/sim/m32r/addx.cgs b/sim/testsuite/sim/m32r/addx.cgs new file mode 100644 index 00000000000..630e3dbe15a --- /dev/null +++ b/sim/testsuite/sim/m32r/addx.cgs @@ -0,0 +1,42 @@ +# m32r testcase for addx $dr,$sr +# mach(): m32r m32rx +# timeout(): 42 + +# timeout is set to test it + + .include "testutils.inc" + + start + + .global addx +addx: + mvi_h_condbit 1 + mvi_h_gr r4, 1 + mvi_h_gr r5, 2 + addx r4, r5 + bc not_ok + test_h_gr r4, 4 + + mvi_h_gr r4, 0xfffffffe + addx r4, r5 + bnc not_ok + test_h_gr r4, 0 + + mvi_h_gr r4, -1 + mvi_h_gr r5, -1 + mvi_h_condbit 1 + addx r4,r5 + bnc not_ok + test_h_gr r4, -1 + + mvi_h_gr r4,-1 + mvi_h_gr r5,0x7fffffff + mvi_h_condbit 1 + addx r5,r4 + bnc not_ok + test_h_gr r5,0x7fffffff + + pass + +not_ok: + fail diff --git a/sim/testsuite/sim/m32r/allinsn.exp b/sim/testsuite/sim/m32r/allinsn.exp new file mode 100644 index 00000000000..8eed80f91d6 --- /dev/null +++ b/sim/testsuite/sim/m32r/allinsn.exp @@ -0,0 +1,21 @@ +# M32R simulator testsuite. + +if [istarget m32r*-*-*] { + # load support procs + # load_lib cgen.exp + + # all machines + set all_machs "m32r" + + + # The .cgs suffix is for "cgen .s". + foreach src [lsort [glob -nocomplain $srcdir/$subdir/*.cgs]] { + # If we're only testing specific files and this isn't one of them, + # skip it. + if ![runtest_file_p $runtests $src] { + continue + } + + run_sim_test $src $all_machs + } +} diff --git a/sim/testsuite/sim/m32r/and.cgs b/sim/testsuite/sim/m32r/and.cgs new file mode 100644 index 00000000000..1c268855411 --- /dev/null +++ b/sim/testsuite/sim/m32r/and.cgs @@ -0,0 +1,17 @@ +# m32r testcase for and $dr,$sr +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global and +and: + mvi_h_gr r4, 3 + mvi_h_gr r5, 6 + + and r4, r5 + + test_h_gr r4, 2 + + pass diff --git a/sim/testsuite/sim/m32r/and3.cgs b/sim/testsuite/sim/m32r/and3.cgs new file mode 100644 index 00000000000..395de3028e9 --- /dev/null +++ b/sim/testsuite/sim/m32r/and3.cgs @@ -0,0 +1,17 @@ +# m32r testcase for and3 $dr,$sr,#$uimm16 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global and3 +and3: + mvi_h_gr r4, 0 + mvi_h_gr r5, 6 + + and3 r4, r5, #3 + + test_h_gr r4, 2 + + pass diff --git a/sim/testsuite/sim/m32r/bc24.cgs b/sim/testsuite/sim/m32r/bc24.cgs new file mode 100644 index 00000000000..6bb43334e8f --- /dev/null +++ b/sim/testsuite/sim/m32r/bc24.cgs @@ -0,0 +1,24 @@ +# m32r testcase for bc $disp24 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global bc24 +bc24: + + mvi_h_condbit 0 + bc.l test0fail + bra test0pass +test0fail: + fail +test0pass: + + mvi_h_condbit 1 + bc.l test1pass + fail +test1pass: + + pass + diff --git a/sim/testsuite/sim/m32r/bc8.cgs b/sim/testsuite/sim/m32r/bc8.cgs new file mode 100644 index 00000000000..ceb622c1661 --- /dev/null +++ b/sim/testsuite/sim/m32r/bc8.cgs @@ -0,0 +1,23 @@ +# m32r testcase for bc $disp8 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global bc8 +bc8: + + mvi_h_condbit 0 + bc.s test0fail + bra test0pass +test0fail: + fail +test0pass: + + mvi_h_condbit 1 + bc.s test1pass + fail +test1pass: + + pass diff --git a/sim/testsuite/sim/m32r/beq.cgs b/sim/testsuite/sim/m32r/beq.cgs new file mode 100644 index 00000000000..c4d6d8bf0aa --- /dev/null +++ b/sim/testsuite/sim/m32r/beq.cgs @@ -0,0 +1,20 @@ +# m32r testcase for beq $src1,$src2,$disp16 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global beq +beq: + mvi_h_condbit 0 + mvi_h_gr r4, 12 + mvi_h_gr r5, 12 + beq r4, r5, ok +not_ok: + fail +ok: + mvi_h_gr r5, 11 + beq r4, r5, not_ok + + pass diff --git a/sim/testsuite/sim/m32r/beqz.cgs b/sim/testsuite/sim/m32r/beqz.cgs new file mode 100644 index 00000000000..654737d3d46 --- /dev/null +++ b/sim/testsuite/sim/m32r/beqz.cgs @@ -0,0 +1,18 @@ +# m32r testcase for beqz $src2,$disp16 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global beqz +beqz: + mvi_h_gr r4, 0 + beqz r4, ok +not_ok: + fail +ok: + mvi_h_gr r4, 1 + beqz r4, not_ok + + pass diff --git a/sim/testsuite/sim/m32r/bgez.cgs b/sim/testsuite/sim/m32r/bgez.cgs new file mode 100644 index 00000000000..f7031f0edcb --- /dev/null +++ b/sim/testsuite/sim/m32r/bgez.cgs @@ -0,0 +1,18 @@ +# m32r testcase for bgez $src2,$disp16 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global bgez +bgez: + mvi_h_gr r4, 1 + bgez r4, ok +not_ok: + fail +ok: + mvi_h_gr r4, -1 + bgez r4, not_ok + + pass diff --git a/sim/testsuite/sim/m32r/bgtz.cgs b/sim/testsuite/sim/m32r/bgtz.cgs new file mode 100644 index 00000000000..6ab8989c7e0 --- /dev/null +++ b/sim/testsuite/sim/m32r/bgtz.cgs @@ -0,0 +1,18 @@ +# m32r testcase for bgtz $src2,$disp16 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global bgtz +bgtz: + mvi_h_gr r4, 1 + bgtz r4, ok +not_ok: + fail +ok: + mvi_h_gr r4, 0 + bgtz r4, not_ok + + pass diff --git a/sim/testsuite/sim/m32r/bl24.cgs b/sim/testsuite/sim/m32r/bl24.cgs new file mode 100644 index 00000000000..fd6f0dd69d5 --- /dev/null +++ b/sim/testsuite/sim/m32r/bl24.cgs @@ -0,0 +1,18 @@ +# m32r testcase for bl $disp24 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global bl24 +bl24: + bl.l test0pass +test1fail: + fail + +test0pass: + mvaddr_h_gr r4, test1fail + bne r4, r14, test1fail + + pass diff --git a/sim/testsuite/sim/m32r/bl8.cgs b/sim/testsuite/sim/m32r/bl8.cgs new file mode 100644 index 00000000000..d26369853b7 --- /dev/null +++ b/sim/testsuite/sim/m32r/bl8.cgs @@ -0,0 +1,18 @@ +# m32r testcase for bl $disp8 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global bl8 +bl8: + bl.s test0pass +test1fail: + fail + +test0pass: + mvaddr_h_gr r4, test1fail + bne r4, r14, test1fail + + pass diff --git a/sim/testsuite/sim/m32r/blez.cgs b/sim/testsuite/sim/m32r/blez.cgs new file mode 100644 index 00000000000..e3d198d93ad --- /dev/null +++ b/sim/testsuite/sim/m32r/blez.cgs @@ -0,0 +1,19 @@ +# m32r testcase for blez $src2,$disp16 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global blez +blez: + mvi_h_gr r4, 0 + blez r4, test0pass +test1fail: + fail + +test0pass: + mvi_h_gr r4, 1 + blez r4, test1fail + + pass diff --git a/sim/testsuite/sim/m32r/bltz.cgs b/sim/testsuite/sim/m32r/bltz.cgs new file mode 100644 index 00000000000..c9377fcaab1 --- /dev/null +++ b/sim/testsuite/sim/m32r/bltz.cgs @@ -0,0 +1,19 @@ +# m32r testcase for bltz $src2,$disp16 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global bltz +bltz: + mvi_h_gr r4, -1 + bltz r4, test0pass +test1fail: + fail + +test0pass: + mvi_h_gr r4, 0 + bltz r4, test1fail + + pass diff --git a/sim/testsuite/sim/m32r/bnc24.cgs b/sim/testsuite/sim/m32r/bnc24.cgs new file mode 100644 index 00000000000..692d2d58436 --- /dev/null +++ b/sim/testsuite/sim/m32r/bnc24.cgs @@ -0,0 +1,20 @@ +# m32r testcase for bnc $disp24 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global bnc24 +bnc24: + mvi_h_condbit 0 + bnc.l test0pass + +test1fail: + fail +test0pass: + + mvi_h_condbit 1 + bnc.l test1fail + + pass diff --git a/sim/testsuite/sim/m32r/bnc8.cgs b/sim/testsuite/sim/m32r/bnc8.cgs new file mode 100644 index 00000000000..dae2613cc9f --- /dev/null +++ b/sim/testsuite/sim/m32r/bnc8.cgs @@ -0,0 +1,20 @@ +# m32r testcase for bnc $disp8 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global bnc8 +bnc8: + mvi_h_condbit 0 + bnc.s test0pass + +test1fail: + fail + +test0pass: + mvi_h_condbit 1 + bnc.s test1fail + + pass diff --git a/sim/testsuite/sim/m32r/bne.cgs b/sim/testsuite/sim/m32r/bne.cgs new file mode 100644 index 00000000000..5e1d7a6ecc5 --- /dev/null +++ b/sim/testsuite/sim/m32r/bne.cgs @@ -0,0 +1,20 @@ +# m32r testcase for bne $src1,$src2,$disp16 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global bne +bne: + mvi_h_gr r4, 1 + mvi_h_gr r5, 2 + bne r4, r5, test0pass +test1fail: + fail + +test0pass: + mvi_h_gr r4, 2 + bne r4, r5, test1fail + + pass diff --git a/sim/testsuite/sim/m32r/bnez.cgs b/sim/testsuite/sim/m32r/bnez.cgs new file mode 100644 index 00000000000..9f102895029 --- /dev/null +++ b/sim/testsuite/sim/m32r/bnez.cgs @@ -0,0 +1,19 @@ +# m32r testcase for bnez $src2,$disp16 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global bnez +bnez: + mvi_h_gr r4, 1 + bnez r4, test0pass +test1fail: + fail + +test0pass: + mvi_h_gr r4, 0 + bnez r4, test1fail + + pass diff --git a/sim/testsuite/sim/m32r/bra24.cgs b/sim/testsuite/sim/m32r/bra24.cgs new file mode 100644 index 00000000000..d62d2bf0ec3 --- /dev/null +++ b/sim/testsuite/sim/m32r/bra24.cgs @@ -0,0 +1,15 @@ +# m32r testcase for bra $disp24 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global bra24 +bra24: + bra.l ok + + fail + +ok: + pass diff --git a/sim/testsuite/sim/m32r/bra8.cgs b/sim/testsuite/sim/m32r/bra8.cgs new file mode 100644 index 00000000000..f5f50ad2d93 --- /dev/null +++ b/sim/testsuite/sim/m32r/bra8.cgs @@ -0,0 +1,14 @@ +# m32r testcase for bra $disp8 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global bra8 +bra8: + bra.s ok + + fail +ok: + pass diff --git a/sim/testsuite/sim/m32r/cmp.cgs b/sim/testsuite/sim/m32r/cmp.cgs new file mode 100644 index 00000000000..6ea67206218 --- /dev/null +++ b/sim/testsuite/sim/m32r/cmp.cgs @@ -0,0 +1,23 @@ +# m32r testcase for cmp $src1,$src2 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global cmp +cmp: + mvi_h_condbit 0 + mvi_h_gr r4, 1 + mvi_h_gr r5, 2 + cmp r4, r5 + bc ok +not_ok: + fail +ok: + mvi_h_condbit 1 + mvi_h_gr r4, 2 + cmp r4, r5 + bc not_ok + + pass diff --git a/sim/testsuite/sim/m32r/cmpi.cgs b/sim/testsuite/sim/m32r/cmpi.cgs new file mode 100644 index 00000000000..af11283d68d --- /dev/null +++ b/sim/testsuite/sim/m32r/cmpi.cgs @@ -0,0 +1,24 @@ +# m32r testcase for cmpi $src2,#$simm16 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global cmpi +cmpi: + mvi_h_condbit 0 + mvi_h_gr r4, 1 + + cmpi r4, #2 + bc ok +not_ok: + fail +ok: + mvi_h_condbit 1 + mvi_h_gr r4, 2 + cmpi r4, #2 + bc not_ok + + + pass diff --git a/sim/testsuite/sim/m32r/cmpu.cgs b/sim/testsuite/sim/m32r/cmpu.cgs new file mode 100644 index 00000000000..e0b4ef10180 --- /dev/null +++ b/sim/testsuite/sim/m32r/cmpu.cgs @@ -0,0 +1,23 @@ +# m32r testcase for cmpu $src1,$src2 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global cmpu +cmpu: + mvi_h_condbit 0 + mvi_h_gr r4, 1 + mvi_h_gr r5, -2 + cmpu r4, r5 + bc ok +not_ok: + fail +ok: + mvi_h_condbit 1 + mvi_h_gr r4, -1 + cmpu r4, r5 + bc not_ok + + pass diff --git a/sim/testsuite/sim/m32r/cmpui.cgs b/sim/testsuite/sim/m32r/cmpui.cgs new file mode 100644 index 00000000000..aa30207d933 --- /dev/null +++ b/sim/testsuite/sim/m32r/cmpui.cgs @@ -0,0 +1,22 @@ +# m32r testcase for cmpui $src2,#$simm16 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global cmpui +cmpui: + mvi_h_condbit 0 + mvi_h_gr r4, 1 + cmpui r4, #2 + bc ok +not_ok: + fail +ok: + mvi_h_condbit 1 + mvi_h_gr r4, -1 + cmpui r4, #2 + bc not_ok + + pass diff --git a/sim/testsuite/sim/m32r/div.cgs b/sim/testsuite/sim/m32r/div.cgs new file mode 100644 index 00000000000..733f3629680 --- /dev/null +++ b/sim/testsuite/sim/m32r/div.cgs @@ -0,0 +1,17 @@ +# m32r testcase for div $dr,$sr +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global div +div: + mvi_h_gr r4, 0x18000 + mvi_h_gr r5, 8 + + div r4, r5 + + test_h_gr r4, 0x3000 + + pass diff --git a/sim/testsuite/sim/m32r/divu.cgs b/sim/testsuite/sim/m32r/divu.cgs new file mode 100644 index 00000000000..25342d5dccc --- /dev/null +++ b/sim/testsuite/sim/m32r/divu.cgs @@ -0,0 +1,17 @@ +# m32r testcase for divu $dr,$sr +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global divu +divu: + mvi_h_gr r4, 0x18000 + mvi_h_gr r5, 8 + + divu r4, r5 + + test_h_gr r4, 0x3000 + + pass diff --git a/sim/testsuite/sim/m32r/hello.ms b/sim/testsuite/sim/m32r/hello.ms new file mode 100644 index 00000000000..7ae22778001 --- /dev/null +++ b/sim/testsuite/sim/m32r/hello.ms @@ -0,0 +1,19 @@ +# output(): Hello world!\n +# mach(): m32r m32rx + + .globl _start +_start: + +; write (hello world) + ldi8 r3,#14 + ld24 r2,#hello + ldi8 r1,#1 + ldi8 r0,#5 + trap #0 +; exit (0) + ldi8 r1,#0 + ldi8 r0,#1 + trap #0 + +length: .long 14 +hello: .ascii "Hello world!\r\n" diff --git a/sim/testsuite/sim/m32r/hw-trap.ms b/sim/testsuite/sim/m32r/hw-trap.ms new file mode 100644 index 00000000000..2aa200b5d70 --- /dev/null +++ b/sim/testsuite/sim/m32r/hw-trap.ms @@ -0,0 +1,31 @@ +# mach(): m32r m32rx +# output(): pass\n + + .include "testutils.inc" + + start + +; construct bra trap2_handler in trap 2 slot + ld24 r0,#bra_insn + ld r0,@r0 + ld24 r1,#trap2_handler + addi r1,#-0x48 ; pc relative address from trap 2 slot to handler + srai r1,#2 + or r0,r1 + ld24 r2,#0x48 ; address of trap 2 slot + st r0,@r2 + +; perform trap + ldi r4,#0 + trap #2 + test_h_gr r4,42 + + pass + +; trap 2 handler +trap2_handler: + ldi r4,#42 + rte + +bra_insn: + bra.l 0 diff --git a/sim/testsuite/sim/m32r/jl.cgs b/sim/testsuite/sim/m32r/jl.cgs new file mode 100644 index 00000000000..a89c26a86bf --- /dev/null +++ b/sim/testsuite/sim/m32r/jl.cgs @@ -0,0 +1,18 @@ +# m32r testcase for jl $sr +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global jl +jl: + mvaddr_h_gr r4, ok + jl r4 +not_ok: + fail +ok: + mvaddr_h_gr r4, not_ok + bne r4, r14, not_ok + + pass diff --git a/sim/testsuite/sim/m32r/jmp.cgs b/sim/testsuite/sim/m32r/jmp.cgs new file mode 100644 index 00000000000..ba0864a53f0 --- /dev/null +++ b/sim/testsuite/sim/m32r/jmp.cgs @@ -0,0 +1,19 @@ +# m32r testcase for jmp $sr +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global jmp +jmp: + mvaddr_h_gr r4, ok1 + jmp r4 + fail +ok1: + mvaddr_h_gr r4, ok2 + addi r4,#1 + jmp r4 + fail +ok2: + pass diff --git a/sim/testsuite/sim/m32r/ld-d.cgs b/sim/testsuite/sim/m32r/ld-d.cgs new file mode 100644 index 00000000000..151743672b2 --- /dev/null +++ b/sim/testsuite/sim/m32r/ld-d.cgs @@ -0,0 +1,22 @@ +# m32r testcase for ld $dr,@($slo16,$sr) +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global ld_d +ld_d: + mvaddr_h_gr r4, data_loc + mvi_h_gr r5, 0 + + ld r5, @(#4, r4) + + test_h_gr r5, 0x12345678 + + pass + +data_loc: + .word 0x11223344 + .word 0x12345678 + diff --git a/sim/testsuite/sim/m32r/ld-plus.cgs b/sim/testsuite/sim/m32r/ld-plus.cgs new file mode 100644 index 00000000000..5feaf62596e --- /dev/null +++ b/sim/testsuite/sim/m32r/ld-plus.cgs @@ -0,0 +1,28 @@ +# m32r testcase for ld $dr,@$sr+ +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global ld_plus +ld_plus: + mvaddr_h_gr r4, data_loc + mvi_h_gr r5, 0 + + ld r5, @r4+ + + test_h_gr r5, 0x12345678 + + mvaddr_h_gr r5, data_loc2 + bne r4, r5, not_ok + + pass +not_ok: + fail + +data_loc: + .word 0x12345678 +data_loc2: + .word 0x11223344 + diff --git a/sim/testsuite/sim/m32r/ld.cgs b/sim/testsuite/sim/m32r/ld.cgs new file mode 100644 index 00000000000..ad0b86ff6d5 --- /dev/null +++ b/sim/testsuite/sim/m32r/ld.cgs @@ -0,0 +1,21 @@ +# m32r testcase for ld $dr,@$sr +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global ld +ld: + mvaddr_h_gr r4, data_loc + mvi_h_gr r5, 0 + + ld r5, @r4 + + test_h_gr r5, 0x12345678 + + pass + +data_loc: + .word 0x12345678 + diff --git a/sim/testsuite/sim/m32r/ld24.cgs b/sim/testsuite/sim/m32r/ld24.cgs new file mode 100644 index 00000000000..74b155518c8 --- /dev/null +++ b/sim/testsuite/sim/m32r/ld24.cgs @@ -0,0 +1,14 @@ +# m32r testcase for ld24 $dr,#$uimm24 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global ld24 +ld24: + ld24 r4, #0x123456 + + test_h_gr r4, 0x123456 + + pass diff --git a/sim/testsuite/sim/m32r/ldb-d.cgs b/sim/testsuite/sim/m32r/ldb-d.cgs new file mode 100644 index 00000000000..4a1cebb1fc3 --- /dev/null +++ b/sim/testsuite/sim/m32r/ldb-d.cgs @@ -0,0 +1,20 @@ +# m32r testcase for ldb $dr,@($slo16,$sr) +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global ldb_d +ldb_d: + mvaddr_h_gr r4, data_loc + mvi_h_gr r5, 0 + + ldb r5, @(#2, r4) + + test_h_gr r5, 0x56 ; big endian processor + + pass + +data_loc: + .word 0x12345678 diff --git a/sim/testsuite/sim/m32r/ldb.cgs b/sim/testsuite/sim/m32r/ldb.cgs new file mode 100644 index 00000000000..9b895450f08 --- /dev/null +++ b/sim/testsuite/sim/m32r/ldb.cgs @@ -0,0 +1,21 @@ +# m32r testcase for ldb $dr,@$sr +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global ldb +ldb: + mvaddr_h_gr r4, data_loc + mvi_h_gr r5, 0 + + ldb r5, @r4 + + test_h_gr r5, 0x12 ; big endian processor + + pass + +data_loc: + .word 0x12345678 + diff --git a/sim/testsuite/sim/m32r/ldh-d.cgs b/sim/testsuite/sim/m32r/ldh-d.cgs new file mode 100644 index 00000000000..0be0309b1ef --- /dev/null +++ b/sim/testsuite/sim/m32r/ldh-d.cgs @@ -0,0 +1,21 @@ +# m32r testcase for ldh $dr,@($slo16,$sr) +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global ldh_d +ldh_d: + mvaddr_h_gr r4, data_loc + mvi_h_gr r5, 0 + + ldh r5, @(#2, r4) + + test_h_gr r5, 0x5678 ; big endian processor + + pass + +data_loc: + .word 0x12345678 + diff --git a/sim/testsuite/sim/m32r/ldh.cgs b/sim/testsuite/sim/m32r/ldh.cgs new file mode 100644 index 00000000000..3d8db953d3d --- /dev/null +++ b/sim/testsuite/sim/m32r/ldh.cgs @@ -0,0 +1,22 @@ +# m32r testcase for ldh $dr,@$sr +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global ldh +ldh: + mvaddr_h_gr r4, data_loc + mvi_h_gr r5, 0 + + ldh r5, @r4 + + test_h_gr r5, 0x1234 ; big endian processor + + pass + +data_loc: + .word 0x12345678 + + pass diff --git a/sim/testsuite/sim/m32r/ldi16.cgs b/sim/testsuite/sim/m32r/ldi16.cgs new file mode 100644 index 00000000000..478df1c1b32 --- /dev/null +++ b/sim/testsuite/sim/m32r/ldi16.cgs @@ -0,0 +1,14 @@ +# m32r testcase for ldi $dr,$slo16 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global ldi16 +ldi16: + ldi r4, #0x1234 + + test_h_gr r4, 0x1234 + + pass diff --git a/sim/testsuite/sim/m32r/ldi8.cgs b/sim/testsuite/sim/m32r/ldi8.cgs new file mode 100644 index 00000000000..081e7a86f35 --- /dev/null +++ b/sim/testsuite/sim/m32r/ldi8.cgs @@ -0,0 +1,14 @@ +# m32r testcase for ldi $dr,#$simm8 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global ldi8 +ldi8: + ldi r4, #0x78 + + test_h_gr r4, 0x78 + + pass diff --git a/sim/testsuite/sim/m32r/ldub-d.cgs b/sim/testsuite/sim/m32r/ldub-d.cgs new file mode 100644 index 00000000000..7661071b820 --- /dev/null +++ b/sim/testsuite/sim/m32r/ldub-d.cgs @@ -0,0 +1,21 @@ +# m32r testcase for ldub $dr,@($slo16,$sr) +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global ldub_d +ldub_d: + mvaddr_h_gr r4, data_loc + mvi_h_gr r5, 0 + + ldub r5, @(#2, r4) + + test_h_gr r5, 0xa0 ; big endian processor + + pass + +data_loc: + .word 0x8090a0b0 + diff --git a/sim/testsuite/sim/m32r/ldub.cgs b/sim/testsuite/sim/m32r/ldub.cgs new file mode 100644 index 00000000000..27913b51f59 --- /dev/null +++ b/sim/testsuite/sim/m32r/ldub.cgs @@ -0,0 +1,21 @@ +# m32r testcase for ldub $dr,@$sr +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global ldub +ldub: + mvaddr_h_gr r4, data_loc + mvi_h_gr r5, 0 + + ldub r5, @r4 + + test_h_gr r5, 0x80 ; big endian processor + + pass + +data_loc: + .word 0x800000f0 + diff --git a/sim/testsuite/sim/m32r/lduh-d.cgs b/sim/testsuite/sim/m32r/lduh-d.cgs new file mode 100644 index 00000000000..96e294f0ec8 --- /dev/null +++ b/sim/testsuite/sim/m32r/lduh-d.cgs @@ -0,0 +1,20 @@ +# m32r testcase for lduh $dr,@($slo16,$sr) +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global lduh_d +lduh_d: + mvaddr_h_gr r4, data_loc + mvi_h_gr r5, 0 + + lduh r5, @(#2, r4) + + test_h_gr r5, 0xf000 ; big endian processor + + pass + +data_loc: + .word 0x8000f000 diff --git a/sim/testsuite/sim/m32r/lduh.cgs b/sim/testsuite/sim/m32r/lduh.cgs new file mode 100644 index 00000000000..a03bbee240d --- /dev/null +++ b/sim/testsuite/sim/m32r/lduh.cgs @@ -0,0 +1,22 @@ +# m32r testcase for lduh $dr,@$sr +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global lduh +lduh: + mvaddr_h_gr r4, data_loc + mvi_h_gr r5, 0 + + lduh r5, @r4 + + test_h_gr r5, 0x8010 ; big endian processor + + pass + +data_loc: + .word 0x8010f020 + + pass diff --git a/sim/testsuite/sim/m32r/lock.cgs b/sim/testsuite/sim/m32r/lock.cgs new file mode 100644 index 00000000000..631525ebbbf --- /dev/null +++ b/sim/testsuite/sim/m32r/lock.cgs @@ -0,0 +1,25 @@ +# m32r testcase for lock $dr,@$sr +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global lock +lock: + mvaddr_h_gr r4, data_loc + mvi_h_gr r5, 0 + + lock r5, @r4 + + test_h_gr r5, 0x12345678 + + ; There is no way to test the lock bit + + unlock r5, @r4 ; Unlock the processor + + pass + +data_loc: + .word 0x12345678 + diff --git a/sim/testsuite/sim/m32r/machi.cgs b/sim/testsuite/sim/m32r/machi.cgs new file mode 100644 index 00000000000..2e2ef00294c --- /dev/null +++ b/sim/testsuite/sim/m32r/machi.cgs @@ -0,0 +1,17 @@ +# m32r testcase for machi $src1,$src2 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global machi +machi: + + mvi_h_accum0 0, 1 + mvi_h_gr r4, 0x10123 + mvi_h_gr r5, 0x20456 + machi r4, r5 + test_h_accum0 0, 0x20001 + + pass diff --git a/sim/testsuite/sim/m32r/maclo.cgs b/sim/testsuite/sim/m32r/maclo.cgs new file mode 100644 index 00000000000..5d035394dc4 --- /dev/null +++ b/sim/testsuite/sim/m32r/maclo.cgs @@ -0,0 +1,17 @@ +# m32r testcase for maclo $src1,$src2 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global maclo +maclo: + + mvi_h_accum0 0, 1 + mvi_h_gr r4, 0x1230001 + mvi_h_gr r5, 0x4560002 + maclo r4, r5 + test_h_accum0 0, 0x20001 + + pass diff --git a/sim/testsuite/sim/m32r/macwhi.cgs b/sim/testsuite/sim/m32r/macwhi.cgs new file mode 100644 index 00000000000..9ee7a5b0bb9 --- /dev/null +++ b/sim/testsuite/sim/m32r/macwhi.cgs @@ -0,0 +1,18 @@ +# m32r testcase for macwhi $src1,$src2 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global macwhi +macwhi: + mvi_h_accum0 0, 1 + mvi_h_gr r4, 0x10123 + mvi_h_gr r5, 0x20456 + + macwhi r4, r5 + + test_h_accum0 0, 0x20247 + + pass diff --git a/sim/testsuite/sim/m32r/macwlo.cgs b/sim/testsuite/sim/m32r/macwlo.cgs new file mode 100644 index 00000000000..a7ce4edac5c --- /dev/null +++ b/sim/testsuite/sim/m32r/macwlo.cgs @@ -0,0 +1,18 @@ +# m32r testcase for macwlo $src1,$src2 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global macwlo +macwlo: + mvi_h_accum0 0, 1 + mvi_h_gr r4, 0x10123 + mvi_h_gr r5, 0x40002 + + macwlo r4, r5 + + test_h_accum0 0, 0x20247 + + pass diff --git a/sim/testsuite/sim/m32r/misc.exp b/sim/testsuite/sim/m32r/misc.exp new file mode 100644 index 00000000000..6ed5638ab29 --- /dev/null +++ b/sim/testsuite/sim/m32r/misc.exp @@ -0,0 +1,21 @@ +# Miscellaneous M32R simulator testcases + +if [istarget m32r*-*-*] { + # load support procs + # load_lib cgen.exp + + # all machines + set all_machs "m32r" + + + # The .ms suffix is for "miscellaneous .s". + foreach src [lsort [glob -nocomplain $srcdir/$subdir/*.ms]] { + # If we're only testing specific files and this isn't one of them, + # skip it. + if ![runtest_file_p $runtests $src] { + continue + } + + run_sim_test $src $all_machs + } +} diff --git a/sim/testsuite/sim/m32r/mul.cgs b/sim/testsuite/sim/m32r/mul.cgs new file mode 100644 index 00000000000..c78f24b8117 --- /dev/null +++ b/sim/testsuite/sim/m32r/mul.cgs @@ -0,0 +1,17 @@ +# m32r testcase for mul $dr,$sr +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global mul +mul: + mvi_h_gr r4, 3 + mvi_h_gr r5, 7 + + mul r5, r4 + + test_h_gr r5, 21 + + pass diff --git a/sim/testsuite/sim/m32r/mulhi.cgs b/sim/testsuite/sim/m32r/mulhi.cgs new file mode 100644 index 00000000000..77c103d6f36 --- /dev/null +++ b/sim/testsuite/sim/m32r/mulhi.cgs @@ -0,0 +1,16 @@ +# m32r testcase for mulhi $src1,$src2 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global mulhi +mulhi: + + mvi_h_gr r4, 0x40000 + mvi_h_gr r5, 0x50000 + mulhi r4, r5 + test_h_accum0 0, 0x140000 + + pass diff --git a/sim/testsuite/sim/m32r/mullo.cgs b/sim/testsuite/sim/m32r/mullo.cgs new file mode 100644 index 00000000000..11aadff3794 --- /dev/null +++ b/sim/testsuite/sim/m32r/mullo.cgs @@ -0,0 +1,16 @@ +# m32r testcase for mullo $src1,$src2 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global mullo +mullo: + + mvi_h_gr r4, 4 + mvi_h_gr r5, 5 + mullo r4, r5 + test_h_accum0 0, 0x140000 + + pass diff --git a/sim/testsuite/sim/m32r/mulwhi.cgs b/sim/testsuite/sim/m32r/mulwhi.cgs new file mode 100644 index 00000000000..eb18562d9e7 --- /dev/null +++ b/sim/testsuite/sim/m32r/mulwhi.cgs @@ -0,0 +1,18 @@ +# m32r testcase for mulwhi $src1,$src2 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global mulwhi +mulwhi: + mvi_h_accum0 0, 1 + mvi_h_gr r4, 0x10123 + mvi_h_gr r5, 0x20456 + + mulwhi r4, r5 + + test_h_accum0 0, 0x20246 + + pass diff --git a/sim/testsuite/sim/m32r/mulwlo.cgs b/sim/testsuite/sim/m32r/mulwlo.cgs new file mode 100644 index 00000000000..d22c26827cd --- /dev/null +++ b/sim/testsuite/sim/m32r/mulwlo.cgs @@ -0,0 +1,18 @@ +# m32r testcase for mulwlo $src1,$src2 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global mulwlo +mulwlo: + mvi_h_accum0 0, 1 + mvi_h_gr r4, 0x10123 + mvi_h_gr r5, 0x40002 + + mulwlo r4, r5 + + test_h_accum0 0, 0x20246 + + pass diff --git a/sim/testsuite/sim/m32r/mv.cgs b/sim/testsuite/sim/m32r/mv.cgs new file mode 100644 index 00000000000..694569535b7 --- /dev/null +++ b/sim/testsuite/sim/m32r/mv.cgs @@ -0,0 +1,17 @@ +# m32r testcase for mv $dr,$sr +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global mv +mv: + mvi_h_gr r4, 1 + mvi_h_gr r5, 0 + + mv r5, r4 + + test_h_gr r5, 1 + + pass diff --git a/sim/testsuite/sim/m32r/mvfachi.cgs b/sim/testsuite/sim/m32r/mvfachi.cgs new file mode 100644 index 00000000000..0222e1b9118 --- /dev/null +++ b/sim/testsuite/sim/m32r/mvfachi.cgs @@ -0,0 +1,22 @@ +# m32r testcase for mvfachi $dr +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global mvfachi +mvfachi: + mvi_h_accum0 0x11223344, 0x55667788 + mvi_h_gr r4, 0 + + mvfachi r4 + test_h_gr r4, 0x223344 + + mvi_h_accum0 0x99aabbcc, 0x55667788 + mvi_h_gr r4, 0 + + mvfachi r4 + test_h_gr r4, 0xffaabbcc + + pass diff --git a/sim/testsuite/sim/m32r/mvfaclo.cgs b/sim/testsuite/sim/m32r/mvfaclo.cgs new file mode 100644 index 00000000000..0a88d849aee --- /dev/null +++ b/sim/testsuite/sim/m32r/mvfaclo.cgs @@ -0,0 +1,17 @@ +# m32r testcase for mvfaclo $dr +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global mvfaclo +mvfaclo: + mvi_h_accum0 0x11223344, 0x55667788 + mvi_h_gr r4, 0 + + mvfaclo r4 + + test_h_gr r4, 0x55667788 + + pass diff --git a/sim/testsuite/sim/m32r/mvfacmi.cgs b/sim/testsuite/sim/m32r/mvfacmi.cgs new file mode 100644 index 00000000000..580bcae9890 --- /dev/null +++ b/sim/testsuite/sim/m32r/mvfacmi.cgs @@ -0,0 +1,15 @@ +# m32r testcase for mvfacmi $dr +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global mvfacmi +mvfacmi: + + mvi_h_accum0 0x12345678, 0x87654321 + mvfacmi r4 + test_h_gr r4, 0x56788765 + + pass diff --git a/sim/testsuite/sim/m32r/mvfc.cgs b/sim/testsuite/sim/m32r/mvfc.cgs new file mode 100644 index 00000000000..ca2470e1e2d --- /dev/null +++ b/sim/testsuite/sim/m32r/mvfc.cgs @@ -0,0 +1,23 @@ +# m32r testcase for mvfc $dr,$scr +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global mvfc +mvfc: + mvi_h_condbit 0 + mvi_h_gr r4, 1 + + mvfc r4, cr1 + + test_h_gr r4, 0 + + mvi_h_condbit 1 + + mvfc r4, cr1 + + test_h_gr r4, 1 + + pass diff --git a/sim/testsuite/sim/m32r/mvtachi.cgs b/sim/testsuite/sim/m32r/mvtachi.cgs new file mode 100644 index 00000000000..6d596169557 --- /dev/null +++ b/sim/testsuite/sim/m32r/mvtachi.cgs @@ -0,0 +1,20 @@ +# m32r testcase for mvtachi $src1 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global mvtachi +mvtachi: + mvi_h_accum0 0, 0 + + mvi_h_gr r4, 0x11223344 + mvtachi r4 + test_h_accum0 0x223344, 0x0 + + mvi_h_gr r4, 0x99aabbcc + mvtachi r4 + test_h_accum0 0xffaabbcc, 0x0 + + pass diff --git a/sim/testsuite/sim/m32r/mvtaclo.cgs b/sim/testsuite/sim/m32r/mvtaclo.cgs new file mode 100644 index 00000000000..baafd839acb --- /dev/null +++ b/sim/testsuite/sim/m32r/mvtaclo.cgs @@ -0,0 +1,17 @@ +# m32r testcase for mvtaclo $src1 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global mvtaclo +mvtaclo: + mvi_h_accum0 0, 0 + mvi_h_gr r4, 0x11223344 + + mvtaclo r4 + + test_h_accum0 0, 0x11223344 + + pass diff --git a/sim/testsuite/sim/m32r/mvtc.cgs b/sim/testsuite/sim/m32r/mvtc.cgs new file mode 100644 index 00000000000..94780dfa11a --- /dev/null +++ b/sim/testsuite/sim/m32r/mvtc.cgs @@ -0,0 +1,18 @@ +# m32r testcase for mvtc $sr,$dcr +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global mvtc +mvtc: + mvi_h_condbit 0 + mvi_h_gr r4, 1 + + mvtc r4, cr1 + bc ok + + fail +ok: + pass diff --git a/sim/testsuite/sim/m32r/neg.cgs b/sim/testsuite/sim/m32r/neg.cgs new file mode 100644 index 00000000000..6051efaf256 --- /dev/null +++ b/sim/testsuite/sim/m32r/neg.cgs @@ -0,0 +1,17 @@ +# m32r testcase for neg $dr,$sr +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global neg +neg: + mvi_h_gr r4, 1 + mvi_h_gr r5, 2 + + neg r4, r5 + + test_h_gr r4, -2 + + pass diff --git a/sim/testsuite/sim/m32r/nop.cgs b/sim/testsuite/sim/m32r/nop.cgs new file mode 100644 index 00000000000..05b44bc552d --- /dev/null +++ b/sim/testsuite/sim/m32r/nop.cgs @@ -0,0 +1,10 @@ +# m32r testcase for nop +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global nop +nop: + pass diff --git a/sim/testsuite/sim/m32r/not.cgs b/sim/testsuite/sim/m32r/not.cgs new file mode 100644 index 00000000000..e6ceb643ebf --- /dev/null +++ b/sim/testsuite/sim/m32r/not.cgs @@ -0,0 +1,17 @@ +# m32r testcase for not $dr,$sr +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global not +not: + mvi_h_gr r4, 1 + mvi_h_gr r5, 2 + + not r4, r5 + + test_h_gr r4, 0xfffffffd + + pass diff --git a/sim/testsuite/sim/m32r/or.cgs b/sim/testsuite/sim/m32r/or.cgs new file mode 100644 index 00000000000..1b08bd0c2a7 --- /dev/null +++ b/sim/testsuite/sim/m32r/or.cgs @@ -0,0 +1,17 @@ +# m32r testcase for or $dr,$sr +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global or +or: + mvi_h_gr r4, 3 + mvi_h_gr r5, 6 + + or r4, r5 + + test_h_gr r4, 7 + + pass diff --git a/sim/testsuite/sim/m32r/or3.cgs b/sim/testsuite/sim/m32r/or3.cgs new file mode 100644 index 00000000000..dc76ada9333 --- /dev/null +++ b/sim/testsuite/sim/m32r/or3.cgs @@ -0,0 +1,17 @@ +# m32r testcase for or3 $dr,$sr,#$ulo16 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global or3 +or3: + mvi_h_gr r4, 0 + mvi_h_gr r5, 6 + + or3 r4, r5, #3 + + test_h_gr r4, 7 + + pass diff --git a/sim/testsuite/sim/m32r/rac.cgs b/sim/testsuite/sim/m32r/rac.cgs new file mode 100644 index 00000000000..35b9ae3cd91 --- /dev/null +++ b/sim/testsuite/sim/m32r/rac.cgs @@ -0,0 +1,23 @@ +# m32r testcase for rac +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global rac +rac: + + mvi_h_accum0 1, 0x4001 + rac + test_h_accum0 2, 0x10000 + + mvi_h_accum0 0x3fff, 0xffff4000 + rac + test_h_accum0 0x7fff, 0xffff0000 + + mvi_h_accum0 0xffff8000, 0 + rac + test_h_accum0 0xffff8000, 0 + + pass diff --git a/sim/testsuite/sim/m32r/rach.cgs b/sim/testsuite/sim/m32r/rach.cgs new file mode 100644 index 00000000000..c22469834f7 --- /dev/null +++ b/sim/testsuite/sim/m32r/rach.cgs @@ -0,0 +1,22 @@ +# m32r testcase for rach +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global rach +rach: + mvi_h_accum0 1, 0x40004001 + rach + test_h_accum0 3, 0 + + mvi_h_accum0 0x3fff, 0xc0000000 + rach + test_h_accum0 0x7fff, 0 + + mvi_h_accum0 0xffff8000, 0 + rach + test_h_accum0 0xffff8000, 0 + + pass diff --git a/sim/testsuite/sim/m32r/rem.cgs b/sim/testsuite/sim/m32r/rem.cgs new file mode 100644 index 00000000000..78c11cbcf90 --- /dev/null +++ b/sim/testsuite/sim/m32r/rem.cgs @@ -0,0 +1,17 @@ +# m32r testcase for rem $dr,$sr +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global rem +rem: + mvi_h_gr r4, 12345678 + mvi_h_gr r5, 7 + + rem r4, r5 + + test_h_gr r4, 2 + + pass diff --git a/sim/testsuite/sim/m32r/remu.cgs b/sim/testsuite/sim/m32r/remu.cgs new file mode 100644 index 00000000000..36336306b27 --- /dev/null +++ b/sim/testsuite/sim/m32r/remu.cgs @@ -0,0 +1,23 @@ +# m32r testcase for remu $dr,$sr +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global remu +remu: + mvi_h_gr r4, 17 + mvi_h_gr r5, 7 + + remu r4, r5 + + test_h_gr r4, 3 + + mvi_h_gr r4, -17 + + remu r4, r5 + + test_h_gr r4, 1 + + pass diff --git a/sim/testsuite/sim/m32r/rte.cgs b/sim/testsuite/sim/m32r/rte.cgs new file mode 100644 index 00000000000..b389fe15431 --- /dev/null +++ b/sim/testsuite/sim/m32r/rte.cgs @@ -0,0 +1,87 @@ +# m32r testcase for rte +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global rte +rte: + +; Test 1: bbpsw = 0, bpsw = 1, psw = 0 + + ; bbsm = 0, bie = 0, bbcond = 0 + mvi_h_gr r4, 0 + mvtc r4, cr8 + + ; bsm = 1, bie = 1, bcond = 1, sm = 0, ie = 0, cond = 0 + mvi_h_gr r4, 0xc100 + mvtc r4, cr0 + + ; bbpc = 0 + mvaddr_h_gr r4, 0 + mvtc r4, bbpc + + ; bpc = ret1 + mvaddr_h_gr r4, ret1 + mvtc r4, bpc + + rte + fail + +ret1: + ; test bbsm = 0, bbie = 0, bbcond = 0 + mvfc r4, cr8 + test_h_gr r4, 0 + + ; test bsm = 0, bie = 0, bcond = 0, sm = 1, ie = 1, cond = 1 + mvfc r4, cr0 + test_h_gr r4, 0xc1 + + ; test bbpc = 0 + mvfc r4, bbpc + test_h_gr r4, 0 + + ; test bpc = 0 + mvfc r4, bpc + test_h_gr r4, 0 + +; Test 2: bbpsw = 1, bpsw = 0, psw = 1 + + ; bbsm = 1, bie = 1, bbcond = 1 + mvi_h_gr r4, 0xc1 + mvtc r4, cr8 + + ; bsm = 0, bie = 0, bcond = 0, sm = 1, ie = 1, cond = 1 + mvi_h_gr r4, 0xc1 + mvtc r4, cr0 + + ; bbpc = 42 + mvaddr_h_gr r4, 42 + mvtc r4, bbpc + + ; bpc = ret2 + 2 + mvaddr_h_gr r4, ret2 + 2 + mvtc r4, bpc + + rte + fail + +ret2: + ; test bbsm = 1, bbie = 1, bbcond = 1 + mvfc r4, cr8 + test_h_gr r4, 0xc1 + + ; test bsm = 1, bie = 1, bcond = 1, sm = 0, ie = 0, cond = 0 + mvfc r4, cr0 + test_h_gr r4, 0xc100 + + ; test bbpc = 42 + mvfc r4, bbpc + test_h_gr r4, 42 + + ; test bpc = 42 + mvfc r4, bpc + test_h_gr r4, 42 + + pass diff --git a/sim/testsuite/sim/m32r/seth.cgs b/sim/testsuite/sim/m32r/seth.cgs new file mode 100644 index 00000000000..aec3230a548 --- /dev/null +++ b/sim/testsuite/sim/m32r/seth.cgs @@ -0,0 +1,20 @@ +# m32r testcase for seth $dr,#$hi16 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global seth +seth: + seth r4, #0x1234 + + ; do not use test_h_gr macro since this uses seth + + srli r4, #16 + ld24 r5, #0x1234 + beq r4, r5, ok + + fail +ok: + pass diff --git a/sim/testsuite/sim/m32r/sll.cgs b/sim/testsuite/sim/m32r/sll.cgs new file mode 100644 index 00000000000..fa3cfed8861 --- /dev/null +++ b/sim/testsuite/sim/m32r/sll.cgs @@ -0,0 +1,15 @@ +# m32r testcase for sll $dr,$sr +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global sll +sll: + mvi_h_gr r4, 6 + mvi_h_gr r5, 1 + sll r4, r5 + test_h_gr r4, 12 + + pass diff --git a/sim/testsuite/sim/m32r/sll3.cgs b/sim/testsuite/sim/m32r/sll3.cgs new file mode 100644 index 00000000000..ddd360cd111 --- /dev/null +++ b/sim/testsuite/sim/m32r/sll3.cgs @@ -0,0 +1,15 @@ +# m32r testcase for sll3 $dr,$sr,#$simm16 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global sll3 +sll3: + mvi_h_gr r4, 1 + mvi_h_gr r5, 6 + sll3 r4, r5, #1 + test_h_gr r4, 12 + + pass diff --git a/sim/testsuite/sim/m32r/slli.cgs b/sim/testsuite/sim/m32r/slli.cgs new file mode 100644 index 00000000000..eab77daa695 --- /dev/null +++ b/sim/testsuite/sim/m32r/slli.cgs @@ -0,0 +1,14 @@ +# m32r testcase for slli $dr,#$uimm5 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global slli +slli: + mvi_h_gr r4, 6 + slli r4, #1 + test_h_gr r4, 12 + + pass diff --git a/sim/testsuite/sim/m32r/sra.cgs b/sim/testsuite/sim/m32r/sra.cgs new file mode 100644 index 00000000000..11671ed8658 --- /dev/null +++ b/sim/testsuite/sim/m32r/sra.cgs @@ -0,0 +1,16 @@ +# m32r testcase for sra $dr,$sr +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global sra +sra: + + mvi_h_gr r4, 0xf0f0f0ff + mvi_h_gr r5, 4 + sra r4, r5 + test_h_gr r4, 0xff0f0f0f + + pass diff --git a/sim/testsuite/sim/m32r/sra3.cgs b/sim/testsuite/sim/m32r/sra3.cgs new file mode 100644 index 00000000000..0dd387adf46 --- /dev/null +++ b/sim/testsuite/sim/m32r/sra3.cgs @@ -0,0 +1,16 @@ +# m32r testcase for sra3 $dr,$sr,#$simm16 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global sra3 +sra3: + + mvi_h_gr r4, 0 + mvi_h_gr r5, 0xf0f0f0ff + sra3 r4, r5, #4 + test_h_gr r4, 0xff0f0f0f + + pass diff --git a/sim/testsuite/sim/m32r/srai.cgs b/sim/testsuite/sim/m32r/srai.cgs new file mode 100644 index 00000000000..2a1569422a5 --- /dev/null +++ b/sim/testsuite/sim/m32r/srai.cgs @@ -0,0 +1,14 @@ +# m32r testcase for srai $dr,#$uimm5 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global srai +srai: + mvi_h_gr r5, 0xf0f0f0ff + srai r5, #4 + test_h_gr r5, 0xff0f0f0f + + pass diff --git a/sim/testsuite/sim/m32r/srl.cgs b/sim/testsuite/sim/m32r/srl.cgs new file mode 100644 index 00000000000..8838c2fbd48 --- /dev/null +++ b/sim/testsuite/sim/m32r/srl.cgs @@ -0,0 +1,15 @@ +# m32r testcase for srl $dr,$sr +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global srl +srl: + mvi_h_gr r4, 6 + mvi_h_gr r5, 1 + srl r4, r5 + test_h_gr r4, 3 + + pass diff --git a/sim/testsuite/sim/m32r/srl3.cgs b/sim/testsuite/sim/m32r/srl3.cgs new file mode 100644 index 00000000000..a1dc4840f63 --- /dev/null +++ b/sim/testsuite/sim/m32r/srl3.cgs @@ -0,0 +1,15 @@ +# m32r testcase for srl3 $dr,$sr,#$simm16 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global srl3 +srl3: + mvi_h_gr r4, 0 + mvi_h_gr r5, 6 + srl3 r4, r5, #1 + test_h_gr r4, 3 + + pass diff --git a/sim/testsuite/sim/m32r/srli.cgs b/sim/testsuite/sim/m32r/srli.cgs new file mode 100644 index 00000000000..f358a768a7f --- /dev/null +++ b/sim/testsuite/sim/m32r/srli.cgs @@ -0,0 +1,15 @@ +# m32r testcase for srli $dr,#$uimm5 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global srli +srli: + mvi_h_gr r5, 6 + srli r5, #1 + test_h_gr r5, 3 + + + pass diff --git a/sim/testsuite/sim/m32r/st-d.cgs b/sim/testsuite/sim/m32r/st-d.cgs new file mode 100644 index 00000000000..e2668a05c04 --- /dev/null +++ b/sim/testsuite/sim/m32r/st-d.cgs @@ -0,0 +1,26 @@ +# m32r testcase for st $src1,@($slo16,$src2) +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global st_d +st_d: + mvaddr_h_gr r4, data_loc + mvi_h_gr r5, 1 + + st r5, @(#8,r4) + + mvaddr_h_gr r4, data_loc2 + ld r4, @r4 + test_h_gr r4, 1 + + pass + +data_loc: + .word 0 + .word 0 +data_loc2: + .word 0 + diff --git a/sim/testsuite/sim/m32r/st-minus.cgs b/sim/testsuite/sim/m32r/st-minus.cgs new file mode 100644 index 00000000000..fc90351c389 --- /dev/null +++ b/sim/testsuite/sim/m32r/st-minus.cgs @@ -0,0 +1,29 @@ +# m32r testcase for st $src1,@-$src2 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global st_minus +st_minus: + mvaddr_h_gr r4, data_loc2 + mvi_h_gr r5, 1 + + st r5, @-r4 + + mvaddr_h_gr r5, data_loc + + bne r4, r5, not_ok + ld r4, @r4 + test_h_gr r4, 1 + + pass +not_ok: + fail + +data_loc: + .word 0 +data_loc2: + .word 0 + diff --git a/sim/testsuite/sim/m32r/st-plus.cgs b/sim/testsuite/sim/m32r/st-plus.cgs new file mode 100644 index 00000000000..7bb4dd16fe7 --- /dev/null +++ b/sim/testsuite/sim/m32r/st-plus.cgs @@ -0,0 +1,28 @@ +# m32r testcase for st $src1,@+$src2 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global st_plus +st_plus: + mvaddr_h_gr r4, data_loc + mvi_h_gr r5, 1 + + st r5, @+r4 + + mvaddr_h_gr r5, data_loc2 + + bne r4, r5, not_ok + ld r4, @r4 + test_h_gr r4, 1 + + pass +not_ok: + fail + +data_loc: + .word 0 +data_loc2: + .word 0 diff --git a/sim/testsuite/sim/m32r/st.cgs b/sim/testsuite/sim/m32r/st.cgs new file mode 100644 index 00000000000..9588b8c40c8 --- /dev/null +++ b/sim/testsuite/sim/m32r/st.cgs @@ -0,0 +1,21 @@ +# m32r testcase for st $src1,@$src2 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global st +st: + mvaddr_h_gr r4, data_loc + mvi_h_gr r5, 1 + + st r5, @r4 + + ld r4, @r4 + test_h_gr r4, 1 + + pass + +data_loc: + .word 0 diff --git a/sim/testsuite/sim/m32r/stb-d.cgs b/sim/testsuite/sim/m32r/stb-d.cgs new file mode 100644 index 00000000000..37c2d733d72 --- /dev/null +++ b/sim/testsuite/sim/m32r/stb-d.cgs @@ -0,0 +1,25 @@ +# m32r testcase for stb $src1,@($slo16,$src2) +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global stb_d +stb_d: + mvaddr_h_gr r4, data_loc + mvi_h_gr r5, 0x1234 + + stb r5, @(#8,r4) + + mvaddr_h_gr r4, data_loc2 + ld r4, @r4 + test_h_gr r4, 0x34000000 ; big endian processor + + pass + +data_loc: + .word 0 + .word 0 +data_loc2: + .word 0 diff --git a/sim/testsuite/sim/m32r/stb.cgs b/sim/testsuite/sim/m32r/stb.cgs new file mode 100644 index 00000000000..01283169023 --- /dev/null +++ b/sim/testsuite/sim/m32r/stb.cgs @@ -0,0 +1,21 @@ +# m32r testcase for stb $src1,@$src2 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global stb +stb: + mvaddr_h_gr r4, data_loc + mvi_h_gr r5, 0x1234 + + stb r5, @r4 + + ld r4, @r4 + test_h_gr r4, 0x34000000 ; big endian processor + + pass + +data_loc: + .word 0 diff --git a/sim/testsuite/sim/m32r/sth-d.cgs b/sim/testsuite/sim/m32r/sth-d.cgs new file mode 100644 index 00000000000..11aaa6d76c1 --- /dev/null +++ b/sim/testsuite/sim/m32r/sth-d.cgs @@ -0,0 +1,25 @@ +# m32r testcase for sth $src1,@($slo16,$src2) +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global sth_d +sth_d: + mvaddr_h_gr r4, data_loc + mvi_h_gr r5, 0x123456 + + sth r5, @(#8,r4) + + mvaddr_h_gr r4, data_loc2 + ld r4, @r4 + test_h_gr r4, 0x34560000 ; big endian processor + + pass + +data_loc: + .word 0 + .word 0 +data_loc2: + .word 0 diff --git a/sim/testsuite/sim/m32r/sth.cgs b/sim/testsuite/sim/m32r/sth.cgs new file mode 100644 index 00000000000..1a10fde1ce3 --- /dev/null +++ b/sim/testsuite/sim/m32r/sth.cgs @@ -0,0 +1,21 @@ +# m32r testcase for sth $src1,@$src2 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global sth +sth: + mvaddr_h_gr r4, data_loc + mvi_h_gr r5, 0x123456 + + sth r5, @r4 + + ld r4, @r4 + test_h_gr r4, 0x34560000 ; big endian processor + + pass + +data_loc: + .word 0 diff --git a/sim/testsuite/sim/m32r/sub.cgs b/sim/testsuite/sim/m32r/sub.cgs new file mode 100644 index 00000000000..4d676e58083 --- /dev/null +++ b/sim/testsuite/sim/m32r/sub.cgs @@ -0,0 +1,18 @@ +# m32r testcase for sub $dr,$sr +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global sub +sub: + + mvi_h_gr r4, 7 + mvi_h_gr r5, 3 + + sub r4, r5 + + test_h_gr r4, 4 + + pass diff --git a/sim/testsuite/sim/m32r/subv.cgs b/sim/testsuite/sim/m32r/subv.cgs new file mode 100644 index 00000000000..9474766e55b --- /dev/null +++ b/sim/testsuite/sim/m32r/subv.cgs @@ -0,0 +1,20 @@ +# m32r testcase for subv $dr,$sr +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global subv +subv: + mvi_h_condbit 0 + mvi_h_gr r4, 0x80000000 + mvi_h_gr r5, 3 + + subv r4, r5 + + bc ok + + fail +ok: + pass diff --git a/sim/testsuite/sim/m32r/subx.cgs b/sim/testsuite/sim/m32r/subx.cgs new file mode 100644 index 00000000000..e890fcfabd7 --- /dev/null +++ b/sim/testsuite/sim/m32r/subx.cgs @@ -0,0 +1,26 @@ +# m32r testcase for subx $dr,$sr +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global subx +subx: + mvi_h_condbit 1 + mvi_h_gr r4, 6 + mvi_h_gr r5, 4 + subx r4, r5 + bc not_ok + test_h_gr r4, 1 + + mvi_h_condbit 1 + mvi_h_gr r4, 4 + mvi_h_gr r5, 4 + subx r4, r5 + bnc not_ok + test_h_gr r4, 0xffffffff + + pass +not_ok: + fail diff --git a/sim/testsuite/sim/m32r/testutils.inc b/sim/testsuite/sim/m32r/testutils.inc new file mode 100644 index 00000000000..1d8822ae098 --- /dev/null +++ b/sim/testsuite/sim/m32r/testutils.inc @@ -0,0 +1,95 @@ +# r0-r3 are used as tmps, consider them call clobbered by these macros. + + .macro start + .data +failmsg: + .ascii "fail\n" +passmsg: + .ascii "pass\n" + .text + .global _start +_start: + .endm + + .macro exit rc + ldi8 r1, \rc + ldi8 r0, #1 + trap #0 + .endm + + .macro pass + ldi8 r3, 5 + ld24 r2, passmsg + ldi8 r1, 1 + ldi8 r0, 5 + trap #0 + exit 0 + .endm + + .macro fail + ldi8 r3, 5 + ld24 r2, failmsg + ldi8 r1, 1 + ldi8 r0, 5 + trap #0 + exit 1 + .endm + + .macro mvi_h_gr reg, val + .if (\val >= -128) && (\val <= 127) + ldi8 \reg, \val + .else + seth \reg, high(\val) + or3 \reg, \reg, low(\val) + .endif + .endm + + .macro mvaddr_h_gr reg, addr + seth \reg, high(\addr) + or3 \reg, \reg, low(\addr) + .endm + +# Other macros know this only clobbers r0. + .macro test_h_gr reg, val + mvaddr_h_gr r0, \val + beq \reg, r0, test_gr\@ + fail +test_gr\@: + .endm + + .macro mvi_h_condbit val + ldi8 r0, 0 + ldi8 r1, 1 + .if \val + cmp r0, r1 + .else + cmp r1, r0 + .endif + .endm + + .macro test_h_condbit val + .if \val + bc test_c1\@ + fail +test_c1\@: + .else + bnc test_c0\@ + fail +test_c0\@: + .endif + .endm + + .macro mvi_h_accum0 hi, lo + mvi_h_gr r0, \hi + mvtachi r0 + mvi_h_gr r0, \lo + mvtaclo r0 + .endm + + .macro test_h_accum0 hi, lo + mvfachi r1 + test_h_gr r1, \hi + mvfaclo r1 + test_h_gr r1, \lo + .endm + diff --git a/sim/testsuite/sim/m32r/trap.cgs b/sim/testsuite/sim/m32r/trap.cgs new file mode 100644 index 00000000000..59e136a0173 --- /dev/null +++ b/sim/testsuite/sim/m32r/trap.cgs @@ -0,0 +1,109 @@ +# m32r testcase for trap #$uimm4 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global trap +trap: + +; Test 1: bbpsw = 0, bpsw = 1, psw = 0 + + ; bbsm = 0, bie = 0, bbcond = 0 + mvi_h_gr r4, 0 + mvtc r4, cr8 + + ; bsm = 1, bie = 1, bcond = 1, sm = 0, ie = 0, cond = 0 + mvi_h_gr r4, 0xc100 + mvtc r4, cr0 + + ; bbpc = 0 + mvaddr_h_gr r4, 0 + mvtc r4, bbpc + + ; bpc = 42 + mvaddr_h_gr r4, 42 + mvtc r4, bpc + + ; Copy trap2_handler to trap area of memory. + ld24 r0,#0x48 ; address of trap 2 handler + ld24 r1,#trap2_handler + ld r2,@r1 + st r2,@r0 + ; Set up return address. + ld24 r5,#trap2_ret1 + +trap_insn1: + trap #2 + fail + +trap2_ret1: + ; test bbsm = 1, bbie = 1, bbcond = 1 + mvfc r4, cr8 + test_h_gr r4, 0xc1 + + ; test bsm = 0, bie = 0, bcond = 0, sm = 0, ie = 0, cond = 0 + mvfc r4, cr0 + test_h_gr r4, 0 + + ; test bbpc = 42 + mvfc r4, bbpc + test_h_gr r4, 42 + + ; test bpc = proper return address + mvfc r4, bpc + test_h_gr r4, trap_insn1 + 4 + +; Test 2: bbpsw = 1, bpsw = 0, psw = 1 + + ; bbsm = 1, bie = 1, bbcond = 1 + mvi_h_gr r4, 0xc1 + mvtc r4, cr8 + + ; bsm = 0, bie = 0, bcond = 0, sm = 1, ie = 1, cond = 1 + mvi_h_gr r4, 0xc1 + mvtc r4, cr0 + + ; bbpc = 42 + mvaddr_h_gr r4, 42 + mvtc r4, bbpc + + ; bpc = 0 + mvaddr_h_gr r4, 0 + mvtc r4, bpc + + ; Set up return address. + ld24 r5,#trap2_ret2 + +trap_insn2: + trap #2 + fail + +trap2_ret2: + ; test bbsm = 0, bbie = 0, bbcond = 0 + mvfc r4, cr8 + test_h_gr r4, 0 + + ; test bsm = 1, bie = 1, bcond = 1, sm = 1, ie = 0, cond = 0 + mvfc r4, cr0 + test_h_gr r4, 0xc180 + + ; test bbpc = 0 + mvfc r4, bbpc + test_h_gr r4, 0 + + ; test bpc = proper return address + mvfc r4, bpc + test_h_gr r4, trap_insn2 + 4 + + pass + + .data + +; Don't use rte as it will undo the effects of trap we're testing. + + .p2align 2 +trap2_handler: + jmp r5 + nop diff --git a/sim/testsuite/sim/m32r/unlock.cgs b/sim/testsuite/sim/m32r/unlock.cgs new file mode 100644 index 00000000000..1a51b7ae4cf --- /dev/null +++ b/sim/testsuite/sim/m32r/unlock.cgs @@ -0,0 +1,30 @@ +# m32r testcase for unlock $src1,@$src2 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global unlock +unlock: + mvaddr_h_gr r4, data_loc + mvi_h_gr r5, 1 + + lock r5, @r4 + + mvi_h_gr r5, 2 + unlock r5, @r4 + + ld r6, @r4 + test_h_gr r6, 2 + + mvi_h_gr r5, 0 + unlock r5, @r4 ; This should be a nop since the processor should be unlocked. + + ld r6, @r4 + test_h_gr r6, 2 + + pass + +data_loc: + .word 0 diff --git a/sim/testsuite/sim/m32r/uread16.ms b/sim/testsuite/sim/m32r/uread16.ms new file mode 100644 index 00000000000..550e99a2dfc --- /dev/null +++ b/sim/testsuite/sim/m32r/uread16.ms @@ -0,0 +1,18 @@ +# mach: m32r m32rx +# xerror: +# output: *misaligned read* + + .include "testutils.inc" + + start + +; construct bra trap2_handler in trap 2 slot + ld24 r0,#foo+1 + ldh r0,@r0 + fail + exit 0 + +.data + .p2align 2 +foo: + .short 42 diff --git a/sim/testsuite/sim/m32r/uread32.ms b/sim/testsuite/sim/m32r/uread32.ms new file mode 100644 index 00000000000..935c71624e4 --- /dev/null +++ b/sim/testsuite/sim/m32r/uread32.ms @@ -0,0 +1,18 @@ +# mach: m32r m32rx +# xerror: +# output: *misaligned read* + + .include "testutils.inc" + + start + +; construct bra trap2_handler in trap 2 slot + ld24 r0,#foo+1 + ld r0,@r0 + fail + exit 0 + +.data + .p2align 2 +foo: + .word 42 diff --git a/sim/testsuite/sim/m32r/uwrite16.ms b/sim/testsuite/sim/m32r/uwrite16.ms new file mode 100644 index 00000000000..11bfd6ee2a9 --- /dev/null +++ b/sim/testsuite/sim/m32r/uwrite16.ms @@ -0,0 +1,18 @@ +# mach: m32r m32rx +# xerror: +# output: *misaligned write* + + .include "testutils.inc" + + start + +; construct bra trap2_handler in trap 2 slot + ld24 r0,#foo+1 + sth r0,@r0 + fail + exit 0 + +.data + .p2align 2 +foo: + .short 42 diff --git a/sim/testsuite/sim/m32r/uwrite32.ms b/sim/testsuite/sim/m32r/uwrite32.ms new file mode 100644 index 00000000000..495a123b60e --- /dev/null +++ b/sim/testsuite/sim/m32r/uwrite32.ms @@ -0,0 +1,18 @@ +# mach: m32r m32rx +# xerror: +# output: *misaligned write* + + .include "testutils.inc" + + start + +; construct bra trap2_handler in trap 2 slot + ld24 r0,#foo+1 + st r0,@r0 + fail + exit 0 + +.data + .p2align 2 +foo: + .word 42 diff --git a/sim/testsuite/sim/m32r/xor.cgs b/sim/testsuite/sim/m32r/xor.cgs new file mode 100644 index 00000000000..254da798167 --- /dev/null +++ b/sim/testsuite/sim/m32r/xor.cgs @@ -0,0 +1,16 @@ +# m32r testcase for xor $dr,$sr +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global xor +xor: + + mvi_h_gr r4, 3 + mvi_h_gr r5, 6 + xor r4, r5 + test_h_gr r4, 5 + + pass diff --git a/sim/testsuite/sim/m32r/xor3.cgs b/sim/testsuite/sim/m32r/xor3.cgs new file mode 100644 index 00000000000..eee7269f934 --- /dev/null +++ b/sim/testsuite/sim/m32r/xor3.cgs @@ -0,0 +1,16 @@ +# m32r testcase for xor3 $dr,$sr,#$uimm16 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global xor3 +xor3: + + mvi_h_gr r5, 0 + mvi_h_gr r4, 3 + xor3 r5, r4, #6 + test_h_gr r5, 5 + + pass |