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* Only allow 32-bit/64-bit registers for bndcl/bndcu/bndcnH.J. Lu2013-10-121-2/+2
* opcodes/Roland McGrath2013-10-111-20/+28
* Remove PREFIX_EVEX_0F3A3E and PREFIX_EVEX_0F3A3FH.J. Lu2013-08-191-2/+0
* Add Intel AVX-512 supportH.J. Lu2013-07-261-31/+1306
* Support Intel SHAH.J. Lu2013-07-251-7/+49
* Support Intel MPXH.J. Lu2013-07-241-47/+126
* Properly check address mode for SIBH.J. Lu2013-03-271-4/+4
* Implement Intel SMAP instructionsH.J. Lu2013-02-191-0/+2
* gas/testsuite/Roland McGrath2012-10-241-58/+61
* gas/testsuite/Roland McGrath2012-08-071-0/+30
* gas/testsuite/Roland McGrath2012-08-061-6/+12
* gas/testsuite/Roland McGrath2012-08-061-30/+34
* Use vex_len_table in xop_tableH.J. Lu2012-07-191-8/+56
* Implement RDRSEED, ADX and PRFCHW instructionsH.J. Lu2012-07-161-1/+11
* Implement Intel Transactional Synchronization ExtensionsH.J. Lu2012-02-081-60/+175
* Add vmfuncH.J. Lu2012-01-131-0/+3
* PR binutils/13348Nick Clifton2011-10-261-1/+1
* opcodes/qneill2011-08-021-1/+1
* Check R_X86_64_32 overflow and allow R_X86_64_64 for x32.H.J. Lu2011-08-011-33/+11
* Add initial Intel K1OM support.H.J. Lu2011-07-221-3/+8
* Update rorxS.H.J. Lu2011-07-011-1/+1
* Fix rorx in BMI2.H.J. Lu2011-06-301-1/+1
* Re-indent prefix_table.H.J. Lu2011-06-211-2/+2
* Support AVX Programming Reference (June, 2011).H.J. Lu2011-06-101-960/+840
* 2011-02-09 Michael Snyder <msnyder@vmware.com>Michael Snyder2011-02-091-5/+5
* Properly sign-extend byte.H.J. Lu2011-01-181-3/+28
* Add support for TBM instructions.qneill2011-01-171-5/+28
* Implement BMI instructions.H.J. Lu2011-01-051-4/+80
* Add VexGdq.H.J. Lu2011-01-041-2/+8
* Add x86-64 ILP32 support.H.J. Lu2010-12-311-0/+5
* Remove duplicated RMAL.H.J. Lu2010-10-021-1/+0
* Fix "pushw imm16" for x86-64 disassembler.H.J. Lu2010-08-311-38/+30
* Replace Eb with Mb on prefetch and prefetchw.H.J. Lu2010-08-171-2/+2
* Add ud1 to x86.H.J. Lu2010-08-061-2/+2
* Add 0F to VEX opcode enums.H.J. Lu2010-07-281-2259/+2259
* Replace rdrnd with rdrand.H.J. Lu2010-07-051-1/+1
* Support AVX Programming Reference (June, 2010)H.J. Lu2010-07-011-3/+52
* Add SIB.H.J. Lu2010-05-261-4/+28
* Remove extra breack.H.J. Lu2010-04-161-1/+0
* Return bad_opcode on unknown bits in opcode.H.J. Lu2010-04-161-5/+17
* bfd/ChangeLogNick Clifton2010-04-091-8/+0
* 2010-03-22 Sebastian Pop <sebastian.pop@amd.com>spop2010-03-231-18/+4
* Update copyright.H.J. Lu2010-02-111-1/+1
* 2010-02-10 Quentin Neill <quentin.neill@amd.com>spop2010-02-111-2/+73
* Allow VL=1 on scalar FMA instructions.H.J. Lu2010-01-281-13/+18
* Allow VL=1 on AVX scalar instructions.H.J. Lu2010-01-271-44/+125
* Remove trailing { Bad_Opcode }.H.J. Lu2010-01-241-1/+0
* Remove trailing { Bad_Opcode } in vex_len_table.H.J. Lu2010-01-241-1/+0
* Remove trailing { Bad_Opcode }.H.J. Lu2010-01-241-1/+0
* Remove trailing "(bad)" entries and replace { "(bad)", { XX } }H.J. Lu2010-01-241-3561/+2647
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