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* Add support for V850E3V5 architectureNick Clifton2013-01-243-197/+955
* include/opcode/yufeng2013-01-175-10/+28
* Add OPERAND_TYPE_IMM32_64H.J. Lu2013-01-164-2/+16
* * config/tc-v850.c (md_assemble): Allow signed values forNick Clifton2013-01-153-2/+10
* * metag-dis.c (REG_WIDTH): Increase to 64.Nick Clifton2013-01-142-1/+5
* include/opcode/Peter Bergner2013-01-113-1/+76
* * common.h: Fix case of "Meta".Nick Clifton2013-01-107-0/+3409
* oops - typo correction.Nick Clifton2013-01-071-1/+1
* (make_instruction): Rename to cr16_make_instruction.Nick Clifton2013-01-072-4/+9
* * archures.c: Add support for MIPS r5900Nick Clifton2013-01-043-138/+341
* opcodes/yufeng2013-01-043-8/+33
* * aarch64-opc.c (aarch64_prfops): Update to support PLIL1KEEP,Nick Clifton2013-01-042-14/+19
* Update copyright year to 2013H.J. Lu2013-01-022-2/+6
* opcodes/ChangeLogNick Clifton2013-01-023-1111/+1140
* Add copyright noticesNick Clifton2012-12-1711-2/+187
* PR binutils/14950Alan Modra2012-12-132-65/+46
* Add copyright noticesNick Clifton2012-12-1013-0/+81
* 2012-11-30 Oleg Raikhman <oleg@adapteva.com>Joern Rennecke2012-11-304-121/+126
* opcodes/Roland McGrath2012-11-292-5/+9
* opcodes/Changelog:eager2012-11-293-7/+13
* include/opcode/Alan Modra2012-11-232-24/+76
* Add swap byte (swapb) and swap halfword (swaph) opcodes.eager2012-11-213-2/+9
* Add stack high register and stack low register for MicroBlazeeager2012-11-213-0/+15
* Fix opcode for 64-bit jecxzH.J. Lu2012-11-203-2/+9
* 2012-11-20 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>Andreas Krebbel2012-11-202-2/+6
* opcodes/eager2012-11-144-4/+45
* Add clz opcode.eager2012-11-143-2/+8
* Add the endian reversing versions of load/store instructions;eager2012-11-143-2/+16
* 2012-11-09 Nick Clifton <nickc@redhat.com>Nick Clifton2012-11-094-0/+9
* Remove trailing redundant `;'H.J. Lu2012-11-093-2/+7
* Regenerate.Alan Modra2012-11-082-0/+15
* * configure.in: Apply 2012-09-10 change to config.in here.Alan Modra2012-11-052-2/+7
* 2012-10-26 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>Andreas Krebbel2012-10-264-3/+32
* gas/testsuite:Christian Groessler2012-10-263-61/+59
* * ppc-opc (powerpc_opcodes): "lfdp" and "stfdp" use DS offset.Alan Modra2012-10-262-2/+6
* gas/testsuite/Roland McGrath2012-10-242-58/+66
* opcodes/Peter Bergner2012-10-222-1/+5
* * tic54x-dis.c (print_instruction): Don't use K&R style.Tom Tromey2012-10-182-38/+37
* * aarch64-asm.c (aarch64_ins_ldst_reglist): InitializeKai Tietz2012-10-183-7/+16
* Updated the system register table.yufeng2012-10-152-4/+8
* Added the changelog for the previous commit.yufeng2012-10-151-0/+6
* Added missing alignment check to load/store uimm12 immediate offset.yufeng2012-10-151-1/+1
* 2012-10-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>Richard Earnshaw2012-10-112-5/+10
* Add AMD bdver3 support.neggone2012-10-093-0/+13
* opcodes/Peter Bergner2012-10-053-1/+21
* * v850-dis.c (disassemble): Place square parentheses around secondNick Clifton2012-10-042-4/+21
* 2012-10-04 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>Andreas Krebbel2012-10-044-34/+90
* Don't abort() when disassembling bad moxie instructions.Anthony Green2012-09-283-29/+102
* Add missing Cpu flags in bd and bt coresH.J. Lu2012-09-253-16/+23
* Replace CpuSSE3 with CpuCX16 for cmpxchg16bH.J. Lu2012-09-206-2964/+2989
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