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* gdb:Joseph Myers2011-05-0410-9/+29
* sim: bfin: constify dmac pmap arraysMike Frysinger2011-04-272-13/+22
* sim: gpio: add output supportMike Frysinger2011-04-262-16/+53
* sim: gpio: update mask a/b signals betterMike Frysinger2011-04-262-12/+49
* sim: add sim_complete_command stubs for non-common-using portsMike Frysinger2011-04-1614-0/+69
* sim: bfin: use store buffer with more 32bit insnsMike Frysinger2011-04-162-23/+37
* gdb: sim: add style fixes lost between git->cvsMike Frysinger2011-04-151-0/+1
* gdb: sim: add command line completionMike Frysinger2011-04-152-0/+56
* sim: bfin: handle implicit DISALGNEXCPT with video insnsMike Frysinger2011-04-152-0/+30
* sim: bfin: respect the port level on signals to the SICMike Frysinger2011-04-112-16/+32
* sim: bfin: add missing GPIO pin 15Mike Frysinger2011-04-112-0/+5
* sim: dv-glue: fix up style a bitMike Frysinger2011-04-022-7/+38
* sim: fix up style a bitMike Frysinger2011-04-0214-80/+137
* sim: bfin: add OTP output portMike Frysinger2011-04-012-0/+12
* sim: bfin: regen configure to include new cfi deviceMike Frysinger2011-03-292-1/+5
* sim: cfi: new flash device simulationMike Frysinger2011-03-295-1/+869
* sim: bfin: fix sign extension with 16bit acc add insnsMike Frysinger2011-03-292-9/+9
* sim: bfin: handle saturation with RND12 sub insnsMike Frysinger2011-03-272-1/+11
* sim: bfin: add missing VS set with add/sub insnsMike Frysinger2011-03-262-0/+7
* sim: bfin: add hw tracing to gpio/sic port eventsMike Frysinger2011-03-253-10/+64
* sim: bfin: fix GPIO logic bugs when processing eventsMike Frysinger2011-03-252-4/+16
* sim: bfin: fix clear/set/toggle GPIO handlingMike Frysinger2011-03-252-0/+11
* sim: bfin: document SIC limitationMike Frysinger2011-03-242-1/+27
* sim: bfin: fix inverted W1C logicMike Frysinger2011-03-2414-17/+34
* sim: bfin: define more UART LSR bitsMike Frysinger2011-03-242-7/+16
* sim: bfin: fix typo in TWI stat regMike Frysinger2011-03-242-1/+5
* sim: bfin: update VIT_MAX behavior to match hardware when Acc.X bits are setMike Frysinger2011-03-242-2/+7
* sim: bfin: always do 16bit sign extension with the SEARCH insnMike Frysinger2011-03-242-0/+10
* sim: bfin: update AV and AC ASTAT bits with acc negationMike Frysinger2011-03-242-6/+14
* sim: bfin: fix thinko in SIC pin encodingMike Frysinger2011-03-242-511/+516
* sim: bfin: allow byteop[123]p src regs to be the sameMike Frysinger2011-03-242-9/+5
* sim: bfin: fix thinko in bfin_gpio bus addressesMike Frysinger2011-03-242-30/+38
* * gennltvals.sh: Search sys/_default_fcntl.h, in addition toKevin Buettner2011-03-215-384/+390
* * simops (OP_10007E0): Update errno handling as most trapsKevin Buettner2011-03-212-3/+88
* sim: bfin: check for kill/preadMike Frysinger2011-03-175-2/+25
* sim: bfin: add GPIO device simulationMike Frysinger2011-03-157-28/+369
* sim: bfin: fix brace styleMike Frysinger2011-03-1527-27/+54
* sim: bfin: fix brace styleMike Frysinger2011-03-1527-54/+27
* sim: bfin: fix brace styleMike Frysinger2011-03-1527-27/+54
* sim: bfin: fix brace styleMike Frysinger2011-03-1558-161/+342
* sim: bfin: handle AZ updates with 16bit adds/subsMike Frysinger2011-03-152-1/+6
* sim: bfin: skip acc/ASTAT updates for movesMike Frysinger2011-03-152-6/+10
* sim: bfin: handle AN (negative overflows) in dsp mult insnsMike Frysinger2011-03-152-8/+40
* sim: bfin: handle V overflows in dsp mult insnsMike Frysinger2011-03-152-7/+15
* sim: bfin: decode ASTAT on failureMike Frysinger2011-03-152-34/+79
* sim: bfin: handle saturation with fract multiplicationsMike Frysinger2011-03-152-149/+55
* sim: bfin: handle AZ updates with 16bit adds/subsMike Frysinger2011-03-152-1/+6
* sim: bfin: skip acc/ASTAT updates for movesMike Frysinger2011-03-152-6/+10
* sim: bfin: handle AN (negative overflows) in dsp mult insnsMike Frysinger2011-03-152-8/+40
* sim: bfin: handle V overflows in dsp mult insnsMike Frysinger2011-03-152-7/+15
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