summaryrefslogtreecommitdiff
path: root/src/gf_cpu.c
diff options
context:
space:
mode:
Diffstat (limited to 'src/gf_cpu.c')
-rw-r--r--src/gf_cpu.c33
1 files changed, 24 insertions, 9 deletions
diff --git a/src/gf_cpu.c b/src/gf_cpu.c
index ee2f847..fae2cd5 100644
--- a/src/gf_cpu.c
+++ b/src/gf_cpu.c
@@ -22,20 +22,35 @@ int gf_cpu_supports_arm_neon = 0;
#if defined(__x86_64__)
+#if defined(_MSC_VER)
+
+#define cpuid(info, x) __cpuidex(info, x, 0)
+
+#elif defined(__GNUC__)
+
+#include <cpuid.h>
+void cpuid(int info[4], int InfoType){
+ __cpuid_count(InfoType, 0, info[0], info[1], info[2], info[3]);
+}
+
+#else
+
+#error please add a way to detect CPU SIMD support at runtime
+
+#endif
+
void gf_cpu_identify(void)
{
if (gf_cpu_identified) {
return;
}
- int op = 1, eax, ebx, ecx, edx;
+ int reg[4];
- __asm__("cpuid"
- : "=a" (eax), "=b" (ebx), "=c" (ecx), "=d" (edx)
- : "a" (op));
+ cpuid(reg, 1);
#if defined(INTEL_SSE4_PCLMUL)
- if ((ecx & 1) != 0 && !getenv("GF_COMPLETE_DISABLE_SSE4_PCLMUL")) {
+ if ((reg[2] & 1) != 0 && !getenv("GF_COMPLETE_DISABLE_SSE4_PCLMUL")) {
gf_cpu_supports_intel_pclmul = 1;
#ifdef DEBUG_CPU_DETECTION
printf("#gf_cpu_supports_intel_pclmul\n");
@@ -44,7 +59,7 @@ void gf_cpu_identify(void)
#endif
#if defined(INTEL_SSE4)
- if (((ecx & (1<<20)) != 0 || (ecx & (1<<19)) != 0) && !getenv("GF_COMPLETE_DISABLE_SSE4")) {
+ if (((reg[2] & (1<<20)) != 0 || (reg[2] & (1<<19)) != 0) && !getenv("GF_COMPLETE_DISABLE_SSE4")) {
gf_cpu_supports_intel_sse4 = 1;
#ifdef DEBUG_CPU_DETECTION
printf("#gf_cpu_supports_intel_sse4\n");
@@ -53,7 +68,7 @@ void gf_cpu_identify(void)
#endif
#if defined(INTEL_SSSE3)
- if ((ecx & (1<<9)) != 0 && !getenv("GF_COMPLETE_DISABLE_SSSE3")) {
+ if ((reg[2] & (1<<9)) != 0 && !getenv("GF_COMPLETE_DISABLE_SSSE3")) {
gf_cpu_supports_intel_ssse3 = 1;
#ifdef DEBUG_CPU_DETECTION
printf("#gf_cpu_supports_intel_ssse3\n");
@@ -62,7 +77,7 @@ void gf_cpu_identify(void)
#endif
#if defined(INTEL_SSE3)
- if ((ecx & 1) != 0 && !getenv("GF_COMPLETE_DISABLE_SSE3")) {
+ if ((reg[2] & 1) != 0 && !getenv("GF_COMPLETE_DISABLE_SSE3")) {
gf_cpu_supports_intel_sse3 = 1;
#ifdef DEBUG_CPU_DETECTION
printf("#gf_cpu_supports_intel_sse3\n");
@@ -71,7 +86,7 @@ void gf_cpu_identify(void)
#endif
#if defined(INTEL_SSE2)
- if ((edx & (1<<26)) != 0 && !getenv("GF_COMPLETE_DISABLE_SSE2")) {
+ if ((reg[3] & (1<<26)) != 0 && !getenv("GF_COMPLETE_DISABLE_SSE2")) {
gf_cpu_supports_intel_sse2 = 1;
#ifdef DEBUG_CPU_DETECTION
printf("#gf_cpu_supports_intel_sse2\n");