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authorKevin Ryde <user42@zip.com.au>2003-10-21 02:44:51 +0200
committerKevin Ryde <user42@zip.com.au>2003-10-21 02:44:51 +0200
commitb7c1e64b10f2854aa84ea7a94702820ed83a0f47 (patch)
treea5128a3ef08333c2658de25c916a91b61c50e106 /doc/tasks.html
parent09a0c8a7bd6e09949d2ed77334285268d0c81dd5 (diff)
downloadgmp-b7c1e64b10f2854aa84ea7a94702820ed83a0f47.tar.gz
Reword ARM V5 clz, add gcc 3.4 __builtin_clzl.
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@@ -293,8 +293,9 @@ MA 02111-1307, USA.
making <code>configure</code> choose the slower
<code>malloc-reentrant</code> allocation method. Is there a better way?
Maybe variable-length arrays per notes below.
-<li> ARM: On v5 cpus see if the <code>clz</code> instruction can be used for
- <code>count_leading_zeros</code>.
+<li> ARM V5: <code>count_leading_zeros</code> can use the <code>clz</code>
+ instruction. For GCC 3.4 and up, do this via <code>__builtin_clzl</code>
+ since then gcc knows it's "predicable".
<li> Itanium: <code>mpn_hamdist</code> could be put together based on the
current <code>mpn_popcount</code>.
<li> Itanium: GCC 3.4 introduces <code>__builtin_popcount</code> which can be