Initial support for RISCV64

Add the RISCV64 architecture

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>

4 files changed, 143 insertions, 1 deletions

diff --git a/lib/Makefile b/lib/Makefile
index d0902ca..cf4239d 100644
--- a/lib/Makefile
+++ b/lib/Makefile
@@ -64,7 +64,7 @@ endif
 
 OBJS  = $(FILES:%=%.o)
 
-SUBDIRS = ia32 x86_64 ia64 aarch64 arm mips64el runtime
+SUBDIRS = ia32 x86_64 ia64 aarch64 arm mips64el riscv64 runtime
 
 LIBDIRINSTALL = $(INSTALLROOT)$(LIBDIR)
 
diff --git a/lib/riscv64/initplat.c b/lib/riscv64/initplat.c
new file mode 100644
index 0000000..ed42037
--- /dev/null
+++ b/lib/riscv64/initplat.c
@@ -0,0 +1,11 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+#include "lib.h"
+
+VOID
+InitializeLibPlatform (
+    IN EFI_HANDLE           ImageHandle EFI_UNUSED,
+    IN EFI_SYSTEM_TABLE     *SystemTable EFI_UNUSED
+    )
+{
+}
diff --git a/lib/riscv64/math.c b/lib/riscv64/math.c
new file mode 100644
index 0000000..3653e42
--- /dev/null
+++ b/lib/riscv64/math.c
@@ -0,0 +1,62 @@
+// SPDX-License-Identifier: BSD-2-Clause-Patent
+/*
+ * This code is based on EDK II MdePkg/Library/BaseLib/Math64.c
+ * Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.
+ */
+
+#include "lib.h"
+
+/**
+ * LShiftU64() - left shift
+ */
+UINT64
+LShiftU64 (
+	IN UINT64   Operand,
+	IN UINTN    Count
+)
+{
+	return Operand << Count;
+}
+
+/**
+ * RShiftU64() - right shift
+ */
+UINT64
+RShiftU64 (
+	IN UINT64   Operand,
+	IN UINTN    Count
+)
+{
+	return Operand >> Count;
+}
+
+/**
+ * MultU64x32() - multiply
+ */
+UINT64
+MultU64x32 (
+	IN UINT64   Multiplicand,
+	IN UINTN    Multiplier
+)
+{
+	return Multiplicand * Multiplier;
+}
+
+/**
+ * DivU64x32() - divide
+ */
+UINT64
+DivU64x32 (
+	IN UINT64   Dividend,
+	IN UINTN    Divisor,
+	OUT UINTN   *Remainder OPTIONAL
+)
+{
+	ASSERT(Divisor != 0);
+
+	if (Remainder) {
+		*Remainder = Dividend % Divisor;
+	}
+
+	return Dividend / Divisor;
+}
diff --git a/lib/riscv64/setjmp.S b/lib/riscv64/setjmp.S
new file mode 100644
index 0000000..fa187d1
--- /dev/null
+++ b/lib/riscv64/setjmp.S
@@ -0,0 +1,69 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright Heinrich Schuchardt <xypron.glpk@gmx.de>
+ */
+
+	.text
+	.p2align 3
+
+#define GREG_LIST \
+	REG_ONE(s0, 0); \
+	REG_ONE(s1, 8); \
+	REG_ONE(s2, 16); \
+	REG_ONE(s3, 24); \
+	REG_ONE(s4, 32); \
+	REG_ONE(s5, 40); \
+	REG_ONE(s6, 48); \
+	REG_ONE(s7, 56); \
+	REG_ONE(s8, 64); \
+	REG_ONE(s9, 72); \
+	REG_ONE(s10, 80); \
+	REG_ONE(s11, 88); \
+	REG_ONE(sp, 96); \
+	REG_ONE(ra, 104);
+
+#define FREG_LIST \
+	FREG_ONE(fs0,  112); \
+	FREG_ONE(fs1,  120); \
+	FREG_ONE(fs2,  128); \
+	FREG_ONE(fs3,  136); \
+	FREG_ONE(fs4,  144); \
+	FREG_ONE(fs5,  152); \
+	FREG_ONE(fs6,  160); \
+	FREG_ONE(fs7,  168); \
+	FREG_ONE(fs8,  176); \
+	FREG_ONE(fs9,  184); \
+	FREG_ONE(fs10, 192); \
+	FREG_ONE(fs11, 200);
+
+#define REG_ONE(R, P) sd R, P(a0)
+#define FREG_ONE(R, P) fsd R, P(a0)
+
+	.globl setjmp
+	.type setjmp, @function
+
+setjmp:
+	GREG_LIST
+#ifndef __riscv_float_abi_soft
+	FREG_LIST
+#endif
+	li a0, 0
+	ret
+
+#undef REG_ONE
+#undef FREG_ONE
+
+#define REG_ONE(R, P) ld R, P(a0)
+#define FREG_ONE(R, P) fld R, P(a0)
+
+	.globl longjmp
+	.type longjmp, @function
+
+longjmp:
+	GREG_LIST
+#ifndef __riscv_float_abi_soft
+	FREG_LIST
+#endif
+	seqz a0, a1
+	add a0, a0, a1
+	ret