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author | sewardj <unknown> | 2000-10-12 15:17:08 +0000 |
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committer | sewardj <unknown> | 2000-10-12 15:17:08 +0000 |
commit | 6dd3b5de2be9fd591722101a4ecf2efcc81880fe (patch) | |
tree | 9a5db5b14d57671c525655f34822884ccaf40515 | |
parent | 90f7d2bdb87e53a8715fd7987c41c9fd5bb99f13 (diff) | |
download | haskell-6dd3b5de2be9fd591722101a4ecf2efcc81880fe.tar.gz |
[project @ 2000-10-12 15:17:07 by sewardj]
FastInt fixes
-rw-r--r-- | ghc/compiler/absCSyn/AbsCSyn.lhs | 13 | ||||
-rw-r--r-- | ghc/compiler/absCSyn/CLabel.lhs | 8 | ||||
-rw-r--r-- | ghc/compiler/basicTypes/Module.lhs | 4 | ||||
-rw-r--r-- | ghc/compiler/codeGen/CgRetConv.lhs | 67 |
4 files changed, 52 insertions, 40 deletions
diff --git a/ghc/compiler/absCSyn/AbsCSyn.lhs b/ghc/compiler/absCSyn/AbsCSyn.lhs index 6bd34a6fb8..830f819cf4 100644 --- a/ghc/compiler/absCSyn/AbsCSyn.lhs +++ b/ghc/compiler/absCSyn/AbsCSyn.lhs @@ -1,7 +1,7 @@ % % (c) The GRASP/AQUA Project, Glasgow University, 1992-1998 % -% $Id: AbsCSyn.lhs,v 1.34 2000/10/12 13:11:46 simonmar Exp $ +% $Id: AbsCSyn.lhs,v 1.35 2000/10/12 15:17:07 sewardj Exp $ % \section[AbstractC]{Abstract C: the last stop before machine code} @@ -50,6 +50,7 @@ import Unique ( Unique ) import StgSyn ( SRT(..) ) import TyCon ( TyCon ) import BitSet -- for liveness masks +import FastTypes \end{code} @@ -388,16 +389,16 @@ data ReturnInfo hpRel :: VirtualHeapOffset -- virtual offset of Hp -> VirtualHeapOffset -- virtual offset of The Thing -> RegRelative -- integer offset -hpRel _IBOX(hp) _IBOX(off) = HpRel (hp _SUB_ off) +hpRel hp off = HpRel (iUnbox (hp - off)) spRel :: VirtualSpOffset -- virtual offset of Sp -> VirtualSpOffset -- virtual offset of The Thing -> RegRelative -- integer offset -spRel sp off = SpRel (case spRelToInt sp off of { _IBOX(i) -> i }) +spRel sp off = SpRel (iUnbox (spRelToInt sp off)) nodeRel :: VirtualHeapOffset -> RegRelative -nodeRel _IBOX(off) = NodeRel off +nodeRel off = NodeRel (iUnbox off) \end{code} @@ -476,8 +477,8 @@ data MagicId | CurrentNursery -- pointer to allocation area -node = VanillaReg PtrRep _ILIT(1) -- A convenient alias for Node -tagreg = VanillaReg WordRep _ILIT(2) -- A convenient alias for TagReg +node = VanillaReg PtrRep (_ILIT 1) -- A convenient alias for Node +tagreg = VanillaReg WordRep (_ILIT 2) -- A convenient alias for TagReg nodeReg = CReg node \end{code} diff --git a/ghc/compiler/absCSyn/CLabel.lhs b/ghc/compiler/absCSyn/CLabel.lhs index ac71fe6f74..01fb02307d 100644 --- a/ghc/compiler/absCSyn/CLabel.lhs +++ b/ghc/compiler/absCSyn/CLabel.lhs @@ -1,7 +1,7 @@ % % (c) The GRASP/AQUA Project, Glasgow University, 1992-1998 % -% $Id: CLabel.lhs,v 1.38 2000/08/02 14:13:26 rrt Exp $ +% $Id: CLabel.lhs,v 1.39 2000/10/12 15:17:07 sewardj Exp $ % \section[CLabel]{@CLabel@: Information to make C Labels} @@ -84,7 +84,8 @@ import {-# SOURCE #-} MachMisc ( underscorePrefix, fmtAsmLbl ) import CmdLineOpts ( opt_Static, opt_DoTickyProfiling ) import CStrings ( pp_cSEP ) import DataCon ( ConTag, DataCon ) -import Module ( ModuleName, moduleName, Module, isLocalModule ) +import Module ( ModuleName, moduleName, moduleNameFS, + Module, isLocalModule ) import Name ( Name, getName, isDllName, isExternallyVisibleName ) import TyCon ( TyCon ) import Unique ( pprUnique, Unique ) @@ -525,7 +526,8 @@ pprCLbl (DataConLabel con flavor) = ppr con <> ppConFlavor flavor pprCLbl (CC_Label cc) = ppr cc pprCLbl (CCS_Label ccs) = ppr ccs -pprCLbl (ModuleInitLabel mod) = ptext SLIT("__init_") <> ptext (moduleName mod) +pprCLbl (ModuleInitLabel mod) + = ptext SLIT("__init_") <> ptext (moduleNameFS (moduleName mod)) ppIdFlavor :: IdLabelInfo -> SDoc diff --git a/ghc/compiler/basicTypes/Module.lhs b/ghc/compiler/basicTypes/Module.lhs index 7a4e91ddc7..61e625195a 100644 --- a/ghc/compiler/basicTypes/Module.lhs +++ b/ghc/compiler/basicTypes/Module.lhs @@ -29,6 +29,7 @@ module Module , moduleNameString -- :: ModuleName -> EncodedString , moduleNameUserString -- :: ModuleName -> UserString + , moduleNameFS -- :: ModuleName -> EncodedFS , moduleString -- :: Module -> EncodedString , moduleUserString -- :: Module -> UserString @@ -168,6 +169,9 @@ instance Outputable ModuleName where pprModuleName :: ModuleName -> SDoc pprModuleName (ModuleName nm) = pprEncodedFS nm +moduleNameFS :: ModuleName -> EncodedFS +moduleNameFS (ModuleName mod) = mod + moduleNameString :: ModuleName -> EncodedString moduleNameString (ModuleName mod) = _UNPK_ mod diff --git a/ghc/compiler/codeGen/CgRetConv.lhs b/ghc/compiler/codeGen/CgRetConv.lhs index 29e795e3fe..4c6d89b9c6 100644 --- a/ghc/compiler/codeGen/CgRetConv.lhs +++ b/ghc/compiler/codeGen/CgRetConv.lhs @@ -1,7 +1,7 @@ % % (c) The GRASP Project, Glasgow University, 1992-1998 % -% $Id: CgRetConv.lhs,v 1.26 2000/09/07 13:25:28 simonpj Exp $ +% $Id: CgRetConv.lhs,v 1.27 2000/10/12 15:17:08 sewardj Exp $ % \section[CgRetConv]{Return conventions for the code generator} @@ -30,7 +30,7 @@ import Maybes ( catMaybes ) import PrimRep ( isFloatingRep, PrimRep(..), is64BitRep ) import TyCon ( TyCon, tyConFamilySize ) import Util ( isn'tIn ) - +import FastTypes import Outputable \end{code} @@ -75,26 +75,26 @@ ctrlReturnConvAlg tycon \begin{code} dataReturnConvPrim :: PrimRep -> MagicId -dataReturnConvPrim IntRep = VanillaReg IntRep ILIT(1) -dataReturnConvPrim WordRep = VanillaReg WordRep ILIT(1) -dataReturnConvPrim Int64Rep = LongReg Int64Rep ILIT(1) -dataReturnConvPrim Word64Rep = LongReg Word64Rep ILIT(1) -dataReturnConvPrim AddrRep = VanillaReg AddrRep ILIT(1) -dataReturnConvPrim CharRep = VanillaReg CharRep ILIT(1) -dataReturnConvPrim Int8Rep = VanillaReg Int8Rep ILIT(1) -dataReturnConvPrim FloatRep = FloatReg ILIT(1) -dataReturnConvPrim DoubleRep = DoubleReg ILIT(1) +dataReturnConvPrim IntRep = VanillaReg IntRep (_ILIT 1) +dataReturnConvPrim WordRep = VanillaReg WordRep (_ILIT 1) +dataReturnConvPrim Int64Rep = LongReg Int64Rep (_ILIT 1) +dataReturnConvPrim Word64Rep = LongReg Word64Rep (_ILIT 1) +dataReturnConvPrim AddrRep = VanillaReg AddrRep (_ILIT 1) +dataReturnConvPrim CharRep = VanillaReg CharRep (_ILIT 1) +dataReturnConvPrim Int8Rep = VanillaReg Int8Rep (_ILIT 1) +dataReturnConvPrim FloatRep = FloatReg (_ILIT 1) +dataReturnConvPrim DoubleRep = DoubleReg (_ILIT 1) dataReturnConvPrim VoidRep = VoidReg -- Return a primitive-array pointer in the usual register: -dataReturnConvPrim ArrayRep = VanillaReg ArrayRep ILIT(1) -dataReturnConvPrim ByteArrayRep = VanillaReg ByteArrayRep ILIT(1) -dataReturnConvPrim PrimPtrRep = VanillaReg PrimPtrRep ILIT(1) -dataReturnConvPrim ThreadIdRep = VanillaReg ThreadIdRep ILIT(1) +dataReturnConvPrim ArrayRep = VanillaReg ArrayRep (_ILIT 1) +dataReturnConvPrim ByteArrayRep = VanillaReg ByteArrayRep (_ILIT 1) +dataReturnConvPrim PrimPtrRep = VanillaReg PrimPtrRep (_ILIT 1) +dataReturnConvPrim ThreadIdRep = VanillaReg ThreadIdRep (_ILIT 1) -dataReturnConvPrim StablePtrRep = VanillaReg StablePtrRep ILIT(1) -dataReturnConvPrim ForeignObjRep = VanillaReg ForeignObjRep ILIT(1) -dataReturnConvPrim WeakPtrRep = VanillaReg WeakPtrRep ILIT(1) +dataReturnConvPrim StablePtrRep = VanillaReg StablePtrRep (_ILIT 1) +dataReturnConvPrim ForeignObjRep = VanillaReg ForeignObjRep (_ILIT 1) +dataReturnConvPrim WeakPtrRep = VanillaReg WeakPtrRep (_ILIT 1) #ifdef DEBUG dataReturnConvPrim rep = pprPanic "dataReturnConvPrim:" (ppr rep) @@ -148,21 +148,26 @@ assign_reg (VoidRep:ks) acc supply = assign_reg ks (VoidReg:acc) supply -- one VoidReg is enough for everybody! -assign_reg (FloatRep:ks) acc (vanilla_rs, IBOX(f):float_rs, double_rs, long_rs) - = assign_reg ks (FloatReg f:acc) (vanilla_rs, float_rs, double_rs, long_rs) +assign_reg (FloatRep:ks) acc (vanilla_rs, f:float_rs, double_rs, long_rs) + = assign_reg ks (FloatReg (iUnbox f):acc) + (vanilla_rs, float_rs, double_rs, long_rs) -assign_reg (DoubleRep:ks) acc (vanilla_rs, float_rs, IBOX(d):double_rs, long_rs) - = assign_reg ks (DoubleReg d:acc) (vanilla_rs, float_rs, double_rs, long_rs) +assign_reg (DoubleRep:ks) acc (vanilla_rs, float_rs, d:double_rs, long_rs) + = assign_reg ks (DoubleReg (iUnbox d):acc) + (vanilla_rs, float_rs, double_rs, long_rs) -assign_reg (Word64Rep:ks) acc (vanilla_rs, float_rs, double_rs, IBOX(u):long_rs) - = assign_reg ks (LongReg Word64Rep u:acc) (vanilla_rs, float_rs, double_rs, long_rs) +assign_reg (Word64Rep:ks) acc (vanilla_rs, float_rs, double_rs, u:long_rs) + = assign_reg ks (LongReg Word64Rep (iUnbox u):acc) + (vanilla_rs, float_rs, double_rs, long_rs) -assign_reg (Int64Rep:ks) acc (vanilla_rs, float_rs, double_rs, IBOX(l):long_rs) - = assign_reg ks (LongReg Int64Rep l:acc) (vanilla_rs, float_rs, double_rs, long_rs) +assign_reg (Int64Rep:ks) acc (vanilla_rs, float_rs, double_rs, l:long_rs) + = assign_reg ks (LongReg Int64Rep (iUnbox l):acc) + (vanilla_rs, float_rs, double_rs, long_rs) -assign_reg (k:ks) acc (IBOX(v):vanilla_rs, float_rs, double_rs, long_rs) +assign_reg (k:ks) acc (v:vanilla_rs, float_rs, double_rs, long_rs) | not (isFloatingRep k || is64BitRep k) - = assign_reg ks (VanillaReg k v:acc) (vanilla_rs, float_rs, double_rs, long_rs) + = assign_reg ks (VanillaReg k (iUnbox v):acc) + (vanilla_rs, float_rs, double_rs, long_rs) -- The catch-all. It can happen because either -- (a) we've assigned all the regs so leftover_ks is [] @@ -218,13 +223,13 @@ mkRegTbl' regs_in_use vanillas floats doubles longs ok_long = catMaybes (map (select (LongReg Int64Rep)) longs) -- rep isn't looked at, hence we can use any old rep. - select :: (FAST_INT -> MagicId) -> Int{-cand-} -> Maybe Int + select :: (FastInt -> MagicId) -> Int{-cand-} -> Maybe Int -- one we've unboxed the Int, we make a MagicId -- and see if it is already in use; if not, return its number. - select mk_reg_fun cand@IBOX(i) + select mk_reg_fun cand = let - reg = mk_reg_fun i + reg = mk_reg_fun (iUnbox cand) in if reg `not_elem` regs_in_use then Just cand |